[linux-block.git] / arch / blackfin / mach-bf533 / head.S

/*
 * File:         arch/blackfin/mach-bf533/head.S
 * Based on:
 * Author:       Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
 *
 * Created:      1998
 * Description:  bf533 startup file
 *
 * Modified:
 *               Copyright 2004-2006 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/blackfin.h>
#include <asm/trace.h>
#ifdef CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h>
#include <asm/mach/mem_init.h>
#endif

.extern ___bss_stop
.extern ___bss_start
.extern _bf53x_relocate_l1_mem

#define INITIAL_STACK	0xFFB01000

__INIT

ENTRY(__start)
	/* R0: argument of command line string, passed from uboot, save it */
	R7 = R0;
	/* Enable Cycle Counter and Nesting Of Interrupts */
#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
	R0 = SYSCFG_SNEN;
#else
	R0 = SYSCFG_SNEN | SYSCFG_CCEN;
#endif
	SYSCFG = R0;
	R0 = 0;

	/* Clear Out All the data and pointer Registers */
	R1 = R0;
	R2 = R0;
	R3 = R0;
	R4 = R0;
	R5 = R0;
	R6 = R0;

	P0 = R0;
	P1 = R0;
	P2 = R0;
	P3 = R0;
	P4 = R0;
	P5 = R0;

	LC0 = r0;
	LC1 = r0;
	L0 = r0;
	L1 = r0;
	L2 = r0;
	L3 = r0;

	/* Clear Out All the DAG Registers */
	B0 = r0;
	B1 = r0;
	B2 = r0;
	B3 = r0;

	I0 = r0;
	I1 = r0;
	I2 = r0;
	I3 = r0;

	M0 = r0;
	M1 = r0;
	M2 = r0;
	M3 = r0;

	trace_buffer_init(p0,r0);
	P0 = R1;
	R0 = R1;

	p0.h = hi(FIO_MASKA_C);
	p0.l = lo(FIO_MASKA_C);
	r0 = 0xFFFF(Z);
	w[p0] = r0.L;	/* Disable all interrupts */
	ssync;

	p0.h = hi(FIO_MASKB_C);
	p0.l = lo(FIO_MASKB_C);
	r0 = 0xFFFF(Z);
	w[p0] = r0.L;	/* Disable all interrupts */
	ssync;

	/* Turn off the icache */
	p0.l = LO(IMEM_CONTROL);
	p0.h = HI(IMEM_CONTROL);
	R1 = [p0];
	R0 = ~ENICPLB;
	R0 = R0 & R1;

	/* Anomaly 05000125 */
#if ANOMALY_05000125
	CLI R2;
	SSYNC;
#endif
	[p0] = R0;
	SSYNC;
#if ANOMALY_05000125
	STI R2;
#endif

	/* Turn off the dcache */
	p0.l = LO(DMEM_CONTROL);
	p0.h = HI(DMEM_CONTROL);
	R1 = [p0];
	R0 = ~ENDCPLB;
	R0 = R0 & R1;

	/* Anomaly 05000125 */
#if ANOMALY_05000125
	CLI R2;
	SSYNC;
#endif
	[p0] = R0;
	SSYNC;
#if ANOMALY_05000125
	STI R2;
#endif

	/* Initialise UART - when booting from u-boot, the UART is not disabled
	 * so if we dont initalize here, our serial console gets hosed */
	p0.h = hi(BFIN_UART_LCR);
	p0.l = lo(BFIN_UART_LCR);
	r0 = 0x0(Z);
	w[p0] = r0.L;	/* To enable DLL writes */
	ssync;

	p0.h = hi(BFIN_UART_DLL);
	p0.l = lo(BFIN_UART_DLL);
	r0 = 0x0(Z);
	w[p0] = r0.L;
	ssync;

	p0.h = hi(BFIN_UART_DLH);
	p0.l = lo(BFIN_UART_DLH);
	r0 = 0x00(Z);
	w[p0] = r0.L;
	ssync;

	p0.h = hi(BFIN_UART_GCTL);
	p0.l = lo(BFIN_UART_GCTL);
	r0 = 0x0(Z);
	w[p0] = r0.L;	/* To enable UART clock */
	ssync;

	/* Initialize stack pointer */
	sp.l = lo(INITIAL_STACK);
	sp.h = hi(INITIAL_STACK);
	fp = sp;
	usp = sp;

#ifdef CONFIG_EARLY_PRINTK
	SP += -12;
	call _init_early_exception_vectors;
	SP += 12;
#endif

	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
	call _bf53x_relocate_l1_mem;
#ifdef CONFIG_BFIN_KERNEL_CLOCK
	call _start_dma_code;
#endif

	/* Code for initializing Async memory banks */

	p2.h = hi(EBIU_AMBCTL1);
	p2.l = lo(EBIU_AMBCTL1);
	r0.h = hi(AMBCTL1VAL);
	r0.l = lo(AMBCTL1VAL);
	[p2] = r0;
	ssync;

	p2.h = hi(EBIU_AMBCTL0);
	p2.l = lo(EBIU_AMBCTL0);
	r0.h = hi(AMBCTL0VAL);
	r0.l = lo(AMBCTL0VAL);
	[p2] = r0;
	ssync;

	p2.h = hi(EBIU_AMGCTL);
	p2.l = lo(EBIU_AMGCTL);
	r0 = AMGCTLVAL;
	w[p2] = r0;
	ssync;

	/* This section keeps the processor in supervisor mode
	 * during kernel boot.  Switches to user mode at end of boot.
	 * See page 3-9 of Hardware Reference manual for documentation.
	 */

	/* EVT15 = _real_start */

	p0.l = lo(EVT15);
	p0.h = hi(EVT15);
	p1.l = _real_start;
	p1.h = _real_start;
	[p0] = p1;
	csync;

	p0.l = lo(IMASK);
	p0.h = hi(IMASK);
	p1.l = IMASK_IVG15;
	p1.h = 0x0;
	[p0] = p1;
	csync;

	raise 15;
	p0.l = .LWAIT_HERE;
	p0.h = .LWAIT_HERE;
	reti = p0;
#if ANOMALY_05000281
	nop; nop; nop;
#endif
	rti;

.LWAIT_HERE:
	jump .LWAIT_HERE;
ENDPROC(__start)

ENTRY(_real_start)
	[ -- sp ] = reti;
	p0.l = lo(WDOG_CTL);
	p0.h = hi(WDOG_CTL);
	r0 = 0xAD6(z);
	w[p0] = r0;	/* watchdog off for now */
	ssync;

	/* Code update for BSS size == 0
	 * Zero out the bss region.
	 */

	p1.l = ___bss_start;
	p1.h = ___bss_start;
	p2.l = ___bss_stop;
	p2.h = ___bss_stop;
	r0 = 0;
	p2 -= p1;
	lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
.L_clear_bss:
	B[p1++] = r0;

	/* In case there is a NULL pointer reference
	 * Zero out region before stext
	 */

	p1.l = 0x0;
	p1.h = 0x0;
	r0.l = __stext;
	r0.h = __stext;
	r0 = r0 >> 1;
	p2 = r0;
	r0 = 0;
	lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
.L_clear_zero:
	W[p1++] = r0;

	/* pass the uboot arguments to the global value command line */
	R0 = R7;
	call _cmdline_init;

	p1.l = __rambase;
	p1.h = __rambase;
	r0.l = __sdata;
	r0.h = __sdata;
	[p1] = r0;

	p1.l = __ramstart;
	p1.h = __ramstart;
	p3.l = ___bss_stop;
	p3.h = ___bss_stop;

	r1 = p3;
	[p1] = r1;

	/*
	 * load the current thread pointer and stack
	 */
	r1.l = _init_thread_union;
	r1.h = _init_thread_union;

	r2.l = 0x2000;
	r2.h = 0x0000;
	r1 = r1 + r2;
	sp = r1;
	usp = sp;
	fp = sp;
	jump.l _start_kernel;
ENDPROC(_real_start)

__FINIT

.section .l1.text
#ifdef CONFIG_BFIN_KERNEL_CLOCK
ENTRY(_start_dma_code)
	p0.h = hi(SIC_IWR);
	p0.l = lo(SIC_IWR);
	r0.l = 0x1;
	r0.h = 0x0;
	[p0] = r0;
	SSYNC;

	/*
	 *  Set PLL_CTL
	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
	 *   - [7]     = output delay (add 200ps of delay to mem signals)
	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
	 *   - [5]     = PDWN      : 1=All Clocks off
	 *   - [3]     = STOPCK    : 1=Core Clock off
	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
	 *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
	 *   all other bits set to zero
	 */

	p0.h = hi(PLL_LOCKCNT);
	p0.l = lo(PLL_LOCKCNT);
	r0 = 0x300(Z);
	w[p0] = r0.l;
	ssync;

	P2.H = hi(EBIU_SDGCTL);
	P2.L = lo(EBIU_SDGCTL);
	R0 = [P2];
	BITSET (R0, 24);
	[P2] = R0;
	SSYNC;

	r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
	r0 = r0 << 9;                    /* Shift it over,                  */
	r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
	r0 = r1 | r0;
	r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
	r1 = r1 << 8;                    /* Shift it over                   */
	r0 = r1 | r0;                    /* add them all together           */

	p0.h = hi(PLL_CTL);
	p0.l = lo(PLL_CTL);              /* Load the address                */
	cli r2;                          /* Disable interrupts              */
	ssync;
	w[p0] = r0.l;                    /* Set the value                   */
	idle;                            /* Wait for the PLL to stablize    */
	sti r2;                          /* Enable interrupts               */

.Lcheck_again:
	p0.h = hi(PLL_STAT);
	p0.l = lo(PLL_STAT);
	R0 = W[P0](Z);
	CC = BITTST(R0,5);
	if ! CC jump .Lcheck_again;

	/* Configure SCLK & CCLK Dividers */
	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
	p0.h = hi(PLL_DIV);
	p0.l = lo(PLL_DIV);
	w[p0] = r0.l;
	ssync;

	p0.l = lo(EBIU_SDRRC);
	p0.h = hi(EBIU_SDRRC);
	r0 = mem_SDRRC;
	w[p0] = r0.l;
	ssync;

	P2.H = hi(EBIU_SDGCTL);
	P2.L = lo(EBIU_SDGCTL);
	R0 = [P2];
	BITCLR (R0, 24);
	p0.h = hi(EBIU_SDSTAT);
	p0.l = lo(EBIU_SDSTAT);
	r2.l = w[p0];
	cc = bittst(r2,3);
	if !cc jump .Lskip;
	NOP;
	BITSET (R0, 23);
.Lskip:
	[P2] = R0;
	SSYNC;

	R0.L = lo(mem_SDGCTL);
	R0.H = hi(mem_SDGCTL);
	R1 = [p2];
	R1 = R1 | R0;
	[P2] = R1;
	SSYNC;

	p0.h = hi(SIC_IWR);
	p0.l = lo(SIC_IWR);
	r0.l = lo(IWR_ENABLE_ALL);
	r0.h = hi(IWR_ENABLE_ALL);
	[p0] = r0;
	SSYNC;

	RTS;
ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
Commit	Line	Data
1394f032 BW	1	/*
	2	* File: arch/blackfin/mach-bf533/head.S
	3	* Based on:
	4	* Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
	5	*
	6	* Created: 1998
	7	* Description: bf533 startup file
	8	*
	9	* Modified:
	10	* Copyright 2004-2006 Analog Devices Inc.
	11	*
	12	* Bugs: Enter bugs at http://blackfin.uclinux.org/
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2 of the License, or
	17	* (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, see the file COPYING, or write
	26	* to the Free Software Foundation, Inc.,
	27	* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	28	*/
	29
	30	#include <linux/linkage.h>
52a07812	31	#include <linux/init.h>
1394f032	32	#include <asm/blackfin.h>
669b792c	33	#include <asm/trace.h>
68e2fc78	34	#ifdef CONFIG_BFIN_KERNEL_CLOCK
f16295e7	35	#include <asm/mach-common/clocks.h>
1394f032 BW	36	#include <asm/mach/mem_init.h>
1394f032 BW	37	#endif
1394f032	38
1394f032 BW	39	.extern ___bss_stop
	40	.extern ___bss_start
	41	.extern _bf53x_relocate_l1_mem
	42
	43	#define INITIAL_STACK 0xFFB01000
	44
52a07812	45	__INIT
1394f032 BW	46
1394f032 BW	47	ENTRY(__start)
1394f032 BW	48	/* R0: argument of command line string, passed from uboot, save it */
1394f032 BW	49	R7 = R0;
f0b5d12f MF	50	/* Enable Cycle Counter and Nesting Of Interrupts */
	51	#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
	52	R0 = SYSCFG_SNEN;
	53	#else
	54	R0 = SYSCFG_SNEN \| SYSCFG_CCEN;
	55	#endif
1394f032 BW	56	SYSCFG = R0;
	57	R0 = 0;
	58
83a5c3e3	59	/* Clear Out All the data and pointer Registers */
1394f032 BW	60	R1 = R0;
	61	R2 = R0;
	62	R3 = R0;
	63	R4 = R0;
	64	R5 = R0;
	65	R6 = R0;
	66
	67	P0 = R0;
	68	P1 = R0;
	69	P2 = R0;
	70	P3 = R0;
	71	P4 = R0;
	72	P5 = R0;
	73
	74	LC0 = r0;
	75	LC1 = r0;
	76	L0 = r0;
	77	L1 = r0;
	78	L2 = r0;
	79	L3 = r0;
	80
83a5c3e3	81	/* Clear Out All the DAG Registers */
1394f032 BW	82	B0 = r0;
	83	B1 = r0;
	84	B2 = r0;
	85	B3 = r0;
	86
	87	I0 = r0;
	88	I1 = r0;
	89	I2 = r0;
	90	I3 = r0;
	91
	92	M0 = r0;
	93	M1 = r0;
	94	M2 = r0;
	95	M3 = r0;
	96
518039bc	97	trace_buffer_init(p0,r0);
669b792c RG	98	P0 = R1;
	99	R0 = R1;
	100
1394f032 BW	101	p0.h = hi(FIO_MASKA_C);
	102	p0.l = lo(FIO_MASKA_C);
	103	r0 = 0xFFFF(Z);
	104	w[p0] = r0.L; /* Disable all interrupts */
	105	ssync;
	106
	107	p0.h = hi(FIO_MASKB_C);
	108	p0.l = lo(FIO_MASKB_C);
	109	r0 = 0xFFFF(Z);
	110	w[p0] = r0.L; /* Disable all interrupts */
	111	ssync;
	112
	113	/* Turn off the icache */
e208f83a MF	114	p0.l = LO(IMEM_CONTROL);
e208f83a MF	115	p0.h = HI(IMEM_CONTROL);
1394f032 BW	116	R1 = [p0];
	117	R0 = ~ENICPLB;
	118	R0 = R0 & R1;
	119
	120	/* Anomaly 05000125 */
1aafd909	121	#if ANOMALY_05000125
1394f032 BW	122	CLI R2;
	123	SSYNC;
	124	#endif
	125	[p0] = R0;
	126	SSYNC;
1aafd909	127	#if ANOMALY_05000125
1394f032 BW	128	STI R2;
	129	#endif
	130
	131	/* Turn off the dcache */
e208f83a MF	132	p0.l = LO(DMEM_CONTROL);
e208f83a MF	133	p0.h = HI(DMEM_CONTROL);
1394f032 BW	134	R1 = [p0];
	135	R0 = ~ENDCPLB;
	136	R0 = R0 & R1;
	137
	138	/* Anomaly 05000125 */
1aafd909	139	#if ANOMALY_05000125
1394f032 BW	140	CLI R2;
	141	SSYNC;
	142	#endif
	143	[p0] = R0;
	144	SSYNC;
1aafd909	145	#if ANOMALY_05000125
1394f032 BW	146	STI R2;
	147	#endif
	148
5079df99 MF	149	/* Initialise UART - when booting from u-boot, the UART is not disabled
5079df99 MF	150	* so if we dont initalize here, our serial console gets hosed */
6ed83942 GY	151	p0.h = hi(BFIN_UART_LCR);
6ed83942 GY	152	p0.l = lo(BFIN_UART_LCR);
1394f032 BW	153	r0 = 0x0(Z);
	154	w[p0] = r0.L; /* To enable DLL writes */
	155	ssync;
	156
6ed83942 GY	157	p0.h = hi(BFIN_UART_DLL);
6ed83942 GY	158	p0.l = lo(BFIN_UART_DLL);
1394f032 BW	159	r0 = 0x0(Z);
	160	w[p0] = r0.L;
	161	ssync;
	162
6ed83942 GY	163	p0.h = hi(BFIN_UART_DLH);
6ed83942 GY	164	p0.l = lo(BFIN_UART_DLH);
1394f032 BW	165	r0 = 0x00(Z);
	166	w[p0] = r0.L;
	167	ssync;
	168
6ed83942 GY	169	p0.h = hi(BFIN_UART_GCTL);
6ed83942 GY	170	p0.l = lo(BFIN_UART_GCTL);
1394f032 BW	171	r0 = 0x0(Z);
	172	w[p0] = r0.L; /* To enable UART clock */
	173	ssync;
	174
	175	/* Initialize stack pointer */
	176	sp.l = lo(INITIAL_STACK);
	177	sp.h = hi(INITIAL_STACK);
	178	fp = sp;
	179	usp = sp;
	180
337d390b RG	181	#ifdef CONFIG_EARLY_PRINTK
	182	SP += -12;
	183	call _init_early_exception_vectors;
	184	SP += 12;
	185	#endif
	186
1394f032 BW	187	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
1394f032 BW	188	call _bf53x_relocate_l1_mem;
68e2fc78	189	#ifdef CONFIG_BFIN_KERNEL_CLOCK
1394f032 BW	190	call _start_dma_code;
	191	#endif
	192
	193	/* Code for initializing Async memory banks */
	194
	195	p2.h = hi(EBIU_AMBCTL1);
	196	p2.l = lo(EBIU_AMBCTL1);
	197	r0.h = hi(AMBCTL1VAL);
	198	r0.l = lo(AMBCTL1VAL);
	199	[p2] = r0;
	200	ssync;
	201
	202	p2.h = hi(EBIU_AMBCTL0);
	203	p2.l = lo(EBIU_AMBCTL0);
	204	r0.h = hi(AMBCTL0VAL);
	205	r0.l = lo(AMBCTL0VAL);
	206	[p2] = r0;
	207	ssync;
	208
	209	p2.h = hi(EBIU_AMGCTL);
	210	p2.l = lo(EBIU_AMGCTL);
	211	r0 = AMGCTLVAL;
	212	w[p2] = r0;
	213	ssync;
	214
	215	/* This section keeps the processor in supervisor mode
	216	* during kernel boot. Switches to user mode at end of boot.
	217	* See page 3-9 of Hardware Reference manual for documentation.
	218	*/
	219
	220	/* EVT15 = _real_start */
	221
	222	p0.l = lo(EVT15);
	223	p0.h = hi(EVT15);
	224	p1.l = _real_start;
	225	p1.h = _real_start;
	226	[p0] = p1;
	227	csync;
	228
	229	p0.l = lo(IMASK);
	230	p0.h = hi(IMASK);
	231	p1.l = IMASK_IVG15;
	232	p1.h = 0x0;
	233	[p0] = p1;
	234	csync;
	235
	236	raise 15;
	237	p0.l = .LWAIT_HERE;
	238	p0.h = .LWAIT_HERE;
	239	reti = p0;
1aafd909	240	#if ANOMALY_05000281
1394f032 BW	241	nop; nop; nop;
	242	#endif
	243	rti;
	244
	245	.LWAIT_HERE:
	246	jump .LWAIT_HERE;
52a07812	247	ENDPROC(__start)
1394f032 BW	248
	249	ENTRY(_real_start)
	250	[ -- sp ] = reti;
	251	p0.l = lo(WDOG_CTL);
	252	p0.h = hi(WDOG_CTL);
	253	r0 = 0xAD6(z);
	254	w[p0] = r0; /* watchdog off for now */
	255	ssync;
	256
	257	/* Code update for BSS size == 0
	258	* Zero out the bss region.
	259	*/
	260
	261	p1.l = ___bss_start;
	262	p1.h = ___bss_start;
	263	p2.l = ___bss_stop;
	264	p2.h = ___bss_stop;
	265	r0 = 0;
	266	p2 -= p1;
	267	lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
	268	.L_clear_bss:
	269	B[p1++] = r0;
	270
	271	/* In case there is a NULL pointer reference
	272	* Zero out region before stext
	273	*/
	274
	275	p1.l = 0x0;
	276	p1.h = 0x0;
	277	r0.l = __stext;
	278	r0.h = __stext;
	279	r0 = r0 >> 1;
	280	p2 = r0;
	281	r0 = 0;
	282	lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
	283	.L_clear_zero:
	284	W[p1++] = r0;
	285
83a5c3e3	286	/* pass the uboot arguments to the global value command line */
1394f032 BW	287	R0 = R7;
	288	call _cmdline_init;
	289
	290	p1.l = __rambase;
	291	p1.h = __rambase;
	292	r0.l = __sdata;
	293	r0.h = __sdata;
	294	[p1] = r0;
	295
	296	p1.l = __ramstart;
	297	p1.h = __ramstart;
	298	p3.l = ___bss_stop;
	299	p3.h = ___bss_stop;
	300
	301	r1 = p3;
	302	[p1] = r1;
	303
	304	/*
83a5c3e3	305	* load the current thread pointer and stack
1394f032 BW	306	*/
	307	r1.l = _init_thread_union;
	308	r1.h = _init_thread_union;
	309
	310	r2.l = 0x2000;
	311	r2.h = 0x0000;
	312	r1 = r1 + r2;
	313	sp = r1;
	314	usp = sp;
	315	fp = sp;
52a07812 MF	316	jump.l _start_kernel;
	317	ENDPROC(_real_start)
	318
	319	__FINIT
1394f032 BW	320
1394f032 BW	321	.section .l1.text
68e2fc78	322	#ifdef CONFIG_BFIN_KERNEL_CLOCK
1394f032 BW	323	ENTRY(_start_dma_code)
	324	p0.h = hi(SIC_IWR);
	325	p0.l = lo(SIC_IWR);
	326	r0.l = 0x1;
	327	r0.h = 0x0;
	328	[p0] = r0;
	329	SSYNC;
	330
	331	/*
	332	* Set PLL_CTL
	333	* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
	334	* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
	335	* - [7] = output delay (add 200ps of delay to mem signals)
	336	* - [6] = input delay (add 200ps of input delay to mem signals)
	337	* - [5] = PDWN : 1=All Clocks off
	338	* - [3] = STOPCK : 1=Core Clock off
	339	* - [1] = PLL_OFF : 1=Disable Power to PLL
	340	* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
	341	* all other bits set to zero
	342	*/
	343
	344	p0.h = hi(PLL_LOCKCNT);
	345	p0.l = lo(PLL_LOCKCNT);
	346	r0 = 0x300(Z);
	347	w[p0] = r0.l;
	348	ssync;
	349
	350	P2.H = hi(EBIU_SDGCTL);
	351	P2.L = lo(EBIU_SDGCTL);
	352	R0 = [P2];
	353	BITSET (R0, 24);
	354	[P2] = R0;
	355	SSYNC;
	356
	357	r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
	358	r0 = r0 << 9; /* Shift it over, */
	359	r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
	360	r0 = r1 \| r0;
	361	r1 = PLL_BYPASS; /* Bypass the PLL? */
	362	r1 = r1 << 8; /* Shift it over */
	363	r0 = r1 \| r0; /* add them all together */
	364
	365	p0.h = hi(PLL_CTL);
	366	p0.l = lo(PLL_CTL); /* Load the address */
	367	cli r2; /* Disable interrupts */
	368	ssync;
	369	w[p0] = r0.l; /* Set the value */
	370	idle; /* Wait for the PLL to stablize */
	371	sti r2; /* Enable interrupts */
	372
	373	.Lcheck_again:
	374	p0.h = hi(PLL_STAT);
	375	p0.l = lo(PLL_STAT);
	376	R0 = W[P0](Z);
	377	CC = BITTST(R0,5);
	378	if ! CC jump .Lcheck_again;
	379
	380	/* Configure SCLK & CCLK Dividers */
	381	r0 = (CONFIG_CCLK_ACT_DIV \| CONFIG_SCLK_DIV);
	382	p0.h = hi(PLL_DIV);
	383	p0.l = lo(PLL_DIV);
	384	w[p0] = r0.l;
	385	ssync;
	386
387	p0.l = lo(EBIU_SDRRC);
388	p0.h = hi(EBIU_SDRRC);
389	r0 = mem_SDRRC;
390	w[p0] = r0.l;
391	ssync;
392
1394f032 BW	393	P2.H = hi(EBIU_SDGCTL);
	394	P2.L = lo(EBIU_SDGCTL);
	395	R0 = [P2];
	396	BITCLR (R0, 24);
	397	p0.h = hi(EBIU_SDSTAT);
	398	p0.l = lo(EBIU_SDSTAT);
	399	r2.l = w[p0];
	400	cc = bittst(r2,3);
	401	if !cc jump .Lskip;
	402	NOP;
	403	BITSET (R0, 23);
	404	.Lskip:
	405	[P2] = R0;
	406	SSYNC;
	407
	408	R0.L = lo(mem_SDGCTL);
	409	R0.H = hi(mem_SDGCTL);
	410	R1 = [p2];
	411	R1 = R1 \| R0;
	412	[P2] = R1;
	413	SSYNC;
	414
	415	p0.h = hi(SIC_IWR);
	416	p0.l = lo(SIC_IWR);
83a5c3e3 MF	417	r0.l = lo(IWR_ENABLE_ALL);
83a5c3e3 MF	418	r0.h = hi(IWR_ENABLE_ALL);
1394f032 BW	419	[p0] = r0;
	420	SSYNC;
	421
	422	RTS;
52a07812	423	ENDPROC(_start_dma_code)
1394f032	424	#endif /* CONFIG_BFIN_KERNEL_CLOCK */