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ab472a04 | 1 | /* |
96f1050d RG |
2 | * Copyright 2004-2009 Analog Devices Inc. |
3 | * 2007-2008 HV Sistemas S.L. | |
4 | * Javier Herrero <jherrero@hvsistemas.es> | |
5 | * 2005 National ICT Australia (NICTA) | |
6 | * Aidan Williams <aidan@nicta.com.au> | |
ab472a04 | 7 | * |
96f1050d | 8 | * Licensed under the GPL-2 or later. |
ab472a04 JH |
9 | */ |
10 | ||
11 | #include <linux/device.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/mtd/mtd.h> | |
14 | #include <linux/mtd/partitions.h> | |
15 | #include <linux/spi/spi.h> | |
16 | #include <linux/spi/flash.h> | |
17 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | |
f02bcec5 | 18 | #include <linux/usb/isp1362.h> |
ab472a04 | 19 | #endif |
ab472a04 | 20 | #include <linux/irq.h> |
fb96c56d | 21 | |
ab472a04 JH |
22 | #include <asm/dma.h> |
23 | #include <asm/bfin5xx_spi.h> | |
24 | #include <asm/reboot.h> | |
5d448dd5 | 25 | #include <asm/portmux.h> |
ab472a04 JH |
26 | |
27 | /* | |
28 | * Name the Board for the /proc/cpuinfo | |
29 | */ | |
30 | const char bfin_board_name[] = "HV Sistemas H8606"; | |
31 | ||
09db9487 | 32 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) |
ab472a04 JH |
33 | static struct platform_device rtc_device = { |
34 | .name = "rtc-bfin", | |
35 | .id = -1, | |
36 | }; | |
37 | #endif | |
38 | ||
39 | /* | |
40 | * Driver needs to know address, irq and flag pin. | |
41 | */ | |
42 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) | |
43 | static struct resource dm9000_resources[] = { | |
44 | [0] = { | |
45 | .start = 0x20300000, | |
45138439 | 46 | .end = 0x20300002, |
ab472a04 JH |
47 | .flags = IORESOURCE_MEM, |
48 | }, | |
49 | [1] = { | |
45138439 JH |
50 | .start = 0x20300004, |
51 | .end = 0x20300006, | |
da3854fc LP |
52 | .flags = IORESOURCE_MEM, |
53 | }, | |
54 | [2] = { | |
ab472a04 JH |
55 | .start = IRQ_PF10, |
56 | .end = IRQ_PF10, | |
45138439 | 57 | .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IRQF_SHARED | IRQF_TRIGGER_HIGH), |
ab472a04 JH |
58 | }, |
59 | }; | |
60 | ||
61 | static struct platform_device dm9000_device = { | |
62 | .id = 0, | |
63 | .name = "dm9000", | |
64 | .resource = dm9000_resources, | |
65 | .num_resources = ARRAY_SIZE(dm9000_resources), | |
66 | }; | |
67 | #endif | |
68 | ||
69 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | |
61f09b5a MH |
70 | #include <linux/smc91x.h> |
71 | ||
72 | static struct smc91x_platdata smc91x_info = { | |
73 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | |
74 | .leda = RPC_LED_100_10, | |
75 | .ledb = RPC_LED_TX_RX, | |
76 | }; | |
77 | ||
ab472a04 JH |
78 | static struct resource smc91x_resources[] = { |
79 | { | |
80 | .name = "smc91x-regs", | |
81 | .start = 0x20300300, | |
82 | .end = 0x20300300 + 16, | |
83 | .flags = IORESOURCE_MEM, | |
84 | }, { | |
85 | .start = IRQ_PROG_INTB, | |
86 | .end = IRQ_PROG_INTB, | |
87 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
88 | }, { | |
ab472a04 JH |
89 | .start = IRQ_PF7, |
90 | .end = IRQ_PF7, | |
91 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
92 | }, | |
93 | }; | |
94 | ||
95 | static struct platform_device smc91x_device = { | |
96 | .name = "smc91x", | |
97 | .id = 0, | |
98 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
99 | .resource = smc91x_resources, | |
61f09b5a MH |
100 | .dev = { |
101 | .platform_data = &smc91x_info, | |
102 | }, | |
ab472a04 JH |
103 | }; |
104 | #endif | |
105 | ||
106 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | |
107 | static struct resource net2272_bfin_resources[] = { | |
108 | { | |
109 | .start = 0x20300000, | |
110 | .end = 0x20300000 + 0x100, | |
111 | .flags = IORESOURCE_MEM, | |
112 | }, { | |
113 | .start = IRQ_PF10, | |
114 | .end = IRQ_PF10, | |
115 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
116 | }, | |
117 | }; | |
118 | ||
119 | static struct platform_device net2272_bfin_device = { | |
120 | .name = "net2272", | |
121 | .id = -1, | |
122 | .num_resources = ARRAY_SIZE(net2272_bfin_resources), | |
123 | .resource = net2272_bfin_resources, | |
124 | }; | |
125 | #endif | |
126 | ||
127 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
128 | /* all SPI peripherals info goes here */ | |
129 | ||
130 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) | |
131 | static struct mtd_partition bfin_spi_flash_partitions[] = { | |
132 | { | |
45138439 JH |
133 | .name = "bootloader (spi)", |
134 | .size = 0x40000, | |
ab472a04 JH |
135 | .offset = 0, |
136 | .mask_flags = MTD_CAP_ROM | |
137 | }, { | |
45138439 JH |
138 | .name = "fpga (spi)", |
139 | .size = 0x30000, | |
140 | .offset = 0x40000 | |
ab472a04 | 141 | }, { |
45138439 JH |
142 | .name = "linux kernel (spi)", |
143 | .size = 0x150000, | |
144 | .offset = 0x70000 | |
145 | }, { | |
146 | .name = "jffs2 root file system (spi)", | |
147 | .size = 0x640000, | |
148 | .offset = 0x1c0000, | |
ab472a04 JH |
149 | } |
150 | }; | |
151 | ||
152 | static struct flash_platform_data bfin_spi_flash_data = { | |
153 | .name = "m25p80", | |
154 | .parts = bfin_spi_flash_partitions, | |
155 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | |
156 | .type = "m25p64", | |
157 | }; | |
158 | ||
159 | /* SPI flash chip (m25p64) */ | |
160 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | |
161 | .enable_dma = 0, /* use dma transfer with this chip*/ | |
162 | .bits_per_word = 8, | |
163 | }; | |
164 | #endif | |
165 | ||
a261eec0 | 166 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
ab472a04 JH |
167 | /* SPI ADC chip */ |
168 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | |
ab472a04 JH |
169 | .enable_dma = 1, /* use dma transfer with this chip*/ |
170 | .bits_per_word = 16, | |
171 | }; | |
172 | #endif | |
173 | ||
d40bd71f | 174 | #if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) |
ab472a04 | 175 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { |
ab472a04 JH |
176 | .enable_dma = 0, |
177 | .bits_per_word = 16, | |
178 | }; | |
179 | #endif | |
180 | ||
ab472a04 JH |
181 | /* Notice: for blackfin, the speed_hz is the value of register |
182 | * SPI_BAUD, not the real baudrate */ | |
183 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | |
184 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) | |
185 | { | |
186 | /* the modalias must be the same as spi device driver name */ | |
187 | .modalias = "m25p80", /* Name of spi_driver for this device */ | |
188 | /* this value is the baudrate divisor */ | |
189 | .max_speed_hz = 50000000, /* actual baudrate is SCLK/(2xspeed_hz) */ | |
190 | .bus_num = 0, /* Framework bus number */ | |
191 | .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/ | |
192 | .platform_data = &bfin_spi_flash_data, | |
193 | .controller_data = &spi_flash_chip_info, | |
194 | .mode = SPI_MODE_3, | |
195 | }, | |
196 | #endif | |
197 | ||
a261eec0 | 198 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
ab472a04 JH |
199 | { |
200 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | |
201 | .max_speed_hz = 4, /* actual baudrate is SCLK/(2xspeed_hz) */ | |
202 | .bus_num = 1, /* Framework bus number */ | |
203 | .chip_select = 1, /* Framework chip select. */ | |
204 | .platform_data = NULL, /* No spi_driver specific config */ | |
205 | .controller_data = &spi_adc_chip_info, | |
206 | }, | |
207 | #endif | |
208 | ||
d40bd71f | 209 | #if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) |
ab472a04 | 210 | { |
dac98174 | 211 | .modalias = "ad1836", |
ab472a04 JH |
212 | .max_speed_hz = 16, |
213 | .bus_num = 1, | |
214 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | |
215 | .controller_data = &ad1836_spi_chip_info, | |
216 | }, | |
217 | #endif | |
218 | ||
ab472a04 JH |
219 | }; |
220 | ||
221 | /* SPI (0) */ | |
222 | static struct resource bfin_spi0_resource[] = { | |
223 | [0] = { | |
224 | .start = SPI0_REGBASE, | |
225 | .end = SPI0_REGBASE + 0xFF, | |
226 | .flags = IORESOURCE_MEM, | |
227 | }, | |
228 | [1] = { | |
229 | .start = CH_SPI, | |
230 | .end = CH_SPI, | |
53122693 YL |
231 | .flags = IORESOURCE_DMA, |
232 | }, | |
233 | [2] = { | |
234 | .start = IRQ_SPI, | |
235 | .end = IRQ_SPI, | |
ab472a04 JH |
236 | .flags = IORESOURCE_IRQ, |
237 | } | |
238 | }; | |
239 | ||
240 | ||
241 | /* SPI controller data */ | |
242 | static struct bfin5xx_spi_master bfin_spi0_info = { | |
243 | .num_chipselect = 8, | |
244 | .enable_dma = 1, /* master has the ability to do dma transfer */ | |
5d448dd5 | 245 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, |
ab472a04 JH |
246 | }; |
247 | ||
248 | static struct platform_device bfin_spi0_device = { | |
249 | .name = "bfin-spi", | |
250 | .id = 0, /* Bus number */ | |
251 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | |
252 | .resource = bfin_spi0_resource, | |
253 | .dev = { | |
254 | .platform_data = &bfin_spi0_info, /* Passed to driver */ | |
255 | }, | |
256 | }; | |
257 | #endif /* spi master and devices */ | |
258 | ||
ab472a04 | 259 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) |
6bd1fbea SZ |
260 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
261 | static struct resource bfin_uart0_resources[] = { | |
ab472a04 | 262 | { |
6bd1fbea SZ |
263 | .start = BFIN_UART_THR, |
264 | .end = BFIN_UART_GCTL+2, | |
ab472a04 JH |
265 | .flags = IORESOURCE_MEM, |
266 | }, | |
6bd1fbea SZ |
267 | { |
268 | .start = IRQ_UART0_RX, | |
269 | .end = IRQ_UART0_RX + 1, | |
270 | .flags = IORESOURCE_IRQ, | |
271 | }, | |
272 | { | |
273 | .start = IRQ_UART0_ERROR, | |
274 | .end = IRQ_UART0_ERROR, | |
275 | .flags = IORESOURCE_IRQ, | |
276 | }, | |
277 | { | |
278 | .start = CH_UART0_TX, | |
279 | .end = CH_UART0_TX, | |
280 | .flags = IORESOURCE_DMA, | |
281 | }, | |
282 | { | |
283 | .start = CH_UART0_RX, | |
284 | .end = CH_UART0_RX, | |
285 | .flags = IORESOURCE_DMA, | |
286 | }, | |
287 | }; | |
288 | ||
289 | unsigned short bfin_uart0_peripherals[] = { | |
290 | P_UART0_TX, P_UART0_RX, 0 | |
ab472a04 JH |
291 | }; |
292 | ||
6bd1fbea | 293 | static struct platform_device bfin_uart0_device = { |
ab472a04 | 294 | .name = "bfin-uart", |
6bd1fbea SZ |
295 | .id = 0, |
296 | .num_resources = ARRAY_SIZE(bfin_uart0_resources), | |
297 | .resource = bfin_uart0_resources, | |
298 | .dev = { | |
299 | .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ | |
300 | }, | |
ab472a04 JH |
301 | }; |
302 | #endif | |
6bd1fbea | 303 | #endif |
ab472a04 | 304 | |
5be36d22 | 305 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
5be36d22 | 306 | #ifdef CONFIG_BFIN_SIR0 |
42bd8bcb | 307 | static struct resource bfin_sir0_resources[] = { |
5be36d22 GY |
308 | { |
309 | .start = 0xFFC00400, | |
310 | .end = 0xFFC004FF, | |
311 | .flags = IORESOURCE_MEM, | |
312 | }, | |
42bd8bcb GY |
313 | { |
314 | .start = IRQ_UART0_RX, | |
315 | .end = IRQ_UART0_RX+1, | |
316 | .flags = IORESOURCE_IRQ, | |
317 | }, | |
318 | { | |
319 | .start = CH_UART0_RX, | |
320 | .end = CH_UART0_RX+1, | |
321 | .flags = IORESOURCE_DMA, | |
322 | }, | |
5be36d22 GY |
323 | }; |
324 | ||
42bd8bcb | 325 | static struct platform_device bfin_sir0_device = { |
5be36d22 GY |
326 | .name = "bfin_sir", |
327 | .id = 0, | |
42bd8bcb GY |
328 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), |
329 | .resource = bfin_sir0_resources, | |
5be36d22 GY |
330 | }; |
331 | #endif | |
42bd8bcb | 332 | #endif |
5be36d22 | 333 | |
fb96c56d JH |
334 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) |
335 | ||
336 | #include <linux/serial_8250.h> | |
337 | #include <linux/serial.h> | |
338 | ||
339 | /* | |
340 | * Configuration for two 16550 UARTS in FPGA at addresses 0x20200000 and 0x202000010. | |
341 | * running at half system clock, both with interrupt output or-ed to PF8. Change to | |
342 | * suit different FPGA configuration, or to suit real 16550 UARTS connected to the bus | |
343 | */ | |
344 | ||
345 | static struct plat_serial8250_port serial8250_platform_data [] = { | |
346 | { | |
45138439 | 347 | .membase = (void *)0x20200000, |
fb96c56d JH |
348 | .mapbase = 0x20200000, |
349 | .irq = IRQ_PF8, | |
350 | .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, | |
351 | .iotype = UPIO_MEM, | |
352 | .regshift = 1, | |
353 | .uartclk = 66666667, | |
354 | }, { | |
45138439 | 355 | .membase = (void *)0x20200010, |
fb96c56d JH |
356 | .mapbase = 0x20200010, |
357 | .irq = IRQ_PF8, | |
358 | .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, | |
359 | .iotype = UPIO_MEM, | |
360 | .regshift = 1, | |
361 | .uartclk = 66666667, | |
362 | }, { | |
363 | } | |
364 | }; | |
365 | ||
366 | static struct platform_device serial8250_device = { | |
367 | .id = PLAT8250_DEV_PLATFORM, | |
368 | .name = "serial8250", | |
369 | .dev = { | |
370 | .platform_data = serial8250_platform_data, | |
371 | }, | |
372 | }; | |
373 | ||
374 | #endif | |
375 | ||
7a5f8191 JH |
376 | #if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE) |
377 | ||
378 | /* | |
379 | * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030, | |
380 | * interrupt output wired to PF9. Change to suit different FPGA configuration | |
381 | */ | |
382 | ||
383 | static struct resource opencores_kbd_resources[] = { | |
384 | [0] = { | |
385 | .start = 0x20200030, | |
386 | .end = 0x20300030 + 2, | |
387 | .flags = IORESOURCE_MEM, | |
388 | }, | |
389 | [1] = { | |
390 | .start = IRQ_PF9, | |
391 | .end = IRQ_PF9, | |
392 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | |
393 | }, | |
394 | }; | |
395 | ||
396 | static struct platform_device opencores_kbd_device = { | |
397 | .id = -1, | |
398 | .name = "opencores-kbd", | |
399 | .resource = opencores_kbd_resources, | |
400 | .num_resources = ARRAY_SIZE(opencores_kbd_resources), | |
401 | }; | |
402 | #endif | |
403 | ||
fb96c56d | 404 | static struct platform_device *h8606_devices[] __initdata = { |
ab472a04 JH |
405 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) |
406 | &rtc_device, | |
407 | #endif | |
408 | ||
409 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) | |
410 | &dm9000_device, | |
411 | #endif | |
412 | ||
413 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | |
414 | &smc91x_device, | |
415 | #endif | |
416 | ||
417 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | |
418 | &net2272_bfin_device, | |
419 | #endif | |
420 | ||
421 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
422 | &bfin_spi0_device, | |
423 | #endif | |
424 | ||
425 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
6bd1fbea SZ |
426 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
427 | &bfin_uart0_device, | |
428 | #endif | |
ab472a04 | 429 | #endif |
fb96c56d JH |
430 | |
431 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) | |
432 | &serial8250_device, | |
433 | #endif | |
7a5f8191 | 434 | |
5be36d22 | 435 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
42bd8bcb GY |
436 | #ifdef CONFIG_BFIN_SIR0 |
437 | &bfin_sir0_device, | |
438 | #endif | |
5be36d22 GY |
439 | #endif |
440 | ||
7a5f8191 JH |
441 | #if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE) |
442 | &opencores_kbd_device, | |
443 | #endif | |
ab472a04 JH |
444 | }; |
445 | ||
446 | static int __init H8606_init(void) | |
447 | { | |
448 | printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n"); | |
b85d858b | 449 | printk(KERN_INFO "%s(): registering device resources\n", __func__); |
fb96c56d | 450 | platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices)); |
ab472a04 JH |
451 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
452 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | |
453 | #endif | |
454 | return 0; | |
455 | } | |
456 | ||
0feea17f | 457 | arch_initcall(H8606_init); |
c13ce9fd SZ |
458 | |
459 | static struct platform_device *H8606_early_devices[] __initdata = { | |
460 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) | |
461 | #ifdef CONFIG_SERIAL_BFIN_UART0 | |
462 | &bfin_uart0_device, | |
463 | #endif | |
464 | #endif | |
465 | }; | |
466 | ||
467 | void __init native_machine_early_platform_add_devices(void) | |
468 | { | |
469 | printk(KERN_INFO "register early platform devices\n"); | |
470 | early_platform_add_devices(H8606_early_devices, | |
471 | ARRAY_SIZE(H8606_early_devices)); | |
472 | } |