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96f1050d RG |
1 | /* |
2 | * Copyright 2004-2009 Analog Devices Inc. | |
3 | * | |
4 | * Licensed under the GPL-2 or later. | |
5 | */ | |
6 | ||
1394f032 BW |
7 | #ifndef _BLACKFIN_PGTABLE_H |
8 | #define _BLACKFIN_PGTABLE_H | |
9 | ||
10 | #include <asm-generic/4level-fixup.h> | |
11 | ||
12 | #include <asm/page.h> | |
639f6571 | 13 | #include <asm/def_LPBlackfin.h> |
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14 | |
15 | typedef pte_t *pte_addr_t; | |
16 | /* | |
17 | * Trivial page table functions. | |
18 | */ | |
19 | #define pgd_present(pgd) (1) | |
20 | #define pgd_none(pgd) (0) | |
21 | #define pgd_bad(pgd) (0) | |
22 | #define pgd_clear(pgdp) | |
23 | #define kern_addr_valid(addr) (1) | |
24 | ||
25 | #define pmd_offset(a, b) ((void *)0) | |
26 | #define pmd_none(x) (!pmd_val(x)) | |
27 | #define pmd_present(x) (pmd_val(x)) | |
28 | #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0) | |
29 | #define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK) | |
30 | ||
31 | #define kern_addr_valid(addr) (1) | |
32 | ||
33 | #define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */ | |
34 | #define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */ | |
35 | #define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */ | |
36 | #define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */ | |
37 | #define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */ | |
2377feb4 | 38 | #define pgprot_noncached(prot) (prot) |
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39 | |
40 | extern void paging_init(void); | |
41 | ||
42 | #define __swp_type(x) (0) | |
43 | #define __swp_offset(x) (0) | |
44 | #define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) }) | |
45 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
46 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
47 | ||
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48 | #define set_pte(pteptr, pteval) (*(pteptr) = pteval) |
49 | #define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) | |
50 | ||
51 | /* | |
52 | * Page assess control based on Blackfin CPLB management | |
53 | */ | |
54 | #define _PAGE_RD (CPLB_USER_RD) | |
55 | #define _PAGE_WR (CPLB_USER_WR) | |
56 | #define _PAGE_USER (CPLB_USER_RD | CPLB_USER_WR) | |
57 | #define _PAGE_ACCESSED CPLB_ALL_ACCESS | |
58 | #define _PAGE_DIRTY (CPLB_DIRTY) | |
59 | ||
60 | #define PTE_BIT_FUNC(fn, op) \ | |
61 | static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; } | |
62 | ||
63 | PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD); | |
64 | PTE_BIT_FUNC(mkread, |= _PAGE_RD); | |
65 | PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR); | |
66 | PTE_BIT_FUNC(mkwrite, |= _PAGE_WR); | |
67 | PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER); | |
68 | PTE_BIT_FUNC(mkexec, |= _PAGE_USER); | |
69 | PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY); | |
70 | PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY); | |
71 | PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED); | |
72 | PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED); | |
73 | ||
74 | /* | |
75 | * ZERO_PAGE is a global shared page that is always zero: used | |
76 | * for zero-mapped memory areas etc.. | |
77 | */ | |
f074e48e MF |
78 | #define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page) |
79 | extern char empty_zero_page[]; | |
1394f032 | 80 | |
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81 | #define swapper_pg_dir ((pgd_t *) 0) |
82 | /* | |
83 | * No page table caches to initialise. | |
84 | */ | |
85 | #define pgtable_cache_init() do { } while (0) | |
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86 | |
87 | /* | |
88 | * All 32bit addresses are effectively valid for vmalloc... | |
89 | * Sort of meaningless for non-VM targets. | |
90 | */ | |
91 | #define VMALLOC_START 0 | |
92 | #define VMALLOC_END 0xffffffff | |
93 | ||
59bd00c8 TC |
94 | /* provide a special get_unmapped_area for framebuffer mmaps of nommu */ |
95 | extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, | |
96 | unsigned long, unsigned long, | |
97 | unsigned long); | |
98 | #define HAVE_ARCH_FB_UNMAPPED_AREA | |
99 | ||
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100 | #include <asm-generic/pgtable.h> |
101 | ||
102 | #endif /* _BLACKFIN_PGTABLE_H */ |