[linux-2.6-block.git] / arch / blackfin / include / asm / kgdb.h

/* Blackfin KGDB header
 *
 * Copyright 2005-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef __ASM_BLACKFIN_KGDB_H__
#define __ASM_BLACKFIN_KGDB_H__

#include <linux/ptrace.h>

/*
 * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
 * At least NUMREGBYTES*2 are needed for register packets.
 * Longer buffer is needed to list all threads.
 */
#define BUFMAX 2048

/*
 * Note that this register image is different from
 * the register image that Linux produces at interrupt time.
 *
 * Linux's register image is defined by struct pt_regs in ptrace.h.
 */
enum regnames {
  /* Core Registers */
  BFIN_R0 = 0,
  BFIN_R1,
  BFIN_R2,
  BFIN_R3,
  BFIN_R4,
  BFIN_R5,
  BFIN_R6,
  BFIN_R7,
  BFIN_P0,
  BFIN_P1,
  BFIN_P2,
  BFIN_P3,
  BFIN_P4,
  BFIN_P5,
  BFIN_SP,
  BFIN_FP,
  BFIN_I0,
  BFIN_I1,
  BFIN_I2,
  BFIN_I3,
  BFIN_M0,
  BFIN_M1,
  BFIN_M2,
  BFIN_M3,
  BFIN_B0,
  BFIN_B1,
  BFIN_B2,
  BFIN_B3,
  BFIN_L0,
  BFIN_L1,
  BFIN_L2,
  BFIN_L3,
  BFIN_A0_DOT_X,
  BFIN_A0_DOT_W,
  BFIN_A1_DOT_X,
  BFIN_A1_DOT_W,
  BFIN_ASTAT,
  BFIN_RETS,
  BFIN_LC0,
  BFIN_LT0,
  BFIN_LB0,
  BFIN_LC1,
  BFIN_LT1,
  BFIN_LB1,
  BFIN_CYCLES,
  BFIN_CYCLES2,
  BFIN_USP,
  BFIN_SEQSTAT,
  BFIN_SYSCFG,
  BFIN_RETI,
  BFIN_RETX,
  BFIN_RETN,
  BFIN_RETE,

  /* Pseudo Registers */
  BFIN_PC,
  BFIN_CC,
  BFIN_EXTRA1,		/* Address of .text section.  */
  BFIN_EXTRA2,		/* Address of .data section.  */
  BFIN_EXTRA3,		/* Address of .bss section.  */
  BFIN_FDPIC_EXEC,
  BFIN_FDPIC_INTERP,

  /* MMRs */
  BFIN_IPEND,

  /* LAST ENTRY SHOULD NOT BE CHANGED.  */
  BFIN_NUM_REGS		/* The number of all registers.  */
};

/* Number of bytes of registers.  */
#define NUMREGBYTES BFIN_NUM_REGS*4

static inline void arch_kgdb_breakpoint(void)
{
	asm("EXCPT 2;");
}
#define BREAK_INSTR_SIZE	2
#ifdef CONFIG_SMP
# define CACHE_FLUSH_IS_SAFE	0
#else
# define CACHE_FLUSH_IS_SAFE	1
#endif
#define GDB_ADJUSTS_BREAK_OFFSET
#define GDB_SKIP_HW_WATCH_TEST
#define HW_INST_WATCHPOINT_NUM	6
#define HW_WATCHPOINT_NUM	8
#define TYPE_INST_WATCHPOINT	0
#define TYPE_DATA_WATCHPOINT	1

/* Instruction watchpoint address control register bits mask */
#define WPPWR		0x1
#define WPIREN01	0x2
#define WPIRINV01	0x4
#define WPIAEN0		0x8
#define WPIAEN1		0x10
#define WPICNTEN0	0x20
#define WPICNTEN1	0x40
#define EMUSW0		0x80
#define EMUSW1		0x100
#define WPIREN23	0x200
#define WPIRINV23	0x400
#define WPIAEN2		0x800
#define WPIAEN3		0x1000
#define WPICNTEN2	0x2000
#define WPICNTEN3	0x4000
#define EMUSW2		0x8000
#define EMUSW3		0x10000
#define WPIREN45	0x20000
#define WPIRINV45	0x40000
#define WPIAEN4		0x80000
#define WPIAEN5		0x100000
#define WPICNTEN4	0x200000
#define WPICNTEN5	0x400000
#define EMUSW4		0x800000
#define EMUSW5		0x1000000
#define WPAND		0x2000000

/* Data watchpoint address control register bits mask */
#define WPDREN01	0x1
#define WPDRINV01	0x2
#define WPDAEN0		0x4
#define WPDAEN1		0x8
#define WPDCNTEN0	0x10
#define WPDCNTEN1	0x20

#define WPDSRC0		0xc0
#define WPDACC0_OFFSET	8
#define WPDSRC1		0xc00
#define WPDACC1_OFFSET	12

/* Watchpoint status register bits mask */
#define STATIA0		0x1
#define STATIA1		0x2
#define STATIA2		0x4
#define STATIA3		0x8
#define STATIA4		0x10
#define STATIA5		0x20
#define STATDA0		0x40
#define STATDA1		0x80

#endif
Commit	Line	Data
d3522648	1	/* Blackfin KGDB header
474f1a66	2	*
d3522648	3	* Copyright 2005-2009 Analog Devices Inc.
474f1a66	4	*
d3522648	5	* Licensed under the GPL-2 or later.
474f1a66 SZ	6	*/
	7
	8	#ifndef __ASM_BLACKFIN_KGDB_H__
	9	#define __ASM_BLACKFIN_KGDB_H__
	10
	11	#include <linux/ptrace.h>
	12
d3522648 MF	13	/*
	14	* BUFMAX defines the maximum number of characters in inbound/outbound buffers.
	15	* At least NUMREGBYTES*2 are needed for register packets.
	16	* Longer buffer is needed to list all threads.
	17	*/
474f1a66 SZ	18	#define BUFMAX 2048
	19
	20	/*
d3522648 MF	21	* Note that this register image is different from
	22	* the register image that Linux produces at interrupt time.
	23	*
	24	* Linux's register image is defined by struct pt_regs in ptrace.h.
474f1a66 SZ	25	*/
	26	enum regnames {
	27	/* Core Registers */
	28	BFIN_R0 = 0,
	29	BFIN_R1,
	30	BFIN_R2,
	31	BFIN_R3,
	32	BFIN_R4,
	33	BFIN_R5,
	34	BFIN_R6,
	35	BFIN_R7,
	36	BFIN_P0,
	37	BFIN_P1,
	38	BFIN_P2,
	39	BFIN_P3,
	40	BFIN_P4,
	41	BFIN_P5,
	42	BFIN_SP,
	43	BFIN_FP,
	44	BFIN_I0,
	45	BFIN_I1,
	46	BFIN_I2,
	47	BFIN_I3,
	48	BFIN_M0,
	49	BFIN_M1,
	50	BFIN_M2,
	51	BFIN_M3,
	52	BFIN_B0,
	53	BFIN_B1,
	54	BFIN_B2,
	55	BFIN_B3,
	56	BFIN_L0,
	57	BFIN_L1,
	58	BFIN_L2,
	59	BFIN_L3,
	60	BFIN_A0_DOT_X,
	61	BFIN_A0_DOT_W,
	62	BFIN_A1_DOT_X,
	63	BFIN_A1_DOT_W,
	64	BFIN_ASTAT,
	65	BFIN_RETS,
	66	BFIN_LC0,
	67	BFIN_LT0,
	68	BFIN_LB0,
	69	BFIN_LC1,
	70	BFIN_LT1,
	71	BFIN_LB1,
	72	BFIN_CYCLES,
	73	BFIN_CYCLES2,
	74	BFIN_USP,
	75	BFIN_SEQSTAT,
	76	BFIN_SYSCFG,
	77	BFIN_RETI,
	78	BFIN_RETX,
	79	BFIN_RETN,
	80	BFIN_RETE,
d3522648	81
474f1a66 SZ	82	/* Pseudo Registers */
	83	BFIN_PC,
	84	BFIN_CC,
	85	BFIN_EXTRA1, /* Address of .text section. */
	86	BFIN_EXTRA2, /* Address of .data section. */
	87	BFIN_EXTRA3, /* Address of .bss section. */
d3522648	88	BFIN_FDPIC_EXEC,
474f1a66 SZ	89	BFIN_FDPIC_INTERP,
	90
	91	/* MMRs */
	92	BFIN_IPEND,
	93
	94	/* LAST ENTRY SHOULD NOT BE CHANGED. */
	95	BFIN_NUM_REGS /* The number of all registers. */
	96	};
	97
	98	/* Number of bytes of registers. */
	99	#define NUMREGBYTES BFIN_NUM_REGS*4
	100
a5ac0129 SZ	101	static inline void arch_kgdb_breakpoint(void)
a5ac0129 SZ	102	{
d3522648	103	asm("EXCPT 2;");
a5ac0129 SZ	104	}
a5ac0129 SZ	105	#define BREAK_INSTR_SIZE 2
c505217c SZ	106	#ifdef CONFIG_SMP
	107	# define CACHE_FLUSH_IS_SAFE 0
	108	#else
	109	# define CACHE_FLUSH_IS_SAFE 1
	110	#endif
63ab25eb	111	#define GDB_ADJUSTS_BREAK_OFFSET
a5b44eeb	112	#define GDB_SKIP_HW_WATCH_TEST
a5ac0129 SZ	113	#define HW_INST_WATCHPOINT_NUM 6
	114	#define HW_WATCHPOINT_NUM 8
	115	#define TYPE_INST_WATCHPOINT 0
	116	#define TYPE_DATA_WATCHPOINT 1
474f1a66 SZ	117
	118	/* Instruction watchpoint address control register bits mask */
	119	#define WPPWR 0x1
	120	#define WPIREN01 0x2
	121	#define WPIRINV01 0x4
	122	#define WPIAEN0 0x8
	123	#define WPIAEN1 0x10
	124	#define WPICNTEN0 0x20
	125	#define WPICNTEN1 0x40
	126	#define EMUSW0 0x80
	127	#define EMUSW1 0x100
	128	#define WPIREN23 0x200
	129	#define WPIRINV23 0x400
	130	#define WPIAEN2 0x800
	131	#define WPIAEN3 0x1000
	132	#define WPICNTEN2 0x2000
	133	#define WPICNTEN3 0x4000
	134	#define EMUSW2 0x8000
	135	#define EMUSW3 0x10000
	136	#define WPIREN45 0x20000
	137	#define WPIRINV45 0x40000
	138	#define WPIAEN4 0x80000
	139	#define WPIAEN5 0x100000
	140	#define WPICNTEN4 0x200000
	141	#define WPICNTEN5 0x400000
	142	#define EMUSW4 0x800000
	143	#define EMUSW5 0x1000000
	144	#define WPAND 0x2000000
	145
	146	/* Data watchpoint address control register bits mask */
	147	#define WPDREN01 0x1
	148	#define WPDRINV01 0x2
	149	#define WPDAEN0 0x4
	150	#define WPDAEN1 0x8
	151	#define WPDCNTEN0 0x10
	152	#define WPDCNTEN1 0x20
a5ac0129	153
474f1a66	154	#define WPDSRC0 0xc0
a5ac0129	155	#define WPDACC0_OFFSET 8
474f1a66	156	#define WPDSRC1 0xc00
a5ac0129	157	#define WPDACC1_OFFSET 12
474f1a66 SZ	158
	159	/* Watchpoint status register bits mask */
	160	#define STATIA0 0x1
	161	#define STATIA1 0x2
	162	#define STATIA2 0x4
	163	#define STATIA3 0x8
	164	#define STATIA4 0x10
	165	#define STATIA5 0x20
	166	#define STATDA0 0x40
	167	#define STATDA1 0x80
	168
474f1a66	169	#endif