[linux-2.6-block.git] / arch / blackfin / include / asm / dma.h

/*
 * dma.h - Blackfin DMA defines/structures/etc...
 *
 * Copyright 2004-2008 Analog Devices Inc.
 * Licensed under the GPL-2 or later.
 */

#ifndef _BLACKFIN_DMA_H_
#define _BLACKFIN_DMA_H_

#include <linux/interrupt.h>
#include <mach/dma.h>
#include <linux/atomic.h>
#include <asm/blackfin.h>
#include <asm/page.h>
#include <asm-generic/dma.h>
#include <asm/bfin_dma.h>

/*-------------------------
 * config reg bits value
 *-------------------------*/
#define DATA_SIZE_8			0
#define DATA_SIZE_16		1
#define DATA_SIZE_32		2
#ifdef CONFIG_BF60x
#define DATA_SIZE_64		3
#endif

#define DMA_FLOW_STOP		0
#define DMA_FLOW_AUTO		1
#ifdef CONFIG_BF60x
#define DMA_FLOW_LIST		4
#define DMA_FLOW_ARRAY		5
#define DMA_FLOW_LIST_DEMAND	6
#define DMA_FLOW_ARRAY_DEMAND	7
#else
#define DMA_FLOW_ARRAY		4
#define DMA_FLOW_SMALL		6
#define DMA_FLOW_LARGE		7
#endif

#define DIMENSION_LINEAR	0
#define DIMENSION_2D		1

#define DIR_READ			0
#define DIR_WRITE			1

#define INTR_DISABLE		0
#ifdef CONFIG_BF60x
#define INTR_ON_PERI			1
#endif
#define INTR_ON_BUF			2
#define INTR_ON_ROW			3

#define DMA_NOSYNC_KEEP_DMA_BUF	0
#define DMA_SYNC_RESTART		1

#ifdef DMA_MMR_SIZE_32
#define DMA_MMR_SIZE_TYPE long
#define DMA_MMR_READ bfin_read32
#define DMA_MMR_WRITE bfin_write32
#else
#define DMA_MMR_SIZE_TYPE short
#define DMA_MMR_READ bfin_read16
#define DMA_MMR_WRITE bfin_write16
#endif

struct dma_desc_array {
	unsigned long start_addr;
	unsigned DMA_MMR_SIZE_TYPE cfg;
	unsigned DMA_MMR_SIZE_TYPE x_count;
	DMA_MMR_SIZE_TYPE x_modify;
} __attribute__((packed));

struct dmasg {
	void *next_desc_addr;
	unsigned long start_addr;
	unsigned DMA_MMR_SIZE_TYPE cfg;
	unsigned DMA_MMR_SIZE_TYPE x_count;
	DMA_MMR_SIZE_TYPE x_modify;
	unsigned DMA_MMR_SIZE_TYPE y_count;
	DMA_MMR_SIZE_TYPE y_modify;
} __attribute__((packed));

struct dma_register {
	void *next_desc_ptr;	/* DMA Next Descriptor Pointer register */
	unsigned long start_addr;	/* DMA Start address  register */
#ifdef CONFIG_BF60x
	unsigned long cfg;	/* DMA Configuration register */

	unsigned long x_count;	/* DMA x_count register */

	long x_modify;	/* DMA x_modify register */

	unsigned long y_count;	/* DMA y_count register */

	long y_modify;	/* DMA y_modify register */

	unsigned long reserved;
	unsigned long reserved2;

	void *curr_desc_ptr;	/* DMA Current Descriptor Pointer
					   register */
	void *prev_desc_ptr;	/* DMA previous initial Descriptor Pointer
					   register */
	unsigned long curr_addr_ptr;	/* DMA Current Address Pointer
						   register */
	unsigned long irq_status;	/* DMA irq status register */

	unsigned long curr_x_count;	/* DMA Current x-count register */

	unsigned long curr_y_count;	/* DMA Current y-count register */

	unsigned long reserved3;

	unsigned long bw_limit_count;	/* DMA band width limit count register */
	unsigned long curr_bw_limit_count;	/* DMA Current band width limit
							count register */
	unsigned long bw_monitor_count;	/* DMA band width limit count register */
	unsigned long curr_bw_monitor_count;	/* DMA Current band width limit
							count register */
#else
	unsigned short cfg;	/* DMA Configuration register */
	unsigned short dummy1;	/* DMA Configuration register */

	unsigned long reserved;

	unsigned short x_count;	/* DMA x_count register */
	unsigned short dummy2;

	short x_modify;	/* DMA x_modify register */
	unsigned short dummy3;

	unsigned short y_count;	/* DMA y_count register */
	unsigned short dummy4;

	short y_modify;	/* DMA y_modify register */
	unsigned short dummy5;

	void *curr_desc_ptr;	/* DMA Current Descriptor Pointer
					   register */
	unsigned long curr_addr_ptr;	/* DMA Current Address Pointer
						   register */
	unsigned short irq_status;	/* DMA irq status register */
	unsigned short dummy6;

	unsigned short peripheral_map;	/* DMA peripheral map register */
	unsigned short dummy7;

	unsigned short curr_x_count;	/* DMA Current x-count register */
	unsigned short dummy8;

	unsigned long reserved2;

	unsigned short curr_y_count;	/* DMA Current y-count register */
	unsigned short dummy9;

	unsigned long reserved3;
#endif

};

struct dma_channel {
	const char *device_id;
	atomic_t chan_status;
	volatile struct dma_register *regs;
	struct dmasg *sg;		/* large mode descriptor */
	unsigned int irq;
	void *data;
#ifdef CONFIG_PM
	unsigned short saved_peripheral_map;
#endif
};

#ifdef CONFIG_PM
int blackfin_dma_suspend(void);
void blackfin_dma_resume(void);
#endif

/*******************************************************************************
*	DMA API's
*******************************************************************************/
extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
extern int channel2irq(unsigned int channel);

static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
{
	dma_ch[channel].regs->start_addr = addr;
}
static inline void set_dma_next_desc_addr(unsigned int channel, void *addr)
{
	dma_ch[channel].regs->next_desc_ptr = addr;
}
static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
{
	dma_ch[channel].regs->curr_desc_ptr = addr;
}
static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count)
{
	dma_ch[channel].regs->x_count = x_count;
}
static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count)
{
	dma_ch[channel].regs->y_count = y_count;
}
static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify)
{
	dma_ch[channel].regs->x_modify = x_modify;
}
static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify)
{
	dma_ch[channel].regs->y_modify = y_modify;
}
static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config)
{
	dma_ch[channel].regs->cfg = config;
}
static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
{
	dma_ch[channel].regs->curr_addr_ptr = addr;
}

#ifdef CONFIG_BF60x
static inline unsigned long
set_bfin_dma_config2(char direction, char flow_mode, char intr_mode,
		     char dma_mode, char mem_width, char syncmode, char peri_width)
{
	unsigned long config = 0;

	switch (intr_mode) {
	case INTR_ON_BUF:
		if (dma_mode == DIMENSION_2D)
			config = DI_EN_Y;
		else
			config = DI_EN_X;
		break;
	case INTR_ON_ROW:
		config = DI_EN_X;
		break;
	case INTR_ON_PERI:
		config = DI_EN_P;
		break;
	};

	return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) |
		(flow_mode << 12) | (syncmode << 2) | (peri_width << 4);
}
#endif

static inline unsigned DMA_MMR_SIZE_TYPE
set_bfin_dma_config(char direction, char flow_mode,
		    char intr_mode, char dma_mode, char mem_width, char syncmode)
{
#ifdef CONFIG_BF60x
	return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode,
		mem_width, syncmode, mem_width);
#else
	return (direction << 1) | (mem_width << 2) | (dma_mode << 4) |
		(intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
#endif
}

static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel)
{
	return dma_ch[channel].regs->irq_status;
}
static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel)
{
	return dma_ch[channel].regs->curr_x_count;
}
static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel)
{
	return dma_ch[channel].regs->curr_y_count;
}
static inline void *get_dma_next_desc_ptr(unsigned int channel)
{
	return dma_ch[channel].regs->next_desc_ptr;
}
static inline void *get_dma_curr_desc_ptr(unsigned int channel)
{
	return dma_ch[channel].regs->curr_desc_ptr;
}
static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel)
{
	return dma_ch[channel].regs->cfg;
}
static inline unsigned long get_dma_curr_addr(unsigned int channel)
{
	return dma_ch[channel].regs->curr_addr_ptr;
}

static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
{
	/* Make sure the internal data buffers in the core are drained
	 * so that the DMA descriptors are completely written when the
	 * DMA engine goes to fetch them below.
	 */
	SSYNC();

	dma_ch[channel].regs->next_desc_ptr = sg;
	dma_ch[channel].regs->cfg =
		(dma_ch[channel].regs->cfg & ~NDSIZE) |
		((ndsize << NDSIZE_OFFSET) & NDSIZE);
}

static inline int dma_channel_active(unsigned int channel)
{
	return atomic_read(&dma_ch[channel].chan_status);
}

static inline void disable_dma(unsigned int channel)
{
	dma_ch[channel].regs->cfg &= ~DMAEN;
	SSYNC();
}
static inline void enable_dma(unsigned int channel)
{
	dma_ch[channel].regs->curr_x_count = 0;
	dma_ch[channel].regs->curr_y_count = 0;
	dma_ch[channel].regs->cfg |= DMAEN;
}
int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);

static inline void dma_disable_irq(unsigned int channel)
{
	disable_irq(dma_ch[channel].irq);
}
static inline void dma_disable_irq_nosync(unsigned int channel)
{
	disable_irq_nosync(dma_ch[channel].irq);
}
static inline void dma_enable_irq(unsigned int channel)
{
	enable_irq(dma_ch[channel].irq);
}
static inline void clear_dma_irqstat(unsigned int channel)
{
	dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ;
}

void *dma_memcpy(void *dest, const void *src, size_t count);
void *dma_memcpy_nocache(void *dest, const void *src, size_t count);
void *safe_dma_memcpy(void *dest, const void *src, size_t count);
void blackfin_dma_early_init(void);
void early_dma_memcpy(void *dest, const void *src, size_t count);
void early_dma_memcpy_done(void);

#endif
Commit	Line	Data
1394f032	1	/*
b03f2039	2	* dma.h - Blackfin DMA defines/structures/etc...
1394f032	3	*
b03f2039 MF	4	* Copyright 2004-2008 Analog Devices Inc.
b03f2039 MF	5	* Licensed under the GPL-2 or later.
1394f032 BW	6	*/
	7
	8	#ifndef _BLACKFIN_DMA_H_
	9	#define _BLACKFIN_DMA_H_
	10
1394f032	11	#include <linux/interrupt.h>
4c1ed6a5	12	#include <mach/dma.h>
60063497	13	#include <linux/atomic.h>
1394f032	14	#include <asm/blackfin.h>
4c1ed6a5	15	#include <asm/page.h>
dd3b0e3e	16	#include <asm-generic/dma.h>
6c8e75a0	17	#include <asm/bfin_dma.h>
1394f032 BW	18
	19	/*-------------------------
	20	* config reg bits value
	21	-------------------------/
00d24604 MF	22	#define DATA_SIZE_8 0
	23	#define DATA_SIZE_16 1
	24	#define DATA_SIZE_32 2
b5affb01 BL	25	#ifdef CONFIG_BF60x
	26	#define DATA_SIZE_64 3
	27	#endif
1394f032	28
00d24604 MF	29	#define DMA_FLOW_STOP 0
00d24604 MF	30	#define DMA_FLOW_AUTO 1
b5affb01 BL	31	#ifdef CONFIG_BF60x
	32	#define DMA_FLOW_LIST 4
	33	#define DMA_FLOW_ARRAY 5
	34	#define DMA_FLOW_LIST_DEMAND 6
	35	#define DMA_FLOW_ARRAY_DEMAND 7
	36	#else
00d24604 MF	37	#define DMA_FLOW_ARRAY 4
	38	#define DMA_FLOW_SMALL 6
	39	#define DMA_FLOW_LARGE 7
b5affb01	40	#endif
1394f032	41
00d24604 MF	42	#define DIMENSION_LINEAR 0
00d24604 MF	43	#define DIMENSION_2D 1
1394f032	44
00d24604 MF	45	#define DIR_READ 0
00d24604 MF	46	#define DIR_WRITE 1
1394f032	47
00d24604	48	#define INTR_DISABLE 0
b5affb01 BL	49	#ifdef CONFIG_BF60x
	50	#define INTR_ON_PERI 1
	51	#endif
00d24604 MF	52	#define INTR_ON_BUF 2
00d24604 MF	53	#define INTR_ON_ROW 3
1394f032	54
2047e40d	55	#define DMA_NOSYNC_KEEP_DMA_BUF 0
00d24604	56	#define DMA_SYNC_RESTART 1
2047e40d	57
b5affb01 BL	58	#ifdef DMA_MMR_SIZE_32
	59	#define DMA_MMR_SIZE_TYPE long
	60	#define DMA_MMR_READ bfin_read32
	61	#define DMA_MMR_WRITE bfin_write32
	62	#else
	63	#define DMA_MMR_SIZE_TYPE short
	64	#define DMA_MMR_READ bfin_read16
	65	#define DMA_MMR_WRITE bfin_write16
	66	#endif
	67
	68	struct dma_desc_array {
	69	unsigned long start_addr;
	70	unsigned DMA_MMR_SIZE_TYPE cfg;
	71	unsigned DMA_MMR_SIZE_TYPE x_count;
	72	DMA_MMR_SIZE_TYPE x_modify;
	73	} __attribute__((packed));
	74
1394f032	75	struct dmasg {
6ab729d8	76	void *next_desc_addr;
1394f032	77	unsigned long start_addr;
b5affb01 BL	78	unsigned DMA_MMR_SIZE_TYPE cfg;
	79	unsigned DMA_MMR_SIZE_TYPE x_count;
	80	DMA_MMR_SIZE_TYPE x_modify;
	81	unsigned DMA_MMR_SIZE_TYPE y_count;
	82	DMA_MMR_SIZE_TYPE y_modify;
1394f032 BW	83	} __attribute__((packed));
	84
	85	struct dma_register {
6ab729d8	86	void next_desc_ptr; / DMA Next Descriptor Pointer register */
1394f032	87	unsigned long start_addr; /* DMA Start address register */
b5affb01 BL	88	#ifdef CONFIG_BF60x
b5affb01 BL	89	unsigned long cfg; /* DMA Configuration register */
1394f032	90
b5affb01 BL	91	unsigned long x_count; /* DMA x_count register */
	92
	93	long x_modify; /* DMA x_modify register */
	94
	95	unsigned long y_count; /* DMA y_count register */
	96
	97	long y_modify; /* DMA y_modify register */
	98
	99	unsigned long reserved;
	100	unsigned long reserved2;
	101
	102	void curr_desc_ptr; / DMA Current Descriptor Pointer
	103	register */
	104	void prev_desc_ptr; / DMA previous initial Descriptor Pointer
	105	register */
	106	unsigned long curr_addr_ptr; /* DMA Current Address Pointer
	107	register */
	108	unsigned long irq_status; /* DMA irq status register */
	109
	110	unsigned long curr_x_count; /* DMA Current x-count register */
	111
	112	unsigned long curr_y_count; /* DMA Current y-count register */
	113
	114	unsigned long reserved3;
	115
	116	unsigned long bw_limit_count; /* DMA band width limit count register */
	117	unsigned long curr_bw_limit_count; /* DMA Current band width limit
	118	count register */
	119	unsigned long bw_monitor_count; /* DMA band width limit count register */
	120	unsigned long curr_bw_monitor_count; /* DMA Current band width limit
	121	count register */
	122	#else
1394f032 BW	123	unsigned short cfg; /* DMA Configuration register */
	124	unsigned short dummy1; /* DMA Configuration register */
	125
	126	unsigned long reserved;
	127
	128	unsigned short x_count; /* DMA x_count register */
	129	unsigned short dummy2;
	130
	131	short x_modify; /* DMA x_modify register */
	132	unsigned short dummy3;
	133
	134	unsigned short y_count; /* DMA y_count register */
	135	unsigned short dummy4;
	136
	137	short y_modify; /* DMA y_modify register */
	138	unsigned short dummy5;
	139
6ab729d8	140	void curr_desc_ptr; / DMA Current Descriptor Pointer
1394f032	141	register */
452af71f	142	unsigned long curr_addr_ptr; /* DMA Current Address Pointer
1394f032 BW	143	register */
	144	unsigned short irq_status; /* DMA irq status register */
	145	unsigned short dummy6;
	146
	147	unsigned short peripheral_map; /* DMA peripheral map register */
	148	unsigned short dummy7;
	149
	150	unsigned short curr_x_count; /* DMA Current x-count register */
	151	unsigned short dummy8;
	152
	153	unsigned long reserved2;
	154
	155	unsigned short curr_y_count; /* DMA Current y-count register */
	156	unsigned short dummy9;
	157
	158	unsigned long reserved3;
b5affb01	159	#endif
1394f032 BW	160
	161	};
	162
1394f032	163	struct dma_channel {
99532fd2	164	const char *device_id;
d2e015d6	165	atomic_t chan_status;
4ce18736	166	volatile struct dma_register *regs;
1394f032	167	struct dmasg sg; / large mode descriptor */
a2ba8b19	168	unsigned int irq;
1394f032	169	void *data;
1efc80b5 MH	170	#ifdef CONFIG_PM
	171	unsigned short saved_peripheral_map;
	172	#endif
1394f032 BW	173	};
1394f032 BW	174
1efc80b5 MH	175	#ifdef CONFIG_PM
	176	int blackfin_dma_suspend(void);
	177	void blackfin_dma_resume(void);
	178	#endif
	179
1394f032 BW	180	/*******************************************************************************
	181	* DMA API's
	182	*******************************************************************************/
9c417a43	183	extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
5e3bcf30	184	extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
9c417a43 MF	185	extern int channel2irq(unsigned int channel);
	186
	187	static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
	188	{
	189	dma_ch[channel].regs->start_addr = addr;
	190	}
6ab729d8	191	static inline void set_dma_next_desc_addr(unsigned int channel, void *addr)
9c417a43 MF	192	{
	193	dma_ch[channel].regs->next_desc_ptr = addr;
	194	}
6ab729d8	195	static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
9c417a43 MF	196	{
	197	dma_ch[channel].regs->curr_desc_ptr = addr;
	198	}
b5affb01	199	static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count)
9c417a43 MF	200	{
	201	dma_ch[channel].regs->x_count = x_count;
	202	}
b5affb01	203	static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count)
9c417a43 MF	204	{
	205	dma_ch[channel].regs->y_count = y_count;
	206	}
b5affb01	207	static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify)
9c417a43 MF	208	{
	209	dma_ch[channel].regs->x_modify = x_modify;
	210	}
b5affb01	211	static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify)
9c417a43 MF	212	{
	213	dma_ch[channel].regs->y_modify = y_modify;
	214	}
b5affb01	215	static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config)
9c417a43 MF	216	{
	217	dma_ch[channel].regs->cfg = config;
	218	}
	219	static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
	220	{
	221	dma_ch[channel].regs->curr_addr_ptr = addr;
	222	}
	223
b5affb01 BL	224	#ifdef CONFIG_BF60x
	225	static inline unsigned long
	226	set_bfin_dma_config2(char direction, char flow_mode, char intr_mode,
	227	char dma_mode, char mem_width, char syncmode, char peri_width)
	228	{
	229	unsigned long config = 0;
	230
	231	switch (intr_mode) {
	232	case INTR_ON_BUF:
	233	if (dma_mode == DIMENSION_2D)
	234	config = DI_EN_Y;
	235	else
	236	config = DI_EN_X;
	237	break;
	238	case INTR_ON_ROW:
	239	config = DI_EN_X;
	240	break;
	241	case INTR_ON_PERI:
	242	config = DI_EN_P;
	243	break;
	244	};
	245
	246	return config \| (direction << 1) \| (mem_width << 8) \| (dma_mode << 26) \|
	247	(flow_mode << 12) \| (syncmode << 2) \| (peri_width << 4);
	248	}
	249	#endif
	250
	251	static inline unsigned DMA_MMR_SIZE_TYPE
9c417a43	252	set_bfin_dma_config(char direction, char flow_mode,
b5affb01	253	char intr_mode, char dma_mode, char mem_width, char syncmode)
9c417a43	254	{
b5affb01 BL	255	#ifdef CONFIG_BF60x
	256	return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode,
	257	mem_width, syncmode, mem_width);
	258	#else
	259	return (direction << 1) \| (mem_width << 2) \| (dma_mode << 4) \|
9c417a43	260	(intr_mode << 6) \| (flow_mode << 12) \| (syncmode << 5);
b5affb01	261	#endif
9c417a43 MF	262	}
9c417a43 MF	263
b5affb01	264	static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel)
9c417a43 MF	265	{
	266	return dma_ch[channel].regs->irq_status;
	267	}
b5affb01	268	static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel)
9c417a43 MF	269	{
	270	return dma_ch[channel].regs->curr_x_count;
	271	}
b5affb01	272	static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel)
9c417a43 MF	273	{
	274	return dma_ch[channel].regs->curr_y_count;
	275	}
6ab729d8	276	static inline void *get_dma_next_desc_ptr(unsigned int channel)
9c417a43 MF	277	{
	278	return dma_ch[channel].regs->next_desc_ptr;
	279	}
6ab729d8	280	static inline void *get_dma_curr_desc_ptr(unsigned int channel)
9c417a43 MF	281	{
	282	return dma_ch[channel].regs->curr_desc_ptr;
	283	}
b5affb01	284	static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel)
71f5ca35 MF	285	{
	286	return dma_ch[channel].regs->cfg;
	287	}
9c417a43 MF	288	static inline unsigned long get_dma_curr_addr(unsigned int channel)
	289	{
	290	return dma_ch[channel].regs->curr_addr_ptr;
	291	}
	292
	293	static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
	294	{
ea8538a0 SZ	295	/* Make sure the internal data buffers in the core are drained
	296	* so that the DMA descriptors are completely written when the
	297	* DMA engine goes to fetch them below.
	298	*/
	299	SSYNC();
	300
	301	dma_ch[channel].regs->next_desc_ptr = sg;
d41e8009	302	dma_ch[channel].regs->cfg =
b5affb01 BL	303	(dma_ch[channel].regs->cfg & ~NDSIZE) \|
b5affb01 BL	304	((ndsize << NDSIZE_OFFSET) & NDSIZE);
9c417a43 MF	305	}
	306
	307	static inline int dma_channel_active(unsigned int channel)
	308	{
d2e015d6	309	return atomic_read(&dma_ch[channel].chan_status);
9c417a43 MF	310	}
	311
	312	static inline void disable_dma(unsigned int channel)
	313	{
	314	dma_ch[channel].regs->cfg &= ~DMAEN;
	315	SSYNC();
9c417a43 MF	316	}
	317	static inline void enable_dma(unsigned int channel)
	318	{
ff5ae12d SM	319	dma_ch[channel].regs->curr_x_count = 0;
ff5ae12d SM	320	dma_ch[channel].regs->curr_y_count = 0;
9c417a43	321	dma_ch[channel].regs->cfg \|= DMAEN;
9c417a43	322	}
9c417a43 MF	323	int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
	324
	325	static inline void dma_disable_irq(unsigned int channel)
	326	{
	327	disable_irq(dma_ch[channel].irq);
	328	}
4ab069e5 BS	329	static inline void dma_disable_irq_nosync(unsigned int channel)
	330	{
	331	disable_irq_nosync(dma_ch[channel].irq);
	332	}
9c417a43 MF	333	static inline void dma_enable_irq(unsigned int channel)
	334	{
	335	enable_irq(dma_ch[channel].irq);
	336	}
	337	static inline void clear_dma_irqstat(unsigned int channel)
	338	{
b5affb01	339	dma_ch[channel].regs->irq_status = DMA_DONE \| DMA_ERR \| DMA_PIRQ;
9c417a43 MF	340	}
9c417a43 MF	341
1394f032	342	void dma_memcpy(void dest, const void *src, size_t count);
d1401e1d	343	void dma_memcpy_nocache(void dest, const void *src, size_t count);
1394f032	344	void safe_dma_memcpy(void dest, const void *src, size_t count);
dd3dd384	345	void blackfin_dma_early_init(void);
fecbd736 RG	346	void early_dma_memcpy(void dest, const void src, size_t count);
fecbd736 RG	347	void early_dma_memcpy_done(void);
1394f032 BW	348
1394f032 BW	349	#endif