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96f1050d RG |
1 | /* |
2 | * Blackfin core register bit & address definitions | |
3 | * | |
4 | * Copyright 2005-2008 Analog Devices Inc. | |
5 | * | |
de450838 | 6 | * Licensed under the Clear BSD license or GPL-2 (or later). |
96f1050d | 7 | */ |
1394f032 BW |
8 | |
9 | #ifndef _DEF_LPBLACKFIN_H | |
10 | #define _DEF_LPBLACKFIN_H | |
11 | ||
639f6571 | 12 | #include <mach/anomaly.h> |
1394f032 | 13 | |
1394f032 | 14 | #define MK_BMSK_(x) (1<<x) |
3630ac34 MF |
15 | #define BFIN_DEPOSIT(mask, x) (((x) << __ffs(mask)) & (mask)) |
16 | #define BFIN_EXTRACT(mask, x) (((x) & (mask)) >> __ffs(mask)) | |
1394f032 | 17 | |
1aafd909 | 18 | #ifndef __ASSEMBLY__ |
1394f032 | 19 | |
1aafd909 | 20 | #include <linux/types.h> |
1394f032 | 21 | |
1aafd909 MF |
22 | #if ANOMALY_05000198 |
23 | # define NOP_PAD_ANOMALY_05000198 "nop;" | |
1394f032 | 24 | #else |
1aafd909 | 25 | # define NOP_PAD_ANOMALY_05000198 |
1394f032 BW |
26 | #endif |
27 | ||
69e1d8a6 MF |
28 | #define _bfin_readX(addr, size, asm_size, asm_ext) ({ \ |
29 | u32 __v; \ | |
1aafd909 MF |
30 | __asm__ __volatile__( \ |
31 | NOP_PAD_ANOMALY_05000198 \ | |
69e1d8a6 | 32 | "%0 = " #asm_size "[%1]" #asm_ext ";" \ |
1aafd909 MF |
33 | : "=d" (__v) \ |
34 | : "a" (addr) \ | |
35 | ); \ | |
36 | __v; }) | |
69e1d8a6 | 37 | #define _bfin_writeX(addr, val, size, asm_size) \ |
1aafd909 MF |
38 | __asm__ __volatile__( \ |
39 | NOP_PAD_ANOMALY_05000198 \ | |
69e1d8a6 | 40 | #asm_size "[%0] = %1;" \ |
1aafd909 | 41 | : \ |
69e1d8a6 | 42 | : "a" (addr), "d" ((u##size)(val)) \ |
1aafd909 MF |
43 | : "memory" \ |
44 | ) | |
45 | ||
69e1d8a6 MF |
46 | #define bfin_read8(addr) _bfin_readX(addr, 8, b, (z)) |
47 | #define bfin_read16(addr) _bfin_readX(addr, 16, w, (z)) | |
48 | #define bfin_read32(addr) _bfin_readX(addr, 32, , ) | |
49 | #define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b) | |
50 | #define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w) | |
51 | #define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, ) | |
1aafd909 | 52 | |
f2521ce9 MF |
53 | #define bfin_read(addr) \ |
54 | ({ \ | |
d763c58a MF |
55 | sizeof(*(addr)) == 1 ? bfin_read8(addr) : \ |
56 | sizeof(*(addr)) == 2 ? bfin_read16(addr) : \ | |
57 | sizeof(*(addr)) == 4 ? bfin_read32(addr) : \ | |
58 | ({ BUG(); 0; }); \ | |
f2521ce9 MF |
59 | }) |
60 | #define bfin_write(addr, val) \ | |
b5fc12df | 61 | do { \ |
f2521ce9 MF |
62 | switch (sizeof(*(addr))) { \ |
63 | case 1: bfin_write8(addr, val); break; \ | |
64 | case 2: bfin_write16(addr, val); break; \ | |
65 | case 4: bfin_write32(addr, val); break; \ | |
66 | default: BUG(); \ | |
67 | } \ | |
b5fc12df MF |
68 | } while (0) |
69 | ||
70 | #define bfin_write_or(addr, bits) \ | |
71 | do { \ | |
7a7a430f | 72 | typeof(addr) __addr = (addr); \ |
b5fc12df MF |
73 | bfin_write(__addr, bfin_read(__addr) | (bits)); \ |
74 | } while (0) | |
75 | ||
76 | #define bfin_write_and(addr, bits) \ | |
77 | do { \ | |
7a7a430f | 78 | typeof(addr) __addr = (addr); \ |
b5fc12df MF |
79 | bfin_write(__addr, bfin_read(__addr) & (bits)); \ |
80 | } while (0) | |
f2521ce9 | 81 | |
1aafd909 MF |
82 | #endif /* __ASSEMBLY__ */ |
83 | ||
1394f032 BW |
84 | /************************************************** |
85 | * System Register Bits | |
86 | **************************************************/ | |
87 | ||
88 | /************************************************** | |
89 | * ASTAT register | |
90 | **************************************************/ | |
91 | ||
92 | /* definitions of ASTAT bit positions*/ | |
93 | ||
94 | /*Result of last ALU0 or shifter operation is zero*/ | |
95 | #define ASTAT_AZ_P 0x00000000 | |
96 | /*Result of last ALU0 or shifter operation is negative*/ | |
97 | #define ASTAT_AN_P 0x00000001 | |
98 | /*Condition Code, used for holding comparison results*/ | |
99 | #define ASTAT_CC_P 0x00000005 | |
100 | /*Quotient Bit*/ | |
101 | #define ASTAT_AQ_P 0x00000006 | |
102 | /*Rounding mode, set for biased, clear for unbiased*/ | |
103 | #define ASTAT_RND_MOD_P 0x00000008 | |
104 | /*Result of last ALU0 operation generated a carry*/ | |
105 | #define ASTAT_AC0_P 0x0000000C | |
106 | /*Result of last ALU0 operation generated a carry*/ | |
107 | #define ASTAT_AC0_COPY_P 0x00000002 | |
108 | /*Result of last ALU1 operation generated a carry*/ | |
109 | #define ASTAT_AC1_P 0x0000000D | |
110 | /*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/ | |
111 | #define ASTAT_AV0_P 0x00000010 | |
112 | /*Sticky version of ASTAT_AV0 */ | |
113 | #define ASTAT_AV0S_P 0x00000011 | |
114 | /*Result of last MAC1 operation overflowed, sticky for MAC*/ | |
115 | #define ASTAT_AV1_P 0x00000012 | |
116 | /*Sticky version of ASTAT_AV1 */ | |
117 | #define ASTAT_AV1S_P 0x00000013 | |
118 | /*Result of last ALU0 or MAC0 operation overflowed*/ | |
119 | #define ASTAT_V_P 0x00000018 | |
120 | /*Result of last ALU0 or MAC0 operation overflowed*/ | |
121 | #define ASTAT_V_COPY_P 0x00000003 | |
122 | /*Sticky version of ASTAT_V*/ | |
123 | #define ASTAT_VS_P 0x00000019 | |
124 | ||
125 | /* Masks */ | |
126 | ||
127 | /*Result of last ALU0 or shifter operation is zero*/ | |
128 | #define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) | |
129 | /*Result of last ALU0 or shifter operation is negative*/ | |
130 | #define ASTAT_AN MK_BMSK_(ASTAT_AN_P) | |
131 | /*Result of last ALU0 operation generated a carry*/ | |
132 | #define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) | |
133 | /*Result of last ALU0 operation generated a carry*/ | |
134 | #define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) | |
135 | /*Result of last ALU0 operation generated a carry*/ | |
136 | #define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) | |
137 | /*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/ | |
138 | #define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) | |
139 | /*Result of last MAC1 operation overflowed, sticky for MAC*/ | |
140 | #define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) | |
141 | /*Condition Code, used for holding comparison results*/ | |
142 | #define ASTAT_CC MK_BMSK_(ASTAT_CC_P) | |
143 | /*Quotient Bit*/ | |
144 | #define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) | |
145 | /*Rounding mode, set for biased, clear for unbiased*/ | |
146 | #define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) | |
147 | /*Overflow Bit*/ | |
148 | #define ASTAT_V MK_BMSK_(ASTAT_V_P) | |
149 | /*Overflow Bit*/ | |
150 | #define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) | |
151 | ||
152 | /************************************************** | |
153 | * SEQSTAT register | |
154 | **************************************************/ | |
155 | ||
156 | /* Bit Positions */ | |
157 | #define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */ | |
158 | #define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */ | |
159 | #define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */ | |
160 | #define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */ | |
161 | #define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */ | |
162 | #define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */ | |
163 | #define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, | |
164 | * set by IDLE instruction. | |
165 | */ | |
166 | #define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last | |
167 | * reset was a software reset | |
168 | * (=1) | |
169 | */ | |
170 | #define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */ | |
171 | #define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */ | |
172 | #define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */ | |
173 | #define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */ | |
174 | #define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */ | |
175 | /* Masks */ | |
176 | /* Exception cause */ | |
177 | #define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \ | |
178 | MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \ | |
179 | MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \ | |
180 | MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \ | |
181 | MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \ | |
182 | MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \ | |
183 | 0) | |
184 | ||
185 | /* Indicates whether the last reset was a software reset (=1) */ | |
186 | #define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P)) | |
187 | ||
188 | /* Last hw error cause */ | |
189 | #define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \ | |
190 | MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \ | |
191 | MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \ | |
192 | MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \ | |
193 | MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \ | |
194 | 0) | |
195 | ||
196 | /* Translate bits to something useful */ | |
197 | ||
198 | /* Last hw error cause */ | |
199 | #define SEQSTAT_HWERRCAUSE_SHIFT (14) | |
200 | #define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT) | |
201 | #define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT) | |
202 | #define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT) | |
203 | #define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT) | |
204 | ||
205 | /************************************************** | |
206 | * SYSCFG register | |
207 | **************************************************/ | |
208 | ||
209 | /* Bit Positions */ | |
210 | #define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when | |
211 | * set it forces an exception | |
212 | * for each instruction executed | |
213 | */ | |
214 | #define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */ | |
215 | #define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */ | |
216 | ||
217 | /* Masks */ | |
218 | ||
219 | /* Supervisor single step, when set it forces an exception for each | |
220 | *instruction executed | |
221 | */ | |
222 | #define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P ) | |
223 | /* Enable cycle counter (=1) */ | |
224 | #define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P ) | |
225 | /* Self Nesting Interrupt Enable */ | |
226 | #define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P) | |
227 | /* Backward-compatibility for typos in prior releases */ | |
228 | #define SYSCFG_SSSSTEP SYSCFG_SSSTEP | |
229 | #define SYSCFG_CCCEN SYSCFG_CCEN | |
230 | ||
231 | /**************************************************** | |
232 | * Core MMR Register Map | |
233 | ****************************************************/ | |
234 | ||
235 | /* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */ | |
236 | ||
237 | #define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */ | |
238 | #define DMEM_CONTROL 0xFFE00004 /* Data memory control */ | |
239 | #define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside | |
240 | * Buffer Status | |
241 | */ | |
242 | #define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */ | |
243 | #define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside | |
244 | * Buffer Fault Address | |
245 | */ | |
246 | #define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside | |
247 | * Buffer 0 | |
248 | */ | |
249 | #define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside | |
250 | * Buffer 1 | |
251 | */ | |
252 | #define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside | |
253 | * Buffer 2 | |
254 | */ | |
255 | #define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection | |
256 | * Lookaside Buffer 3 | |
257 | */ | |
258 | #define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection | |
259 | * Lookaside Buffer 4 | |
260 | */ | |
261 | #define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection | |
262 | * Lookaside Buffer 5 | |
263 | */ | |
264 | #define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection | |
265 | * Lookaside Buffer 6 | |
266 | */ | |
267 | #define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection | |
268 | * Lookaside Buffer 7 | |
269 | */ | |
270 | #define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection | |
271 | * Lookaside Buffer 8 | |
272 | */ | |
273 | #define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection | |
274 | * Lookaside Buffer 9 | |
275 | */ | |
276 | #define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection | |
277 | * Lookaside Buffer 10 | |
278 | */ | |
279 | #define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection | |
280 | * Lookaside Buffer 11 | |
281 | */ | |
282 | #define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection | |
283 | * Lookaside Buffer 12 | |
284 | */ | |
285 | #define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection | |
286 | * Lookaside Buffer 13 | |
287 | */ | |
288 | #define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection | |
289 | * Lookaside Buffer 14 | |
290 | */ | |
291 | #define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection | |
292 | * Lookaside Buffer 15 | |
293 | */ | |
294 | #define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ | |
295 | #define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ | |
296 | #define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ | |
297 | #define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ | |
298 | #define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ | |
299 | #define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ | |
300 | #define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ | |
301 | #define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ | |
302 | #define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ | |
303 | #define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ | |
304 | #define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ | |
305 | #define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ | |
306 | #define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ | |
307 | #define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ | |
308 | #define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ | |
309 | #define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ | |
310 | #define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */ | |
311 | ||
312 | #define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ | |
313 | #define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ | |
314 | #define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ | |
315 | ||
316 | /* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */ | |
317 | ||
318 | #define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ | |
319 | #define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */ | |
320 | #define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */ | |
321 | #define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */ | |
322 | #define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */ | |
323 | #define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability | |
324 | * Protection Lookaside Buffer 0 | |
325 | */ | |
326 | #define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability | |
327 | * Protection Lookaside Buffer 1 | |
328 | */ | |
329 | #define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability | |
330 | * Protection Lookaside Buffer 2 | |
331 | */ | |
332 | #define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability | |
333 | * Protection Lookaside Buffer 3 | |
334 | */ | |
335 | #define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability | |
336 | * Protection Lookaside Buffer 4 | |
337 | */ | |
338 | #define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability | |
339 | * Protection Lookaside Buffer 5 | |
340 | */ | |
341 | #define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability | |
342 | * Protection Lookaside Buffer 6 | |
343 | */ | |
344 | #define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability | |
345 | * Protection Lookaside Buffer 7 | |
346 | */ | |
347 | #define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability | |
348 | * Protection Lookaside Buffer 8 | |
349 | */ | |
350 | #define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability | |
351 | * Protection Lookaside Buffer 9 | |
352 | */ | |
353 | #define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability | |
354 | * Protection Lookaside Buffer 10 | |
355 | */ | |
356 | #define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability | |
357 | * Protection Lookaside Buffer 11 | |
358 | */ | |
359 | #define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability | |
360 | * Protection Lookaside Buffer 12 | |
361 | */ | |
362 | #define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability | |
363 | * Protection Lookaside Buffer 13 | |
364 | */ | |
365 | #define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability | |
366 | * Protection Lookaside Buffer 14 | |
367 | */ | |
368 | #define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability | |
369 | * Protection Lookaside Buffer 15 | |
370 | */ | |
371 | #define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ | |
372 | #define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ | |
373 | #define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ | |
374 | #define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ | |
375 | #define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ | |
376 | #define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ | |
377 | #define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ | |
378 | #define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ | |
379 | #define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ | |
380 | #define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ | |
381 | #define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ | |
382 | #define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ | |
383 | #define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ | |
384 | #define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ | |
385 | #define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ | |
386 | #define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ | |
387 | #define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ | |
388 | #define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ | |
389 | #define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ | |
390 | ||
391 | /* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */ | |
392 | ||
393 | #define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ | |
394 | #define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ | |
395 | #define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ | |
396 | #define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ | |
397 | #define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ | |
398 | #define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ | |
399 | #define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ | |
400 | #define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ | |
401 | #define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ | |
402 | #define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ | |
403 | #define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ | |
404 | #define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ | |
405 | #define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ | |
406 | #define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ | |
407 | #define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ | |
408 | #define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ | |
ada09172 | 409 | #define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */ |
1394f032 BW |
410 | #define IMASK 0xFFE02104 /* Interrupt Mask Register */ |
411 | #define IPEND 0xFFE02108 /* Interrupt Pending Register */ | |
412 | #define ILAT 0xFFE0210C /* Interrupt Latch Register */ | |
413 | #define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */ | |
414 | ||
415 | /* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */ | |
416 | ||
417 | #define TCNTL 0xFFE03000 /* Core Timer Control Register */ | |
418 | #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ | |
419 | #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ | |
420 | #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ | |
421 | ||
422 | /* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */ | |
423 | #define DSPID 0xFFE05000 /* DSP Processor ID Register for | |
424 | * MP implementations | |
425 | */ | |
426 | ||
427 | #define DBGSTAT 0xFFE05008 /* Debug Status Register */ | |
428 | ||
429 | /* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */ | |
430 | ||
431 | #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ | |
432 | #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ | |
433 | #define TBUF 0xFFE06100 /* Trace Buffer */ | |
434 | ||
435 | /* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */ | |
436 | ||
437 | /* Watchpoint Instruction Address Control Register */ | |
438 | #define WPIACTL 0xFFE07000 | |
439 | /* Watchpoint Instruction Address Register 0 */ | |
440 | #define WPIA0 0xFFE07040 | |
441 | /* Watchpoint Instruction Address Register 1 */ | |
442 | #define WPIA1 0xFFE07044 | |
443 | /* Watchpoint Instruction Address Register 2 */ | |
444 | #define WPIA2 0xFFE07048 | |
445 | /* Watchpoint Instruction Address Register 3 */ | |
446 | #define WPIA3 0xFFE0704C | |
447 | /* Watchpoint Instruction Address Register 4 */ | |
448 | #define WPIA4 0xFFE07050 | |
449 | /* Watchpoint Instruction Address Register 5 */ | |
450 | #define WPIA5 0xFFE07054 | |
451 | /* Watchpoint Instruction Address Count Register 0 */ | |
452 | #define WPIACNT0 0xFFE07080 | |
453 | /* Watchpoint Instruction Address Count Register 1 */ | |
454 | #define WPIACNT1 0xFFE07084 | |
455 | /* Watchpoint Instruction Address Count Register 2 */ | |
456 | #define WPIACNT2 0xFFE07088 | |
457 | /* Watchpoint Instruction Address Count Register 3 */ | |
458 | #define WPIACNT3 0xFFE0708C | |
459 | /* Watchpoint Instruction Address Count Register 4 */ | |
460 | #define WPIACNT4 0xFFE07090 | |
461 | /* Watchpoint Instruction Address Count Register 5 */ | |
462 | #define WPIACNT5 0xFFE07094 | |
463 | /* Watchpoint Data Address Control Register */ | |
464 | #define WPDACTL 0xFFE07100 | |
465 | /* Watchpoint Data Address Register 0 */ | |
466 | #define WPDA0 0xFFE07140 | |
467 | /* Watchpoint Data Address Register 1 */ | |
468 | #define WPDA1 0xFFE07144 | |
469 | /* Watchpoint Data Address Count Value Register 0 */ | |
470 | #define WPDACNT0 0xFFE07180 | |
471 | /* Watchpoint Data Address Count Value Register 1 */ | |
472 | #define WPDACNT1 0xFFE07184 | |
473 | /* Watchpoint Status Register */ | |
474 | #define WPSTAT 0xFFE07200 | |
475 | ||
476 | /* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */ | |
477 | ||
478 | /* Performance Monitor Control Register */ | |
479 | #define PFCTL 0xFFE08000 | |
480 | /* Performance Monitor Counter Register 0 */ | |
481 | #define PFCNTR0 0xFFE08100 | |
482 | /* Performance Monitor Counter Register 1 */ | |
483 | #define PFCNTR1 0xFFE08104 | |
484 | ||
485 | /**************************************************** | |
486 | * Core MMR Register Bits | |
487 | ****************************************************/ | |
488 | ||
489 | /************************************************** | |
490 | * EVT registers (ILAT, IMASK, and IPEND). | |
491 | **************************************************/ | |
492 | ||
493 | /* Bit Positions */ | |
494 | #define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */ | |
495 | #define EVT_RST_P 0x00000001 /* Reset interrupt bit position */ | |
496 | #define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */ | |
497 | #define EVT_EVX_P 0x00000003 /* Exception bit position */ | |
498 | #define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */ | |
499 | #define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */ | |
500 | #define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */ | |
501 | #define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */ | |
502 | #define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */ | |
503 | #define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */ | |
504 | #define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */ | |
505 | #define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */ | |
506 | #define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */ | |
507 | #define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */ | |
508 | #define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */ | |
509 | #define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */ | |
510 | ||
511 | /* Masks */ | |
512 | #define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */ | |
513 | #define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */ | |
514 | #define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */ | |
515 | #define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */ | |
516 | #define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */ | |
517 | #define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */ | |
518 | #define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */ | |
519 | #define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */ | |
520 | #define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */ | |
521 | #define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */ | |
522 | #define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */ | |
523 | #define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */ | |
524 | #define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */ | |
525 | #define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */ | |
526 | #define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */ | |
527 | #define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */ | |
528 | ||
529 | /************************************************** | |
530 | * DMEM_CONTROL Register | |
531 | **************************************************/ | |
532 | /* Bit Positions */ | |
533 | #define ENDM_P 0x00 /* (doesn't really exist) Enable | |
534 | *Data Memory L1 | |
535 | */ | |
536 | #define DMCTL_ENDM_P ENDM_P /* "" (older define) */ | |
537 | ||
538 | #define ENDCPLB_P 0x01 /* Enable DCPLBS */ | |
539 | #define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */ | |
540 | #define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */ | |
541 | #define DMCTL_DMC0_P DMC0_P /* "" (older define) */ | |
542 | #define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */ | |
543 | #define DMCTL_DMC1_P DMC1_P /* "" (older define) */ | |
544 | #define DCBS_P 0x04 /* L1 Data Cache Bank Select */ | |
545 | #define PORT_PREF0_P 0x12 /* DAG0 Port Preference */ | |
546 | #define PORT_PREF1_P 0x13 /* DAG1 Port Preference */ | |
1b601239 | 547 | #define RDCHK 0x9 /* Enable L1 Parity Check */ |
1394f032 BW |
548 | |
549 | /* Masks */ | |
550 | #define ENDM 0x00000001 /* (doesn't really exist) Enable | |
551 | * Data Memory L1 | |
552 | */ | |
553 | #define ENDCPLB 0x00000002 /* Enable DCPLB */ | |
554 | #define ASRAM_BSRAM 0x00000000 | |
555 | #define ACACHE_BSRAM 0x00000008 | |
556 | #define ACACHE_BCACHE 0x0000000C | |
557 | #define DCBS 0x00000010 /* L1 Data Cache Bank Select */ | |
558 | #define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ | |
559 | #define PORT_PREF1 0x00002000 /* DAG1 Port Preference */ | |
560 | ||
561 | /* IMEM_CONTROL Register */ | |
562 | /* Bit Positions */ | |
563 | #define ENIM_P 0x00 /* Enable L1 Code Memory */ | |
564 | #define IMCTL_ENIM_P 0x00 /* "" (older define) */ | |
565 | #define ENICPLB_P 0x01 /* Enable ICPLB */ | |
566 | #define IMCTL_ENICPLB_P 0x01 /* "" (older define) */ | |
567 | #define IMC_P 0x02 /* Enable */ | |
568 | #define IMCTL_IMC_P 0x02 /* Configure L1 code memory as | |
569 | * cache (0=SRAM) | |
570 | */ | |
571 | #define ILOC0_P 0x03 /* Lock Way 0 */ | |
572 | #define ILOC1_P 0x04 /* Lock Way 1 */ | |
573 | #define ILOC2_P 0x05 /* Lock Way 2 */ | |
574 | #define ILOC3_P 0x06 /* Lock Way 3 */ | |
575 | #define LRUPRIORST_P 0x0D /* Least Recently Used Replacement | |
576 | * Priority | |
577 | */ | |
578 | /* Masks */ | |
579 | #define ENIM 0x00000001 /* Enable L1 Code Memory */ | |
580 | #define ENICPLB 0x00000002 /* Enable ICPLB */ | |
581 | #define IMC 0x00000004 /* Configure L1 code memory as | |
582 | * cache (0=SRAM) | |
583 | */ | |
584 | #define ILOC0 0x00000008 /* Lock Way 0 */ | |
585 | #define ILOC1 0x00000010 /* Lock Way 1 */ | |
586 | #define ILOC2 0x00000020 /* Lock Way 2 */ | |
587 | #define ILOC3 0x00000040 /* Lock Way 3 */ | |
588 | #define LRUPRIORST 0x00002000 /* Least Recently Used Replacement | |
589 | * Priority | |
590 | */ | |
591 | ||
592 | /* TCNTL Masks */ | |
593 | #define TMPWR 0x00000001 /* Timer Low Power Control, | |
594 | * 0=low power mode, 1=active state | |
595 | */ | |
596 | #define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */ | |
597 | #define TAUTORLD 0x00000004 /* Timer auto reload */ | |
598 | #define TINT 0x00000008 /* Timer generated interrupt 0=no | |
599 | * interrupt has been generated, | |
600 | * 1=interrupt has been generated | |
601 | * (sticky) | |
602 | */ | |
603 | ||
604 | /* DCPLB_DATA and ICPLB_DATA Registers */ | |
605 | /* Bit Positions */ | |
606 | #define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ | |
607 | #define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry | |
608 | * locked | |
609 | */ | |
610 | #define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access | |
611 | * allowed (user mode) | |
612 | */ | |
613 | /* Masks */ | |
614 | #define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ | |
615 | #define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry | |
616 | * locked | |
617 | */ | |
618 | #define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access | |
619 | * allowed (user mode) | |
620 | */ | |
3bebca2d | 621 | |
1394f032 BW |
622 | #define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ |
623 | #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ | |
624 | #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ | |
625 | #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ | |
5ae89ee0 | 626 | #ifdef CONFIG_BF60x |
7adede5b BL |
627 | #define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */ |
628 | #define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */ | |
629 | #define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */ | |
630 | #define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */ | |
5ae89ee0 | 631 | #endif |
1394f032 BW |
632 | #define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not |
633 | * mapped to L1 | |
634 | */ | |
635 | #define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high | |
636 | * priority port | |
637 | */ | |
638 | #define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable | |
639 | * in L1 | |
640 | */ | |
641 | /* ICPLB_DATA only */ | |
642 | #define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, | |
643 | * 1=priority for non-replacement | |
644 | */ | |
645 | /* DCPLB_DATA only */ | |
646 | #define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write | |
647 | * access allowed (user mode) | |
648 | */ | |
649 | #define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write | |
650 | * access allowed (supervisor mode) | |
651 | */ | |
652 | #define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ | |
653 | #define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on | |
654 | * write-through writes, | |
655 | * 1= allocate cache lines on | |
656 | * write-through writes. | |
657 | */ | |
658 | #define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ | |
659 | ||
3bebca2d RG |
660 | #define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR |
661 | ||
1394f032 BW |
662 | /* TBUFCTL Masks */ |
663 | #define TBUFPWR 0x0001 | |
664 | #define TBUFEN 0x0002 | |
665 | #define TBUFOVF 0x0004 | |
666 | #define TBUFCMPLP_SINGLE 0x0008 | |
667 | #define TBUFCMPLP_DOUBLE 0x0010 | |
668 | #define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE) | |
669 | ||
670 | /* TBUFSTAT Masks */ | |
671 | #define TBUFCNT 0x001F | |
672 | ||
673 | /* ITEST_COMMAND and DTEST_COMMAND Registers */ | |
674 | /* Masks */ | |
675 | #define TEST_READ 0x00000000 /* Read Access */ | |
676 | #define TEST_WRITE 0x00000002 /* Write Access */ | |
677 | #define TEST_TAG 0x00000000 /* Access TAG */ | |
678 | #define TEST_DATA 0x00000004 /* Access DATA */ | |
679 | #define TEST_DW0 0x00000000 /* Select Double Word 0 */ | |
680 | #define TEST_DW1 0x00000008 /* Select Double Word 1 */ | |
681 | #define TEST_DW2 0x00000010 /* Select Double Word 2 */ | |
682 | #define TEST_DW3 0x00000018 /* Select Double Word 3 */ | |
683 | #define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */ | |
684 | #define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */ | |
685 | #define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */ | |
686 | #define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */ | |
687 | #define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */ | |
688 | #define TEST_WAY0 0x00000000 /* Access Way0 */ | |
689 | #define TEST_WAY1 0x04000000 /* Access Way1 */ | |
690 | /* ITEST_COMMAND only */ | |
691 | #define TEST_WAY2 0x08000000 /* Access Way2 */ | |
692 | #define TEST_WAY3 0x0C000000 /* Access Way3 */ | |
693 | /* DTEST_COMMAND only */ | |
694 | #define TEST_BNKSELA 0x00000000 /* Access SuperBank A */ | |
695 | #define TEST_BNKSELB 0x00800000 /* Access SuperBank B */ | |
696 | ||
697 | #endif /* _DEF_LPBLACKFIN_H */ |