projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 3bebca2d RG |
1 | /* |
| 2 | * File: include/asm-blackfin/cplb.h | |
| 3 | * Based on: include/asm-blackfin/mach-bf537/bf537.h | |
| 4 | * Author: Robin Getz <rgetz@blackfin.uclinux.org> | |
| 1394f032 | 5 | * |
| 3bebca2d RG |
6 | * Created: 2000 |
| 7 | * Description: Common CPLB definitions for CPLB init | |
| 1394f032 | 8 | * |
| 3bebca2d RG |
9 | * Modified: |
| 10 | * Copyright 2004-2007 Analog Devices Inc. | |
| 1394f032 | 11 | * |
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12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 13 | * | |
| 14 | * This program is free software; you can redistribute it and/or modify | |
| 15 | * it under the terms of the GNU General Public License as published by | |
| 16 | * the Free Software Foundation; either version 2 of the License, or | |
| 17 | * (at your option) any later version. | |
| 18 | * | |
| 19 | * This program is distributed in the hope that it will be useful, | |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 22 | * GNU General Public License for more details. | |
| 23 | * | |
| 24 | * You should have received a copy of the GNU General Public License | |
| 25 | * along with this program; if not, see the file COPYING, or write | |
| 26 | * to the Free Software Foundation, Inc., | |
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
| 28 | */ | |
| 1394f032 BW |
29 | |
| 30 | #ifndef _CPLB_H | |
| 31 | #define _CPLB_H | |
| 32 | ||
| 639f6571 | 33 | #include <mach/anomaly.h> |
| 1394f032 | 34 | |
| 3bebca2d RG |
35 | #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) |
| 36 | #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) | |
| 37 | #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) | |
| 38 | #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) | |
| 39 | ||
| 40 | /*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/ | |
| 41 | ||
| 42 | #if ANOMALY_05000158 | |
| 43 | #define ANOMALY_05000158_WORKAROUND 0x200 | |
| 44 | #else | |
| 45 | #define ANOMALY_05000158_WORKAROUND 0x0 | |
| 46 | #endif | |
| 47 | ||
| 48 | #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) | |
| 49 | ||
| 50 | #ifdef CONFIG_BFIN_WB /*Write Back Policy */ | |
| 51 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON) | |
| 52 | #else /*Write Through */ | |
| 53 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) | |
| 54 | #endif | |
| 55 | ||
| 56 | #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) | |
| b8a98989 GY |
57 | |
| 58 | #ifdef CONFIG_SMP | |
| 59 | #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) | |
| 60 | #define L2_IMEMORY (CPLB_COMMON | CPLB_LOCK) | |
| 61 | #define L2_DMEMORY (CPLB_COMMON | CPLB_LOCK) | |
| 62 | ||
| 63 | #else | |
| f099f39a SZ |
64 | #ifdef CONFIG_BFIN_L2_CACHEABLE |
| 65 | #define L2_IMEMORY (SDRAM_IGENERIC) | |
| 66 | #define L2_DMEMORY (SDRAM_DGENERIC) | |
| 67 | #else | |
| 68 | #define L2_IMEMORY (CPLB_COMMON) | |
| 69 | #define L2_DMEMORY (CPLB_COMMON) | |
| b8a98989 GY |
70 | #endif /* CONFIG_BFIN_L2_CACHEABLE */ |
| 71 | ||
| 72 | #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) | |
| 73 | #endif /* CONFIG_SMP */ | |
| 74 | ||
| 3bebca2d RG |
75 | #define SDRAM_DNON_CHBL (CPLB_COMMON) |
| 76 | #define SDRAM_EBIU (CPLB_COMMON) | |
| 77 | #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) | |
| 78 | ||
| 79 | #define SIZE_1K 0x00000400 /* 1K */ | |
| 80 | #define SIZE_4K 0x00001000 /* 4K */ | |
| 81 | #define SIZE_1M 0x00100000 /* 1M */ | |
| 82 | #define SIZE_4M 0x00400000 /* 4M */ | |
| 83 | ||
| b97b8a99 | 84 | #define MAX_CPLBS 16 |
| 07bdda02 | 85 | |
| 1394f032 BW |
86 | #define CPLB_ENABLE_ICACHE_P 0 |
| 87 | #define CPLB_ENABLE_DCACHE_P 1 | |
| 88 | #define CPLB_ENABLE_DCACHE2_P 2 | |
| 89 | #define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */ | |
| 90 | #define CPLB_ENABLE_ICPLBS_P 4 | |
| 91 | #define CPLB_ENABLE_DCPLBS_P 5 | |
| 92 | ||
| 93 | #define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P) | |
| 94 | #define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P) | |
| 95 | #define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P) | |
| 96 | #define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P) | |
| 97 | #define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P) | |
| 98 | #define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P) | |
| 99 | #define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \ | |
| 100 | CPLB_ENABLE_ICPLBS | \ | |
| 101 | CPLB_ENABLE_DCPLBS | |
| 102 | ||
| 103 | #define CPLB_RELOADED 0x0000 | |
| 104 | #define CPLB_NO_UNLOCKED 0x0001 | |
| 105 | #define CPLB_NO_ADDR_MATCH 0x0002 | |
| 106 | #define CPLB_PROT_VIOL 0x0003 | |
| 107 | #define CPLB_UNKNOWN_ERR 0x0004 | |
| 108 | ||
| 109 | #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT | |
| 110 | #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY | |
| 111 | ||
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112 | #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID |
| 113 | #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID | |
| 114 | #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID | |
| 115 | #define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE | |
| 116 | #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID | |
| 117 | #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL | |
| 118 | ||
| dbdf20db BS |
119 | #define FAULT_RW (1 << 16) |
| 120 | #define FAULT_USERSUPV (1 << 17) | |
| 121 | #define FAULT_CPLBBITS 0x0000ffff | |
| 122 | ||
| 1394f032 | 123 | #endif /* _CPLB_H */ |