Commit | Line | Data |
---|---|---|
1394f032 | 1 | /* |
96f1050d | 2 | * Blackfin low-level cache routines |
1394f032 | 3 | * |
96f1050d | 4 | * Copyright 2004-2009 Analog Devices Inc. |
1394f032 | 5 | * |
96f1050d | 6 | * Licensed under the GPL-2 or later. |
1394f032 BW |
7 | */ |
8 | ||
9 | #ifndef _BLACKFIN_CACHEFLUSH_H | |
10 | #define _BLACKFIN_CACHEFLUSH_H | |
11 | ||
5d89137a | 12 | #include <asm/blackfin.h> /* for SSYNC() */ |
bbc51e97 | 13 | #include <asm/sections.h> /* for _ramend */ |
71a66287 GY |
14 | #ifdef CONFIG_SMP |
15 | #include <asm/smp.h> | |
16 | #endif | |
5d89137a | 17 | |
8fb4f8f0 MF |
18 | extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); |
19 | extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); | |
20 | extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address); | |
21 | extern void blackfin_dflush_page(void *page); | |
6b3087c6 | 22 | extern void blackfin_invalidate_entire_dcache(void); |
47e9dedb | 23 | extern void blackfin_invalidate_entire_icache(void); |
1394f032 BW |
24 | |
25 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | |
26 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | |
27 | #define flush_cache_mm(mm) do { } while (0) | |
28 | #define flush_cache_range(vma, start, end) do { } while (0) | |
29 | #define flush_cache_page(vma, vmaddr) do { } while (0) | |
30 | #define flush_cache_vmap(start, end) do { } while (0) | |
31 | #define flush_cache_vunmap(start, end) do { } while (0) | |
32 | ||
6b3087c6 GY |
33 | #ifdef CONFIG_SMP |
34 | #define flush_icache_range_others(start, end) \ | |
35 | smp_icache_flush_range_others((start), (end)) | |
36 | #else | |
37 | #define flush_icache_range_others(start, end) do { } while (0) | |
38 | #endif | |
39 | ||
1394f032 BW |
40 | static inline void flush_icache_range(unsigned start, unsigned end) |
41 | { | |
bc6b92f8 SZ |
42 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) |
43 | if (end <= physical_mem_end) | |
44 | blackfin_dcache_flush_range(start, end); | |
45 | #endif | |
46 | #if defined(CONFIG_BFIN_L2_WRITEBACK) | |
47 | if (start >= L2_START && end <= L2_START + L2_LENGTH) | |
48 | blackfin_dcache_flush_range(start, end); | |
5d89137a | 49 | #endif |
1394f032 | 50 | |
5d89137a MF |
51 | /* Make sure all write buffers in the data side of the core |
52 | * are flushed before trying to invalidate the icache. This | |
53 | * needs to be after the data flush and before the icache | |
54 | * flush so that the SSYNC does the right thing in preventing | |
55 | * the instruction prefetcher from hitting things in cached | |
56 | * memory at the wrong time -- it runs much further ahead than | |
57 | * the pipeline. | |
58 | */ | |
59 | SSYNC(); | |
bc6b92f8 SZ |
60 | #if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) |
61 | if (end <= physical_mem_end) { | |
62 | blackfin_icache_flush_range(start, end); | |
63 | flush_icache_range_others(start, end); | |
64 | } | |
65 | #endif | |
66 | #if defined(CONFIG_BFIN_L2_ICACHEABLE) | |
67 | if (start >= L2_START && end <= L2_START + L2_LENGTH) { | |
68 | blackfin_icache_flush_range(start, end); | |
69 | flush_icache_range_others(start, end); | |
70 | } | |
1394f032 BW |
71 | #endif |
72 | } | |
73 | ||
6b3087c6 GY |
74 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ |
75 | do { memcpy(dst, src, len); \ | |
76 | flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ | |
1394f032 | 77 | } while (0) |
6b3087c6 | 78 | |
1394f032 BW |
79 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) |
80 | ||
3bebca2d | 81 | #if defined(CONFIG_BFIN_DCACHE) |
1394f032 BW |
82 | # define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end)) |
83 | #else | |
84 | # define invalidate_dcache_range(start,end) do { } while (0) | |
85 | #endif | |
41ba653f | 86 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
1394f032 | 87 | # define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) |
2d4dc890 | 88 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 |
41ba653f | 89 | # define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) |
1394f032 BW |
90 | #else |
91 | # define flush_dcache_range(start,end) do { } while (0) | |
2d4dc890 | 92 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 |
6b3087c6 | 93 | # define flush_dcache_page(page) do { } while (0) |
1394f032 BW |
94 | #endif |
95 | ||
04be80ef MF |
96 | extern unsigned long reserved_mem_dcache_on; |
97 | extern unsigned long reserved_mem_icache_on; | |
98 | ||
67834fa9 | 99 | static inline int bfin_addr_dcacheable(unsigned long addr) |
04be80ef | 100 | { |
41ba653f | 101 | #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE |
04be80ef MF |
102 | if (addr < (_ramend - DMA_UNCACHED_REGION)) |
103 | return 1; | |
104 | #endif | |
105 | ||
106 | if (reserved_mem_dcache_on && | |
107 | addr >= _ramend && addr < physical_mem_end) | |
108 | return 1; | |
109 | ||
41ba653f | 110 | #ifdef CONFIG_BFIN_L2_DCACHEABLE |
f339f46b MF |
111 | if (addr >= L2_START && addr < L2_START + L2_LENGTH) |
112 | return 1; | |
113 | #endif | |
114 | ||
04be80ef MF |
115 | return 0; |
116 | } | |
117 | ||
3bebca2d | 118 | #endif /* _BLACKFIN_ICACHEFLUSH_H */ |