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cdbf4c3c MF |
1 | /* Blackfin on-chip ROM API |
2 | * | |
3 | * Copyright 2008 Analog Devices Inc. | |
4 | * | |
5 | * Licensed under the GPL-2 or later. | |
6 | */ | |
7 | ||
8 | #ifndef __BFROM_H__ | |
9 | #define __BFROM_H__ | |
10 | ||
11 | #include <linux/types.h> | |
12 | ||
13 | /* Possible syscontrol action flags */ | |
14 | #define SYSCTRL_READ 0x00000000 /* read registers */ | |
15 | #define SYSCTRL_WRITE 0x00000001 /* write registers */ | |
16 | #define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */ | |
17 | #define SYSCTRL_CORERESET 0x00000004 /* perform core reset */ | |
18 | #define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */ | |
19 | #define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */ | |
20 | #define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */ | |
21 | #define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */ | |
22 | #define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */ | |
23 | #define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */ | |
24 | #define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */ | |
25 | #define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */ | |
26 | #define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */ | |
27 | ||
28 | typedef struct ADI_SYSCTRL_VALUES { | |
29 | uint16_t uwVrCtl; | |
30 | uint16_t uwPllCtl; | |
31 | uint16_t uwPllDiv; | |
32 | uint16_t uwPllLockCnt; | |
33 | uint16_t uwPllStat; | |
34 | } ADI_SYSCTRL_VALUES; | |
35 | ||
36 | static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038; | |
37 | ||
38 | /* We need a dedicated function since we need to screw with the stack pointer | |
39 | * when resetting. The on-chip ROM will save/restore registers on the stack | |
40 | * when doing a system reset, so the stack cannot be outside of the chip. | |
41 | */ | |
42 | __attribute__((__noreturn__)) | |
43 | static inline void bfrom_SoftReset(void *new_stack) | |
44 | { | |
45 | while (1) | |
26fe19f7 RG |
46 | /* |
47 | * We don't declare the SP as clobbered on purpose, since | |
48 | * it confuses the heck out of the compiler, and this function | |
49 | * never returns | |
50 | */ | |
cdbf4c3c MF |
51 | __asm__ __volatile__( |
52 | "sp = %[stack];" | |
53 | "jump (%[bfrom_syscontrol]);" | |
54 | : : [bfrom_syscontrol] "p"(bfrom_SysControl), | |
55 | "q0"(SYSCTRL_SOFTRESET), | |
56 | "q1"(0), | |
57 | "q2"(NULL), | |
58 | [stack] "p"(new_stack) | |
59 | ); | |
60 | } | |
61 | ||
62 | /* OTP Functions */ | |
63 | static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018; | |
64 | static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A; | |
65 | static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001C; | |
66 | ||
67 | /* otp command: defines for "command" */ | |
68 | #define OTP_INIT 0x00000001 | |
69 | #define OTP_CLOSE 0x00000002 | |
70 | ||
71 | /* otp read/write: defines for "flags" */ | |
72 | #define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */ | |
73 | #define OTP_UPPER_HALF 0x00000001 | |
74 | #define OTP_NO_ECC 0x00000010 /* do not use ECC */ | |
75 | #define OTP_LOCK 0x00000020 /* sets page protection bit for page */ | |
76 | #define OTP_CHECK_FOR_PREV_WRITE 0x00000080 | |
77 | ||
78 | /* Return values for all functions */ | |
79 | #define OTP_SUCCESS 0x00000000 | |
80 | #define OTP_MASTER_ERROR 0x001 | |
81 | #define OTP_WRITE_ERROR 0x003 | |
82 | #define OTP_READ_ERROR 0x005 | |
83 | #define OTP_ACC_VIO_ERROR 0x009 | |
84 | #define OTP_DATA_MULT_ERROR 0x011 | |
85 | #define OTP_ECC_MULT_ERROR 0x021 | |
86 | #define OTP_PREV_WR_ERROR 0x041 | |
87 | #define OTP_DATA_SB_WARN 0x100 | |
88 | #define OTP_ECC_SB_WARN 0x200 | |
89 | ||
90 | #endif |