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b1524e29 MF |
1 | /* |
2 | * bfin_serial.h - Blackfin UART/Serial definitions | |
3 | * | |
4 | * Copyright 2006-2010 Analog Devices Inc. | |
5 | * | |
6 | * Licensed under the GPL-2 or later. | |
7 | */ | |
8 | ||
9 | #ifndef __BFIN_ASM_SERIAL_H__ | |
10 | #define __BFIN_ASM_SERIAL_H__ | |
11 | ||
b725680f | 12 | #include <linux/circ_buf.h> |
b1524e29 | 13 | #include <linux/serial_core.h> |
0f66e50a | 14 | #include <linux/spinlock.h> |
b725680f JS |
15 | #include <linux/timer.h> |
16 | #include <linux/workqueue.h> | |
b1524e29 MF |
17 | #include <mach/anomaly.h> |
18 | #include <mach/bfin_serial.h> | |
19 | ||
57afb399 SZ |
20 | #if defined(CONFIG_BFIN_UART0_CTSRTS) || \ |
21 | defined(CONFIG_BFIN_UART1_CTSRTS) || \ | |
22 | defined(CONFIG_BFIN_UART2_CTSRTS) || \ | |
23 | defined(CONFIG_BFIN_UART3_CTSRTS) | |
b5affb01 | 24 | # if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE) |
60d0da51 | 25 | # define SERIAL_BFIN_HARD_CTSRTS |
57afb399 | 26 | # else |
60d0da51 | 27 | # define SERIAL_BFIN_CTSRTS |
57afb399 SZ |
28 | # endif |
29 | #endif | |
30 | ||
b1524e29 MF |
31 | struct bfin_serial_port { |
32 | struct uart_port port; | |
33 | unsigned int old_status; | |
edb0a640 SZ |
34 | int tx_irq; |
35 | int rx_irq; | |
b1524e29 MF |
36 | int status_irq; |
37 | #ifndef BFIN_UART_BF54X_STYLE | |
38 | unsigned int lsr; | |
39 | #endif | |
40 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
41 | int tx_done; | |
42 | int tx_count; | |
43 | struct circ_buf rx_dma_buf; | |
44 | struct timer_list rx_dma_timer; | |
45 | int rx_dma_nrows; | |
0f66e50a | 46 | spinlock_t rx_lock; |
b1524e29 MF |
47 | unsigned int tx_dma_channel; |
48 | unsigned int rx_dma_channel; | |
49 | struct work_struct tx_dma_workqueue; | |
50 | #elif ANOMALY_05000363 | |
51 | unsigned int anomaly_threshold; | |
52 | #endif | |
60d0da51 VR |
53 | #if defined(SERIAL_BFIN_CTSRTS) || \ |
54 | defined(SERIAL_BFIN_HARD_CTSRTS) | |
b1524e29 MF |
55 | int cts_pin; |
56 | int rts_pin; | |
57 | #endif | |
58 | }; | |
59 | ||
b5affb01 BL |
60 | #ifdef BFIN_UART_BF60X_STYLE |
61 | ||
62 | /* UART_CTL Masks */ | |
63 | #define UCEN 0x1 /* Enable UARTx Clocks */ | |
64 | #define LOOP_ENA 0x2 /* Loopback Mode Enable */ | |
65 | #define UMOD_MDB 0x10 /* Enable MDB Mode */ | |
66 | #define UMOD_IRDA 0x20 /* Enable IrDA Mode */ | |
67 | #define UMOD_MASK 0x30 /* Uart Mode Mask */ | |
68 | #define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */ | |
69 | #define WLS_MASK 0x300 /* Word length Select Mask */ | |
8e2f524f | 70 | #define WLS_OFFSET 8 /* Word length Select Offset */ |
b5affb01 BL |
71 | #define STB 0x1000 /* Stop Bits */ |
72 | #define STBH 0x2000 /* Half Stop Bits */ | |
73 | #define PEN 0x4000 /* Parity Enable */ | |
74 | #define EPS 0x8000 /* Even Parity Select */ | |
75 | #define STP 0x10000 /* Stick Parity */ | |
76 | #define FPE 0x20000 /* Force Parity Error On Transmit */ | |
77 | #define FFE 0x40000 /* Force Framing Error On Transmit */ | |
78 | #define SB 0x80000 /* Set Break */ | |
8e2f524f | 79 | #define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK) |
b5affb01 BL |
80 | #define FCPOL 0x400000 /* Flow Control Pin Polarity */ |
81 | #define RPOLC 0x800000 /* IrDA RX Polarity Change */ | |
82 | #define TPOLC 0x1000000 /* IrDA TX Polarity Change */ | |
83 | #define MRTS 0x2000000 /* Manual Request To Send */ | |
84 | #define XOFF 0x4000000 /* Transmitter Off */ | |
85 | #define ARTS 0x8000000 /* Automatic Request To Send */ | |
86 | #define ACTS 0x10000000 /* Automatic Clear To Send */ | |
87 | #define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */ | |
88 | #define RFRT 0x40000000 /* Receive FIFO RTS Threshold */ | |
89 | ||
90 | /* UART_STAT Masks */ | |
91 | #define DR 0x01 /* Data Ready */ | |
92 | #define OE 0x02 /* Overrun Error */ | |
93 | #define PE 0x04 /* Parity Error */ | |
94 | #define FE 0x08 /* Framing Error */ | |
95 | #define BI 0x10 /* Break Interrupt */ | |
96 | #define THRE 0x20 /* THR Empty */ | |
97 | #define TEMT 0x80 /* TSR and UART_THR Empty */ | |
98 | #define TFI 0x100 /* Transmission Finished Indicator */ | |
99 | ||
100 | #define ASTKY 0x200 /* Address Sticky */ | |
101 | #define ADDR 0x400 /* Address bit status */ | |
102 | #define RO 0x800 /* Reception Ongoing */ | |
103 | #define SCTS 0x1000 /* Sticky CTS */ | |
104 | #define CTS 0x10000 /* Clear To Send */ | |
105 | #define RFCS 0x20000 /* Receive FIFO Count Status */ | |
106 | ||
107 | /* UART_CLOCK Masks */ | |
108 | #define EDBO 0x80000000 /* Enable Devide by One */ | |
109 | ||
110 | #else /* BFIN_UART_BF60X_STYLE */ | |
111 | ||
b1524e29 MF |
112 | /* UART_LCR Masks */ |
113 | #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ | |
b5affb01 | 114 | #define WLS_MASK 0x03 /* Word length Select Mask */ |
8e2f524f | 115 | #define WLS_OFFSET 0 /* Word length Select Offset */ |
b1524e29 MF |
116 | #define STB 0x04 /* Stop Bits */ |
117 | #define PEN 0x08 /* Parity Enable */ | |
118 | #define EPS 0x10 /* Even Parity Select */ | |
119 | #define STP 0x20 /* Stick Parity */ | |
120 | #define SB 0x40 /* Set Break */ | |
121 | #define DLAB 0x80 /* Divisor Latch Access */ | |
8e2f524f | 122 | #define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK) |
b1524e29 MF |
123 | |
124 | /* UART_LSR Masks */ | |
125 | #define DR 0x01 /* Data Ready */ | |
126 | #define OE 0x02 /* Overrun Error */ | |
127 | #define PE 0x04 /* Parity Error */ | |
128 | #define FE 0x08 /* Framing Error */ | |
129 | #define BI 0x10 /* Break Interrupt */ | |
130 | #define THRE 0x20 /* THR Empty */ | |
131 | #define TEMT 0x40 /* TSR and UART_THR Empty */ | |
132 | #define TFI 0x80 /* Transmission Finished Indicator */ | |
133 | ||
b1524e29 MF |
134 | /* UART_MCR Masks */ |
135 | #define XOFF 0x01 /* Transmitter Off */ | |
136 | #define MRTS 0x02 /* Manual Request To Send */ | |
137 | #define RFIT 0x04 /* Receive FIFO IRQ Threshold */ | |
138 | #define RFRT 0x08 /* Receive FIFO RTS Threshold */ | |
139 | #define LOOP_ENA 0x10 /* Loopback Mode Enable */ | |
140 | #define FCPOL 0x20 /* Flow Control Pin Polarity */ | |
141 | #define ARTS 0x40 /* Automatic Request To Send */ | |
142 | #define ACTS 0x80 /* Automatic Clear To Send */ | |
143 | ||
144 | /* UART_MSR Masks */ | |
145 | #define SCTS 0x01 /* Sticky CTS */ | |
146 | #define CTS 0x10 /* Clear To Send */ | |
147 | #define RFCS 0x20 /* Receive FIFO Count Status */ | |
148 | ||
149 | /* UART_GCTL Masks */ | |
150 | #define UCEN 0x01 /* Enable UARTx Clocks */ | |
b5affb01 BL |
151 | #define UMOD_IRDA 0x02 /* Enable IrDA Mode */ |
152 | #define UMOD_MASK 0x02 /* Uart Mode Mask */ | |
b1524e29 MF |
153 | #define TPOLC 0x04 /* IrDA TX Polarity Change */ |
154 | #define RPOLC 0x08 /* IrDA RX Polarity Change */ | |
155 | #define FPE 0x10 /* Force Parity Error On Transmit */ | |
156 | #define FFE 0x20 /* Force Framing Error On Transmit */ | |
157 | ||
b5affb01 BL |
158 | #endif /* BFIN_UART_BF60X_STYLE */ |
159 | ||
160 | /* UART_IER Masks */ | |
161 | #define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ | |
162 | #define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ | |
163 | #define ELSI 0x04 /* Enable RX Status Interrupt */ | |
164 | #define EDSSI 0x08 /* Enable Modem Status Interrupt */ | |
165 | #define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ | |
166 | #define ETFI 0x20 /* Enable Transmission Finished Interrupt */ | |
167 | #define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ | |
168 | ||
169 | #if defined(BFIN_UART_BF60X_STYLE) | |
170 | # define OFFSET_REDIV 0x00 /* Version ID Register */ | |
171 | # define OFFSET_CTL 0x04 /* Control Register */ | |
172 | # define OFFSET_STAT 0x08 /* Status Register */ | |
173 | # define OFFSET_SCR 0x0C /* SCR Scratch Register */ | |
174 | # define OFFSET_CLK 0x10 /* Clock Rate Register */ | |
175 | # define OFFSET_IER 0x14 /* Interrupt Enable Register */ | |
176 | # define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */ | |
177 | # define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */ | |
178 | # define OFFSET_RBR 0x20 /* Receive Buffer register */ | |
179 | # define OFFSET_THR 0x24 /* Transmit Holding register */ | |
180 | #elif defined(BFIN_UART_BF54X_STYLE) | |
b1524e29 MF |
181 | # define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ |
182 | # define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ | |
183 | # define OFFSET_GCTL 0x08 /* Global Control Register */ | |
184 | # define OFFSET_LCR 0x0C /* Line Control Register */ | |
185 | # define OFFSET_MCR 0x10 /* Modem Control Register */ | |
186 | # define OFFSET_LSR 0x14 /* Line Status Register */ | |
187 | # define OFFSET_MSR 0x18 /* Modem Status Register */ | |
188 | # define OFFSET_SCR 0x1C /* SCR Scratch Register */ | |
189 | # define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */ | |
190 | # define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */ | |
191 | # define OFFSET_THR 0x28 /* Transmit Holding register */ | |
192 | # define OFFSET_RBR 0x2C /* Receive Buffer register */ | |
193 | #else /* BF533 style */ | |
194 | # define OFFSET_THR 0x00 /* Transmit Holding register */ | |
195 | # define OFFSET_RBR 0x00 /* Receive Buffer register */ | |
196 | # define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | |
197 | # define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ | |
198 | # define OFFSET_IER 0x04 /* Interrupt Enable Register */ | |
199 | # define OFFSET_IIR 0x08 /* Interrupt Identification Register */ | |
200 | # define OFFSET_LCR 0x0C /* Line Control Register */ | |
201 | # define OFFSET_MCR 0x10 /* Modem Control Register */ | |
202 | # define OFFSET_LSR 0x14 /* Line Status Register */ | |
203 | # define OFFSET_MSR 0x18 /* Modem Status Register */ | |
204 | # define OFFSET_SCR 0x1C /* SCR Scratch Register */ | |
205 | # define OFFSET_GCTL 0x24 /* Global Control Register */ | |
206 | /* code should not need IIR, so force build error if they use it */ | |
207 | # undef OFFSET_IIR | |
208 | #endif | |
209 | ||
210 | /* | |
211 | * All Blackfin system MMRs are padded to 32bits even if the register | |
212 | * itself is only 16bits. So use a helper macro to streamline this. | |
213 | */ | |
214 | #define __BFP(m) u16 m; u16 __pad_##m | |
215 | struct bfin_uart_regs { | |
b5affb01 BL |
216 | #if defined(BFIN_UART_BF60X_STYLE) |
217 | u32 revid; | |
218 | u32 ctl; | |
219 | u32 stat; | |
220 | u32 scr; | |
221 | u32 clk; | |
222 | u32 ier; | |
223 | u32 ier_set; | |
224 | u32 ier_clear; | |
225 | u32 rbr; | |
226 | u32 thr; | |
227 | u32 taip; | |
228 | u32 tsr; | |
229 | u32 rsr; | |
230 | u32 txdiv; | |
231 | u32 rxdiv; | |
232 | #elif defined(BFIN_UART_BF54X_STYLE) | |
b1524e29 MF |
233 | __BFP(dll); |
234 | __BFP(dlh); | |
235 | __BFP(gctl); | |
236 | __BFP(lcr); | |
237 | __BFP(mcr); | |
238 | __BFP(lsr); | |
239 | __BFP(msr); | |
240 | __BFP(scr); | |
241 | __BFP(ier_set); | |
242 | __BFP(ier_clear); | |
243 | __BFP(thr); | |
244 | __BFP(rbr); | |
245 | #else | |
246 | union { | |
247 | u16 dll; | |
248 | u16 thr; | |
249 | const u16 rbr; | |
250 | }; | |
251 | const u16 __pad0; | |
252 | union { | |
253 | u16 dlh; | |
254 | u16 ier; | |
255 | }; | |
256 | const u16 __pad1; | |
257 | const __BFP(iir); | |
258 | __BFP(lcr); | |
259 | __BFP(mcr); | |
260 | __BFP(lsr); | |
261 | __BFP(msr); | |
262 | __BFP(scr); | |
263 | const u32 __pad2; | |
264 | __BFP(gctl); | |
265 | #endif | |
266 | }; | |
267 | #undef __BFP | |
268 | ||
b5affb01 BL |
269 | #define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase) |
270 | ||
271 | /* | |
b1524e29 | 272 | #ifndef port_membase |
091c7598 | 273 | # define port_membase(p) 0 |
b1524e29 | 274 | #endif |
b5affb01 BL |
275 | */ |
276 | #ifdef BFIN_UART_BF60X_STYLE | |
277 | ||
278 | #define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR) | |
279 | #define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK) | |
280 | #define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL) | |
281 | #define UART_GET_GCTL(p) UART_GET_CTL(p) | |
282 | #define UART_GET_LCR(p) UART_GET_CTL(p) | |
283 | #define UART_GET_MCR(p) UART_GET_CTL(p) | |
2a26a205 | 284 | #if ANOMALY_16000030 |
913f2f2d SZ |
285 | #define UART_GET_STAT(p) \ |
286 | ({ \ | |
287 | u32 __ret; \ | |
288 | unsigned long flags; \ | |
289 | flags = hard_local_irq_save(); \ | |
290 | __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \ | |
291 | hard_local_irq_restore(flags); \ | |
292 | __ret; \ | |
293 | }) | |
294 | #else | |
b5affb01 | 295 | #define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT) |
913f2f2d | 296 | #endif |
b5affb01 BL |
297 | #define UART_GET_MSR(p) UART_GET_STAT(p) |
298 | ||
299 | #define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v) | |
300 | #define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v) | |
301 | #define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v) | |
302 | #define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v) | |
303 | #define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v) | |
304 | #define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v) | |
305 | #define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v) | |
306 | ||
307 | #define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v) | |
308 | #define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER) | |
309 | #define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v) | |
310 | ||
311 | #define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */ | |
312 | #define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */ | |
313 | ||
314 | #define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1) | |
315 | #define UART_GET_LSR(p) UART_GET_STAT(p) | |
316 | #define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v) | |
317 | ||
318 | /* This handles hard CTS/RTS */ | |
319 | #define BFIN_UART_CTSRTS_HARD | |
320 | #define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS) | |
321 | #define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) | |
322 | #define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS)) | |
323 | #define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS) | |
324 | #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) | |
325 | #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) | |
326 | ||
327 | #else /* BFIN_UART_BF60X_STYLE */ | |
b1524e29 MF |
328 | |
329 | #define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR) | |
330 | #define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL) | |
331 | #define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH) | |
b5affb01 | 332 | #define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p)) |
b1524e29 MF |
333 | #define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL) |
334 | #define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR) | |
335 | #define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR) | |
336 | #define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR) | |
337 | ||
338 | #define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v) | |
339 | #define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v) | |
340 | #define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v) | |
b5affb01 BL |
341 | #define UART_PUT_CLK(p, v) do \ |
342 | {\ | |
343 | UART_PUT_DLL(p, v & 0xFF); \ | |
344 | UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0); | |
345 | ||
b1524e29 MF |
346 | #define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v) |
347 | #define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v) | |
348 | #define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v) | |
349 | ||
350 | #ifdef BFIN_UART_BF54X_STYLE | |
351 | ||
352 | #define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v) | |
353 | #define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET) | |
354 | #define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v) | |
355 | ||
356 | #define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */ | |
357 | #define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */ | |
358 | ||
359 | #define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1) | |
360 | #define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR) | |
361 | #define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v) | |
362 | ||
363 | /* This handles hard CTS/RTS */ | |
57afb399 | 364 | #define BFIN_UART_CTSRTS_HARD |
b1524e29 MF |
365 | #define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS) |
366 | #define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) | |
367 | #define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS)) | |
368 | #define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS) | |
369 | #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) | |
370 | #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) | |
371 | ||
372 | #else /* BF533 style */ | |
373 | ||
374 | #define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v)) | |
375 | #define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER) | |
376 | #define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v) | |
377 | #define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v)) | |
378 | ||
379 | #define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0) | |
380 | #define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0) | |
381 | ||
b5affb01 BL |
382 | #define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr) |
383 | #define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v)) | |
384 | ||
385 | /* | |
b1524e29 | 386 | #ifndef put_lsr_cache |
091c7598 | 387 | # define put_lsr_cache(p, v) |
b1524e29 MF |
388 | #endif |
389 | #ifndef get_lsr_cache | |
091c7598 | 390 | # define get_lsr_cache(p) 0 |
b1524e29 | 391 | #endif |
b5affb01 | 392 | */ |
b1524e29 MF |
393 | |
394 | /* The hardware clears the LSR bits upon read, so we need to cache | |
395 | * some of the more fun bits in software so they don't get lost | |
396 | * when checking the LSR in other code paths (TX). | |
397 | */ | |
398 | static inline void UART_CLEAR_LSR(void *p) | |
399 | { | |
400 | put_lsr_cache(p, 0); | |
401 | bfin_write16(port_membase(p) + OFFSET_LSR, -1); | |
402 | } | |
403 | static inline unsigned int UART_GET_LSR(void *p) | |
404 | { | |
405 | unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR); | |
406 | put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE))); | |
407 | return lsr | get_lsr_cache(p); | |
408 | } | |
409 | static inline void UART_PUT_LSR(void *p, uint16_t val) | |
410 | { | |
411 | put_lsr_cache(p, get_lsr_cache(p) & ~val); | |
412 | } | |
413 | ||
414 | /* This handles soft CTS/RTS */ | |
415 | #define UART_GET_CTS(x) gpio_get_value((x)->cts_pin) | |
416 | #define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1) | |
417 | #define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0) | |
418 | #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) | |
419 | #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) | |
420 | ||
b5affb01 BL |
421 | #endif /* BFIN_UART_BF54X_STYLE */ |
422 | ||
423 | #endif /* BFIN_UART_BF60X_STYLE */ | |
b1524e29 MF |
424 | |
425 | #ifndef BFIN_UART_TX_FIFO_SIZE | |
426 | # define BFIN_UART_TX_FIFO_SIZE 2 | |
427 | #endif | |
428 | ||
429 | #endif /* __BFIN_ASM_SERIAL_H__ */ |