Commit | Line | Data |
---|---|---|
1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
9 | bool | |
10 | default n | |
11 | ||
12 | config FPU | |
13 | bool | |
14 | default n | |
15 | ||
16 | config RWSEM_GENERIC_SPINLOCK | |
17 | bool | |
18 | default y | |
19 | ||
20 | config RWSEM_XCHGADD_ALGORITHM | |
21 | bool | |
22 | default n | |
23 | ||
24 | config BLACKFIN | |
25 | bool | |
26 | default y | |
ec7748b5 | 27 | select HAVE_IDE |
42d4b839 | 28 | select HAVE_OPROFILE |
1394f032 | 29 | |
e3defffe AL |
30 | config ZONE_DMA |
31 | bool | |
32 | default y | |
33 | ||
1394f032 BW |
34 | config GENERIC_FIND_NEXT_BIT |
35 | bool | |
36 | default y | |
37 | ||
38 | config GENERIC_HWEIGHT | |
39 | bool | |
40 | default y | |
41 | ||
42 | config GENERIC_HARDIRQS | |
43 | bool | |
44 | default y | |
45 | ||
46 | config GENERIC_IRQ_PROBE | |
e4e9a7ad | 47 | bool |
1394f032 BW |
48 | default y |
49 | ||
b2d1583f | 50 | config GENERIC_GPIO |
1394f032 BW |
51 | bool |
52 | default y | |
53 | ||
54 | config FORCE_MAX_ZONEORDER | |
55 | int | |
56 | default "14" | |
57 | ||
58 | config GENERIC_CALIBRATE_DELAY | |
59 | bool | |
60 | default y | |
61 | ||
7d2284b0 MD |
62 | config HARDWARE_PM |
63 | def_bool y | |
64 | depends on OPROFILE | |
65 | ||
1394f032 | 66 | source "init/Kconfig" |
dc52ddc0 | 67 | |
1394f032 BW |
68 | source "kernel/Kconfig.preempt" |
69 | ||
dc52ddc0 MH |
70 | source "kernel/Kconfig.freezer" |
71 | ||
1394f032 BW |
72 | menu "Blackfin Processor Options" |
73 | ||
74 | comment "Processor and Board Settings" | |
75 | ||
76 | choice | |
77 | prompt "CPU" | |
78 | default BF533 | |
79 | ||
59003145 MH |
80 | config BF522 |
81 | bool "BF522" | |
82 | help | |
83 | BF522 Processor Support. | |
84 | ||
1545a111 MF |
85 | config BF523 |
86 | bool "BF523" | |
87 | help | |
88 | BF523 Processor Support. | |
89 | ||
90 | config BF524 | |
91 | bool "BF524" | |
92 | help | |
93 | BF524 Processor Support. | |
94 | ||
59003145 MH |
95 | config BF525 |
96 | bool "BF525" | |
97 | help | |
98 | BF525 Processor Support. | |
99 | ||
1545a111 MF |
100 | config BF526 |
101 | bool "BF526" | |
102 | help | |
103 | BF526 Processor Support. | |
104 | ||
59003145 MH |
105 | config BF527 |
106 | bool "BF527" | |
107 | help | |
108 | BF527 Processor Support. | |
109 | ||
1394f032 BW |
110 | config BF531 |
111 | bool "BF531" | |
112 | help | |
113 | BF531 Processor Support. | |
114 | ||
115 | config BF532 | |
116 | bool "BF532" | |
117 | help | |
118 | BF532 Processor Support. | |
119 | ||
120 | config BF533 | |
121 | bool "BF533" | |
122 | help | |
123 | BF533 Processor Support. | |
124 | ||
125 | config BF534 | |
126 | bool "BF534" | |
127 | help | |
128 | BF534 Processor Support. | |
129 | ||
130 | config BF536 | |
131 | bool "BF536" | |
132 | help | |
133 | BF536 Processor Support. | |
134 | ||
135 | config BF537 | |
136 | bool "BF537" | |
137 | help | |
138 | BF537 Processor Support. | |
139 | ||
dc26aec2 MH |
140 | config BF538 |
141 | bool "BF538" | |
142 | help | |
143 | BF538 Processor Support. | |
144 | ||
145 | config BF539 | |
146 | bool "BF539" | |
147 | help | |
148 | BF539 Processor Support. | |
149 | ||
24a07a12 RH |
150 | config BF542 |
151 | bool "BF542" | |
152 | help | |
153 | BF542 Processor Support. | |
154 | ||
155 | config BF544 | |
156 | bool "BF544" | |
157 | help | |
158 | BF544 Processor Support. | |
159 | ||
7c7fd170 MF |
160 | config BF547 |
161 | bool "BF547" | |
162 | help | |
163 | BF547 Processor Support. | |
164 | ||
24a07a12 RH |
165 | config BF548 |
166 | bool "BF548" | |
167 | help | |
168 | BF548 Processor Support. | |
169 | ||
170 | config BF549 | |
171 | bool "BF549" | |
172 | help | |
173 | BF549 Processor Support. | |
174 | ||
1394f032 BW |
175 | config BF561 |
176 | bool "BF561" | |
177 | help | |
cd88b4dc | 178 | BF561 Processor Support. |
1394f032 BW |
179 | |
180 | endchoice | |
181 | ||
0c0497c2 MF |
182 | config BF_REV_MIN |
183 | int | |
184 | default 0 if (BF52x || BF54x) | |
185 | default 2 if (BF537 || BF536 || BF534) | |
186 | default 3 if (BF561 ||BF533 || BF532 || BF531) | |
dc26aec2 | 187 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
188 | |
189 | config BF_REV_MAX | |
190 | int | |
191 | default 2 if (BF52x || BF54x) | |
192 | default 3 if (BF537 || BF536 || BF534) | |
dc26aec2 | 193 | default 5 if (BF561|| BF538 || BF539) |
0c0497c2 MF |
194 | default 6 if (BF533 || BF532 || BF531) |
195 | ||
1394f032 BW |
196 | choice |
197 | prompt "Silicon Rev" | |
46ce0d9a MF |
198 | default BF_REV_0_1 if (BF52x || BF54x) |
199 | default BF_REV_0_2 if (BF534 || BF536 || BF537) | |
200 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561) | |
24a07a12 RH |
201 | |
202 | config BF_REV_0_0 | |
203 | bool "0.0" | |
d07f4380 | 204 | depends on (BF52x || BF54x) |
59003145 MH |
205 | |
206 | config BF_REV_0_1 | |
d07f4380 MF |
207 | bool "0.1" |
208 | depends on (BF52x || BF54x) | |
1394f032 BW |
209 | |
210 | config BF_REV_0_2 | |
211 | bool "0.2" | |
49f7253c | 212 | depends on (BF52x || BF537 || BF536 || BF534 || BF54x) |
1394f032 BW |
213 | |
214 | config BF_REV_0_3 | |
215 | bool "0.3" | |
216 | depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) | |
217 | ||
218 | config BF_REV_0_4 | |
219 | bool "0.4" | |
dc26aec2 | 220 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
221 | |
222 | config BF_REV_0_5 | |
223 | bool "0.5" | |
dc26aec2 | 224 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 225 | |
49f7253c MF |
226 | config BF_REV_0_6 |
227 | bool "0.6" | |
228 | depends on (BF533 || BF532 || BF531) | |
229 | ||
de3025f4 JZ |
230 | config BF_REV_ANY |
231 | bool "any" | |
232 | ||
233 | config BF_REV_NONE | |
234 | bool "none" | |
235 | ||
1394f032 BW |
236 | endchoice |
237 | ||
59003145 MH |
238 | config BF52x |
239 | bool | |
1545a111 | 240 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
59003145 MH |
241 | default y |
242 | ||
24a07a12 RH |
243 | config BF53x |
244 | bool | |
245 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
246 | default y | |
247 | ||
248 | config BF54x | |
249 | bool | |
7c7fd170 | 250 | depends on (BF542 || BF544 || BF547 || BF548 || BF549) |
24a07a12 RH |
251 | default y |
252 | ||
1394f032 BW |
253 | config MEM_GENERIC_BOARD |
254 | bool | |
255 | depends on GENERIC_BOARD | |
256 | default y | |
257 | ||
258 | config MEM_MT48LC64M4A2FB_7E | |
259 | bool | |
260 | depends on (BFIN533_STAMP) | |
261 | default y | |
262 | ||
263 | config MEM_MT48LC16M16A2TG_75 | |
264 | bool | |
265 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
ab472a04 | 266 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
9db144fe | 267 | || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM) |
1394f032 BW |
268 | default y |
269 | ||
270 | config MEM_MT48LC32M8A2_75 | |
271 | bool | |
dc26aec2 | 272 | depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
273 | default y |
274 | ||
275 | config MEM_MT48LC8M32B2B5_7 | |
276 | bool | |
277 | depends on (BFIN561_BLUETECHNIX_CM) | |
278 | default y | |
279 | ||
59003145 MH |
280 | config MEM_MT48LC32M16A2TG_75 |
281 | bool | |
8cc7117e | 282 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) |
59003145 MH |
283 | default y |
284 | ||
59003145 | 285 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
286 | source "arch/blackfin/mach-bf533/Kconfig" |
287 | source "arch/blackfin/mach-bf561/Kconfig" | |
288 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 289 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 290 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
291 | |
292 | menu "Board customizations" | |
293 | ||
294 | config CMDLINE_BOOL | |
295 | bool "Default bootloader kernel arguments" | |
296 | ||
297 | config CMDLINE | |
298 | string "Initial kernel command string" | |
299 | depends on CMDLINE_BOOL | |
300 | default "console=ttyBF0,57600" | |
301 | help | |
302 | If you don't have a boot loader capable of passing a command line string | |
303 | to the kernel, you may specify one here. As a minimum, you should specify | |
304 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
305 | ||
5f004c20 MF |
306 | config BOOT_LOAD |
307 | hex "Kernel load address for booting" | |
308 | default "0x1000" | |
309 | range 0x1000 0x20000000 | |
310 | help | |
311 | This option allows you to set the load address of the kernel. | |
312 | This can be useful if you are on a board which has a small amount | |
313 | of memory or you wish to reserve some memory at the beginning of | |
314 | the address space. | |
315 | ||
316 | Note that you need to keep this value above 4k (0x1000) as this | |
317 | memory region is used to capture NULL pointer references as well | |
318 | as some core kernel functions. | |
319 | ||
8cc7117e MH |
320 | config ROM_BASE |
321 | hex "Kernel ROM Base" | |
322 | default "0x20040000" | |
323 | range 0x20000000 0x20400000 if !(BF54x || BF561) | |
324 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
325 | help | |
326 | ||
f16295e7 | 327 | comment "Clock/PLL Setup" |
1394f032 BW |
328 | |
329 | config CLKIN_HZ | |
2fb6cb41 | 330 | int "Frequency of the crystal on the board in Hz" |
1394f032 BW |
331 | default "11059200" if BFIN533_STAMP |
332 | default "27000000" if BFIN533_EZKIT | |
dc26aec2 | 333 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT) |
1394f032 BW |
334 | default "30000000" if BFIN561_EZKIT |
335 | default "24576000" if PNAV10 | |
5d1617b2 | 336 | default "10000000" if BFIN532_IP0X |
1394f032 BW |
337 | help |
338 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
339 | Warning: This value should match the crystal on the board. Otherwise, |
340 | peripherals won't work properly. | |
1394f032 | 341 | |
f16295e7 RG |
342 | config BFIN_KERNEL_CLOCK |
343 | bool "Re-program Clocks while Kernel boots?" | |
344 | default n | |
345 | help | |
346 | This option decides if kernel clocks are re-programed from the | |
347 | bootloader settings. If the clocks are not set, the SDRAM settings | |
348 | are also not changed, and the Bootloader does 100% of the hardware | |
349 | configuration. | |
350 | ||
351 | config PLL_BYPASS | |
e4e9a7ad MF |
352 | bool "Bypass PLL" |
353 | depends on BFIN_KERNEL_CLOCK | |
354 | default n | |
f16295e7 RG |
355 | |
356 | config CLKIN_HALF | |
357 | bool "Half Clock In" | |
358 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
359 | default n | |
360 | help | |
361 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
362 | ||
363 | config VCO_MULT | |
364 | int "VCO Multiplier" | |
365 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
366 | range 1 64 | |
367 | default "22" if BFIN533_EZKIT | |
368 | default "45" if BFIN533_STAMP | |
dc26aec2 | 369 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 370 | default "22" if BFIN533_BLUETECHNIX_CM |
9db144fe | 371 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 372 | default "20" if BFIN561_EZKIT |
8cc7117e | 373 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD) |
f16295e7 RG |
374 | help |
375 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
376 | PLL Frequency = (Crystal Frequency) * (this setting) | |
377 | ||
378 | choice | |
379 | prompt "Core Clock Divider" | |
380 | depends on BFIN_KERNEL_CLOCK | |
381 | default CCLK_DIV_1 | |
382 | help | |
383 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
384 | Core Frequency = (PLL frequency) / (this setting) | |
385 | ||
386 | config CCLK_DIV_1 | |
387 | bool "1" | |
388 | ||
389 | config CCLK_DIV_2 | |
390 | bool "2" | |
391 | ||
392 | config CCLK_DIV_4 | |
393 | bool "4" | |
394 | ||
395 | config CCLK_DIV_8 | |
396 | bool "8" | |
397 | endchoice | |
398 | ||
399 | config SCLK_DIV | |
400 | int "System Clock Divider" | |
401 | depends on BFIN_KERNEL_CLOCK | |
402 | range 1 15 | |
5f004c20 | 403 | default 5 |
f16295e7 RG |
404 | help |
405 | This sets the frequency of the system clock (including SDRAM or DDR). | |
406 | This can be between 1 and 15 | |
407 | System Clock = (PLL frequency) / (this setting) | |
408 | ||
5f004c20 MF |
409 | choice |
410 | prompt "DDR SDRAM Chip Type" | |
411 | depends on BFIN_KERNEL_CLOCK | |
412 | depends on BF54x | |
413 | default MEM_MT46V32M16_5B | |
414 | ||
415 | config MEM_MT46V32M16_6T | |
416 | bool "MT46V32M16_6T" | |
417 | ||
418 | config MEM_MT46V32M16_5B | |
419 | bool "MT46V32M16_5B" | |
420 | endchoice | |
421 | ||
7eb2c23f MF |
422 | config MAX_MEM_SIZE |
423 | int "Max SDRAM Memory Size in MBytes" | |
424 | depends on !MPU | |
425 | default 512 | |
426 | help | |
427 | This is the max memory size that the kernel will create CPLB | |
428 | tables for. Your system will not be able to handle any more. | |
429 | ||
f16295e7 RG |
430 | # |
431 | # Max & Min Speeds for various Chips | |
432 | # | |
433 | config MAX_VCO_HZ | |
434 | int | |
435 | default 600000000 if BF522 | |
1545a111 MF |
436 | default 400000000 if BF523 |
437 | default 400000000 if BF524 | |
f16295e7 | 438 | default 600000000 if BF525 |
1545a111 | 439 | default 400000000 if BF526 |
f16295e7 RG |
440 | default 600000000 if BF527 |
441 | default 400000000 if BF531 | |
442 | default 400000000 if BF532 | |
443 | default 750000000 if BF533 | |
444 | default 500000000 if BF534 | |
445 | default 400000000 if BF536 | |
446 | default 600000000 if BF537 | |
f72eecb9 RG |
447 | default 533333333 if BF538 |
448 | default 533333333 if BF539 | |
f16295e7 | 449 | default 600000000 if BF542 |
f72eecb9 | 450 | default 533333333 if BF544 |
1545a111 MF |
451 | default 600000000 if BF547 |
452 | default 600000000 if BF548 | |
f72eecb9 | 453 | default 533333333 if BF549 |
f16295e7 RG |
454 | default 600000000 if BF561 |
455 | ||
456 | config MIN_VCO_HZ | |
457 | int | |
458 | default 50000000 | |
459 | ||
460 | config MAX_SCLK_HZ | |
461 | int | |
f72eecb9 | 462 | default 133333333 |
f16295e7 RG |
463 | |
464 | config MIN_SCLK_HZ | |
465 | int | |
466 | default 27000000 | |
467 | ||
468 | comment "Kernel Timer/Scheduler" | |
469 | ||
470 | source kernel/Kconfig.hz | |
471 | ||
8b5f79f9 VM |
472 | config GENERIC_TIME |
473 | bool "Generic time" | |
474 | default y | |
475 | ||
476 | config GENERIC_CLOCKEVENTS | |
477 | bool "Generic clock events" | |
478 | depends on GENERIC_TIME | |
479 | default y | |
480 | ||
481 | config CYCLES_CLOCKSOURCE | |
482 | bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)" | |
483 | depends on EXPERIMENTAL | |
484 | depends on GENERIC_CLOCKEVENTS | |
485 | depends on !BFIN_SCRATCH_REG_CYCLES | |
486 | default n | |
487 | help | |
488 | If you say Y here, you will enable support for using the 'cycles' | |
489 | registers as a clock source. Doing so means you will be unable to | |
490 | safely write to the 'cycles' register during runtime. You will | |
491 | still be able to read it (such as for performance monitoring), but | |
492 | writing the registers will most likely crash the kernel. | |
493 | ||
494 | source kernel/time/Kconfig | |
495 | ||
5f004c20 | 496 | comment "Misc" |
971d5bc4 | 497 | |
f0b5d12f MF |
498 | choice |
499 | prompt "Blackfin Exception Scratch Register" | |
500 | default BFIN_SCRATCH_REG_RETN | |
501 | help | |
502 | Select the resource to reserve for the Exception handler: | |
503 | - RETN: Non-Maskable Interrupt (NMI) | |
504 | - RETE: Exception Return (JTAG/ICE) | |
505 | - CYCLES: Performance counter | |
506 | ||
507 | If you are unsure, please select "RETN". | |
508 | ||
509 | config BFIN_SCRATCH_REG_RETN | |
510 | bool "RETN" | |
511 | help | |
512 | Use the RETN register in the Blackfin exception handler | |
513 | as a stack scratch register. This means you cannot | |
514 | safely use NMI on the Blackfin while running Linux, but | |
515 | you can debug the system with a JTAG ICE and use the | |
516 | CYCLES performance registers. | |
517 | ||
518 | If you are unsure, please select "RETN". | |
519 | ||
520 | config BFIN_SCRATCH_REG_RETE | |
521 | bool "RETE" | |
522 | help | |
523 | Use the RETE register in the Blackfin exception handler | |
524 | as a stack scratch register. This means you cannot | |
525 | safely use a JTAG ICE while debugging a Blackfin board, | |
526 | but you can safely use the CYCLES performance registers | |
527 | and the NMI. | |
528 | ||
529 | If you are unsure, please select "RETN". | |
530 | ||
531 | config BFIN_SCRATCH_REG_CYCLES | |
532 | bool "CYCLES" | |
533 | help | |
534 | Use the CYCLES register in the Blackfin exception handler | |
535 | as a stack scratch register. This means you cannot | |
536 | safely use the CYCLES performance registers on a Blackfin | |
537 | board at anytime, but you can debug the system with a JTAG | |
538 | ICE and use the NMI. | |
539 | ||
540 | If you are unsure, please select "RETN". | |
541 | ||
542 | endchoice | |
543 | ||
1394f032 BW |
544 | endmenu |
545 | ||
546 | ||
547 | menu "Blackfin Kernel Optimizations" | |
548 | ||
1394f032 BW |
549 | comment "Memory Optimizations" |
550 | ||
551 | config I_ENTRY_L1 | |
552 | bool "Locate interrupt entry code in L1 Memory" | |
553 | default y | |
554 | help | |
01dd2fbf ML |
555 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
556 | into L1 instruction memory. (less latency) | |
1394f032 BW |
557 | |
558 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 559 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
560 | default y |
561 | help | |
01dd2fbf | 562 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 563 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 564 | (less latency) |
1394f032 BW |
565 | |
566 | config DO_IRQ_L1 | |
567 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
568 | default y | |
569 | help | |
01dd2fbf ML |
570 | If enabled, the frequently called do_irq dispatcher function is linked |
571 | into L1 instruction memory. (less latency) | |
1394f032 BW |
572 | |
573 | config CORE_TIMER_IRQ_L1 | |
574 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
575 | default y | |
576 | help | |
01dd2fbf ML |
577 | If enabled, the frequently called timer_interrupt() function is linked |
578 | into L1 instruction memory. (less latency) | |
1394f032 BW |
579 | |
580 | config IDLE_L1 | |
581 | bool "Locate frequently idle function in L1 Memory" | |
582 | default y | |
583 | help | |
01dd2fbf ML |
584 | If enabled, the frequently called idle function is linked |
585 | into L1 instruction memory. (less latency) | |
1394f032 BW |
586 | |
587 | config SCHEDULE_L1 | |
588 | bool "Locate kernel schedule function in L1 Memory" | |
589 | default y | |
590 | help | |
01dd2fbf ML |
591 | If enabled, the frequently called kernel schedule is linked |
592 | into L1 instruction memory. (less latency) | |
1394f032 BW |
593 | |
594 | config ARITHMETIC_OPS_L1 | |
595 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
596 | default y | |
597 | help | |
01dd2fbf ML |
598 | If enabled, arithmetic functions are linked |
599 | into L1 instruction memory. (less latency) | |
1394f032 BW |
600 | |
601 | config ACCESS_OK_L1 | |
602 | bool "Locate access_ok function in L1 Memory" | |
603 | default y | |
604 | help | |
01dd2fbf ML |
605 | If enabled, the access_ok function is linked |
606 | into L1 instruction memory. (less latency) | |
1394f032 BW |
607 | |
608 | config MEMSET_L1 | |
609 | bool "Locate memset function in L1 Memory" | |
610 | default y | |
611 | help | |
01dd2fbf ML |
612 | If enabled, the memset function is linked |
613 | into L1 instruction memory. (less latency) | |
1394f032 BW |
614 | |
615 | config MEMCPY_L1 | |
616 | bool "Locate memcpy function in L1 Memory" | |
617 | default y | |
618 | help | |
01dd2fbf ML |
619 | If enabled, the memcpy function is linked |
620 | into L1 instruction memory. (less latency) | |
1394f032 BW |
621 | |
622 | config SYS_BFIN_SPINLOCK_L1 | |
623 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
624 | default y | |
625 | help | |
01dd2fbf ML |
626 | If enabled, sys_bfin_spinlock function is linked |
627 | into L1 instruction memory. (less latency) | |
1394f032 BW |
628 | |
629 | config IP_CHECKSUM_L1 | |
630 | bool "Locate IP Checksum function in L1 Memory" | |
631 | default n | |
632 | help | |
01dd2fbf ML |
633 | If enabled, the IP Checksum function is linked |
634 | into L1 instruction memory. (less latency) | |
1394f032 BW |
635 | |
636 | config CACHELINE_ALIGNED_L1 | |
637 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
638 | default y if !BF54x |
639 | default n if BF54x | |
1394f032 BW |
640 | depends on !BF531 |
641 | help | |
01dd2fbf ML |
642 | If enabled, cacheline_anligned data is linked |
643 | into L1 data memory. (less latency) | |
1394f032 BW |
644 | |
645 | config SYSCALL_TAB_L1 | |
646 | bool "Locate Syscall Table L1 Data Memory" | |
647 | default n | |
648 | depends on !BF531 | |
649 | help | |
01dd2fbf ML |
650 | If enabled, the Syscall LUT is linked |
651 | into L1 data memory. (less latency) | |
1394f032 BW |
652 | |
653 | config CPLB_SWITCH_TAB_L1 | |
654 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
655 | default n | |
656 | depends on !BF531 | |
657 | help | |
01dd2fbf ML |
658 | If enabled, the CPLB Switch Tables are linked |
659 | into L1 data memory. (less latency) | |
1394f032 | 660 | |
ca87b7ad GY |
661 | config APP_STACK_L1 |
662 | bool "Support locating application stack in L1 Scratch Memory" | |
663 | default y | |
664 | help | |
665 | If enabled the application stack can be located in L1 | |
666 | scratch memory (less latency). | |
667 | ||
668 | Currently only works with FLAT binaries. | |
669 | ||
251383c7 RG |
670 | comment "Speed Optimizations" |
671 | config BFIN_INS_LOWOVERHEAD | |
672 | bool "ins[bwl] low overhead, higher interrupt latency" | |
673 | default y | |
674 | help | |
675 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
676 | they can be interrupted at any time (even after they have been issued | |
677 | on to the external bus), and re-issued after the interrupt occurs. | |
678 | For memory - this is not a big deal, since memory does not change if | |
679 | it sees a read. | |
680 | ||
681 | If a FIFO is sitting on the end of the read, it will see two reads, | |
682 | when the core only sees one since the FIFO receives both the read | |
683 | which is cancelled (and not delivered to the core) and the one which | |
684 | is re-issued (which is delivered to the core). | |
685 | ||
686 | To solve this, interrupts are turned off before reads occur to | |
687 | I/O space. This option controls which the overhead/latency of | |
688 | controlling interrupts during this time | |
689 | "n" turns interrupts off every read | |
690 | (higher overhead, but lower interrupt latency) | |
691 | "y" turns interrupts off every loop | |
692 | (low overhead, but longer interrupt latency) | |
693 | ||
694 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
695 | interrupt latency issues, it is safe and OK to turn this off. | |
696 | ||
1394f032 BW |
697 | endmenu |
698 | ||
699 | ||
700 | choice | |
701 | prompt "Kernel executes from" | |
702 | help | |
703 | Choose the memory type that the kernel will be running in. | |
704 | ||
705 | config RAMKERNEL | |
706 | bool "RAM" | |
707 | help | |
708 | The kernel will be resident in RAM when running. | |
709 | ||
710 | config ROMKERNEL | |
711 | bool "ROM" | |
712 | help | |
713 | The kernel will be resident in FLASH/ROM when running. | |
714 | ||
715 | endchoice | |
716 | ||
717 | source "mm/Kconfig" | |
718 | ||
780431e3 MF |
719 | config BFIN_GPTIMERS |
720 | tristate "Enable Blackfin General Purpose Timers API" | |
721 | default n | |
722 | help | |
723 | Enable support for the General Purpose Timers API. If you | |
724 | are unsure, say N. | |
725 | ||
726 | To compile this driver as a module, choose M here: the module | |
727 | will be called gptimers.ko. | |
728 | ||
1394f032 BW |
729 | config BFIN_DMA_5XX |
730 | bool "Enable DMA Support" | |
dc26aec2 | 731 | depends on (BF52x || BF53x || BF561 || BF54x || BF538 || BF539) |
1394f032 BW |
732 | default y |
733 | help | |
734 | DMA driver for BF5xx. | |
735 | ||
736 | choice | |
737 | prompt "Uncached SDRAM region" | |
738 | default DMA_UNCACHED_1M | |
247537b9 | 739 | depends on BFIN_DMA_5XX |
86ad7932 CC |
740 | config DMA_UNCACHED_4M |
741 | bool "Enable 4M DMA region" | |
1394f032 BW |
742 | config DMA_UNCACHED_2M |
743 | bool "Enable 2M DMA region" | |
744 | config DMA_UNCACHED_1M | |
745 | bool "Enable 1M DMA region" | |
746 | config DMA_UNCACHED_NONE | |
747 | bool "Disable DMA region" | |
748 | endchoice | |
749 | ||
750 | ||
751 | comment "Cache Support" | |
3bebca2d | 752 | config BFIN_ICACHE |
1394f032 | 753 | bool "Enable ICACHE" |
3bebca2d | 754 | config BFIN_DCACHE |
1394f032 | 755 | bool "Enable DCACHE" |
3bebca2d | 756 | config BFIN_DCACHE_BANKA |
1394f032 | 757 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 758 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 759 | default n |
3bebca2d RG |
760 | config BFIN_ICACHE_LOCK |
761 | bool "Enable Instruction Cache Locking" | |
1394f032 BW |
762 | |
763 | choice | |
764 | prompt "Policy" | |
3bebca2d RG |
765 | depends on BFIN_DCACHE |
766 | default BFIN_WB | |
767 | config BFIN_WB | |
1394f032 BW |
768 | bool "Write back" |
769 | help | |
770 | Write Back Policy: | |
771 | Cached data will be written back to SDRAM only when needed. | |
772 | This can give a nice increase in performance, but beware of | |
773 | broken drivers that do not properly invalidate/flush their | |
774 | cache. | |
775 | ||
776 | Write Through Policy: | |
777 | Cached data will always be written back to SDRAM when the | |
778 | cache is updated. This is a completely safe setting, but | |
779 | performance is worse than Write Back. | |
780 | ||
781 | If you are unsure of the options and you want to be safe, | |
782 | then go with Write Through. | |
783 | ||
3bebca2d | 784 | config BFIN_WT |
1394f032 BW |
785 | bool "Write through" |
786 | help | |
787 | Write Back Policy: | |
788 | Cached data will be written back to SDRAM only when needed. | |
789 | This can give a nice increase in performance, but beware of | |
790 | broken drivers that do not properly invalidate/flush their | |
791 | cache. | |
792 | ||
793 | Write Through Policy: | |
794 | Cached data will always be written back to SDRAM when the | |
795 | cache is updated. This is a completely safe setting, but | |
796 | performance is worse than Write Back. | |
797 | ||
798 | If you are unsure of the options and you want to be safe, | |
799 | then go with Write Through. | |
800 | ||
801 | endchoice | |
802 | ||
f099f39a SZ |
803 | config BFIN_L2_CACHEABLE |
804 | bool "Cache L2 SRAM" | |
805 | depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561) | |
806 | default n | |
807 | help | |
808 | Select to make L2 SRAM cacheable in L1 data and instruction cache. | |
809 | ||
b97b8a99 BS |
810 | config MPU |
811 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
812 | default n | |
813 | help | |
814 | Use the processor's MPU to protect applications from accessing | |
815 | memory they do not own. This comes at a performance penalty | |
816 | and is recommended only for debugging. | |
817 | ||
1394f032 BW |
818 | comment "Asynchonous Memory Configuration" |
819 | ||
ddf416b2 | 820 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
821 | config C_AMCKEN |
822 | bool "Enable CLKOUT" | |
823 | default y | |
824 | ||
825 | config C_CDPRIO | |
826 | bool "DMA has priority over core for ext. accesses" | |
827 | default n | |
828 | ||
829 | config C_B0PEN | |
830 | depends on BF561 | |
831 | bool "Bank 0 16 bit packing enable" | |
832 | default y | |
833 | ||
834 | config C_B1PEN | |
835 | depends on BF561 | |
836 | bool "Bank 1 16 bit packing enable" | |
837 | default y | |
838 | ||
839 | config C_B2PEN | |
840 | depends on BF561 | |
841 | bool "Bank 2 16 bit packing enable" | |
842 | default y | |
843 | ||
844 | config C_B3PEN | |
845 | depends on BF561 | |
846 | bool "Bank 3 16 bit packing enable" | |
847 | default n | |
848 | ||
849 | choice | |
850 | prompt"Enable Asynchonous Memory Banks" | |
851 | default C_AMBEN_ALL | |
852 | ||
853 | config C_AMBEN | |
854 | bool "Disable All Banks" | |
855 | ||
856 | config C_AMBEN_B0 | |
857 | bool "Enable Bank 0" | |
858 | ||
859 | config C_AMBEN_B0_B1 | |
860 | bool "Enable Bank 0 & 1" | |
861 | ||
862 | config C_AMBEN_B0_B1_B2 | |
863 | bool "Enable Bank 0 & 1 & 2" | |
864 | ||
865 | config C_AMBEN_ALL | |
866 | bool "Enable All Banks" | |
867 | endchoice | |
868 | endmenu | |
869 | ||
870 | menu "EBIU_AMBCTL Control" | |
871 | config BANK_0 | |
872 | hex "Bank 0" | |
873 | default 0x7BB0 | |
874 | ||
875 | config BANK_1 | |
876 | hex "Bank 1" | |
877 | default 0x7BB0 | |
197fba56 | 878 | default 0x5558 if BF54x |
1394f032 BW |
879 | |
880 | config BANK_2 | |
881 | hex "Bank 2" | |
882 | default 0x7BB0 | |
883 | ||
884 | config BANK_3 | |
885 | hex "Bank 3" | |
886 | default 0x99B3 | |
887 | endmenu | |
888 | ||
e40540b3 SZ |
889 | config EBIU_MBSCTLVAL |
890 | hex "EBIU Bank Select Control Register" | |
891 | depends on BF54x | |
892 | default 0 | |
893 | ||
894 | config EBIU_MODEVAL | |
895 | hex "Flash Memory Mode Control Register" | |
896 | depends on BF54x | |
897 | default 1 | |
898 | ||
899 | config EBIU_FCTLVAL | |
900 | hex "Flash Memory Bank Control Register" | |
901 | depends on BF54x | |
902 | default 6 | |
1394f032 BW |
903 | endmenu |
904 | ||
905 | ############################################################################# | |
906 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
907 | ||
908 | config PCI | |
909 | bool "PCI support" | |
a95ca3b2 | 910 | depends on BROKEN |
1394f032 BW |
911 | help |
912 | Support for PCI bus. | |
913 | ||
914 | source "drivers/pci/Kconfig" | |
915 | ||
916 | config HOTPLUG | |
917 | bool "Support for hot-pluggable device" | |
918 | help | |
919 | Say Y here if you want to plug devices into your computer while | |
920 | the system is running, and be able to use them quickly. In many | |
921 | cases, the devices can likewise be unplugged at any time too. | |
922 | ||
923 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
924 | size devices such as network cards, modems or hard drives which are | |
925 | plugged into slots found on all modern laptop computers. Another | |
926 | example, used on modern desktops as well as laptops, is USB. | |
927 | ||
a81792f6 JB |
928 | Enable HOTPLUG and build a modular kernel. Get agent software |
929 | (from <http://linux-hotplug.sourceforge.net/>) and install it. | |
1394f032 BW |
930 | Then your kernel will automatically call out to a user mode "policy |
931 | agent" (/sbin/hotplug) to load modules and set up software needed | |
932 | to use devices as you hotplug them. | |
933 | ||
934 | source "drivers/pcmcia/Kconfig" | |
935 | ||
936 | source "drivers/pci/hotplug/Kconfig" | |
937 | ||
938 | endmenu | |
939 | ||
940 | menu "Executable file formats" | |
941 | ||
942 | source "fs/Kconfig.binfmt" | |
943 | ||
944 | endmenu | |
945 | ||
946 | menu "Power management options" | |
947 | source "kernel/power/Kconfig" | |
948 | ||
f4cb5700 JB |
949 | config ARCH_SUSPEND_POSSIBLE |
950 | def_bool y | |
951 | depends on !SMP | |
952 | ||
1394f032 | 953 | choice |
1efc80b5 | 954 | prompt "Standby Power Saving Mode" |
1394f032 | 955 | depends on PM |
cfefe3c6 MH |
956 | default PM_BFIN_SLEEP_DEEPER |
957 | config PM_BFIN_SLEEP_DEEPER | |
958 | bool "Sleep Deeper" | |
959 | help | |
960 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
961 | power dissipation by disabling the clock to the processor core (CCLK). | |
962 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
963 | to 0.85 V to provide the greatest power savings, while preserving the | |
964 | processor state. | |
965 | The PLL and system clock (SCLK) continue to operate at a very low | |
966 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
967 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
968 | such as GPIO interrupt or RTC activity wakes up the processor. | |
969 | Various Peripherals such as UART, SPORT, PPI may not function as | |
970 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
971 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
972 | ||
1efc80b5 MH |
973 | If unsure, select "Sleep Deeper". |
974 | ||
cfefe3c6 MH |
975 | config PM_BFIN_SLEEP |
976 | bool "Sleep" | |
977 | help | |
978 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
979 | dissipation by disabling the clock to the processor core (CCLK). | |
980 | The PLL and system clock (SCLK), however, continue to operate in | |
981 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
982 | up the processor. When in the sleep mode, system DMA access to L1 |
983 | memory is not supported. | |
984 | ||
985 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 986 | endchoice |
1394f032 | 987 | |
1394f032 | 988 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 989 | bool "Allow Wakeup from Standby by GPIO" |
1394f032 BW |
990 | |
991 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 992 | int "GPIO number" |
1394f032 BW |
993 | range 0 47 |
994 | depends on PM_WAKEUP_BY_GPIO | |
995 | default 2 if BFIN537_STAMP | |
996 | ||
997 | choice | |
998 | prompt "GPIO Polarity" | |
999 | depends on PM_WAKEUP_BY_GPIO | |
1000 | default PM_WAKEUP_GPIO_POLAR_H | |
1001 | config PM_WAKEUP_GPIO_POLAR_H | |
1002 | bool "Active High" | |
1003 | config PM_WAKEUP_GPIO_POLAR_L | |
1004 | bool "Active Low" | |
1005 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
1006 | bool "Falling EDGE" | |
1007 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
1008 | bool "Rising EDGE" | |
1009 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
1010 | bool "Both EDGE" | |
1011 | endchoice | |
1012 | ||
1efc80b5 MH |
1013 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1014 | depends on PM | |
1015 | ||
1efc80b5 MH |
1016 | config PM_BFIN_WAKE_PH6 |
1017 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
1018 | depends on PM && (BF52x || BF534 || BF536 || BF537) | |
1019 | default n | |
1020 | help | |
1021 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1022 | ||
1efc80b5 MH |
1023 | config PM_BFIN_WAKE_GP |
1024 | bool "Allow Wake-Up from GPIOs" | |
1025 | depends on PM && BF54x | |
1026 | default n | |
1027 | help | |
1028 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
1394f032 BW |
1029 | endmenu |
1030 | ||
1394f032 BW |
1031 | menu "CPU Frequency scaling" |
1032 | ||
1033 | source "drivers/cpufreq/Kconfig" | |
1034 | ||
14b03204 MH |
1035 | config CPU_VOLTAGE |
1036 | bool "CPU Voltage scaling" | |
1037 | depends on EXPERIMENTAL | |
1038 | depends on CPU_FREQ | |
1039 | default n | |
1040 | help | |
1041 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1042 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
1043 | manuals. There is a theoretical risk that during VDDINT transitions | |
1044 | the PLL may unlock. | |
1045 | ||
1394f032 BW |
1046 | endmenu |
1047 | ||
1394f032 BW |
1048 | source "net/Kconfig" |
1049 | ||
1050 | source "drivers/Kconfig" | |
1051 | ||
1052 | source "fs/Kconfig" | |
1053 | ||
74ce8322 | 1054 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1055 | |
1056 | source "security/Kconfig" | |
1057 | ||
1058 | source "crypto/Kconfig" | |
1059 | ||
1060 | source "lib/Kconfig" |