Commit | Line | Data |
---|---|---|
1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
9 | bool | |
10 | default n | |
11 | ||
12 | config FPU | |
13 | bool | |
14 | default n | |
15 | ||
16 | config RWSEM_GENERIC_SPINLOCK | |
17 | bool | |
18 | default y | |
19 | ||
20 | config RWSEM_XCHGADD_ALGORITHM | |
21 | bool | |
22 | default n | |
23 | ||
24 | config BLACKFIN | |
25 | bool | |
26 | default y | |
ec7748b5 | 27 | select HAVE_IDE |
42d4b839 | 28 | select HAVE_OPROFILE |
1394f032 | 29 | |
e3defffe AL |
30 | config ZONE_DMA |
31 | bool | |
32 | default y | |
33 | ||
1394f032 BW |
34 | config GENERIC_FIND_NEXT_BIT |
35 | bool | |
36 | default y | |
37 | ||
38 | config GENERIC_HWEIGHT | |
39 | bool | |
40 | default y | |
41 | ||
42 | config GENERIC_HARDIRQS | |
43 | bool | |
44 | default y | |
45 | ||
46 | config GENERIC_IRQ_PROBE | |
e4e9a7ad | 47 | bool |
1394f032 BW |
48 | default y |
49 | ||
b2d1583f | 50 | config GENERIC_GPIO |
1394f032 BW |
51 | bool |
52 | default y | |
53 | ||
54 | config FORCE_MAX_ZONEORDER | |
55 | int | |
56 | default "14" | |
57 | ||
58 | config GENERIC_CALIBRATE_DELAY | |
59 | bool | |
60 | default y | |
61 | ||
7d2284b0 MD |
62 | config HARDWARE_PM |
63 | def_bool y | |
64 | depends on OPROFILE | |
65 | ||
1394f032 | 66 | source "init/Kconfig" |
dc52ddc0 | 67 | |
1394f032 BW |
68 | source "kernel/Kconfig.preempt" |
69 | ||
dc52ddc0 MH |
70 | source "kernel/Kconfig.freezer" |
71 | ||
1394f032 BW |
72 | menu "Blackfin Processor Options" |
73 | ||
74 | comment "Processor and Board Settings" | |
75 | ||
76 | choice | |
77 | prompt "CPU" | |
78 | default BF533 | |
79 | ||
59003145 MH |
80 | config BF522 |
81 | bool "BF522" | |
82 | help | |
83 | BF522 Processor Support. | |
84 | ||
1545a111 MF |
85 | config BF523 |
86 | bool "BF523" | |
87 | help | |
88 | BF523 Processor Support. | |
89 | ||
90 | config BF524 | |
91 | bool "BF524" | |
92 | help | |
93 | BF524 Processor Support. | |
94 | ||
59003145 MH |
95 | config BF525 |
96 | bool "BF525" | |
97 | help | |
98 | BF525 Processor Support. | |
99 | ||
1545a111 MF |
100 | config BF526 |
101 | bool "BF526" | |
102 | help | |
103 | BF526 Processor Support. | |
104 | ||
59003145 MH |
105 | config BF527 |
106 | bool "BF527" | |
107 | help | |
108 | BF527 Processor Support. | |
109 | ||
1394f032 BW |
110 | config BF531 |
111 | bool "BF531" | |
112 | help | |
113 | BF531 Processor Support. | |
114 | ||
115 | config BF532 | |
116 | bool "BF532" | |
117 | help | |
118 | BF532 Processor Support. | |
119 | ||
120 | config BF533 | |
121 | bool "BF533" | |
122 | help | |
123 | BF533 Processor Support. | |
124 | ||
125 | config BF534 | |
126 | bool "BF534" | |
127 | help | |
128 | BF534 Processor Support. | |
129 | ||
130 | config BF536 | |
131 | bool "BF536" | |
132 | help | |
133 | BF536 Processor Support. | |
134 | ||
135 | config BF537 | |
136 | bool "BF537" | |
137 | help | |
138 | BF537 Processor Support. | |
139 | ||
24a07a12 RH |
140 | config BF542 |
141 | bool "BF542" | |
142 | help | |
143 | BF542 Processor Support. | |
144 | ||
145 | config BF544 | |
146 | bool "BF544" | |
147 | help | |
148 | BF544 Processor Support. | |
149 | ||
7c7fd170 MF |
150 | config BF547 |
151 | bool "BF547" | |
152 | help | |
153 | BF547 Processor Support. | |
154 | ||
24a07a12 RH |
155 | config BF548 |
156 | bool "BF548" | |
157 | help | |
158 | BF548 Processor Support. | |
159 | ||
160 | config BF549 | |
161 | bool "BF549" | |
162 | help | |
163 | BF549 Processor Support. | |
164 | ||
1394f032 BW |
165 | config BF561 |
166 | bool "BF561" | |
167 | help | |
cd88b4dc | 168 | BF561 Processor Support. |
1394f032 BW |
169 | |
170 | endchoice | |
171 | ||
0c0497c2 MF |
172 | config BF_REV_MIN |
173 | int | |
174 | default 0 if (BF52x || BF54x) | |
175 | default 2 if (BF537 || BF536 || BF534) | |
176 | default 3 if (BF561 ||BF533 || BF532 || BF531) | |
177 | ||
178 | config BF_REV_MAX | |
179 | int | |
180 | default 2 if (BF52x || BF54x) | |
181 | default 3 if (BF537 || BF536 || BF534) | |
182 | default 5 if (BF561) | |
183 | default 6 if (BF533 || BF532 || BF531) | |
184 | ||
1394f032 BW |
185 | choice |
186 | prompt "Silicon Rev" | |
46ce0d9a MF |
187 | default BF_REV_0_1 if (BF52x || BF54x) |
188 | default BF_REV_0_2 if (BF534 || BF536 || BF537) | |
189 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561) | |
24a07a12 RH |
190 | |
191 | config BF_REV_0_0 | |
192 | bool "0.0" | |
d07f4380 | 193 | depends on (BF52x || BF54x) |
59003145 MH |
194 | |
195 | config BF_REV_0_1 | |
d07f4380 MF |
196 | bool "0.1" |
197 | depends on (BF52x || BF54x) | |
1394f032 BW |
198 | |
199 | config BF_REV_0_2 | |
200 | bool "0.2" | |
49f7253c | 201 | depends on (BF52x || BF537 || BF536 || BF534 || BF54x) |
1394f032 BW |
202 | |
203 | config BF_REV_0_3 | |
204 | bool "0.3" | |
205 | depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) | |
206 | ||
207 | config BF_REV_0_4 | |
208 | bool "0.4" | |
209 | depends on (BF561 || BF533 || BF532 || BF531) | |
210 | ||
211 | config BF_REV_0_5 | |
212 | bool "0.5" | |
213 | depends on (BF561 || BF533 || BF532 || BF531) | |
214 | ||
49f7253c MF |
215 | config BF_REV_0_6 |
216 | bool "0.6" | |
217 | depends on (BF533 || BF532 || BF531) | |
218 | ||
de3025f4 JZ |
219 | config BF_REV_ANY |
220 | bool "any" | |
221 | ||
222 | config BF_REV_NONE | |
223 | bool "none" | |
224 | ||
1394f032 BW |
225 | endchoice |
226 | ||
59003145 MH |
227 | config BF52x |
228 | bool | |
1545a111 | 229 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
59003145 MH |
230 | default y |
231 | ||
24a07a12 RH |
232 | config BF53x |
233 | bool | |
234 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
235 | default y | |
236 | ||
237 | config BF54x | |
238 | bool | |
7c7fd170 | 239 | depends on (BF542 || BF544 || BF547 || BF548 || BF549) |
24a07a12 RH |
240 | default y |
241 | ||
1394f032 BW |
242 | config MEM_GENERIC_BOARD |
243 | bool | |
244 | depends on GENERIC_BOARD | |
245 | default y | |
246 | ||
247 | config MEM_MT48LC64M4A2FB_7E | |
248 | bool | |
249 | depends on (BFIN533_STAMP) | |
250 | default y | |
251 | ||
252 | config MEM_MT48LC16M16A2TG_75 | |
253 | bool | |
254 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
ab472a04 | 255 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
9db144fe | 256 | || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM) |
1394f032 BW |
257 | default y |
258 | ||
259 | config MEM_MT48LC32M8A2_75 | |
260 | bool | |
261 | depends on (BFIN537_STAMP || PNAV10) | |
262 | default y | |
263 | ||
264 | config MEM_MT48LC8M32B2B5_7 | |
265 | bool | |
266 | depends on (BFIN561_BLUETECHNIX_CM) | |
267 | default y | |
268 | ||
59003145 MH |
269 | config MEM_MT48LC32M16A2TG_75 |
270 | bool | |
8cc7117e | 271 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) |
59003145 MH |
272 | default y |
273 | ||
59003145 | 274 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
275 | source "arch/blackfin/mach-bf533/Kconfig" |
276 | source "arch/blackfin/mach-bf561/Kconfig" | |
277 | source "arch/blackfin/mach-bf537/Kconfig" | |
24a07a12 | 278 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
279 | |
280 | menu "Board customizations" | |
281 | ||
282 | config CMDLINE_BOOL | |
283 | bool "Default bootloader kernel arguments" | |
284 | ||
285 | config CMDLINE | |
286 | string "Initial kernel command string" | |
287 | depends on CMDLINE_BOOL | |
288 | default "console=ttyBF0,57600" | |
289 | help | |
290 | If you don't have a boot loader capable of passing a command line string | |
291 | to the kernel, you may specify one here. As a minimum, you should specify | |
292 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
293 | ||
5f004c20 MF |
294 | config BOOT_LOAD |
295 | hex "Kernel load address for booting" | |
296 | default "0x1000" | |
297 | range 0x1000 0x20000000 | |
298 | help | |
299 | This option allows you to set the load address of the kernel. | |
300 | This can be useful if you are on a board which has a small amount | |
301 | of memory or you wish to reserve some memory at the beginning of | |
302 | the address space. | |
303 | ||
304 | Note that you need to keep this value above 4k (0x1000) as this | |
305 | memory region is used to capture NULL pointer references as well | |
306 | as some core kernel functions. | |
307 | ||
8cc7117e MH |
308 | config ROM_BASE |
309 | hex "Kernel ROM Base" | |
310 | default "0x20040000" | |
311 | range 0x20000000 0x20400000 if !(BF54x || BF561) | |
312 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
313 | help | |
314 | ||
f16295e7 | 315 | comment "Clock/PLL Setup" |
1394f032 BW |
316 | |
317 | config CLKIN_HZ | |
2fb6cb41 | 318 | int "Frequency of the crystal on the board in Hz" |
1394f032 BW |
319 | default "11059200" if BFIN533_STAMP |
320 | default "27000000" if BFIN533_EZKIT | |
8cc7117e | 321 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD) |
1394f032 BW |
322 | default "30000000" if BFIN561_EZKIT |
323 | default "24576000" if PNAV10 | |
5d1617b2 | 324 | default "10000000" if BFIN532_IP0X |
1394f032 BW |
325 | help |
326 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
327 | Warning: This value should match the crystal on the board. Otherwise, |
328 | peripherals won't work properly. | |
1394f032 | 329 | |
f16295e7 RG |
330 | config BFIN_KERNEL_CLOCK |
331 | bool "Re-program Clocks while Kernel boots?" | |
332 | default n | |
333 | help | |
334 | This option decides if kernel clocks are re-programed from the | |
335 | bootloader settings. If the clocks are not set, the SDRAM settings | |
336 | are also not changed, and the Bootloader does 100% of the hardware | |
337 | configuration. | |
338 | ||
339 | config PLL_BYPASS | |
e4e9a7ad MF |
340 | bool "Bypass PLL" |
341 | depends on BFIN_KERNEL_CLOCK | |
342 | default n | |
f16295e7 RG |
343 | |
344 | config CLKIN_HALF | |
345 | bool "Half Clock In" | |
346 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
347 | default n | |
348 | help | |
349 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
350 | ||
351 | config VCO_MULT | |
352 | int "VCO Multiplier" | |
353 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
354 | range 1 64 | |
355 | default "22" if BFIN533_EZKIT | |
356 | default "45" if BFIN533_STAMP | |
db68254f | 357 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) |
f16295e7 | 358 | default "22" if BFIN533_BLUETECHNIX_CM |
9db144fe | 359 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 360 | default "20" if BFIN561_EZKIT |
8cc7117e | 361 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD) |
f16295e7 RG |
362 | help |
363 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
364 | PLL Frequency = (Crystal Frequency) * (this setting) | |
365 | ||
366 | choice | |
367 | prompt "Core Clock Divider" | |
368 | depends on BFIN_KERNEL_CLOCK | |
369 | default CCLK_DIV_1 | |
370 | help | |
371 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
372 | Core Frequency = (PLL frequency) / (this setting) | |
373 | ||
374 | config CCLK_DIV_1 | |
375 | bool "1" | |
376 | ||
377 | config CCLK_DIV_2 | |
378 | bool "2" | |
379 | ||
380 | config CCLK_DIV_4 | |
381 | bool "4" | |
382 | ||
383 | config CCLK_DIV_8 | |
384 | bool "8" | |
385 | endchoice | |
386 | ||
387 | config SCLK_DIV | |
388 | int "System Clock Divider" | |
389 | depends on BFIN_KERNEL_CLOCK | |
390 | range 1 15 | |
5f004c20 | 391 | default 5 |
f16295e7 RG |
392 | help |
393 | This sets the frequency of the system clock (including SDRAM or DDR). | |
394 | This can be between 1 and 15 | |
395 | System Clock = (PLL frequency) / (this setting) | |
396 | ||
5f004c20 MF |
397 | choice |
398 | prompt "DDR SDRAM Chip Type" | |
399 | depends on BFIN_KERNEL_CLOCK | |
400 | depends on BF54x | |
401 | default MEM_MT46V32M16_5B | |
402 | ||
403 | config MEM_MT46V32M16_6T | |
404 | bool "MT46V32M16_6T" | |
405 | ||
406 | config MEM_MT46V32M16_5B | |
407 | bool "MT46V32M16_5B" | |
408 | endchoice | |
409 | ||
7eb2c23f MF |
410 | config MAX_MEM_SIZE |
411 | int "Max SDRAM Memory Size in MBytes" | |
412 | depends on !MPU | |
413 | default 512 | |
414 | help | |
415 | This is the max memory size that the kernel will create CPLB | |
416 | tables for. Your system will not be able to handle any more. | |
417 | ||
f16295e7 RG |
418 | # |
419 | # Max & Min Speeds for various Chips | |
420 | # | |
421 | config MAX_VCO_HZ | |
422 | int | |
423 | default 600000000 if BF522 | |
1545a111 MF |
424 | default 400000000 if BF523 |
425 | default 400000000 if BF524 | |
f16295e7 | 426 | default 600000000 if BF525 |
1545a111 | 427 | default 400000000 if BF526 |
f16295e7 RG |
428 | default 600000000 if BF527 |
429 | default 400000000 if BF531 | |
430 | default 400000000 if BF532 | |
431 | default 750000000 if BF533 | |
432 | default 500000000 if BF534 | |
433 | default 400000000 if BF536 | |
434 | default 600000000 if BF537 | |
f72eecb9 RG |
435 | default 533333333 if BF538 |
436 | default 533333333 if BF539 | |
f16295e7 | 437 | default 600000000 if BF542 |
f72eecb9 | 438 | default 533333333 if BF544 |
1545a111 MF |
439 | default 600000000 if BF547 |
440 | default 600000000 if BF548 | |
f72eecb9 | 441 | default 533333333 if BF549 |
f16295e7 RG |
442 | default 600000000 if BF561 |
443 | ||
444 | config MIN_VCO_HZ | |
445 | int | |
446 | default 50000000 | |
447 | ||
448 | config MAX_SCLK_HZ | |
449 | int | |
f72eecb9 | 450 | default 133333333 |
f16295e7 RG |
451 | |
452 | config MIN_SCLK_HZ | |
453 | int | |
454 | default 27000000 | |
455 | ||
456 | comment "Kernel Timer/Scheduler" | |
457 | ||
458 | source kernel/Kconfig.hz | |
459 | ||
8b5f79f9 VM |
460 | config GENERIC_TIME |
461 | bool "Generic time" | |
462 | default y | |
463 | ||
464 | config GENERIC_CLOCKEVENTS | |
465 | bool "Generic clock events" | |
466 | depends on GENERIC_TIME | |
467 | default y | |
468 | ||
469 | config CYCLES_CLOCKSOURCE | |
470 | bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)" | |
471 | depends on EXPERIMENTAL | |
472 | depends on GENERIC_CLOCKEVENTS | |
473 | depends on !BFIN_SCRATCH_REG_CYCLES | |
474 | default n | |
475 | help | |
476 | If you say Y here, you will enable support for using the 'cycles' | |
477 | registers as a clock source. Doing so means you will be unable to | |
478 | safely write to the 'cycles' register during runtime. You will | |
479 | still be able to read it (such as for performance monitoring), but | |
480 | writing the registers will most likely crash the kernel. | |
481 | ||
482 | source kernel/time/Kconfig | |
483 | ||
5f004c20 | 484 | comment "Misc" |
971d5bc4 | 485 | |
f0b5d12f MF |
486 | choice |
487 | prompt "Blackfin Exception Scratch Register" | |
488 | default BFIN_SCRATCH_REG_RETN | |
489 | help | |
490 | Select the resource to reserve for the Exception handler: | |
491 | - RETN: Non-Maskable Interrupt (NMI) | |
492 | - RETE: Exception Return (JTAG/ICE) | |
493 | - CYCLES: Performance counter | |
494 | ||
495 | If you are unsure, please select "RETN". | |
496 | ||
497 | config BFIN_SCRATCH_REG_RETN | |
498 | bool "RETN" | |
499 | help | |
500 | Use the RETN register in the Blackfin exception handler | |
501 | as a stack scratch register. This means you cannot | |
502 | safely use NMI on the Blackfin while running Linux, but | |
503 | you can debug the system with a JTAG ICE and use the | |
504 | CYCLES performance registers. | |
505 | ||
506 | If you are unsure, please select "RETN". | |
507 | ||
508 | config BFIN_SCRATCH_REG_RETE | |
509 | bool "RETE" | |
510 | help | |
511 | Use the RETE register in the Blackfin exception handler | |
512 | as a stack scratch register. This means you cannot | |
513 | safely use a JTAG ICE while debugging a Blackfin board, | |
514 | but you can safely use the CYCLES performance registers | |
515 | and the NMI. | |
516 | ||
517 | If you are unsure, please select "RETN". | |
518 | ||
519 | config BFIN_SCRATCH_REG_CYCLES | |
520 | bool "CYCLES" | |
521 | help | |
522 | Use the CYCLES register in the Blackfin exception handler | |
523 | as a stack scratch register. This means you cannot | |
524 | safely use the CYCLES performance registers on a Blackfin | |
525 | board at anytime, but you can debug the system with a JTAG | |
526 | ICE and use the NMI. | |
527 | ||
528 | If you are unsure, please select "RETN". | |
529 | ||
530 | endchoice | |
531 | ||
1394f032 BW |
532 | endmenu |
533 | ||
534 | ||
535 | menu "Blackfin Kernel Optimizations" | |
536 | ||
1394f032 BW |
537 | comment "Memory Optimizations" |
538 | ||
539 | config I_ENTRY_L1 | |
540 | bool "Locate interrupt entry code in L1 Memory" | |
541 | default y | |
542 | help | |
01dd2fbf ML |
543 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
544 | into L1 instruction memory. (less latency) | |
1394f032 BW |
545 | |
546 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 547 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
548 | default y |
549 | help | |
01dd2fbf | 550 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 551 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 552 | (less latency) |
1394f032 BW |
553 | |
554 | config DO_IRQ_L1 | |
555 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
556 | default y | |
557 | help | |
01dd2fbf ML |
558 | If enabled, the frequently called do_irq dispatcher function is linked |
559 | into L1 instruction memory. (less latency) | |
1394f032 BW |
560 | |
561 | config CORE_TIMER_IRQ_L1 | |
562 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
563 | default y | |
564 | help | |
01dd2fbf ML |
565 | If enabled, the frequently called timer_interrupt() function is linked |
566 | into L1 instruction memory. (less latency) | |
1394f032 BW |
567 | |
568 | config IDLE_L1 | |
569 | bool "Locate frequently idle function in L1 Memory" | |
570 | default y | |
571 | help | |
01dd2fbf ML |
572 | If enabled, the frequently called idle function is linked |
573 | into L1 instruction memory. (less latency) | |
1394f032 BW |
574 | |
575 | config SCHEDULE_L1 | |
576 | bool "Locate kernel schedule function in L1 Memory" | |
577 | default y | |
578 | help | |
01dd2fbf ML |
579 | If enabled, the frequently called kernel schedule is linked |
580 | into L1 instruction memory. (less latency) | |
1394f032 BW |
581 | |
582 | config ARITHMETIC_OPS_L1 | |
583 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
584 | default y | |
585 | help | |
01dd2fbf ML |
586 | If enabled, arithmetic functions are linked |
587 | into L1 instruction memory. (less latency) | |
1394f032 BW |
588 | |
589 | config ACCESS_OK_L1 | |
590 | bool "Locate access_ok function in L1 Memory" | |
591 | default y | |
592 | help | |
01dd2fbf ML |
593 | If enabled, the access_ok function is linked |
594 | into L1 instruction memory. (less latency) | |
1394f032 BW |
595 | |
596 | config MEMSET_L1 | |
597 | bool "Locate memset function in L1 Memory" | |
598 | default y | |
599 | help | |
01dd2fbf ML |
600 | If enabled, the memset function is linked |
601 | into L1 instruction memory. (less latency) | |
1394f032 BW |
602 | |
603 | config MEMCPY_L1 | |
604 | bool "Locate memcpy function in L1 Memory" | |
605 | default y | |
606 | help | |
01dd2fbf ML |
607 | If enabled, the memcpy function is linked |
608 | into L1 instruction memory. (less latency) | |
1394f032 BW |
609 | |
610 | config SYS_BFIN_SPINLOCK_L1 | |
611 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
612 | default y | |
613 | help | |
01dd2fbf ML |
614 | If enabled, sys_bfin_spinlock function is linked |
615 | into L1 instruction memory. (less latency) | |
1394f032 BW |
616 | |
617 | config IP_CHECKSUM_L1 | |
618 | bool "Locate IP Checksum function in L1 Memory" | |
619 | default n | |
620 | help | |
01dd2fbf ML |
621 | If enabled, the IP Checksum function is linked |
622 | into L1 instruction memory. (less latency) | |
1394f032 BW |
623 | |
624 | config CACHELINE_ALIGNED_L1 | |
625 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
626 | default y if !BF54x |
627 | default n if BF54x | |
1394f032 BW |
628 | depends on !BF531 |
629 | help | |
01dd2fbf ML |
630 | If enabled, cacheline_anligned data is linked |
631 | into L1 data memory. (less latency) | |
1394f032 BW |
632 | |
633 | config SYSCALL_TAB_L1 | |
634 | bool "Locate Syscall Table L1 Data Memory" | |
635 | default n | |
636 | depends on !BF531 | |
637 | help | |
01dd2fbf ML |
638 | If enabled, the Syscall LUT is linked |
639 | into L1 data memory. (less latency) | |
1394f032 BW |
640 | |
641 | config CPLB_SWITCH_TAB_L1 | |
642 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
643 | default n | |
644 | depends on !BF531 | |
645 | help | |
01dd2fbf ML |
646 | If enabled, the CPLB Switch Tables are linked |
647 | into L1 data memory. (less latency) | |
1394f032 | 648 | |
ca87b7ad GY |
649 | config APP_STACK_L1 |
650 | bool "Support locating application stack in L1 Scratch Memory" | |
651 | default y | |
652 | help | |
653 | If enabled the application stack can be located in L1 | |
654 | scratch memory (less latency). | |
655 | ||
656 | Currently only works with FLAT binaries. | |
657 | ||
251383c7 RG |
658 | comment "Speed Optimizations" |
659 | config BFIN_INS_LOWOVERHEAD | |
660 | bool "ins[bwl] low overhead, higher interrupt latency" | |
661 | default y | |
662 | help | |
663 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
664 | they can be interrupted at any time (even after they have been issued | |
665 | on to the external bus), and re-issued after the interrupt occurs. | |
666 | For memory - this is not a big deal, since memory does not change if | |
667 | it sees a read. | |
668 | ||
669 | If a FIFO is sitting on the end of the read, it will see two reads, | |
670 | when the core only sees one since the FIFO receives both the read | |
671 | which is cancelled (and not delivered to the core) and the one which | |
672 | is re-issued (which is delivered to the core). | |
673 | ||
674 | To solve this, interrupts are turned off before reads occur to | |
675 | I/O space. This option controls which the overhead/latency of | |
676 | controlling interrupts during this time | |
677 | "n" turns interrupts off every read | |
678 | (higher overhead, but lower interrupt latency) | |
679 | "y" turns interrupts off every loop | |
680 | (low overhead, but longer interrupt latency) | |
681 | ||
682 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
683 | interrupt latency issues, it is safe and OK to turn this off. | |
684 | ||
1394f032 BW |
685 | endmenu |
686 | ||
687 | ||
688 | choice | |
689 | prompt "Kernel executes from" | |
690 | help | |
691 | Choose the memory type that the kernel will be running in. | |
692 | ||
693 | config RAMKERNEL | |
694 | bool "RAM" | |
695 | help | |
696 | The kernel will be resident in RAM when running. | |
697 | ||
698 | config ROMKERNEL | |
699 | bool "ROM" | |
700 | help | |
701 | The kernel will be resident in FLASH/ROM when running. | |
702 | ||
703 | endchoice | |
704 | ||
705 | source "mm/Kconfig" | |
706 | ||
780431e3 MF |
707 | config BFIN_GPTIMERS |
708 | tristate "Enable Blackfin General Purpose Timers API" | |
709 | default n | |
710 | help | |
711 | Enable support for the General Purpose Timers API. If you | |
712 | are unsure, say N. | |
713 | ||
714 | To compile this driver as a module, choose M here: the module | |
715 | will be called gptimers.ko. | |
716 | ||
1394f032 BW |
717 | config BFIN_DMA_5XX |
718 | bool "Enable DMA Support" | |
59003145 | 719 | depends on (BF52x || BF53x || BF561 || BF54x) |
1394f032 BW |
720 | default y |
721 | help | |
722 | DMA driver for BF5xx. | |
723 | ||
724 | choice | |
725 | prompt "Uncached SDRAM region" | |
726 | default DMA_UNCACHED_1M | |
247537b9 | 727 | depends on BFIN_DMA_5XX |
86ad7932 CC |
728 | config DMA_UNCACHED_4M |
729 | bool "Enable 4M DMA region" | |
1394f032 BW |
730 | config DMA_UNCACHED_2M |
731 | bool "Enable 2M DMA region" | |
732 | config DMA_UNCACHED_1M | |
733 | bool "Enable 1M DMA region" | |
734 | config DMA_UNCACHED_NONE | |
735 | bool "Disable DMA region" | |
736 | endchoice | |
737 | ||
738 | ||
739 | comment "Cache Support" | |
3bebca2d | 740 | config BFIN_ICACHE |
1394f032 | 741 | bool "Enable ICACHE" |
3bebca2d | 742 | config BFIN_DCACHE |
1394f032 | 743 | bool "Enable DCACHE" |
3bebca2d | 744 | config BFIN_DCACHE_BANKA |
1394f032 | 745 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 746 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 747 | default n |
3bebca2d RG |
748 | config BFIN_ICACHE_LOCK |
749 | bool "Enable Instruction Cache Locking" | |
1394f032 BW |
750 | |
751 | choice | |
752 | prompt "Policy" | |
3bebca2d RG |
753 | depends on BFIN_DCACHE |
754 | default BFIN_WB | |
755 | config BFIN_WB | |
1394f032 BW |
756 | bool "Write back" |
757 | help | |
758 | Write Back Policy: | |
759 | Cached data will be written back to SDRAM only when needed. | |
760 | This can give a nice increase in performance, but beware of | |
761 | broken drivers that do not properly invalidate/flush their | |
762 | cache. | |
763 | ||
764 | Write Through Policy: | |
765 | Cached data will always be written back to SDRAM when the | |
766 | cache is updated. This is a completely safe setting, but | |
767 | performance is worse than Write Back. | |
768 | ||
769 | If you are unsure of the options and you want to be safe, | |
770 | then go with Write Through. | |
771 | ||
3bebca2d | 772 | config BFIN_WT |
1394f032 BW |
773 | bool "Write through" |
774 | help | |
775 | Write Back Policy: | |
776 | Cached data will be written back to SDRAM only when needed. | |
777 | This can give a nice increase in performance, but beware of | |
778 | broken drivers that do not properly invalidate/flush their | |
779 | cache. | |
780 | ||
781 | Write Through Policy: | |
782 | Cached data will always be written back to SDRAM when the | |
783 | cache is updated. This is a completely safe setting, but | |
784 | performance is worse than Write Back. | |
785 | ||
786 | If you are unsure of the options and you want to be safe, | |
787 | then go with Write Through. | |
788 | ||
789 | endchoice | |
790 | ||
f099f39a SZ |
791 | config BFIN_L2_CACHEABLE |
792 | bool "Cache L2 SRAM" | |
793 | depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561) | |
794 | default n | |
795 | help | |
796 | Select to make L2 SRAM cacheable in L1 data and instruction cache. | |
797 | ||
b97b8a99 BS |
798 | config MPU |
799 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
800 | default n | |
801 | help | |
802 | Use the processor's MPU to protect applications from accessing | |
803 | memory they do not own. This comes at a performance penalty | |
804 | and is recommended only for debugging. | |
805 | ||
1394f032 BW |
806 | comment "Asynchonous Memory Configuration" |
807 | ||
ddf416b2 | 808 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
809 | config C_AMCKEN |
810 | bool "Enable CLKOUT" | |
811 | default y | |
812 | ||
813 | config C_CDPRIO | |
814 | bool "DMA has priority over core for ext. accesses" | |
815 | default n | |
816 | ||
817 | config C_B0PEN | |
818 | depends on BF561 | |
819 | bool "Bank 0 16 bit packing enable" | |
820 | default y | |
821 | ||
822 | config C_B1PEN | |
823 | depends on BF561 | |
824 | bool "Bank 1 16 bit packing enable" | |
825 | default y | |
826 | ||
827 | config C_B2PEN | |
828 | depends on BF561 | |
829 | bool "Bank 2 16 bit packing enable" | |
830 | default y | |
831 | ||
832 | config C_B3PEN | |
833 | depends on BF561 | |
834 | bool "Bank 3 16 bit packing enable" | |
835 | default n | |
836 | ||
837 | choice | |
838 | prompt"Enable Asynchonous Memory Banks" | |
839 | default C_AMBEN_ALL | |
840 | ||
841 | config C_AMBEN | |
842 | bool "Disable All Banks" | |
843 | ||
844 | config C_AMBEN_B0 | |
845 | bool "Enable Bank 0" | |
846 | ||
847 | config C_AMBEN_B0_B1 | |
848 | bool "Enable Bank 0 & 1" | |
849 | ||
850 | config C_AMBEN_B0_B1_B2 | |
851 | bool "Enable Bank 0 & 1 & 2" | |
852 | ||
853 | config C_AMBEN_ALL | |
854 | bool "Enable All Banks" | |
855 | endchoice | |
856 | endmenu | |
857 | ||
858 | menu "EBIU_AMBCTL Control" | |
859 | config BANK_0 | |
860 | hex "Bank 0" | |
861 | default 0x7BB0 | |
862 | ||
863 | config BANK_1 | |
864 | hex "Bank 1" | |
865 | default 0x7BB0 | |
197fba56 | 866 | default 0x5558 if BF54x |
1394f032 BW |
867 | |
868 | config BANK_2 | |
869 | hex "Bank 2" | |
870 | default 0x7BB0 | |
871 | ||
872 | config BANK_3 | |
873 | hex "Bank 3" | |
874 | default 0x99B3 | |
875 | endmenu | |
876 | ||
e40540b3 SZ |
877 | config EBIU_MBSCTLVAL |
878 | hex "EBIU Bank Select Control Register" | |
879 | depends on BF54x | |
880 | default 0 | |
881 | ||
882 | config EBIU_MODEVAL | |
883 | hex "Flash Memory Mode Control Register" | |
884 | depends on BF54x | |
885 | default 1 | |
886 | ||
887 | config EBIU_FCTLVAL | |
888 | hex "Flash Memory Bank Control Register" | |
889 | depends on BF54x | |
890 | default 6 | |
1394f032 BW |
891 | endmenu |
892 | ||
893 | ############################################################################# | |
894 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
895 | ||
896 | config PCI | |
897 | bool "PCI support" | |
a95ca3b2 | 898 | depends on BROKEN |
1394f032 BW |
899 | help |
900 | Support for PCI bus. | |
901 | ||
902 | source "drivers/pci/Kconfig" | |
903 | ||
904 | config HOTPLUG | |
905 | bool "Support for hot-pluggable device" | |
906 | help | |
907 | Say Y here if you want to plug devices into your computer while | |
908 | the system is running, and be able to use them quickly. In many | |
909 | cases, the devices can likewise be unplugged at any time too. | |
910 | ||
911 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
912 | size devices such as network cards, modems or hard drives which are | |
913 | plugged into slots found on all modern laptop computers. Another | |
914 | example, used on modern desktops as well as laptops, is USB. | |
915 | ||
a81792f6 JB |
916 | Enable HOTPLUG and build a modular kernel. Get agent software |
917 | (from <http://linux-hotplug.sourceforge.net/>) and install it. | |
1394f032 BW |
918 | Then your kernel will automatically call out to a user mode "policy |
919 | agent" (/sbin/hotplug) to load modules and set up software needed | |
920 | to use devices as you hotplug them. | |
921 | ||
922 | source "drivers/pcmcia/Kconfig" | |
923 | ||
924 | source "drivers/pci/hotplug/Kconfig" | |
925 | ||
926 | endmenu | |
927 | ||
928 | menu "Executable file formats" | |
929 | ||
930 | source "fs/Kconfig.binfmt" | |
931 | ||
932 | endmenu | |
933 | ||
934 | menu "Power management options" | |
935 | source "kernel/power/Kconfig" | |
936 | ||
f4cb5700 JB |
937 | config ARCH_SUSPEND_POSSIBLE |
938 | def_bool y | |
939 | depends on !SMP | |
940 | ||
1394f032 | 941 | choice |
1efc80b5 | 942 | prompt "Standby Power Saving Mode" |
1394f032 | 943 | depends on PM |
cfefe3c6 MH |
944 | default PM_BFIN_SLEEP_DEEPER |
945 | config PM_BFIN_SLEEP_DEEPER | |
946 | bool "Sleep Deeper" | |
947 | help | |
948 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
949 | power dissipation by disabling the clock to the processor core (CCLK). | |
950 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
951 | to 0.85 V to provide the greatest power savings, while preserving the | |
952 | processor state. | |
953 | The PLL and system clock (SCLK) continue to operate at a very low | |
954 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
955 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
956 | such as GPIO interrupt or RTC activity wakes up the processor. | |
957 | Various Peripherals such as UART, SPORT, PPI may not function as | |
958 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
959 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
960 | ||
1efc80b5 MH |
961 | If unsure, select "Sleep Deeper". |
962 | ||
cfefe3c6 MH |
963 | config PM_BFIN_SLEEP |
964 | bool "Sleep" | |
965 | help | |
966 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
967 | dissipation by disabling the clock to the processor core (CCLK). | |
968 | The PLL and system clock (SCLK), however, continue to operate in | |
969 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
970 | up the processor. When in the sleep mode, system DMA access to L1 |
971 | memory is not supported. | |
972 | ||
973 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 974 | endchoice |
1394f032 | 975 | |
1394f032 | 976 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 977 | bool "Allow Wakeup from Standby by GPIO" |
1394f032 BW |
978 | |
979 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 980 | int "GPIO number" |
1394f032 BW |
981 | range 0 47 |
982 | depends on PM_WAKEUP_BY_GPIO | |
983 | default 2 if BFIN537_STAMP | |
984 | ||
985 | choice | |
986 | prompt "GPIO Polarity" | |
987 | depends on PM_WAKEUP_BY_GPIO | |
988 | default PM_WAKEUP_GPIO_POLAR_H | |
989 | config PM_WAKEUP_GPIO_POLAR_H | |
990 | bool "Active High" | |
991 | config PM_WAKEUP_GPIO_POLAR_L | |
992 | bool "Active Low" | |
993 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
994 | bool "Falling EDGE" | |
995 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
996 | bool "Rising EDGE" | |
997 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
998 | bool "Both EDGE" | |
999 | endchoice | |
1000 | ||
1efc80b5 MH |
1001 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1002 | depends on PM | |
1003 | ||
1efc80b5 MH |
1004 | config PM_BFIN_WAKE_PH6 |
1005 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
1006 | depends on PM && (BF52x || BF534 || BF536 || BF537) | |
1007 | default n | |
1008 | help | |
1009 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1010 | ||
1efc80b5 MH |
1011 | config PM_BFIN_WAKE_GP |
1012 | bool "Allow Wake-Up from GPIOs" | |
1013 | depends on PM && BF54x | |
1014 | default n | |
1015 | help | |
1016 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
1394f032 BW |
1017 | endmenu |
1018 | ||
1394f032 BW |
1019 | menu "CPU Frequency scaling" |
1020 | ||
1021 | source "drivers/cpufreq/Kconfig" | |
1022 | ||
14b03204 MH |
1023 | config CPU_VOLTAGE |
1024 | bool "CPU Voltage scaling" | |
1025 | depends on EXPERIMENTAL | |
1026 | depends on CPU_FREQ | |
1027 | default n | |
1028 | help | |
1029 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1030 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
1031 | manuals. There is a theoretical risk that during VDDINT transitions | |
1032 | the PLL may unlock. | |
1033 | ||
1394f032 BW |
1034 | endmenu |
1035 | ||
1394f032 BW |
1036 | source "net/Kconfig" |
1037 | ||
1038 | source "drivers/Kconfig" | |
1039 | ||
1040 | source "fs/Kconfig" | |
1041 | ||
74ce8322 | 1042 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1043 | |
1044 | source "security/Kconfig" | |
1045 | ||
1046 | source "crypto/Kconfig" | |
1047 | ||
1048 | source "lib/Kconfig" |