Commit | Line | Data |
---|---|---|
1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 | 7 | |
9e1b9b80 AJ |
8 | config SYMBOL_PREFIX |
9 | string | |
10 | default "_" | |
11 | ||
1394f032 | 12 | config MMU |
bac7d89e | 13 | def_bool n |
1394f032 BW |
14 | |
15 | config FPU | |
bac7d89e | 16 | def_bool n |
1394f032 BW |
17 | |
18 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 19 | def_bool y |
1394f032 BW |
20 | |
21 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 22 | def_bool n |
1394f032 BW |
23 | |
24 | config BLACKFIN | |
bac7d89e | 25 | def_bool y |
1ee76d7e | 26 | select HAVE_FUNCTION_GRAPH_TRACER |
1c873be7 | 27 | select HAVE_FUNCTION_TRACER |
ec7748b5 | 28 | select HAVE_IDE |
538067c8 MF |
29 | select HAVE_KERNEL_GZIP |
30 | select HAVE_KERNEL_BZIP2 | |
31 | select HAVE_KERNEL_LZMA | |
42d4b839 | 32 | select HAVE_OPROFILE |
a4f0b32c | 33 | select ARCH_WANT_OPTIONAL_GPIOLIB |
1394f032 | 34 | |
ddf9ddac MF |
35 | config GENERIC_CSUM |
36 | def_bool y | |
37 | ||
70f12567 MF |
38 | config GENERIC_BUG |
39 | def_bool y | |
40 | depends on BUG | |
41 | ||
e3defffe | 42 | config ZONE_DMA |
bac7d89e | 43 | def_bool y |
e3defffe | 44 | |
1394f032 | 45 | config GENERIC_FIND_NEXT_BIT |
bac7d89e | 46 | def_bool y |
1394f032 | 47 | |
1394f032 | 48 | config GENERIC_HARDIRQS |
bac7d89e | 49 | def_bool y |
1394f032 BW |
50 | |
51 | config GENERIC_IRQ_PROBE | |
bac7d89e | 52 | def_bool y |
1394f032 | 53 | |
796dada9 MH |
54 | config GENERIC_HARDIRQS_NO__DO_IRQ |
55 | def_bool y | |
56 | ||
b2d1583f | 57 | config GENERIC_GPIO |
bac7d89e | 58 | def_bool y |
1394f032 BW |
59 | |
60 | config FORCE_MAX_ZONEORDER | |
61 | int | |
62 | default "14" | |
63 | ||
64 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 65 | def_bool y |
1394f032 | 66 | |
6fa68e7a MF |
67 | config LOCKDEP_SUPPORT |
68 | def_bool y | |
69 | ||
c7b412f4 MF |
70 | config STACKTRACE_SUPPORT |
71 | def_bool y | |
72 | ||
8f86001f MF |
73 | config TRACE_IRQFLAGS_SUPPORT |
74 | def_bool y | |
1394f032 | 75 | |
1394f032 | 76 | source "init/Kconfig" |
dc52ddc0 | 77 | |
1394f032 BW |
78 | source "kernel/Kconfig.preempt" |
79 | ||
dc52ddc0 MH |
80 | source "kernel/Kconfig.freezer" |
81 | ||
1394f032 BW |
82 | menu "Blackfin Processor Options" |
83 | ||
84 | comment "Processor and Board Settings" | |
85 | ||
86 | choice | |
87 | prompt "CPU" | |
88 | default BF533 | |
89 | ||
2f6f4bcd BW |
90 | config BF512 |
91 | bool "BF512" | |
92 | help | |
93 | BF512 Processor Support. | |
94 | ||
95 | config BF514 | |
96 | bool "BF514" | |
97 | help | |
98 | BF514 Processor Support. | |
99 | ||
100 | config BF516 | |
101 | bool "BF516" | |
102 | help | |
103 | BF516 Processor Support. | |
104 | ||
105 | config BF518 | |
106 | bool "BF518" | |
107 | help | |
108 | BF518 Processor Support. | |
109 | ||
59003145 MH |
110 | config BF522 |
111 | bool "BF522" | |
112 | help | |
113 | BF522 Processor Support. | |
114 | ||
1545a111 MF |
115 | config BF523 |
116 | bool "BF523" | |
117 | help | |
118 | BF523 Processor Support. | |
119 | ||
120 | config BF524 | |
121 | bool "BF524" | |
122 | help | |
123 | BF524 Processor Support. | |
124 | ||
59003145 MH |
125 | config BF525 |
126 | bool "BF525" | |
127 | help | |
128 | BF525 Processor Support. | |
129 | ||
1545a111 MF |
130 | config BF526 |
131 | bool "BF526" | |
132 | help | |
133 | BF526 Processor Support. | |
134 | ||
59003145 MH |
135 | config BF527 |
136 | bool "BF527" | |
137 | help | |
138 | BF527 Processor Support. | |
139 | ||
1394f032 BW |
140 | config BF531 |
141 | bool "BF531" | |
142 | help | |
143 | BF531 Processor Support. | |
144 | ||
145 | config BF532 | |
146 | bool "BF532" | |
147 | help | |
148 | BF532 Processor Support. | |
149 | ||
150 | config BF533 | |
151 | bool "BF533" | |
152 | help | |
153 | BF533 Processor Support. | |
154 | ||
155 | config BF534 | |
156 | bool "BF534" | |
157 | help | |
158 | BF534 Processor Support. | |
159 | ||
160 | config BF536 | |
161 | bool "BF536" | |
162 | help | |
163 | BF536 Processor Support. | |
164 | ||
165 | config BF537 | |
166 | bool "BF537" | |
167 | help | |
168 | BF537 Processor Support. | |
169 | ||
dc26aec2 MH |
170 | config BF538 |
171 | bool "BF538" | |
172 | help | |
173 | BF538 Processor Support. | |
174 | ||
175 | config BF539 | |
176 | bool "BF539" | |
177 | help | |
178 | BF539 Processor Support. | |
179 | ||
5df326ac | 180 | config BF542_std |
24a07a12 RH |
181 | bool "BF542" |
182 | help | |
183 | BF542 Processor Support. | |
184 | ||
2f89c063 MF |
185 | config BF542M |
186 | bool "BF542m" | |
187 | help | |
188 | BF542 Processor Support. | |
189 | ||
5df326ac | 190 | config BF544_std |
24a07a12 RH |
191 | bool "BF544" |
192 | help | |
193 | BF544 Processor Support. | |
194 | ||
2f89c063 MF |
195 | config BF544M |
196 | bool "BF544m" | |
197 | help | |
198 | BF544 Processor Support. | |
199 | ||
5df326ac | 200 | config BF547_std |
7c7fd170 MF |
201 | bool "BF547" |
202 | help | |
203 | BF547 Processor Support. | |
204 | ||
2f89c063 MF |
205 | config BF547M |
206 | bool "BF547m" | |
207 | help | |
208 | BF547 Processor Support. | |
209 | ||
5df326ac | 210 | config BF548_std |
24a07a12 RH |
211 | bool "BF548" |
212 | help | |
213 | BF548 Processor Support. | |
214 | ||
2f89c063 MF |
215 | config BF548M |
216 | bool "BF548m" | |
217 | help | |
218 | BF548 Processor Support. | |
219 | ||
5df326ac | 220 | config BF549_std |
24a07a12 RH |
221 | bool "BF549" |
222 | help | |
223 | BF549 Processor Support. | |
224 | ||
2f89c063 MF |
225 | config BF549M |
226 | bool "BF549m" | |
227 | help | |
228 | BF549 Processor Support. | |
229 | ||
1394f032 BW |
230 | config BF561 |
231 | bool "BF561" | |
232 | help | |
cd88b4dc | 233 | BF561 Processor Support. |
1394f032 BW |
234 | |
235 | endchoice | |
236 | ||
46fa5eec GY |
237 | config SMP |
238 | depends on BF561 | |
0d152c27 | 239 | select TICKSOURCE_CORETMR |
46fa5eec GY |
240 | bool "Symmetric multi-processing support" |
241 | ---help--- | |
242 | This enables support for systems with more than one CPU, | |
243 | like the dual core BF561. If you have a system with only one | |
244 | CPU, say N. If you have a system with more than one CPU, say Y. | |
245 | ||
246 | If you don't know what to do here, say N. | |
247 | ||
248 | config NR_CPUS | |
249 | int | |
250 | depends on SMP | |
251 | default 2 if BF561 | |
252 | ||
253 | config IRQ_PER_CPU | |
254 | bool | |
255 | depends on SMP | |
256 | default y | |
257 | ||
ead9b115 GY |
258 | config HAVE_LEGACY_PER_CPU_AREA |
259 | def_bool y | |
260 | depends on SMP | |
261 | ||
0c0497c2 MF |
262 | config BF_REV_MIN |
263 | int | |
2f89c063 | 264 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
0c0497c2 | 265 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 266 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 267 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
268 | |
269 | config BF_REV_MAX | |
270 | int | |
2f89c063 MF |
271 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) |
272 | default 3 if (BF537 || BF536 || BF534 || BF54xM) | |
2f6f4bcd | 273 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
274 | default 6 if (BF533 || BF532 || BF531) |
275 | ||
1394f032 BW |
276 | choice |
277 | prompt "Silicon Rev" | |
f8b55651 MF |
278 | default BF_REV_0_0 if (BF51x || BF52x) |
279 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) | |
2f89c063 | 280 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
281 | |
282 | config BF_REV_0_0 | |
283 | bool "0.0" | |
2f89c063 | 284 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
59003145 MH |
285 | |
286 | config BF_REV_0_1 | |
d07f4380 | 287 | bool "0.1" |
3d15f302 | 288 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
289 | |
290 | config BF_REV_0_2 | |
291 | bool "0.2" | |
2f89c063 | 292 | depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
293 | |
294 | config BF_REV_0_3 | |
295 | bool "0.3" | |
2f89c063 | 296 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
297 | |
298 | config BF_REV_0_4 | |
299 | bool "0.4" | |
dc26aec2 | 300 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
301 | |
302 | config BF_REV_0_5 | |
303 | bool "0.5" | |
dc26aec2 | 304 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 305 | |
49f7253c MF |
306 | config BF_REV_0_6 |
307 | bool "0.6" | |
308 | depends on (BF533 || BF532 || BF531) | |
309 | ||
de3025f4 JZ |
310 | config BF_REV_ANY |
311 | bool "any" | |
312 | ||
313 | config BF_REV_NONE | |
314 | bool "none" | |
315 | ||
1394f032 BW |
316 | endchoice |
317 | ||
24a07a12 RH |
318 | config BF53x |
319 | bool | |
320 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
321 | default y | |
322 | ||
1394f032 BW |
323 | config MEM_GENERIC_BOARD |
324 | bool | |
325 | depends on GENERIC_BOARD | |
326 | default y | |
327 | ||
328 | config MEM_MT48LC64M4A2FB_7E | |
329 | bool | |
330 | depends on (BFIN533_STAMP) | |
331 | default y | |
332 | ||
333 | config MEM_MT48LC16M16A2TG_75 | |
334 | bool | |
335 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
60584344 HK |
336 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
337 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ | |
338 | || BFIN527_BLUETECHNIX_CM) | |
1394f032 BW |
339 | default y |
340 | ||
341 | config MEM_MT48LC32M8A2_75 | |
342 | bool | |
dc26aec2 | 343 | depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
344 | default y |
345 | ||
346 | config MEM_MT48LC8M32B2B5_7 | |
347 | bool | |
348 | depends on (BFIN561_BLUETECHNIX_CM) | |
349 | default y | |
350 | ||
59003145 MH |
351 | config MEM_MT48LC32M16A2TG_75 |
352 | bool | |
6924dfb0 | 353 | depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP) |
59003145 MH |
354 | default y |
355 | ||
4934540d SZ |
356 | config MEM_MT48LC32M8A2_75 |
357 | bool | |
358 | depends on (BFIN518F_EZBRD) | |
359 | default y | |
360 | ||
ee48efb5 GY |
361 | config MEM_MT48H32M16LFCJ_75 |
362 | bool | |
363 | depends on (BFIN526_EZBRD) | |
364 | default y | |
365 | ||
2f6f4bcd | 366 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 367 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
368 | source "arch/blackfin/mach-bf533/Kconfig" |
369 | source "arch/blackfin/mach-bf561/Kconfig" | |
370 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 371 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 372 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
373 | |
374 | menu "Board customizations" | |
375 | ||
376 | config CMDLINE_BOOL | |
377 | bool "Default bootloader kernel arguments" | |
378 | ||
379 | config CMDLINE | |
380 | string "Initial kernel command string" | |
381 | depends on CMDLINE_BOOL | |
382 | default "console=ttyBF0,57600" | |
383 | help | |
384 | If you don't have a boot loader capable of passing a command line string | |
385 | to the kernel, you may specify one here. As a minimum, you should specify | |
386 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
387 | ||
5f004c20 MF |
388 | config BOOT_LOAD |
389 | hex "Kernel load address for booting" | |
390 | default "0x1000" | |
391 | range 0x1000 0x20000000 | |
392 | help | |
393 | This option allows you to set the load address of the kernel. | |
394 | This can be useful if you are on a board which has a small amount | |
395 | of memory or you wish to reserve some memory at the beginning of | |
396 | the address space. | |
397 | ||
398 | Note that you need to keep this value above 4k (0x1000) as this | |
399 | memory region is used to capture NULL pointer references as well | |
400 | as some core kernel functions. | |
401 | ||
8cc7117e MH |
402 | config ROM_BASE |
403 | hex "Kernel ROM Base" | |
86249911 | 404 | depends on ROMKERNEL |
8cc7117e MH |
405 | default "0x20040000" |
406 | range 0x20000000 0x20400000 if !(BF54x || BF561) | |
407 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
408 | help | |
409 | ||
f16295e7 | 410 | comment "Clock/PLL Setup" |
1394f032 BW |
411 | |
412 | config CLKIN_HZ | |
2fb6cb41 | 413 | int "Frequency of the crystal on the board in Hz" |
d0cb9b4e | 414 | default "10000000" if BFIN532_IP0X |
1394f032 | 415 | default "11059200" if BFIN533_STAMP |
d0cb9b4e MF |
416 | default "24576000" if PNAV10 |
417 | default "25000000" # most people use this | |
1394f032 | 418 | default "27000000" if BFIN533_EZKIT |
1394f032 | 419 | default "30000000" if BFIN561_EZKIT |
1394f032 BW |
420 | help |
421 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
422 | Warning: This value should match the crystal on the board. Otherwise, |
423 | peripherals won't work properly. | |
1394f032 | 424 | |
f16295e7 RG |
425 | config BFIN_KERNEL_CLOCK |
426 | bool "Re-program Clocks while Kernel boots?" | |
427 | default n | |
428 | help | |
429 | This option decides if kernel clocks are re-programed from the | |
430 | bootloader settings. If the clocks are not set, the SDRAM settings | |
431 | are also not changed, and the Bootloader does 100% of the hardware | |
432 | configuration. | |
433 | ||
434 | config PLL_BYPASS | |
e4e9a7ad MF |
435 | bool "Bypass PLL" |
436 | depends on BFIN_KERNEL_CLOCK | |
437 | default n | |
f16295e7 RG |
438 | |
439 | config CLKIN_HALF | |
440 | bool "Half Clock In" | |
441 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
442 | default n | |
443 | help | |
444 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
445 | ||
446 | config VCO_MULT | |
447 | int "VCO Multiplier" | |
448 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
449 | range 1 64 | |
450 | default "22" if BFIN533_EZKIT | |
451 | default "45" if BFIN533_STAMP | |
6924dfb0 | 452 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 453 | default "22" if BFIN533_BLUETECHNIX_CM |
60584344 | 454 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 455 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 456 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
f16295e7 RG |
457 | help |
458 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
459 | PLL Frequency = (Crystal Frequency) * (this setting) | |
460 | ||
461 | choice | |
462 | prompt "Core Clock Divider" | |
463 | depends on BFIN_KERNEL_CLOCK | |
464 | default CCLK_DIV_1 | |
465 | help | |
466 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
467 | Core Frequency = (PLL frequency) / (this setting) | |
468 | ||
469 | config CCLK_DIV_1 | |
470 | bool "1" | |
471 | ||
472 | config CCLK_DIV_2 | |
473 | bool "2" | |
474 | ||
475 | config CCLK_DIV_4 | |
476 | bool "4" | |
477 | ||
478 | config CCLK_DIV_8 | |
479 | bool "8" | |
480 | endchoice | |
481 | ||
482 | config SCLK_DIV | |
483 | int "System Clock Divider" | |
484 | depends on BFIN_KERNEL_CLOCK | |
485 | range 1 15 | |
5f004c20 | 486 | default 5 |
f16295e7 RG |
487 | help |
488 | This sets the frequency of the system clock (including SDRAM or DDR). | |
489 | This can be between 1 and 15 | |
490 | System Clock = (PLL frequency) / (this setting) | |
491 | ||
5f004c20 MF |
492 | choice |
493 | prompt "DDR SDRAM Chip Type" | |
494 | depends on BFIN_KERNEL_CLOCK | |
495 | depends on BF54x | |
496 | default MEM_MT46V32M16_5B | |
497 | ||
498 | config MEM_MT46V32M16_6T | |
499 | bool "MT46V32M16_6T" | |
500 | ||
501 | config MEM_MT46V32M16_5B | |
502 | bool "MT46V32M16_5B" | |
503 | endchoice | |
504 | ||
73feb5c0 MH |
505 | choice |
506 | prompt "DDR/SDRAM Timing" | |
507 | depends on BFIN_KERNEL_CLOCK | |
508 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
509 | help | |
510 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
511 | The calculated SDRAM timing parameters may not be 100% | |
512 | accurate - This option is therefore marked experimental. | |
513 | ||
514 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
515 | bool "Calculate Timings (EXPERIMENTAL)" | |
516 | depends on EXPERIMENTAL | |
517 | ||
518 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
519 | bool "Provide accurate Timings based on target SCLK" | |
520 | help | |
521 | Please consult the Blackfin Hardware Reference Manuals as well | |
522 | as the memory device datasheet. | |
523 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
524 | endchoice | |
525 | ||
526 | menu "Memory Init Control" | |
527 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
528 | ||
529 | config MEM_DDRCTL0 | |
530 | depends on BF54x | |
531 | hex "DDRCTL0" | |
532 | default 0x0 | |
533 | ||
534 | config MEM_DDRCTL1 | |
535 | depends on BF54x | |
536 | hex "DDRCTL1" | |
537 | default 0x0 | |
538 | ||
539 | config MEM_DDRCTL2 | |
540 | depends on BF54x | |
541 | hex "DDRCTL2" | |
542 | default 0x0 | |
543 | ||
544 | config MEM_EBIU_DDRQUE | |
545 | depends on BF54x | |
546 | hex "DDRQUE" | |
547 | default 0x0 | |
548 | ||
549 | config MEM_SDRRC | |
550 | depends on !BF54x | |
551 | hex "SDRRC" | |
552 | default 0x0 | |
553 | ||
554 | config MEM_SDGCTL | |
555 | depends on !BF54x | |
556 | hex "SDGCTL" | |
557 | default 0x0 | |
558 | endmenu | |
559 | ||
f16295e7 RG |
560 | # |
561 | # Max & Min Speeds for various Chips | |
562 | # | |
563 | config MAX_VCO_HZ | |
564 | int | |
2f6f4bcd BW |
565 | default 400000000 if BF512 |
566 | default 400000000 if BF514 | |
567 | default 400000000 if BF516 | |
568 | default 400000000 if BF518 | |
7b06263b MF |
569 | default 400000000 if BF522 |
570 | default 600000000 if BF523 | |
1545a111 | 571 | default 400000000 if BF524 |
f16295e7 | 572 | default 600000000 if BF525 |
1545a111 | 573 | default 400000000 if BF526 |
f16295e7 RG |
574 | default 600000000 if BF527 |
575 | default 400000000 if BF531 | |
576 | default 400000000 if BF532 | |
577 | default 750000000 if BF533 | |
578 | default 500000000 if BF534 | |
579 | default 400000000 if BF536 | |
580 | default 600000000 if BF537 | |
f72eecb9 RG |
581 | default 533333333 if BF538 |
582 | default 533333333 if BF539 | |
f16295e7 | 583 | default 600000000 if BF542 |
f72eecb9 | 584 | default 533333333 if BF544 |
1545a111 MF |
585 | default 600000000 if BF547 |
586 | default 600000000 if BF548 | |
f72eecb9 | 587 | default 533333333 if BF549 |
f16295e7 RG |
588 | default 600000000 if BF561 |
589 | ||
590 | config MIN_VCO_HZ | |
591 | int | |
592 | default 50000000 | |
593 | ||
594 | config MAX_SCLK_HZ | |
595 | int | |
f72eecb9 | 596 | default 133333333 |
f16295e7 RG |
597 | |
598 | config MIN_SCLK_HZ | |
599 | int | |
600 | default 27000000 | |
601 | ||
602 | comment "Kernel Timer/Scheduler" | |
603 | ||
604 | source kernel/Kconfig.hz | |
605 | ||
8b5f79f9 | 606 | config GENERIC_TIME |
10f03f1a | 607 | def_bool y |
8b5f79f9 VM |
608 | |
609 | config GENERIC_CLOCKEVENTS | |
610 | bool "Generic clock events" | |
8b5f79f9 VM |
611 | default y |
612 | ||
0d152c27 | 613 | menu "Clock event device" |
1fa9be72 | 614 | depends on GENERIC_CLOCKEVENTS |
1fa9be72 | 615 | config TICKSOURCE_GPTMR0 |
0d152c27 YL |
616 | bool "GPTimer0" |
617 | depends on !SMP | |
1fa9be72 | 618 | select BFIN_GPTIMERS |
1fa9be72 GY |
619 | |
620 | config TICKSOURCE_CORETMR | |
0d152c27 YL |
621 | bool "Core timer" |
622 | default y | |
623 | endmenu | |
1fa9be72 | 624 | |
0d152c27 | 625 | menu "Clock souce" |
8b5f79f9 | 626 | depends on GENERIC_CLOCKEVENTS |
0d152c27 YL |
627 | config CYCLES_CLOCKSOURCE |
628 | bool "CYCLES" | |
629 | default y | |
8b5f79f9 | 630 | depends on !BFIN_SCRATCH_REG_CYCLES |
1fa9be72 | 631 | depends on !SMP |
8b5f79f9 VM |
632 | help |
633 | If you say Y here, you will enable support for using the 'cycles' | |
634 | registers as a clock source. Doing so means you will be unable to | |
635 | safely write to the 'cycles' register during runtime. You will | |
636 | still be able to read it (such as for performance monitoring), but | |
637 | writing the registers will most likely crash the kernel. | |
638 | ||
1fa9be72 | 639 | config GPTMR0_CLOCKSOURCE |
0d152c27 | 640 | bool "GPTimer0" |
3aca47c0 | 641 | select BFIN_GPTIMERS |
1fa9be72 | 642 | depends on !TICKSOURCE_GPTMR0 |
0d152c27 | 643 | endmenu |
1fa9be72 | 644 | |
10f03f1a | 645 | config ARCH_USES_GETTIMEOFFSET |
646 | depends on !GENERIC_CLOCKEVENTS | |
647 | def_bool y | |
648 | ||
8b5f79f9 VM |
649 | source kernel/time/Kconfig |
650 | ||
5f004c20 | 651 | comment "Misc" |
971d5bc4 | 652 | |
f0b5d12f MF |
653 | choice |
654 | prompt "Blackfin Exception Scratch Register" | |
655 | default BFIN_SCRATCH_REG_RETN | |
656 | help | |
657 | Select the resource to reserve for the Exception handler: | |
658 | - RETN: Non-Maskable Interrupt (NMI) | |
659 | - RETE: Exception Return (JTAG/ICE) | |
660 | - CYCLES: Performance counter | |
661 | ||
662 | If you are unsure, please select "RETN". | |
663 | ||
664 | config BFIN_SCRATCH_REG_RETN | |
665 | bool "RETN" | |
666 | help | |
667 | Use the RETN register in the Blackfin exception handler | |
668 | as a stack scratch register. This means you cannot | |
669 | safely use NMI on the Blackfin while running Linux, but | |
670 | you can debug the system with a JTAG ICE and use the | |
671 | CYCLES performance registers. | |
672 | ||
673 | If you are unsure, please select "RETN". | |
674 | ||
675 | config BFIN_SCRATCH_REG_RETE | |
676 | bool "RETE" | |
677 | help | |
678 | Use the RETE register in the Blackfin exception handler | |
679 | as a stack scratch register. This means you cannot | |
680 | safely use a JTAG ICE while debugging a Blackfin board, | |
681 | but you can safely use the CYCLES performance registers | |
682 | and the NMI. | |
683 | ||
684 | If you are unsure, please select "RETN". | |
685 | ||
686 | config BFIN_SCRATCH_REG_CYCLES | |
687 | bool "CYCLES" | |
688 | help | |
689 | Use the CYCLES register in the Blackfin exception handler | |
690 | as a stack scratch register. This means you cannot | |
691 | safely use the CYCLES performance registers on a Blackfin | |
692 | board at anytime, but you can debug the system with a JTAG | |
693 | ICE and use the NMI. | |
694 | ||
695 | If you are unsure, please select "RETN". | |
696 | ||
697 | endchoice | |
698 | ||
1394f032 BW |
699 | endmenu |
700 | ||
701 | ||
702 | menu "Blackfin Kernel Optimizations" | |
46fa5eec | 703 | depends on !SMP |
1394f032 | 704 | |
1394f032 BW |
705 | comment "Memory Optimizations" |
706 | ||
707 | config I_ENTRY_L1 | |
708 | bool "Locate interrupt entry code in L1 Memory" | |
709 | default y | |
710 | help | |
01dd2fbf ML |
711 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
712 | into L1 instruction memory. (less latency) | |
1394f032 BW |
713 | |
714 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 715 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
716 | default y |
717 | help | |
01dd2fbf | 718 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 719 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 720 | (less latency) |
1394f032 BW |
721 | |
722 | config DO_IRQ_L1 | |
723 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
724 | default y | |
725 | help | |
01dd2fbf ML |
726 | If enabled, the frequently called do_irq dispatcher function is linked |
727 | into L1 instruction memory. (less latency) | |
1394f032 BW |
728 | |
729 | config CORE_TIMER_IRQ_L1 | |
730 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
731 | default y | |
732 | help | |
01dd2fbf ML |
733 | If enabled, the frequently called timer_interrupt() function is linked |
734 | into L1 instruction memory. (less latency) | |
1394f032 BW |
735 | |
736 | config IDLE_L1 | |
737 | bool "Locate frequently idle function in L1 Memory" | |
738 | default y | |
739 | help | |
01dd2fbf ML |
740 | If enabled, the frequently called idle function is linked |
741 | into L1 instruction memory. (less latency) | |
1394f032 BW |
742 | |
743 | config SCHEDULE_L1 | |
744 | bool "Locate kernel schedule function in L1 Memory" | |
745 | default y | |
746 | help | |
01dd2fbf ML |
747 | If enabled, the frequently called kernel schedule is linked |
748 | into L1 instruction memory. (less latency) | |
1394f032 BW |
749 | |
750 | config ARITHMETIC_OPS_L1 | |
751 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
752 | default y | |
753 | help | |
01dd2fbf ML |
754 | If enabled, arithmetic functions are linked |
755 | into L1 instruction memory. (less latency) | |
1394f032 BW |
756 | |
757 | config ACCESS_OK_L1 | |
758 | bool "Locate access_ok function in L1 Memory" | |
759 | default y | |
760 | help | |
01dd2fbf ML |
761 | If enabled, the access_ok function is linked |
762 | into L1 instruction memory. (less latency) | |
1394f032 BW |
763 | |
764 | config MEMSET_L1 | |
765 | bool "Locate memset function in L1 Memory" | |
766 | default y | |
767 | help | |
01dd2fbf ML |
768 | If enabled, the memset function is linked |
769 | into L1 instruction memory. (less latency) | |
1394f032 BW |
770 | |
771 | config MEMCPY_L1 | |
772 | bool "Locate memcpy function in L1 Memory" | |
773 | default y | |
774 | help | |
01dd2fbf ML |
775 | If enabled, the memcpy function is linked |
776 | into L1 instruction memory. (less latency) | |
1394f032 BW |
777 | |
778 | config SYS_BFIN_SPINLOCK_L1 | |
779 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
780 | default y | |
781 | help | |
01dd2fbf ML |
782 | If enabled, sys_bfin_spinlock function is linked |
783 | into L1 instruction memory. (less latency) | |
1394f032 BW |
784 | |
785 | config IP_CHECKSUM_L1 | |
786 | bool "Locate IP Checksum function in L1 Memory" | |
787 | default n | |
788 | help | |
01dd2fbf ML |
789 | If enabled, the IP Checksum function is linked |
790 | into L1 instruction memory. (less latency) | |
1394f032 BW |
791 | |
792 | config CACHELINE_ALIGNED_L1 | |
793 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
794 | default y if !BF54x |
795 | default n if BF54x | |
1394f032 BW |
796 | depends on !BF531 |
797 | help | |
692105b8 | 798 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 799 | into L1 data memory. (less latency) |
1394f032 BW |
800 | |
801 | config SYSCALL_TAB_L1 | |
802 | bool "Locate Syscall Table L1 Data Memory" | |
803 | default n | |
804 | depends on !BF531 | |
805 | help | |
01dd2fbf ML |
806 | If enabled, the Syscall LUT is linked |
807 | into L1 data memory. (less latency) | |
1394f032 BW |
808 | |
809 | config CPLB_SWITCH_TAB_L1 | |
810 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
811 | default n | |
812 | depends on !BF531 | |
813 | help | |
01dd2fbf ML |
814 | If enabled, the CPLB Switch Tables are linked |
815 | into L1 data memory. (less latency) | |
1394f032 | 816 | |
ca87b7ad GY |
817 | config APP_STACK_L1 |
818 | bool "Support locating application stack in L1 Scratch Memory" | |
819 | default y | |
820 | help | |
821 | If enabled the application stack can be located in L1 | |
822 | scratch memory (less latency). | |
823 | ||
824 | Currently only works with FLAT binaries. | |
825 | ||
6ad2b84c MF |
826 | config EXCEPTION_L1_SCRATCH |
827 | bool "Locate exception stack in L1 Scratch Memory" | |
828 | default n | |
f82e0a0c | 829 | depends on !APP_STACK_L1 |
6ad2b84c MF |
830 | help |
831 | Whenever an exception occurs, use the L1 Scratch memory for | |
832 | stack storage. You cannot place the stacks of FLAT binaries | |
833 | in L1 when using this option. | |
834 | ||
835 | If you don't use L1 Scratch, then you should say Y here. | |
836 | ||
251383c7 RG |
837 | comment "Speed Optimizations" |
838 | config BFIN_INS_LOWOVERHEAD | |
839 | bool "ins[bwl] low overhead, higher interrupt latency" | |
840 | default y | |
841 | help | |
842 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
843 | they can be interrupted at any time (even after they have been issued | |
844 | on to the external bus), and re-issued after the interrupt occurs. | |
845 | For memory - this is not a big deal, since memory does not change if | |
846 | it sees a read. | |
847 | ||
848 | If a FIFO is sitting on the end of the read, it will see two reads, | |
849 | when the core only sees one since the FIFO receives both the read | |
850 | which is cancelled (and not delivered to the core) and the one which | |
851 | is re-issued (which is delivered to the core). | |
852 | ||
853 | To solve this, interrupts are turned off before reads occur to | |
854 | I/O space. This option controls which the overhead/latency of | |
855 | controlling interrupts during this time | |
856 | "n" turns interrupts off every read | |
857 | (higher overhead, but lower interrupt latency) | |
858 | "y" turns interrupts off every loop | |
859 | (low overhead, but longer interrupt latency) | |
860 | ||
861 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
862 | interrupt latency issues, it is safe and OK to turn this off. | |
863 | ||
1394f032 BW |
864 | endmenu |
865 | ||
1394f032 BW |
866 | choice |
867 | prompt "Kernel executes from" | |
868 | help | |
869 | Choose the memory type that the kernel will be running in. | |
870 | ||
871 | config RAMKERNEL | |
872 | bool "RAM" | |
873 | help | |
874 | The kernel will be resident in RAM when running. | |
875 | ||
876 | config ROMKERNEL | |
877 | bool "ROM" | |
878 | help | |
879 | The kernel will be resident in FLASH/ROM when running. | |
880 | ||
881 | endchoice | |
882 | ||
883 | source "mm/Kconfig" | |
884 | ||
780431e3 MF |
885 | config BFIN_GPTIMERS |
886 | tristate "Enable Blackfin General Purpose Timers API" | |
887 | default n | |
888 | help | |
889 | Enable support for the General Purpose Timers API. If you | |
890 | are unsure, say N. | |
891 | ||
892 | To compile this driver as a module, choose M here: the module | |
4737f097 | 893 | will be called gptimers. |
780431e3 | 894 | |
1394f032 | 895 | choice |
d292b000 | 896 | prompt "Uncached DMA region" |
1394f032 | 897 | default DMA_UNCACHED_1M |
86ad7932 CC |
898 | config DMA_UNCACHED_4M |
899 | bool "Enable 4M DMA region" | |
1394f032 BW |
900 | config DMA_UNCACHED_2M |
901 | bool "Enable 2M DMA region" | |
902 | config DMA_UNCACHED_1M | |
903 | bool "Enable 1M DMA region" | |
c45c0659 BS |
904 | config DMA_UNCACHED_512K |
905 | bool "Enable 512K DMA region" | |
906 | config DMA_UNCACHED_256K | |
907 | bool "Enable 256K DMA region" | |
908 | config DMA_UNCACHED_128K | |
909 | bool "Enable 128K DMA region" | |
1394f032 BW |
910 | config DMA_UNCACHED_NONE |
911 | bool "Disable DMA region" | |
912 | endchoice | |
913 | ||
914 | ||
915 | comment "Cache Support" | |
41ba653f | 916 | |
3bebca2d | 917 | config BFIN_ICACHE |
1394f032 | 918 | bool "Enable ICACHE" |
41ba653f | 919 | default y |
41ba653f JZ |
920 | config BFIN_EXTMEM_ICACHEABLE |
921 | bool "Enable ICACHE for external memory" | |
922 | depends on BFIN_ICACHE | |
923 | default y | |
924 | config BFIN_L2_ICACHEABLE | |
925 | bool "Enable ICACHE for L2 SRAM" | |
926 | depends on BFIN_ICACHE | |
927 | depends on BF54x || BF561 | |
928 | default n | |
929 | ||
3bebca2d | 930 | config BFIN_DCACHE |
1394f032 | 931 | bool "Enable DCACHE" |
41ba653f | 932 | default y |
3bebca2d | 933 | config BFIN_DCACHE_BANKA |
1394f032 | 934 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 935 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 936 | default n |
41ba653f JZ |
937 | config BFIN_EXTMEM_DCACHEABLE |
938 | bool "Enable DCACHE for external memory" | |
3bebca2d | 939 | depends on BFIN_DCACHE |
41ba653f JZ |
940 | default y |
941 | choice | |
942 | prompt "External memory DCACHE policy" | |
943 | depends on BFIN_EXTMEM_DCACHEABLE | |
944 | default BFIN_EXTMEM_WRITEBACK if !SMP | |
945 | default BFIN_EXTMEM_WRITETHROUGH if SMP | |
946 | config BFIN_EXTMEM_WRITEBACK | |
1394f032 | 947 | bool "Write back" |
46fa5eec | 948 | depends on !SMP |
1394f032 BW |
949 | help |
950 | Write Back Policy: | |
951 | Cached data will be written back to SDRAM only when needed. | |
952 | This can give a nice increase in performance, but beware of | |
953 | broken drivers that do not properly invalidate/flush their | |
954 | cache. | |
955 | ||
956 | Write Through Policy: | |
957 | Cached data will always be written back to SDRAM when the | |
958 | cache is updated. This is a completely safe setting, but | |
959 | performance is worse than Write Back. | |
960 | ||
961 | If you are unsure of the options and you want to be safe, | |
962 | then go with Write Through. | |
963 | ||
41ba653f | 964 | config BFIN_EXTMEM_WRITETHROUGH |
1394f032 BW |
965 | bool "Write through" |
966 | help | |
967 | Write Back Policy: | |
968 | Cached data will be written back to SDRAM only when needed. | |
969 | This can give a nice increase in performance, but beware of | |
970 | broken drivers that do not properly invalidate/flush their | |
971 | cache. | |
972 | ||
973 | Write Through Policy: | |
974 | Cached data will always be written back to SDRAM when the | |
975 | cache is updated. This is a completely safe setting, but | |
976 | performance is worse than Write Back. | |
977 | ||
978 | If you are unsure of the options and you want to be safe, | |
979 | then go with Write Through. | |
980 | ||
981 | endchoice | |
982 | ||
41ba653f JZ |
983 | config BFIN_L2_DCACHEABLE |
984 | bool "Enable DCACHE for L2 SRAM" | |
985 | depends on BFIN_DCACHE | |
9c954f89 | 986 | depends on (BF54x || BF561) && !SMP |
41ba653f | 987 | default n |
5ba76675 | 988 | choice |
41ba653f JZ |
989 | prompt "L2 SRAM DCACHE policy" |
990 | depends on BFIN_L2_DCACHEABLE | |
991 | default BFIN_L2_WRITEBACK | |
992 | config BFIN_L2_WRITEBACK | |
5ba76675 | 993 | bool "Write back" |
5ba76675 | 994 | |
41ba653f | 995 | config BFIN_L2_WRITETHROUGH |
5ba76675 | 996 | bool "Write through" |
5ba76675 | 997 | endchoice |
f099f39a | 998 | |
41ba653f JZ |
999 | |
1000 | comment "Memory Protection Unit" | |
b97b8a99 BS |
1001 | config MPU |
1002 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
1003 | default n | |
1004 | help | |
1005 | Use the processor's MPU to protect applications from accessing | |
1006 | memory they do not own. This comes at a performance penalty | |
1007 | and is recommended only for debugging. | |
1008 | ||
692105b8 | 1009 | comment "Asynchronous Memory Configuration" |
1394f032 | 1010 | |
ddf416b2 | 1011 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
1012 | config C_AMCKEN |
1013 | bool "Enable CLKOUT" | |
1014 | default y | |
1015 | ||
1016 | config C_CDPRIO | |
1017 | bool "DMA has priority over core for ext. accesses" | |
1018 | default n | |
1019 | ||
1020 | config C_B0PEN | |
1021 | depends on BF561 | |
1022 | bool "Bank 0 16 bit packing enable" | |
1023 | default y | |
1024 | ||
1025 | config C_B1PEN | |
1026 | depends on BF561 | |
1027 | bool "Bank 1 16 bit packing enable" | |
1028 | default y | |
1029 | ||
1030 | config C_B2PEN | |
1031 | depends on BF561 | |
1032 | bool "Bank 2 16 bit packing enable" | |
1033 | default y | |
1034 | ||
1035 | config C_B3PEN | |
1036 | depends on BF561 | |
1037 | bool "Bank 3 16 bit packing enable" | |
1038 | default n | |
1039 | ||
1040 | choice | |
692105b8 | 1041 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1042 | default C_AMBEN_ALL |
1043 | ||
1044 | config C_AMBEN | |
1045 | bool "Disable All Banks" | |
1046 | ||
1047 | config C_AMBEN_B0 | |
1048 | bool "Enable Bank 0" | |
1049 | ||
1050 | config C_AMBEN_B0_B1 | |
1051 | bool "Enable Bank 0 & 1" | |
1052 | ||
1053 | config C_AMBEN_B0_B1_B2 | |
1054 | bool "Enable Bank 0 & 1 & 2" | |
1055 | ||
1056 | config C_AMBEN_ALL | |
1057 | bool "Enable All Banks" | |
1058 | endchoice | |
1059 | endmenu | |
1060 | ||
1061 | menu "EBIU_AMBCTL Control" | |
1062 | config BANK_0 | |
c8342f87 | 1063 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1064 | default 0x7BB0 |
c8342f87 MF |
1065 | help |
1066 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1067 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1068 | |
1069 | config BANK_1 | |
c8342f87 | 1070 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1071 | default 0x7BB0 |
197fba56 | 1072 | default 0x5558 if BF54x |
c8342f87 MF |
1073 | help |
1074 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1075 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1076 | |
1077 | config BANK_2 | |
c8342f87 | 1078 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1079 | default 0x7BB0 |
c8342f87 MF |
1080 | help |
1081 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1082 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1083 | |
1084 | config BANK_3 | |
c8342f87 | 1085 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1086 | default 0x99B3 |
c8342f87 MF |
1087 | help |
1088 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1089 | used to control the Asynchronous Memory Bank 3 settings. | |
1090 | ||
1394f032 BW |
1091 | endmenu |
1092 | ||
e40540b3 SZ |
1093 | config EBIU_MBSCTLVAL |
1094 | hex "EBIU Bank Select Control Register" | |
1095 | depends on BF54x | |
1096 | default 0 | |
1097 | ||
1098 | config EBIU_MODEVAL | |
1099 | hex "Flash Memory Mode Control Register" | |
1100 | depends on BF54x | |
1101 | default 1 | |
1102 | ||
1103 | config EBIU_FCTLVAL | |
1104 | hex "Flash Memory Bank Control Register" | |
1105 | depends on BF54x | |
1106 | default 6 | |
1394f032 BW |
1107 | endmenu |
1108 | ||
1109 | ############################################################################# | |
1110 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1111 | ||
1112 | config PCI | |
1113 | bool "PCI support" | |
a95ca3b2 | 1114 | depends on BROKEN |
1394f032 BW |
1115 | help |
1116 | Support for PCI bus. | |
1117 | ||
1118 | source "drivers/pci/Kconfig" | |
1119 | ||
1394f032 BW |
1120 | source "drivers/pcmcia/Kconfig" |
1121 | ||
1122 | source "drivers/pci/hotplug/Kconfig" | |
1123 | ||
1124 | endmenu | |
1125 | ||
1126 | menu "Executable file formats" | |
1127 | ||
1128 | source "fs/Kconfig.binfmt" | |
1129 | ||
1130 | endmenu | |
1131 | ||
1132 | menu "Power management options" | |
ad46163a GY |
1133 | depends on !SMP |
1134 | ||
1394f032 BW |
1135 | source "kernel/power/Kconfig" |
1136 | ||
f4cb5700 JB |
1137 | config ARCH_SUSPEND_POSSIBLE |
1138 | def_bool y | |
f4cb5700 | 1139 | |
1394f032 | 1140 | choice |
1efc80b5 | 1141 | prompt "Standby Power Saving Mode" |
1394f032 | 1142 | depends on PM |
cfefe3c6 MH |
1143 | default PM_BFIN_SLEEP_DEEPER |
1144 | config PM_BFIN_SLEEP_DEEPER | |
1145 | bool "Sleep Deeper" | |
1146 | help | |
1147 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1148 | power dissipation by disabling the clock to the processor core (CCLK). | |
1149 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1150 | to 0.85 V to provide the greatest power savings, while preserving the | |
1151 | processor state. | |
1152 | The PLL and system clock (SCLK) continue to operate at a very low | |
1153 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1154 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1155 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1156 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1157 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1158 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1159 | ||
1efc80b5 MH |
1160 | If unsure, select "Sleep Deeper". |
1161 | ||
cfefe3c6 MH |
1162 | config PM_BFIN_SLEEP |
1163 | bool "Sleep" | |
1164 | help | |
1165 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1166 | dissipation by disabling the clock to the processor core (CCLK). | |
1167 | The PLL and system clock (SCLK), however, continue to operate in | |
1168 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1169 | up the processor. When in the sleep mode, system DMA access to L1 |
1170 | memory is not supported. | |
1171 | ||
1172 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1173 | endchoice |
1394f032 | 1174 | |
1394f032 | 1175 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 1176 | bool "Allow Wakeup from Standby by GPIO" |
ff19fed4 | 1177 | depends on PM && !BF54x |
1394f032 BW |
1178 | |
1179 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 1180 | int "GPIO number" |
1394f032 BW |
1181 | range 0 47 |
1182 | depends on PM_WAKEUP_BY_GPIO | |
d1a3336e | 1183 | default 2 |
1394f032 BW |
1184 | |
1185 | choice | |
1186 | prompt "GPIO Polarity" | |
1187 | depends on PM_WAKEUP_BY_GPIO | |
1188 | default PM_WAKEUP_GPIO_POLAR_H | |
1189 | config PM_WAKEUP_GPIO_POLAR_H | |
1190 | bool "Active High" | |
1191 | config PM_WAKEUP_GPIO_POLAR_L | |
1192 | bool "Active Low" | |
1193 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
1194 | bool "Falling EDGE" | |
1195 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
1196 | bool "Rising EDGE" | |
1197 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
1198 | bool "Both EDGE" | |
1199 | endchoice | |
1200 | ||
1efc80b5 MH |
1201 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1202 | depends on PM | |
1203 | ||
1efc80b5 MH |
1204 | config PM_BFIN_WAKE_PH6 |
1205 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1206 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1207 | default n |
1208 | help | |
1209 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1210 | ||
1efc80b5 MH |
1211 | config PM_BFIN_WAKE_GP |
1212 | bool "Allow Wake-Up from GPIOs" | |
1213 | depends on PM && BF54x | |
1214 | default n | |
1215 | help | |
1216 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1217 | (all processors, except ADSP-BF549). This option sets |
1218 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1219 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
1220 | On ADSP-BF549 this option enables the the same functionality on the | |
1221 | /MRXON pin also PH7. | |
1222 | ||
1394f032 BW |
1223 | endmenu |
1224 | ||
1394f032 | 1225 | menu "CPU Frequency scaling" |
ad46163a | 1226 | depends on !SMP |
1394f032 BW |
1227 | |
1228 | source "drivers/cpufreq/Kconfig" | |
1229 | ||
5ad2ca5f MH |
1230 | config BFIN_CPU_FREQ |
1231 | bool | |
1232 | depends on CPU_FREQ | |
1233 | select CPU_FREQ_TABLE | |
1234 | default y | |
1235 | ||
14b03204 MH |
1236 | config CPU_VOLTAGE |
1237 | bool "CPU Voltage scaling" | |
73feb5c0 | 1238 | depends on EXPERIMENTAL |
14b03204 MH |
1239 | depends on CPU_FREQ |
1240 | default n | |
1241 | help | |
1242 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1243 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1244 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1245 | the PLL may unlock. |
1246 | ||
1394f032 BW |
1247 | endmenu |
1248 | ||
1394f032 BW |
1249 | source "net/Kconfig" |
1250 | ||
1251 | source "drivers/Kconfig" | |
1252 | ||
872d024b MF |
1253 | source "drivers/firmware/Kconfig" |
1254 | ||
1394f032 BW |
1255 | source "fs/Kconfig" |
1256 | ||
74ce8322 | 1257 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1258 | |
1259 | source "security/Kconfig" | |
1260 | ||
1261 | source "crypto/Kconfig" | |
1262 | ||
1263 | source "lib/Kconfig" |