Commit | Line | Data |
---|---|---|
1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 | 7 | |
9e1b9b80 AJ |
8 | config SYMBOL_PREFIX |
9 | string | |
10 | default "_" | |
11 | ||
1394f032 | 12 | config MMU |
bac7d89e | 13 | def_bool n |
1394f032 BW |
14 | |
15 | config FPU | |
bac7d89e | 16 | def_bool n |
1394f032 BW |
17 | |
18 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 19 | def_bool y |
1394f032 BW |
20 | |
21 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 22 | def_bool n |
1394f032 BW |
23 | |
24 | config BLACKFIN | |
bac7d89e | 25 | def_bool y |
1ee76d7e | 26 | select HAVE_FUNCTION_GRAPH_TRACER |
1c873be7 | 27 | select HAVE_FUNCTION_TRACER |
ec7748b5 | 28 | select HAVE_IDE |
538067c8 MF |
29 | select HAVE_KERNEL_GZIP |
30 | select HAVE_KERNEL_BZIP2 | |
31 | select HAVE_KERNEL_LZMA | |
42d4b839 | 32 | select HAVE_OPROFILE |
a4f0b32c | 33 | select ARCH_WANT_OPTIONAL_GPIOLIB |
1394f032 | 34 | |
ddf9ddac MF |
35 | config GENERIC_CSUM |
36 | def_bool y | |
37 | ||
70f12567 MF |
38 | config GENERIC_BUG |
39 | def_bool y | |
40 | depends on BUG | |
41 | ||
e3defffe | 42 | config ZONE_DMA |
bac7d89e | 43 | def_bool y |
e3defffe | 44 | |
1394f032 | 45 | config GENERIC_FIND_NEXT_BIT |
bac7d89e | 46 | def_bool y |
1394f032 BW |
47 | |
48 | config GENERIC_HWEIGHT | |
bac7d89e | 49 | def_bool y |
1394f032 BW |
50 | |
51 | config GENERIC_HARDIRQS | |
bac7d89e | 52 | def_bool y |
1394f032 BW |
53 | |
54 | config GENERIC_IRQ_PROBE | |
bac7d89e | 55 | def_bool y |
1394f032 | 56 | |
796dada9 MH |
57 | config GENERIC_HARDIRQS_NO__DO_IRQ |
58 | def_bool y | |
59 | ||
b2d1583f | 60 | config GENERIC_GPIO |
bac7d89e | 61 | def_bool y |
1394f032 BW |
62 | |
63 | config FORCE_MAX_ZONEORDER | |
64 | int | |
65 | default "14" | |
66 | ||
67 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 68 | def_bool y |
1394f032 | 69 | |
6fa68e7a MF |
70 | config LOCKDEP_SUPPORT |
71 | def_bool y | |
72 | ||
c7b412f4 MF |
73 | config STACKTRACE_SUPPORT |
74 | def_bool y | |
75 | ||
8f86001f MF |
76 | config TRACE_IRQFLAGS_SUPPORT |
77 | def_bool y | |
1394f032 | 78 | |
1394f032 | 79 | source "init/Kconfig" |
dc52ddc0 | 80 | |
1394f032 BW |
81 | source "kernel/Kconfig.preempt" |
82 | ||
dc52ddc0 MH |
83 | source "kernel/Kconfig.freezer" |
84 | ||
1394f032 BW |
85 | menu "Blackfin Processor Options" |
86 | ||
87 | comment "Processor and Board Settings" | |
88 | ||
89 | choice | |
90 | prompt "CPU" | |
91 | default BF533 | |
92 | ||
2f6f4bcd BW |
93 | config BF512 |
94 | bool "BF512" | |
95 | help | |
96 | BF512 Processor Support. | |
97 | ||
98 | config BF514 | |
99 | bool "BF514" | |
100 | help | |
101 | BF514 Processor Support. | |
102 | ||
103 | config BF516 | |
104 | bool "BF516" | |
105 | help | |
106 | BF516 Processor Support. | |
107 | ||
108 | config BF518 | |
109 | bool "BF518" | |
110 | help | |
111 | BF518 Processor Support. | |
112 | ||
59003145 MH |
113 | config BF522 |
114 | bool "BF522" | |
115 | help | |
116 | BF522 Processor Support. | |
117 | ||
1545a111 MF |
118 | config BF523 |
119 | bool "BF523" | |
120 | help | |
121 | BF523 Processor Support. | |
122 | ||
123 | config BF524 | |
124 | bool "BF524" | |
125 | help | |
126 | BF524 Processor Support. | |
127 | ||
59003145 MH |
128 | config BF525 |
129 | bool "BF525" | |
130 | help | |
131 | BF525 Processor Support. | |
132 | ||
1545a111 MF |
133 | config BF526 |
134 | bool "BF526" | |
135 | help | |
136 | BF526 Processor Support. | |
137 | ||
59003145 MH |
138 | config BF527 |
139 | bool "BF527" | |
140 | help | |
141 | BF527 Processor Support. | |
142 | ||
1394f032 BW |
143 | config BF531 |
144 | bool "BF531" | |
145 | help | |
146 | BF531 Processor Support. | |
147 | ||
148 | config BF532 | |
149 | bool "BF532" | |
150 | help | |
151 | BF532 Processor Support. | |
152 | ||
153 | config BF533 | |
154 | bool "BF533" | |
155 | help | |
156 | BF533 Processor Support. | |
157 | ||
158 | config BF534 | |
159 | bool "BF534" | |
160 | help | |
161 | BF534 Processor Support. | |
162 | ||
163 | config BF536 | |
164 | bool "BF536" | |
165 | help | |
166 | BF536 Processor Support. | |
167 | ||
168 | config BF537 | |
169 | bool "BF537" | |
170 | help | |
171 | BF537 Processor Support. | |
172 | ||
dc26aec2 MH |
173 | config BF538 |
174 | bool "BF538" | |
175 | help | |
176 | BF538 Processor Support. | |
177 | ||
178 | config BF539 | |
179 | bool "BF539" | |
180 | help | |
181 | BF539 Processor Support. | |
182 | ||
5df326ac | 183 | config BF542_std |
24a07a12 RH |
184 | bool "BF542" |
185 | help | |
186 | BF542 Processor Support. | |
187 | ||
2f89c063 MF |
188 | config BF542M |
189 | bool "BF542m" | |
190 | help | |
191 | BF542 Processor Support. | |
192 | ||
5df326ac | 193 | config BF544_std |
24a07a12 RH |
194 | bool "BF544" |
195 | help | |
196 | BF544 Processor Support. | |
197 | ||
2f89c063 MF |
198 | config BF544M |
199 | bool "BF544m" | |
200 | help | |
201 | BF544 Processor Support. | |
202 | ||
5df326ac | 203 | config BF547_std |
7c7fd170 MF |
204 | bool "BF547" |
205 | help | |
206 | BF547 Processor Support. | |
207 | ||
2f89c063 MF |
208 | config BF547M |
209 | bool "BF547m" | |
210 | help | |
211 | BF547 Processor Support. | |
212 | ||
5df326ac | 213 | config BF548_std |
24a07a12 RH |
214 | bool "BF548" |
215 | help | |
216 | BF548 Processor Support. | |
217 | ||
2f89c063 MF |
218 | config BF548M |
219 | bool "BF548m" | |
220 | help | |
221 | BF548 Processor Support. | |
222 | ||
5df326ac | 223 | config BF549_std |
24a07a12 RH |
224 | bool "BF549" |
225 | help | |
226 | BF549 Processor Support. | |
227 | ||
2f89c063 MF |
228 | config BF549M |
229 | bool "BF549m" | |
230 | help | |
231 | BF549 Processor Support. | |
232 | ||
1394f032 BW |
233 | config BF561 |
234 | bool "BF561" | |
235 | help | |
cd88b4dc | 236 | BF561 Processor Support. |
1394f032 BW |
237 | |
238 | endchoice | |
239 | ||
46fa5eec GY |
240 | config SMP |
241 | depends on BF561 | |
10f03f1a | 242 | select GENERIC_CLOCKEVENTS |
46fa5eec GY |
243 | bool "Symmetric multi-processing support" |
244 | ---help--- | |
245 | This enables support for systems with more than one CPU, | |
246 | like the dual core BF561. If you have a system with only one | |
247 | CPU, say N. If you have a system with more than one CPU, say Y. | |
248 | ||
249 | If you don't know what to do here, say N. | |
250 | ||
251 | config NR_CPUS | |
252 | int | |
253 | depends on SMP | |
254 | default 2 if BF561 | |
255 | ||
256 | config IRQ_PER_CPU | |
257 | bool | |
258 | depends on SMP | |
259 | default y | |
260 | ||
0c0497c2 MF |
261 | config BF_REV_MIN |
262 | int | |
2f89c063 | 263 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
0c0497c2 | 264 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 265 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 266 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
267 | |
268 | config BF_REV_MAX | |
269 | int | |
2f89c063 MF |
270 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) |
271 | default 3 if (BF537 || BF536 || BF534 || BF54xM) | |
2f6f4bcd | 272 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
273 | default 6 if (BF533 || BF532 || BF531) |
274 | ||
1394f032 BW |
275 | choice |
276 | prompt "Silicon Rev" | |
f8b55651 MF |
277 | default BF_REV_0_0 if (BF51x || BF52x) |
278 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) | |
2f89c063 | 279 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
280 | |
281 | config BF_REV_0_0 | |
282 | bool "0.0" | |
2f89c063 | 283 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
59003145 MH |
284 | |
285 | config BF_REV_0_1 | |
d07f4380 | 286 | bool "0.1" |
3d15f302 | 287 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
288 | |
289 | config BF_REV_0_2 | |
290 | bool "0.2" | |
2f89c063 | 291 | depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
292 | |
293 | config BF_REV_0_3 | |
294 | bool "0.3" | |
2f89c063 | 295 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
296 | |
297 | config BF_REV_0_4 | |
298 | bool "0.4" | |
dc26aec2 | 299 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
300 | |
301 | config BF_REV_0_5 | |
302 | bool "0.5" | |
dc26aec2 | 303 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 304 | |
49f7253c MF |
305 | config BF_REV_0_6 |
306 | bool "0.6" | |
307 | depends on (BF533 || BF532 || BF531) | |
308 | ||
de3025f4 JZ |
309 | config BF_REV_ANY |
310 | bool "any" | |
311 | ||
312 | config BF_REV_NONE | |
313 | bool "none" | |
314 | ||
1394f032 BW |
315 | endchoice |
316 | ||
24a07a12 RH |
317 | config BF53x |
318 | bool | |
319 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
320 | default y | |
321 | ||
1394f032 BW |
322 | config MEM_GENERIC_BOARD |
323 | bool | |
324 | depends on GENERIC_BOARD | |
325 | default y | |
326 | ||
327 | config MEM_MT48LC64M4A2FB_7E | |
328 | bool | |
329 | depends on (BFIN533_STAMP) | |
330 | default y | |
331 | ||
332 | config MEM_MT48LC16M16A2TG_75 | |
333 | bool | |
334 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
60584344 HK |
335 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
336 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ | |
337 | || BFIN527_BLUETECHNIX_CM) | |
1394f032 BW |
338 | default y |
339 | ||
340 | config MEM_MT48LC32M8A2_75 | |
341 | bool | |
dc26aec2 | 342 | depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
343 | default y |
344 | ||
345 | config MEM_MT48LC8M32B2B5_7 | |
346 | bool | |
347 | depends on (BFIN561_BLUETECHNIX_CM) | |
348 | default y | |
349 | ||
59003145 MH |
350 | config MEM_MT48LC32M16A2TG_75 |
351 | bool | |
ee48efb5 | 352 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP) |
59003145 MH |
353 | default y |
354 | ||
4934540d SZ |
355 | config MEM_MT48LC32M8A2_75 |
356 | bool | |
357 | depends on (BFIN518F_EZBRD) | |
358 | default y | |
359 | ||
ee48efb5 GY |
360 | config MEM_MT48H32M16LFCJ_75 |
361 | bool | |
362 | depends on (BFIN526_EZBRD) | |
363 | default y | |
364 | ||
2f6f4bcd | 365 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 366 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
367 | source "arch/blackfin/mach-bf533/Kconfig" |
368 | source "arch/blackfin/mach-bf561/Kconfig" | |
369 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 370 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 371 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
372 | |
373 | menu "Board customizations" | |
374 | ||
375 | config CMDLINE_BOOL | |
376 | bool "Default bootloader kernel arguments" | |
377 | ||
378 | config CMDLINE | |
379 | string "Initial kernel command string" | |
380 | depends on CMDLINE_BOOL | |
381 | default "console=ttyBF0,57600" | |
382 | help | |
383 | If you don't have a boot loader capable of passing a command line string | |
384 | to the kernel, you may specify one here. As a minimum, you should specify | |
385 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
386 | ||
5f004c20 MF |
387 | config BOOT_LOAD |
388 | hex "Kernel load address for booting" | |
389 | default "0x1000" | |
390 | range 0x1000 0x20000000 | |
391 | help | |
392 | This option allows you to set the load address of the kernel. | |
393 | This can be useful if you are on a board which has a small amount | |
394 | of memory or you wish to reserve some memory at the beginning of | |
395 | the address space. | |
396 | ||
397 | Note that you need to keep this value above 4k (0x1000) as this | |
398 | memory region is used to capture NULL pointer references as well | |
399 | as some core kernel functions. | |
400 | ||
8cc7117e MH |
401 | config ROM_BASE |
402 | hex "Kernel ROM Base" | |
86249911 | 403 | depends on ROMKERNEL |
8cc7117e MH |
404 | default "0x20040000" |
405 | range 0x20000000 0x20400000 if !(BF54x || BF561) | |
406 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
407 | help | |
408 | ||
f16295e7 | 409 | comment "Clock/PLL Setup" |
1394f032 BW |
410 | |
411 | config CLKIN_HZ | |
2fb6cb41 | 412 | int "Frequency of the crystal on the board in Hz" |
d0cb9b4e | 413 | default "10000000" if BFIN532_IP0X |
1394f032 | 414 | default "11059200" if BFIN533_STAMP |
d0cb9b4e MF |
415 | default "24576000" if PNAV10 |
416 | default "25000000" # most people use this | |
1394f032 | 417 | default "27000000" if BFIN533_EZKIT |
1394f032 | 418 | default "30000000" if BFIN561_EZKIT |
1394f032 BW |
419 | help |
420 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
421 | Warning: This value should match the crystal on the board. Otherwise, |
422 | peripherals won't work properly. | |
1394f032 | 423 | |
f16295e7 RG |
424 | config BFIN_KERNEL_CLOCK |
425 | bool "Re-program Clocks while Kernel boots?" | |
426 | default n | |
427 | help | |
428 | This option decides if kernel clocks are re-programed from the | |
429 | bootloader settings. If the clocks are not set, the SDRAM settings | |
430 | are also not changed, and the Bootloader does 100% of the hardware | |
431 | configuration. | |
432 | ||
433 | config PLL_BYPASS | |
e4e9a7ad MF |
434 | bool "Bypass PLL" |
435 | depends on BFIN_KERNEL_CLOCK | |
436 | default n | |
f16295e7 RG |
437 | |
438 | config CLKIN_HALF | |
439 | bool "Half Clock In" | |
440 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
441 | default n | |
442 | help | |
443 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
444 | ||
445 | config VCO_MULT | |
446 | int "VCO Multiplier" | |
447 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
448 | range 1 64 | |
449 | default "22" if BFIN533_EZKIT | |
450 | default "45" if BFIN533_STAMP | |
dc26aec2 | 451 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 452 | default "22" if BFIN533_BLUETECHNIX_CM |
60584344 | 453 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 454 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 455 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
f16295e7 RG |
456 | help |
457 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
458 | PLL Frequency = (Crystal Frequency) * (this setting) | |
459 | ||
460 | choice | |
461 | prompt "Core Clock Divider" | |
462 | depends on BFIN_KERNEL_CLOCK | |
463 | default CCLK_DIV_1 | |
464 | help | |
465 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
466 | Core Frequency = (PLL frequency) / (this setting) | |
467 | ||
468 | config CCLK_DIV_1 | |
469 | bool "1" | |
470 | ||
471 | config CCLK_DIV_2 | |
472 | bool "2" | |
473 | ||
474 | config CCLK_DIV_4 | |
475 | bool "4" | |
476 | ||
477 | config CCLK_DIV_8 | |
478 | bool "8" | |
479 | endchoice | |
480 | ||
481 | config SCLK_DIV | |
482 | int "System Clock Divider" | |
483 | depends on BFIN_KERNEL_CLOCK | |
484 | range 1 15 | |
5f004c20 | 485 | default 5 |
f16295e7 RG |
486 | help |
487 | This sets the frequency of the system clock (including SDRAM or DDR). | |
488 | This can be between 1 and 15 | |
489 | System Clock = (PLL frequency) / (this setting) | |
490 | ||
5f004c20 MF |
491 | choice |
492 | prompt "DDR SDRAM Chip Type" | |
493 | depends on BFIN_KERNEL_CLOCK | |
494 | depends on BF54x | |
495 | default MEM_MT46V32M16_5B | |
496 | ||
497 | config MEM_MT46V32M16_6T | |
498 | bool "MT46V32M16_6T" | |
499 | ||
500 | config MEM_MT46V32M16_5B | |
501 | bool "MT46V32M16_5B" | |
502 | endchoice | |
503 | ||
73feb5c0 MH |
504 | choice |
505 | prompt "DDR/SDRAM Timing" | |
506 | depends on BFIN_KERNEL_CLOCK | |
507 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
508 | help | |
509 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
510 | The calculated SDRAM timing parameters may not be 100% | |
511 | accurate - This option is therefore marked experimental. | |
512 | ||
513 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
514 | bool "Calculate Timings (EXPERIMENTAL)" | |
515 | depends on EXPERIMENTAL | |
516 | ||
517 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
518 | bool "Provide accurate Timings based on target SCLK" | |
519 | help | |
520 | Please consult the Blackfin Hardware Reference Manuals as well | |
521 | as the memory device datasheet. | |
522 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
523 | endchoice | |
524 | ||
525 | menu "Memory Init Control" | |
526 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
527 | ||
528 | config MEM_DDRCTL0 | |
529 | depends on BF54x | |
530 | hex "DDRCTL0" | |
531 | default 0x0 | |
532 | ||
533 | config MEM_DDRCTL1 | |
534 | depends on BF54x | |
535 | hex "DDRCTL1" | |
536 | default 0x0 | |
537 | ||
538 | config MEM_DDRCTL2 | |
539 | depends on BF54x | |
540 | hex "DDRCTL2" | |
541 | default 0x0 | |
542 | ||
543 | config MEM_EBIU_DDRQUE | |
544 | depends on BF54x | |
545 | hex "DDRQUE" | |
546 | default 0x0 | |
547 | ||
548 | config MEM_SDRRC | |
549 | depends on !BF54x | |
550 | hex "SDRRC" | |
551 | default 0x0 | |
552 | ||
553 | config MEM_SDGCTL | |
554 | depends on !BF54x | |
555 | hex "SDGCTL" | |
556 | default 0x0 | |
557 | endmenu | |
558 | ||
f16295e7 RG |
559 | # |
560 | # Max & Min Speeds for various Chips | |
561 | # | |
562 | config MAX_VCO_HZ | |
563 | int | |
2f6f4bcd BW |
564 | default 400000000 if BF512 |
565 | default 400000000 if BF514 | |
566 | default 400000000 if BF516 | |
567 | default 400000000 if BF518 | |
7b06263b MF |
568 | default 400000000 if BF522 |
569 | default 600000000 if BF523 | |
1545a111 | 570 | default 400000000 if BF524 |
f16295e7 | 571 | default 600000000 if BF525 |
1545a111 | 572 | default 400000000 if BF526 |
f16295e7 RG |
573 | default 600000000 if BF527 |
574 | default 400000000 if BF531 | |
575 | default 400000000 if BF532 | |
576 | default 750000000 if BF533 | |
577 | default 500000000 if BF534 | |
578 | default 400000000 if BF536 | |
579 | default 600000000 if BF537 | |
f72eecb9 RG |
580 | default 533333333 if BF538 |
581 | default 533333333 if BF539 | |
f16295e7 | 582 | default 600000000 if BF542 |
f72eecb9 | 583 | default 533333333 if BF544 |
1545a111 MF |
584 | default 600000000 if BF547 |
585 | default 600000000 if BF548 | |
f72eecb9 | 586 | default 533333333 if BF549 |
f16295e7 RG |
587 | default 600000000 if BF561 |
588 | ||
589 | config MIN_VCO_HZ | |
590 | int | |
591 | default 50000000 | |
592 | ||
593 | config MAX_SCLK_HZ | |
594 | int | |
f72eecb9 | 595 | default 133333333 |
f16295e7 RG |
596 | |
597 | config MIN_SCLK_HZ | |
598 | int | |
599 | default 27000000 | |
600 | ||
601 | comment "Kernel Timer/Scheduler" | |
602 | ||
603 | source kernel/Kconfig.hz | |
604 | ||
8b5f79f9 | 605 | config GENERIC_TIME |
10f03f1a | 606 | def_bool y |
8b5f79f9 VM |
607 | |
608 | config GENERIC_CLOCKEVENTS | |
609 | bool "Generic clock events" | |
8b5f79f9 VM |
610 | default y |
611 | ||
1fa9be72 GY |
612 | choice |
613 | prompt "Kernel Tick Source" | |
614 | depends on GENERIC_CLOCKEVENTS | |
615 | default TICKSOURCE_CORETMR | |
616 | ||
617 | config TICKSOURCE_GPTMR0 | |
618 | bool "Gptimer0 (SCLK domain)" | |
619 | select BFIN_GPTIMERS | |
1fa9be72 GY |
620 | |
621 | config TICKSOURCE_CORETMR | |
622 | bool "Core timer (CCLK domain)" | |
623 | ||
624 | endchoice | |
625 | ||
8b5f79f9 | 626 | config CYCLES_CLOCKSOURCE |
1fa9be72 | 627 | bool "Use 'CYCLES' as a clocksource" |
8b5f79f9 VM |
628 | depends on GENERIC_CLOCKEVENTS |
629 | depends on !BFIN_SCRATCH_REG_CYCLES | |
1fa9be72 | 630 | depends on !SMP |
8b5f79f9 VM |
631 | help |
632 | If you say Y here, you will enable support for using the 'cycles' | |
633 | registers as a clock source. Doing so means you will be unable to | |
634 | safely write to the 'cycles' register during runtime. You will | |
635 | still be able to read it (such as for performance monitoring), but | |
636 | writing the registers will most likely crash the kernel. | |
637 | ||
1fa9be72 | 638 | config GPTMR0_CLOCKSOURCE |
e78feaae | 639 | bool "Use GPTimer0 as a clocksource" |
3aca47c0 | 640 | select BFIN_GPTIMERS |
1fa9be72 GY |
641 | depends on GENERIC_CLOCKEVENTS |
642 | depends on !TICKSOURCE_GPTMR0 | |
643 | ||
10f03f1a | 644 | config ARCH_USES_GETTIMEOFFSET |
645 | depends on !GENERIC_CLOCKEVENTS | |
646 | def_bool y | |
647 | ||
8b5f79f9 VM |
648 | source kernel/time/Kconfig |
649 | ||
5f004c20 | 650 | comment "Misc" |
971d5bc4 | 651 | |
f0b5d12f MF |
652 | choice |
653 | prompt "Blackfin Exception Scratch Register" | |
654 | default BFIN_SCRATCH_REG_RETN | |
655 | help | |
656 | Select the resource to reserve for the Exception handler: | |
657 | - RETN: Non-Maskable Interrupt (NMI) | |
658 | - RETE: Exception Return (JTAG/ICE) | |
659 | - CYCLES: Performance counter | |
660 | ||
661 | If you are unsure, please select "RETN". | |
662 | ||
663 | config BFIN_SCRATCH_REG_RETN | |
664 | bool "RETN" | |
665 | help | |
666 | Use the RETN register in the Blackfin exception handler | |
667 | as a stack scratch register. This means you cannot | |
668 | safely use NMI on the Blackfin while running Linux, but | |
669 | you can debug the system with a JTAG ICE and use the | |
670 | CYCLES performance registers. | |
671 | ||
672 | If you are unsure, please select "RETN". | |
673 | ||
674 | config BFIN_SCRATCH_REG_RETE | |
675 | bool "RETE" | |
676 | help | |
677 | Use the RETE register in the Blackfin exception handler | |
678 | as a stack scratch register. This means you cannot | |
679 | safely use a JTAG ICE while debugging a Blackfin board, | |
680 | but you can safely use the CYCLES performance registers | |
681 | and the NMI. | |
682 | ||
683 | If you are unsure, please select "RETN". | |
684 | ||
685 | config BFIN_SCRATCH_REG_CYCLES | |
686 | bool "CYCLES" | |
687 | help | |
688 | Use the CYCLES register in the Blackfin exception handler | |
689 | as a stack scratch register. This means you cannot | |
690 | safely use the CYCLES performance registers on a Blackfin | |
691 | board at anytime, but you can debug the system with a JTAG | |
692 | ICE and use the NMI. | |
693 | ||
694 | If you are unsure, please select "RETN". | |
695 | ||
696 | endchoice | |
697 | ||
1394f032 BW |
698 | endmenu |
699 | ||
700 | ||
701 | menu "Blackfin Kernel Optimizations" | |
46fa5eec | 702 | depends on !SMP |
1394f032 | 703 | |
1394f032 BW |
704 | comment "Memory Optimizations" |
705 | ||
706 | config I_ENTRY_L1 | |
707 | bool "Locate interrupt entry code in L1 Memory" | |
708 | default y | |
709 | help | |
01dd2fbf ML |
710 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
711 | into L1 instruction memory. (less latency) | |
1394f032 BW |
712 | |
713 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 714 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
715 | default y |
716 | help | |
01dd2fbf | 717 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 718 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 719 | (less latency) |
1394f032 BW |
720 | |
721 | config DO_IRQ_L1 | |
722 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
723 | default y | |
724 | help | |
01dd2fbf ML |
725 | If enabled, the frequently called do_irq dispatcher function is linked |
726 | into L1 instruction memory. (less latency) | |
1394f032 BW |
727 | |
728 | config CORE_TIMER_IRQ_L1 | |
729 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
730 | default y | |
731 | help | |
01dd2fbf ML |
732 | If enabled, the frequently called timer_interrupt() function is linked |
733 | into L1 instruction memory. (less latency) | |
1394f032 BW |
734 | |
735 | config IDLE_L1 | |
736 | bool "Locate frequently idle function in L1 Memory" | |
737 | default y | |
738 | help | |
01dd2fbf ML |
739 | If enabled, the frequently called idle function is linked |
740 | into L1 instruction memory. (less latency) | |
1394f032 BW |
741 | |
742 | config SCHEDULE_L1 | |
743 | bool "Locate kernel schedule function in L1 Memory" | |
744 | default y | |
745 | help | |
01dd2fbf ML |
746 | If enabled, the frequently called kernel schedule is linked |
747 | into L1 instruction memory. (less latency) | |
1394f032 BW |
748 | |
749 | config ARITHMETIC_OPS_L1 | |
750 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
751 | default y | |
752 | help | |
01dd2fbf ML |
753 | If enabled, arithmetic functions are linked |
754 | into L1 instruction memory. (less latency) | |
1394f032 BW |
755 | |
756 | config ACCESS_OK_L1 | |
757 | bool "Locate access_ok function in L1 Memory" | |
758 | default y | |
759 | help | |
01dd2fbf ML |
760 | If enabled, the access_ok function is linked |
761 | into L1 instruction memory. (less latency) | |
1394f032 BW |
762 | |
763 | config MEMSET_L1 | |
764 | bool "Locate memset function in L1 Memory" | |
765 | default y | |
766 | help | |
01dd2fbf ML |
767 | If enabled, the memset function is linked |
768 | into L1 instruction memory. (less latency) | |
1394f032 BW |
769 | |
770 | config MEMCPY_L1 | |
771 | bool "Locate memcpy function in L1 Memory" | |
772 | default y | |
773 | help | |
01dd2fbf ML |
774 | If enabled, the memcpy function is linked |
775 | into L1 instruction memory. (less latency) | |
1394f032 BW |
776 | |
777 | config SYS_BFIN_SPINLOCK_L1 | |
778 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
779 | default y | |
780 | help | |
01dd2fbf ML |
781 | If enabled, sys_bfin_spinlock function is linked |
782 | into L1 instruction memory. (less latency) | |
1394f032 BW |
783 | |
784 | config IP_CHECKSUM_L1 | |
785 | bool "Locate IP Checksum function in L1 Memory" | |
786 | default n | |
787 | help | |
01dd2fbf ML |
788 | If enabled, the IP Checksum function is linked |
789 | into L1 instruction memory. (less latency) | |
1394f032 BW |
790 | |
791 | config CACHELINE_ALIGNED_L1 | |
792 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
793 | default y if !BF54x |
794 | default n if BF54x | |
1394f032 BW |
795 | depends on !BF531 |
796 | help | |
692105b8 | 797 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 798 | into L1 data memory. (less latency) |
1394f032 BW |
799 | |
800 | config SYSCALL_TAB_L1 | |
801 | bool "Locate Syscall Table L1 Data Memory" | |
802 | default n | |
803 | depends on !BF531 | |
804 | help | |
01dd2fbf ML |
805 | If enabled, the Syscall LUT is linked |
806 | into L1 data memory. (less latency) | |
1394f032 BW |
807 | |
808 | config CPLB_SWITCH_TAB_L1 | |
809 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
810 | default n | |
811 | depends on !BF531 | |
812 | help | |
01dd2fbf ML |
813 | If enabled, the CPLB Switch Tables are linked |
814 | into L1 data memory. (less latency) | |
1394f032 | 815 | |
ca87b7ad GY |
816 | config APP_STACK_L1 |
817 | bool "Support locating application stack in L1 Scratch Memory" | |
818 | default y | |
819 | help | |
820 | If enabled the application stack can be located in L1 | |
821 | scratch memory (less latency). | |
822 | ||
823 | Currently only works with FLAT binaries. | |
824 | ||
6ad2b84c MF |
825 | config EXCEPTION_L1_SCRATCH |
826 | bool "Locate exception stack in L1 Scratch Memory" | |
827 | default n | |
f82e0a0c | 828 | depends on !APP_STACK_L1 |
6ad2b84c MF |
829 | help |
830 | Whenever an exception occurs, use the L1 Scratch memory for | |
831 | stack storage. You cannot place the stacks of FLAT binaries | |
832 | in L1 when using this option. | |
833 | ||
834 | If you don't use L1 Scratch, then you should say Y here. | |
835 | ||
251383c7 RG |
836 | comment "Speed Optimizations" |
837 | config BFIN_INS_LOWOVERHEAD | |
838 | bool "ins[bwl] low overhead, higher interrupt latency" | |
839 | default y | |
840 | help | |
841 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
842 | they can be interrupted at any time (even after they have been issued | |
843 | on to the external bus), and re-issued after the interrupt occurs. | |
844 | For memory - this is not a big deal, since memory does not change if | |
845 | it sees a read. | |
846 | ||
847 | If a FIFO is sitting on the end of the read, it will see two reads, | |
848 | when the core only sees one since the FIFO receives both the read | |
849 | which is cancelled (and not delivered to the core) and the one which | |
850 | is re-issued (which is delivered to the core). | |
851 | ||
852 | To solve this, interrupts are turned off before reads occur to | |
853 | I/O space. This option controls which the overhead/latency of | |
854 | controlling interrupts during this time | |
855 | "n" turns interrupts off every read | |
856 | (higher overhead, but lower interrupt latency) | |
857 | "y" turns interrupts off every loop | |
858 | (low overhead, but longer interrupt latency) | |
859 | ||
860 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
861 | interrupt latency issues, it is safe and OK to turn this off. | |
862 | ||
1394f032 BW |
863 | endmenu |
864 | ||
1394f032 BW |
865 | choice |
866 | prompt "Kernel executes from" | |
867 | help | |
868 | Choose the memory type that the kernel will be running in. | |
869 | ||
870 | config RAMKERNEL | |
871 | bool "RAM" | |
872 | help | |
873 | The kernel will be resident in RAM when running. | |
874 | ||
875 | config ROMKERNEL | |
876 | bool "ROM" | |
877 | help | |
878 | The kernel will be resident in FLASH/ROM when running. | |
879 | ||
880 | endchoice | |
881 | ||
882 | source "mm/Kconfig" | |
883 | ||
780431e3 MF |
884 | config BFIN_GPTIMERS |
885 | tristate "Enable Blackfin General Purpose Timers API" | |
886 | default n | |
887 | help | |
888 | Enable support for the General Purpose Timers API. If you | |
889 | are unsure, say N. | |
890 | ||
891 | To compile this driver as a module, choose M here: the module | |
4737f097 | 892 | will be called gptimers. |
780431e3 | 893 | |
1394f032 | 894 | choice |
d292b000 | 895 | prompt "Uncached DMA region" |
1394f032 | 896 | default DMA_UNCACHED_1M |
86ad7932 CC |
897 | config DMA_UNCACHED_4M |
898 | bool "Enable 4M DMA region" | |
1394f032 BW |
899 | config DMA_UNCACHED_2M |
900 | bool "Enable 2M DMA region" | |
901 | config DMA_UNCACHED_1M | |
902 | bool "Enable 1M DMA region" | |
c45c0659 BS |
903 | config DMA_UNCACHED_512K |
904 | bool "Enable 512K DMA region" | |
905 | config DMA_UNCACHED_256K | |
906 | bool "Enable 256K DMA region" | |
907 | config DMA_UNCACHED_128K | |
908 | bool "Enable 128K DMA region" | |
1394f032 BW |
909 | config DMA_UNCACHED_NONE |
910 | bool "Disable DMA region" | |
911 | endchoice | |
912 | ||
913 | ||
914 | comment "Cache Support" | |
41ba653f | 915 | |
3bebca2d | 916 | config BFIN_ICACHE |
1394f032 | 917 | bool "Enable ICACHE" |
41ba653f | 918 | default y |
41ba653f JZ |
919 | config BFIN_EXTMEM_ICACHEABLE |
920 | bool "Enable ICACHE for external memory" | |
921 | depends on BFIN_ICACHE | |
922 | default y | |
923 | config BFIN_L2_ICACHEABLE | |
924 | bool "Enable ICACHE for L2 SRAM" | |
925 | depends on BFIN_ICACHE | |
926 | depends on BF54x || BF561 | |
927 | default n | |
928 | ||
3bebca2d | 929 | config BFIN_DCACHE |
1394f032 | 930 | bool "Enable DCACHE" |
41ba653f | 931 | default y |
3bebca2d | 932 | config BFIN_DCACHE_BANKA |
1394f032 | 933 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 934 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 935 | default n |
41ba653f JZ |
936 | config BFIN_EXTMEM_DCACHEABLE |
937 | bool "Enable DCACHE for external memory" | |
3bebca2d | 938 | depends on BFIN_DCACHE |
41ba653f JZ |
939 | default y |
940 | choice | |
941 | prompt "External memory DCACHE policy" | |
942 | depends on BFIN_EXTMEM_DCACHEABLE | |
943 | default BFIN_EXTMEM_WRITEBACK if !SMP | |
944 | default BFIN_EXTMEM_WRITETHROUGH if SMP | |
945 | config BFIN_EXTMEM_WRITEBACK | |
1394f032 | 946 | bool "Write back" |
46fa5eec | 947 | depends on !SMP |
1394f032 BW |
948 | help |
949 | Write Back Policy: | |
950 | Cached data will be written back to SDRAM only when needed. | |
951 | This can give a nice increase in performance, but beware of | |
952 | broken drivers that do not properly invalidate/flush their | |
953 | cache. | |
954 | ||
955 | Write Through Policy: | |
956 | Cached data will always be written back to SDRAM when the | |
957 | cache is updated. This is a completely safe setting, but | |
958 | performance is worse than Write Back. | |
959 | ||
960 | If you are unsure of the options and you want to be safe, | |
961 | then go with Write Through. | |
962 | ||
41ba653f | 963 | config BFIN_EXTMEM_WRITETHROUGH |
1394f032 BW |
964 | bool "Write through" |
965 | help | |
966 | Write Back Policy: | |
967 | Cached data will be written back to SDRAM only when needed. | |
968 | This can give a nice increase in performance, but beware of | |
969 | broken drivers that do not properly invalidate/flush their | |
970 | cache. | |
971 | ||
972 | Write Through Policy: | |
973 | Cached data will always be written back to SDRAM when the | |
974 | cache is updated. This is a completely safe setting, but | |
975 | performance is worse than Write Back. | |
976 | ||
977 | If you are unsure of the options and you want to be safe, | |
978 | then go with Write Through. | |
979 | ||
980 | endchoice | |
981 | ||
41ba653f JZ |
982 | config BFIN_L2_DCACHEABLE |
983 | bool "Enable DCACHE for L2 SRAM" | |
984 | depends on BFIN_DCACHE | |
9c954f89 | 985 | depends on (BF54x || BF561) && !SMP |
41ba653f | 986 | default n |
5ba76675 | 987 | choice |
41ba653f JZ |
988 | prompt "L2 SRAM DCACHE policy" |
989 | depends on BFIN_L2_DCACHEABLE | |
990 | default BFIN_L2_WRITEBACK | |
991 | config BFIN_L2_WRITEBACK | |
5ba76675 | 992 | bool "Write back" |
5ba76675 | 993 | |
41ba653f | 994 | config BFIN_L2_WRITETHROUGH |
5ba76675 | 995 | bool "Write through" |
5ba76675 | 996 | endchoice |
f099f39a | 997 | |
41ba653f JZ |
998 | |
999 | comment "Memory Protection Unit" | |
b97b8a99 BS |
1000 | config MPU |
1001 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
1002 | default n | |
1003 | help | |
1004 | Use the processor's MPU to protect applications from accessing | |
1005 | memory they do not own. This comes at a performance penalty | |
1006 | and is recommended only for debugging. | |
1007 | ||
692105b8 | 1008 | comment "Asynchronous Memory Configuration" |
1394f032 | 1009 | |
ddf416b2 | 1010 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
1011 | config C_AMCKEN |
1012 | bool "Enable CLKOUT" | |
1013 | default y | |
1014 | ||
1015 | config C_CDPRIO | |
1016 | bool "DMA has priority over core for ext. accesses" | |
1017 | default n | |
1018 | ||
1019 | config C_B0PEN | |
1020 | depends on BF561 | |
1021 | bool "Bank 0 16 bit packing enable" | |
1022 | default y | |
1023 | ||
1024 | config C_B1PEN | |
1025 | depends on BF561 | |
1026 | bool "Bank 1 16 bit packing enable" | |
1027 | default y | |
1028 | ||
1029 | config C_B2PEN | |
1030 | depends on BF561 | |
1031 | bool "Bank 2 16 bit packing enable" | |
1032 | default y | |
1033 | ||
1034 | config C_B3PEN | |
1035 | depends on BF561 | |
1036 | bool "Bank 3 16 bit packing enable" | |
1037 | default n | |
1038 | ||
1039 | choice | |
692105b8 | 1040 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1041 | default C_AMBEN_ALL |
1042 | ||
1043 | config C_AMBEN | |
1044 | bool "Disable All Banks" | |
1045 | ||
1046 | config C_AMBEN_B0 | |
1047 | bool "Enable Bank 0" | |
1048 | ||
1049 | config C_AMBEN_B0_B1 | |
1050 | bool "Enable Bank 0 & 1" | |
1051 | ||
1052 | config C_AMBEN_B0_B1_B2 | |
1053 | bool "Enable Bank 0 & 1 & 2" | |
1054 | ||
1055 | config C_AMBEN_ALL | |
1056 | bool "Enable All Banks" | |
1057 | endchoice | |
1058 | endmenu | |
1059 | ||
1060 | menu "EBIU_AMBCTL Control" | |
1061 | config BANK_0 | |
c8342f87 | 1062 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1063 | default 0x7BB0 |
c8342f87 MF |
1064 | help |
1065 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1066 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1067 | |
1068 | config BANK_1 | |
c8342f87 | 1069 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1070 | default 0x7BB0 |
197fba56 | 1071 | default 0x5558 if BF54x |
c8342f87 MF |
1072 | help |
1073 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1074 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1075 | |
1076 | config BANK_2 | |
c8342f87 | 1077 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1078 | default 0x7BB0 |
c8342f87 MF |
1079 | help |
1080 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1081 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1082 | |
1083 | config BANK_3 | |
c8342f87 | 1084 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1085 | default 0x99B3 |
c8342f87 MF |
1086 | help |
1087 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1088 | used to control the Asynchronous Memory Bank 3 settings. | |
1089 | ||
1394f032 BW |
1090 | endmenu |
1091 | ||
e40540b3 SZ |
1092 | config EBIU_MBSCTLVAL |
1093 | hex "EBIU Bank Select Control Register" | |
1094 | depends on BF54x | |
1095 | default 0 | |
1096 | ||
1097 | config EBIU_MODEVAL | |
1098 | hex "Flash Memory Mode Control Register" | |
1099 | depends on BF54x | |
1100 | default 1 | |
1101 | ||
1102 | config EBIU_FCTLVAL | |
1103 | hex "Flash Memory Bank Control Register" | |
1104 | depends on BF54x | |
1105 | default 6 | |
1394f032 BW |
1106 | endmenu |
1107 | ||
1108 | ############################################################################# | |
1109 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1110 | ||
1111 | config PCI | |
1112 | bool "PCI support" | |
a95ca3b2 | 1113 | depends on BROKEN |
1394f032 BW |
1114 | help |
1115 | Support for PCI bus. | |
1116 | ||
1117 | source "drivers/pci/Kconfig" | |
1118 | ||
1119 | config HOTPLUG | |
1120 | bool "Support for hot-pluggable device" | |
1121 | help | |
1122 | Say Y here if you want to plug devices into your computer while | |
1123 | the system is running, and be able to use them quickly. In many | |
1124 | cases, the devices can likewise be unplugged at any time too. | |
1125 | ||
1126 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
1127 | size devices such as network cards, modems or hard drives which are | |
1128 | plugged into slots found on all modern laptop computers. Another | |
1129 | example, used on modern desktops as well as laptops, is USB. | |
1130 | ||
a81792f6 JB |
1131 | Enable HOTPLUG and build a modular kernel. Get agent software |
1132 | (from <http://linux-hotplug.sourceforge.net/>) and install it. | |
1394f032 BW |
1133 | Then your kernel will automatically call out to a user mode "policy |
1134 | agent" (/sbin/hotplug) to load modules and set up software needed | |
1135 | to use devices as you hotplug them. | |
1136 | ||
1137 | source "drivers/pcmcia/Kconfig" | |
1138 | ||
1139 | source "drivers/pci/hotplug/Kconfig" | |
1140 | ||
1141 | endmenu | |
1142 | ||
1143 | menu "Executable file formats" | |
1144 | ||
1145 | source "fs/Kconfig.binfmt" | |
1146 | ||
1147 | endmenu | |
1148 | ||
1149 | menu "Power management options" | |
ad46163a GY |
1150 | depends on !SMP |
1151 | ||
1394f032 BW |
1152 | source "kernel/power/Kconfig" |
1153 | ||
f4cb5700 JB |
1154 | config ARCH_SUSPEND_POSSIBLE |
1155 | def_bool y | |
f4cb5700 | 1156 | |
1394f032 | 1157 | choice |
1efc80b5 | 1158 | prompt "Standby Power Saving Mode" |
1394f032 | 1159 | depends on PM |
cfefe3c6 MH |
1160 | default PM_BFIN_SLEEP_DEEPER |
1161 | config PM_BFIN_SLEEP_DEEPER | |
1162 | bool "Sleep Deeper" | |
1163 | help | |
1164 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1165 | power dissipation by disabling the clock to the processor core (CCLK). | |
1166 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1167 | to 0.85 V to provide the greatest power savings, while preserving the | |
1168 | processor state. | |
1169 | The PLL and system clock (SCLK) continue to operate at a very low | |
1170 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1171 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1172 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1173 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1174 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1175 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1176 | ||
1efc80b5 MH |
1177 | If unsure, select "Sleep Deeper". |
1178 | ||
cfefe3c6 MH |
1179 | config PM_BFIN_SLEEP |
1180 | bool "Sleep" | |
1181 | help | |
1182 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1183 | dissipation by disabling the clock to the processor core (CCLK). | |
1184 | The PLL and system clock (SCLK), however, continue to operate in | |
1185 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1186 | up the processor. When in the sleep mode, system DMA access to L1 |
1187 | memory is not supported. | |
1188 | ||
1189 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1190 | endchoice |
1394f032 | 1191 | |
1394f032 | 1192 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 1193 | bool "Allow Wakeup from Standby by GPIO" |
ff19fed4 | 1194 | depends on PM && !BF54x |
1394f032 BW |
1195 | |
1196 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 1197 | int "GPIO number" |
1394f032 BW |
1198 | range 0 47 |
1199 | depends on PM_WAKEUP_BY_GPIO | |
d1a3336e | 1200 | default 2 |
1394f032 BW |
1201 | |
1202 | choice | |
1203 | prompt "GPIO Polarity" | |
1204 | depends on PM_WAKEUP_BY_GPIO | |
1205 | default PM_WAKEUP_GPIO_POLAR_H | |
1206 | config PM_WAKEUP_GPIO_POLAR_H | |
1207 | bool "Active High" | |
1208 | config PM_WAKEUP_GPIO_POLAR_L | |
1209 | bool "Active Low" | |
1210 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
1211 | bool "Falling EDGE" | |
1212 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
1213 | bool "Rising EDGE" | |
1214 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
1215 | bool "Both EDGE" | |
1216 | endchoice | |
1217 | ||
1efc80b5 MH |
1218 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1219 | depends on PM | |
1220 | ||
1efc80b5 MH |
1221 | config PM_BFIN_WAKE_PH6 |
1222 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1223 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1224 | default n |
1225 | help | |
1226 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1227 | ||
1efc80b5 MH |
1228 | config PM_BFIN_WAKE_GP |
1229 | bool "Allow Wake-Up from GPIOs" | |
1230 | depends on PM && BF54x | |
1231 | default n | |
1232 | help | |
1233 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1234 | (all processors, except ADSP-BF549). This option sets |
1235 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1236 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
1237 | On ADSP-BF549 this option enables the the same functionality on the | |
1238 | /MRXON pin also PH7. | |
1239 | ||
1394f032 BW |
1240 | endmenu |
1241 | ||
1394f032 | 1242 | menu "CPU Frequency scaling" |
ad46163a | 1243 | depends on !SMP |
1394f032 BW |
1244 | |
1245 | source "drivers/cpufreq/Kconfig" | |
1246 | ||
5ad2ca5f MH |
1247 | config BFIN_CPU_FREQ |
1248 | bool | |
1249 | depends on CPU_FREQ | |
1250 | select CPU_FREQ_TABLE | |
1251 | default y | |
1252 | ||
14b03204 MH |
1253 | config CPU_VOLTAGE |
1254 | bool "CPU Voltage scaling" | |
73feb5c0 | 1255 | depends on EXPERIMENTAL |
14b03204 MH |
1256 | depends on CPU_FREQ |
1257 | default n | |
1258 | help | |
1259 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1260 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1261 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1262 | the PLL may unlock. |
1263 | ||
1394f032 BW |
1264 | endmenu |
1265 | ||
1394f032 BW |
1266 | source "net/Kconfig" |
1267 | ||
1268 | source "drivers/Kconfig" | |
1269 | ||
872d024b MF |
1270 | source "drivers/firmware/Kconfig" |
1271 | ||
1394f032 BW |
1272 | source "fs/Kconfig" |
1273 | ||
74ce8322 | 1274 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1275 | |
1276 | source "security/Kconfig" | |
1277 | ||
1278 | source "crypto/Kconfig" | |
1279 | ||
1280 | source "lib/Kconfig" |