Commit | Line | Data |
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5f97f7f9 HS |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | #include <linux/clk.h> | |
35bf50cc | 9 | #include <linux/delay.h> |
3bfb1d20 | 10 | #include <linux/dw_dmac.h> |
d0a2b7af | 11 | #include <linux/fb.h> |
5f97f7f9 HS |
12 | #include <linux/init.h> |
13 | #include <linux/platform_device.h> | |
6b84bbfc | 14 | #include <linux/dma-mapping.h> |
3c26e170 | 15 | #include <linux/gpio.h> |
41d8ca45 | 16 | #include <linux/spi/spi.h> |
8d855317 | 17 | #include <linux/usb/atmel_usba_udc.h> |
2635d1ba NF |
18 | |
19 | #include <mach/atmel-mci.h> | |
c42aa775 | 20 | #include <linux/atmel-mci.h> |
5f97f7f9 HS |
21 | |
22 | #include <asm/io.h> | |
e7ba176b | 23 | #include <asm/irq.h> |
5f97f7f9 | 24 | |
3663b736 HS |
25 | #include <mach/at32ap700x.h> |
26 | #include <mach/board.h> | |
b47eb409 | 27 | #include <mach/hmatrix.h> |
3663b736 HS |
28 | #include <mach/portmux.h> |
29 | #include <mach/sram.h> | |
5f97f7f9 | 30 | |
6b0c9351 | 31 | #include <sound/atmel-abdac.h> |
2f47c8c5 | 32 | #include <sound/atmel-ac97c.h> |
6b0c9351 | 33 | |
d0a2b7af HS |
34 | #include <video/atmel_lcdc.h> |
35 | ||
5f97f7f9 HS |
36 | #include "clock.h" |
37 | #include "pio.h" | |
7a5b8059 HS |
38 | #include "pm.h" |
39 | ||
5f97f7f9 HS |
40 | |
41 | #define PBMEM(base) \ | |
42 | { \ | |
43 | .start = base, \ | |
44 | .end = base + 0x3ff, \ | |
45 | .flags = IORESOURCE_MEM, \ | |
46 | } | |
47 | #define IRQ(num) \ | |
48 | { \ | |
49 | .start = num, \ | |
50 | .end = num, \ | |
51 | .flags = IORESOURCE_IRQ, \ | |
52 | } | |
53 | #define NAMED_IRQ(num, _name) \ | |
54 | { \ | |
55 | .start = num, \ | |
56 | .end = num, \ | |
57 | .name = _name, \ | |
58 | .flags = IORESOURCE_IRQ, \ | |
59 | } | |
60 | ||
6b84bbfc DB |
61 | /* REVISIT these assume *every* device supports DMA, but several |
62 | * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more. | |
63 | */ | |
5f97f7f9 | 64 | #define DEFINE_DEV(_name, _id) \ |
284901a9 | 65 | static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \ |
5f97f7f9 HS |
66 | static struct platform_device _name##_id##_device = { \ |
67 | .name = #_name, \ | |
68 | .id = _id, \ | |
6b84bbfc DB |
69 | .dev = { \ |
70 | .dma_mask = &_name##_id##_dma_mask, \ | |
284901a9 | 71 | .coherent_dma_mask = DMA_BIT_MASK(32), \ |
6b84bbfc | 72 | }, \ |
5f97f7f9 HS |
73 | .resource = _name##_id##_resource, \ |
74 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
75 | } | |
76 | #define DEFINE_DEV_DATA(_name, _id) \ | |
284901a9 | 77 | static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \ |
5f97f7f9 HS |
78 | static struct platform_device _name##_id##_device = { \ |
79 | .name = #_name, \ | |
80 | .id = _id, \ | |
81 | .dev = { \ | |
6b84bbfc | 82 | .dma_mask = &_name##_id##_dma_mask, \ |
5f97f7f9 | 83 | .platform_data = &_name##_id##_data, \ |
284901a9 | 84 | .coherent_dma_mask = DMA_BIT_MASK(32), \ |
5f97f7f9 HS |
85 | }, \ |
86 | .resource = _name##_id##_resource, \ | |
87 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
88 | } | |
89 | ||
caf18f19 JM |
90 | #define select_peripheral(port, pin_mask, periph, flags) \ |
91 | at32_select_periph(GPIO_##port##_BASE, pin_mask, \ | |
92 | GPIO_##periph, flags) | |
c3e2a79c | 93 | |
5f97f7f9 HS |
94 | #define DEV_CLK(_name, devname, bus, _index) \ |
95 | static struct clk devname##_##_name = { \ | |
96 | .name = #_name, \ | |
97 | .dev = &devname##_device.dev, \ | |
98 | .parent = &bus##_clk, \ | |
99 | .mode = bus##_clk_mode, \ | |
100 | .get_rate = bus##_clk_get_rate, \ | |
101 | .index = _index, \ | |
102 | } | |
103 | ||
7a5b8059 HS |
104 | static DEFINE_SPINLOCK(pm_lock); |
105 | ||
35bf50cc HCE |
106 | static struct clk osc0; |
107 | static struct clk osc1; | |
108 | ||
5f97f7f9 HS |
109 | static unsigned long osc_get_rate(struct clk *clk) |
110 | { | |
60ed7951 | 111 | return at32_board_osc_rates[clk->index]; |
5f97f7f9 HS |
112 | } |
113 | ||
114 | static unsigned long pll_get_rate(struct clk *clk, unsigned long control) | |
115 | { | |
116 | unsigned long div, mul, rate; | |
117 | ||
7a5b8059 HS |
118 | div = PM_BFEXT(PLLDIV, control) + 1; |
119 | mul = PM_BFEXT(PLLMUL, control) + 1; | |
5f97f7f9 HS |
120 | |
121 | rate = clk->parent->get_rate(clk->parent); | |
122 | rate = (rate + div / 2) / div; | |
123 | rate *= mul; | |
124 | ||
125 | return rate; | |
126 | } | |
127 | ||
35bf50cc HCE |
128 | static long pll_set_rate(struct clk *clk, unsigned long rate, |
129 | u32 *pll_ctrl) | |
130 | { | |
131 | unsigned long mul; | |
132 | unsigned long mul_best_fit = 0; | |
133 | unsigned long div; | |
134 | unsigned long div_min; | |
135 | unsigned long div_max; | |
136 | unsigned long div_best_fit = 0; | |
137 | unsigned long base; | |
138 | unsigned long pll_in; | |
139 | unsigned long actual = 0; | |
140 | unsigned long rate_error; | |
141 | unsigned long rate_error_prev = ~0UL; | |
142 | u32 ctrl; | |
143 | ||
144 | /* Rate must be between 80 MHz and 200 Mhz. */ | |
145 | if (rate < 80000000UL || rate > 200000000UL) | |
146 | return -EINVAL; | |
147 | ||
148 | ctrl = PM_BF(PLLOPT, 4); | |
149 | base = clk->parent->get_rate(clk->parent); | |
150 | ||
151 | /* PLL input frequency must be between 6 MHz and 32 MHz. */ | |
152 | div_min = DIV_ROUND_UP(base, 32000000UL); | |
153 | div_max = base / 6000000UL; | |
154 | ||
155 | if (div_max < div_min) | |
156 | return -EINVAL; | |
157 | ||
158 | for (div = div_min; div <= div_max; div++) { | |
159 | pll_in = (base + div / 2) / div; | |
160 | mul = (rate + pll_in / 2) / pll_in; | |
161 | ||
162 | if (mul == 0) | |
163 | continue; | |
164 | ||
165 | actual = pll_in * mul; | |
166 | rate_error = abs(actual - rate); | |
167 | ||
168 | if (rate_error < rate_error_prev) { | |
169 | mul_best_fit = mul; | |
170 | div_best_fit = div; | |
171 | rate_error_prev = rate_error; | |
172 | } | |
173 | ||
174 | if (rate_error == 0) | |
175 | break; | |
176 | } | |
177 | ||
178 | if (div_best_fit == 0) | |
179 | return -EINVAL; | |
180 | ||
181 | ctrl |= PM_BF(PLLMUL, mul_best_fit - 1); | |
182 | ctrl |= PM_BF(PLLDIV, div_best_fit - 1); | |
183 | ctrl |= PM_BF(PLLCOUNT, 16); | |
184 | ||
185 | if (clk->parent == &osc1) | |
186 | ctrl |= PM_BIT(PLLOSC); | |
187 | ||
188 | *pll_ctrl = ctrl; | |
189 | ||
190 | return actual; | |
191 | } | |
192 | ||
5f97f7f9 HS |
193 | static unsigned long pll0_get_rate(struct clk *clk) |
194 | { | |
195 | u32 control; | |
196 | ||
7a5b8059 | 197 | control = pm_readl(PLL0); |
5f97f7f9 HS |
198 | |
199 | return pll_get_rate(clk, control); | |
200 | } | |
201 | ||
35bf50cc HCE |
202 | static void pll1_mode(struct clk *clk, int enabled) |
203 | { | |
204 | unsigned long timeout; | |
205 | u32 status; | |
206 | u32 ctrl; | |
207 | ||
208 | ctrl = pm_readl(PLL1); | |
209 | ||
210 | if (enabled) { | |
211 | if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) { | |
212 | pr_debug("clk %s: failed to enable, rate not set\n", | |
213 | clk->name); | |
214 | return; | |
215 | } | |
216 | ||
217 | ctrl |= PM_BIT(PLLEN); | |
218 | pm_writel(PLL1, ctrl); | |
219 | ||
220 | /* Wait for PLL lock. */ | |
221 | for (timeout = 10000; timeout; timeout--) { | |
222 | status = pm_readl(ISR); | |
223 | if (status & PM_BIT(LOCK1)) | |
224 | break; | |
225 | udelay(10); | |
226 | } | |
227 | ||
228 | if (!(status & PM_BIT(LOCK1))) | |
229 | printk(KERN_ERR "clk %s: timeout waiting for lock\n", | |
230 | clk->name); | |
231 | } else { | |
232 | ctrl &= ~PM_BIT(PLLEN); | |
233 | pm_writel(PLL1, ctrl); | |
234 | } | |
235 | } | |
236 | ||
5f97f7f9 HS |
237 | static unsigned long pll1_get_rate(struct clk *clk) |
238 | { | |
239 | u32 control; | |
240 | ||
7a5b8059 | 241 | control = pm_readl(PLL1); |
5f97f7f9 HS |
242 | |
243 | return pll_get_rate(clk, control); | |
244 | } | |
245 | ||
35bf50cc HCE |
246 | static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply) |
247 | { | |
248 | u32 ctrl = 0; | |
249 | unsigned long actual_rate; | |
250 | ||
251 | actual_rate = pll_set_rate(clk, rate, &ctrl); | |
252 | ||
253 | if (apply) { | |
254 | if (actual_rate != rate) | |
255 | return -EINVAL; | |
256 | if (clk->users > 0) | |
257 | return -EBUSY; | |
258 | pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n", | |
259 | clk->name, rate, actual_rate); | |
260 | pm_writel(PLL1, ctrl); | |
261 | } | |
262 | ||
263 | return actual_rate; | |
264 | } | |
265 | ||
266 | static int pll1_set_parent(struct clk *clk, struct clk *parent) | |
267 | { | |
268 | u32 ctrl; | |
269 | ||
270 | if (clk->users > 0) | |
271 | return -EBUSY; | |
272 | ||
273 | ctrl = pm_readl(PLL1); | |
274 | WARN_ON(ctrl & PM_BIT(PLLEN)); | |
275 | ||
276 | if (parent == &osc0) | |
277 | ctrl &= ~PM_BIT(PLLOSC); | |
278 | else if (parent == &osc1) | |
279 | ctrl |= PM_BIT(PLLOSC); | |
280 | else | |
281 | return -EINVAL; | |
282 | ||
283 | pm_writel(PLL1, ctrl); | |
284 | clk->parent = parent; | |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
5f97f7f9 HS |
289 | /* |
290 | * The AT32AP7000 has five primary clock sources: One 32kHz | |
291 | * oscillator, two crystal oscillators and two PLLs. | |
292 | */ | |
293 | static struct clk osc32k = { | |
294 | .name = "osc32k", | |
295 | .get_rate = osc_get_rate, | |
296 | .users = 1, | |
297 | .index = 0, | |
298 | }; | |
299 | static struct clk osc0 = { | |
300 | .name = "osc0", | |
301 | .get_rate = osc_get_rate, | |
302 | .users = 1, | |
303 | .index = 1, | |
304 | }; | |
305 | static struct clk osc1 = { | |
306 | .name = "osc1", | |
307 | .get_rate = osc_get_rate, | |
308 | .index = 2, | |
309 | }; | |
310 | static struct clk pll0 = { | |
311 | .name = "pll0", | |
312 | .get_rate = pll0_get_rate, | |
313 | .parent = &osc0, | |
314 | }; | |
315 | static struct clk pll1 = { | |
316 | .name = "pll1", | |
35bf50cc | 317 | .mode = pll1_mode, |
5f97f7f9 | 318 | .get_rate = pll1_get_rate, |
35bf50cc HCE |
319 | .set_rate = pll1_set_rate, |
320 | .set_parent = pll1_set_parent, | |
5f97f7f9 HS |
321 | .parent = &osc0, |
322 | }; | |
323 | ||
324 | /* | |
325 | * The main clock can be either osc0 or pll0. The boot loader may | |
326 | * have chosen one for us, so we don't really know which one until we | |
327 | * have a look at the SM. | |
328 | */ | |
329 | static struct clk *main_clock; | |
330 | ||
331 | /* | |
332 | * Synchronous clocks are generated from the main clock. The clocks | |
333 | * must satisfy the constraint | |
334 | * fCPU >= fHSB >= fPB | |
335 | * i.e. each clock must not be faster than its parent. | |
336 | */ | |
337 | static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift) | |
338 | { | |
339 | return main_clock->get_rate(main_clock) >> shift; | |
340 | }; | |
341 | ||
342 | static void cpu_clk_mode(struct clk *clk, int enabled) | |
343 | { | |
5f97f7f9 HS |
344 | unsigned long flags; |
345 | u32 mask; | |
346 | ||
7a5b8059 HS |
347 | spin_lock_irqsave(&pm_lock, flags); |
348 | mask = pm_readl(CPU_MASK); | |
5f97f7f9 HS |
349 | if (enabled) |
350 | mask |= 1 << clk->index; | |
351 | else | |
352 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
353 | pm_writel(CPU_MASK, mask); |
354 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
355 | } |
356 | ||
357 | static unsigned long cpu_clk_get_rate(struct clk *clk) | |
358 | { | |
359 | unsigned long cksel, shift = 0; | |
360 | ||
7a5b8059 HS |
361 | cksel = pm_readl(CKSEL); |
362 | if (cksel & PM_BIT(CPUDIV)) | |
363 | shift = PM_BFEXT(CPUSEL, cksel) + 1; | |
5f97f7f9 HS |
364 | |
365 | return bus_clk_get_rate(clk, shift); | |
366 | } | |
367 | ||
9e58e185 HCE |
368 | static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply) |
369 | { | |
370 | u32 control; | |
371 | unsigned long parent_rate, child_div, actual_rate, div; | |
372 | ||
373 | parent_rate = clk->parent->get_rate(clk->parent); | |
374 | control = pm_readl(CKSEL); | |
375 | ||
376 | if (control & PM_BIT(HSBDIV)) | |
377 | child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1); | |
378 | else | |
379 | child_div = 1; | |
380 | ||
381 | if (rate > 3 * (parent_rate / 4) || child_div == 1) { | |
382 | actual_rate = parent_rate; | |
383 | control &= ~PM_BIT(CPUDIV); | |
384 | } else { | |
385 | unsigned int cpusel; | |
386 | div = (parent_rate + rate / 2) / rate; | |
387 | if (div > child_div) | |
388 | div = child_div; | |
389 | cpusel = (div > 1) ? (fls(div) - 2) : 0; | |
390 | control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control); | |
391 | actual_rate = parent_rate / (1 << (cpusel + 1)); | |
392 | } | |
393 | ||
394 | pr_debug("clk %s: new rate %lu (actual rate %lu)\n", | |
395 | clk->name, rate, actual_rate); | |
396 | ||
397 | if (apply) | |
398 | pm_writel(CKSEL, control); | |
399 | ||
400 | return actual_rate; | |
401 | } | |
402 | ||
5f97f7f9 HS |
403 | static void hsb_clk_mode(struct clk *clk, int enabled) |
404 | { | |
5f97f7f9 HS |
405 | unsigned long flags; |
406 | u32 mask; | |
407 | ||
7a5b8059 HS |
408 | spin_lock_irqsave(&pm_lock, flags); |
409 | mask = pm_readl(HSB_MASK); | |
5f97f7f9 HS |
410 | if (enabled) |
411 | mask |= 1 << clk->index; | |
412 | else | |
413 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
414 | pm_writel(HSB_MASK, mask); |
415 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
416 | } |
417 | ||
418 | static unsigned long hsb_clk_get_rate(struct clk *clk) | |
419 | { | |
420 | unsigned long cksel, shift = 0; | |
421 | ||
7a5b8059 HS |
422 | cksel = pm_readl(CKSEL); |
423 | if (cksel & PM_BIT(HSBDIV)) | |
424 | shift = PM_BFEXT(HSBSEL, cksel) + 1; | |
5f97f7f9 HS |
425 | |
426 | return bus_clk_get_rate(clk, shift); | |
427 | } | |
428 | ||
dd5e1339 | 429 | void pba_clk_mode(struct clk *clk, int enabled) |
5f97f7f9 | 430 | { |
5f97f7f9 HS |
431 | unsigned long flags; |
432 | u32 mask; | |
433 | ||
7a5b8059 HS |
434 | spin_lock_irqsave(&pm_lock, flags); |
435 | mask = pm_readl(PBA_MASK); | |
5f97f7f9 HS |
436 | if (enabled) |
437 | mask |= 1 << clk->index; | |
438 | else | |
439 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
440 | pm_writel(PBA_MASK, mask); |
441 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
442 | } |
443 | ||
dd5e1339 | 444 | unsigned long pba_clk_get_rate(struct clk *clk) |
5f97f7f9 HS |
445 | { |
446 | unsigned long cksel, shift = 0; | |
447 | ||
7a5b8059 HS |
448 | cksel = pm_readl(CKSEL); |
449 | if (cksel & PM_BIT(PBADIV)) | |
450 | shift = PM_BFEXT(PBASEL, cksel) + 1; | |
5f97f7f9 HS |
451 | |
452 | return bus_clk_get_rate(clk, shift); | |
453 | } | |
454 | ||
455 | static void pbb_clk_mode(struct clk *clk, int enabled) | |
456 | { | |
5f97f7f9 HS |
457 | unsigned long flags; |
458 | u32 mask; | |
459 | ||
7a5b8059 HS |
460 | spin_lock_irqsave(&pm_lock, flags); |
461 | mask = pm_readl(PBB_MASK); | |
5f97f7f9 HS |
462 | if (enabled) |
463 | mask |= 1 << clk->index; | |
464 | else | |
465 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
466 | pm_writel(PBB_MASK, mask); |
467 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
468 | } |
469 | ||
470 | static unsigned long pbb_clk_get_rate(struct clk *clk) | |
471 | { | |
472 | unsigned long cksel, shift = 0; | |
473 | ||
7a5b8059 HS |
474 | cksel = pm_readl(CKSEL); |
475 | if (cksel & PM_BIT(PBBDIV)) | |
476 | shift = PM_BFEXT(PBBSEL, cksel) + 1; | |
5f97f7f9 HS |
477 | |
478 | return bus_clk_get_rate(clk, shift); | |
479 | } | |
480 | ||
481 | static struct clk cpu_clk = { | |
482 | .name = "cpu", | |
483 | .get_rate = cpu_clk_get_rate, | |
9e58e185 | 484 | .set_rate = cpu_clk_set_rate, |
5f97f7f9 HS |
485 | .users = 1, |
486 | }; | |
487 | static struct clk hsb_clk = { | |
488 | .name = "hsb", | |
489 | .parent = &cpu_clk, | |
490 | .get_rate = hsb_clk_get_rate, | |
491 | }; | |
492 | static struct clk pba_clk = { | |
493 | .name = "pba", | |
494 | .parent = &hsb_clk, | |
495 | .mode = hsb_clk_mode, | |
496 | .get_rate = pba_clk_get_rate, | |
497 | .index = 1, | |
498 | }; | |
499 | static struct clk pbb_clk = { | |
500 | .name = "pbb", | |
501 | .parent = &hsb_clk, | |
502 | .mode = hsb_clk_mode, | |
503 | .get_rate = pbb_clk_get_rate, | |
504 | .users = 1, | |
505 | .index = 2, | |
506 | }; | |
507 | ||
508 | /* -------------------------------------------------------------------- | |
509 | * Generic Clock operations | |
510 | * -------------------------------------------------------------------- */ | |
511 | ||
512 | static void genclk_mode(struct clk *clk, int enabled) | |
513 | { | |
514 | u32 control; | |
515 | ||
7a5b8059 | 516 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 | 517 | if (enabled) |
7a5b8059 | 518 | control |= PM_BIT(CEN); |
5f97f7f9 | 519 | else |
7a5b8059 HS |
520 | control &= ~PM_BIT(CEN); |
521 | pm_writel(GCCTRL(clk->index), control); | |
5f97f7f9 HS |
522 | } |
523 | ||
524 | static unsigned long genclk_get_rate(struct clk *clk) | |
525 | { | |
526 | u32 control; | |
527 | unsigned long div = 1; | |
528 | ||
7a5b8059 HS |
529 | control = pm_readl(GCCTRL(clk->index)); |
530 | if (control & PM_BIT(DIVEN)) | |
531 | div = 2 * (PM_BFEXT(DIV, control) + 1); | |
5f97f7f9 HS |
532 | |
533 | return clk->parent->get_rate(clk->parent) / div; | |
534 | } | |
535 | ||
536 | static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply) | |
537 | { | |
538 | u32 control; | |
539 | unsigned long parent_rate, actual_rate, div; | |
540 | ||
5f97f7f9 | 541 | parent_rate = clk->parent->get_rate(clk->parent); |
7a5b8059 | 542 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
543 | |
544 | if (rate > 3 * parent_rate / 4) { | |
545 | actual_rate = parent_rate; | |
7a5b8059 | 546 | control &= ~PM_BIT(DIVEN); |
5f97f7f9 HS |
547 | } else { |
548 | div = (parent_rate + rate) / (2 * rate) - 1; | |
7a5b8059 | 549 | control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN); |
5f97f7f9 HS |
550 | actual_rate = parent_rate / (2 * (div + 1)); |
551 | } | |
552 | ||
7a5b8059 HS |
553 | dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n", |
554 | clk->name, rate, actual_rate); | |
5f97f7f9 HS |
555 | |
556 | if (apply) | |
7a5b8059 | 557 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
558 | |
559 | return actual_rate; | |
560 | } | |
561 | ||
562 | int genclk_set_parent(struct clk *clk, struct clk *parent) | |
563 | { | |
564 | u32 control; | |
565 | ||
7a5b8059 HS |
566 | dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n", |
567 | clk->name, parent->name, clk->parent->name); | |
5f97f7f9 | 568 | |
7a5b8059 | 569 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
570 | |
571 | if (parent == &osc1 || parent == &pll1) | |
7a5b8059 | 572 | control |= PM_BIT(OSCSEL); |
5f97f7f9 | 573 | else if (parent == &osc0 || parent == &pll0) |
7a5b8059 | 574 | control &= ~PM_BIT(OSCSEL); |
5f97f7f9 HS |
575 | else |
576 | return -EINVAL; | |
577 | ||
578 | if (parent == &pll0 || parent == &pll1) | |
7a5b8059 | 579 | control |= PM_BIT(PLLSEL); |
5f97f7f9 | 580 | else |
7a5b8059 | 581 | control &= ~PM_BIT(PLLSEL); |
5f97f7f9 | 582 | |
7a5b8059 | 583 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
584 | clk->parent = parent; |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
7a5fe238 HS |
589 | static void __init genclk_init_parent(struct clk *clk) |
590 | { | |
591 | u32 control; | |
592 | struct clk *parent; | |
593 | ||
594 | BUG_ON(clk->index > 7); | |
595 | ||
7a5b8059 HS |
596 | control = pm_readl(GCCTRL(clk->index)); |
597 | if (control & PM_BIT(OSCSEL)) | |
598 | parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1; | |
7a5fe238 | 599 | else |
7a5b8059 | 600 | parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0; |
7a5fe238 HS |
601 | |
602 | clk->parent = parent; | |
603 | } | |
604 | ||
3bfb1d20 HS |
605 | static struct dw_dma_platform_data dw_dmac0_data = { |
606 | .nr_channels = 3, | |
607 | }; | |
608 | ||
609 | static struct resource dw_dmac0_resource[] = { | |
610 | PBMEM(0xff200000), | |
611 | IRQ(2), | |
612 | }; | |
613 | DEFINE_DEV_DATA(dw_dmac, 0); | |
614 | DEV_CLK(hclk, dw_dmac0, hsb, 10); | |
615 | ||
5f97f7f9 HS |
616 | /* -------------------------------------------------------------------- |
617 | * System peripherals | |
618 | * -------------------------------------------------------------------- */ | |
7a5b8059 HS |
619 | static struct resource at32_pm0_resource[] = { |
620 | { | |
621 | .start = 0xfff00000, | |
622 | .end = 0xfff0007f, | |
623 | .flags = IORESOURCE_MEM, | |
624 | }, | |
625 | IRQ(20), | |
5f97f7f9 | 626 | }; |
7a5b8059 HS |
627 | |
628 | static struct resource at32ap700x_rtc0_resource[] = { | |
629 | { | |
630 | .start = 0xfff00080, | |
631 | .end = 0xfff000af, | |
632 | .flags = IORESOURCE_MEM, | |
633 | }, | |
634 | IRQ(21), | |
5f97f7f9 | 635 | }; |
7a5b8059 HS |
636 | |
637 | static struct resource at32_wdt0_resource[] = { | |
638 | { | |
639 | .start = 0xfff000b0, | |
9797bed2 | 640 | .end = 0xfff000cf, |
7a5b8059 HS |
641 | .flags = IORESOURCE_MEM, |
642 | }, | |
643 | }; | |
644 | ||
645 | static struct resource at32_eic0_resource[] = { | |
646 | { | |
647 | .start = 0xfff00100, | |
648 | .end = 0xfff0013f, | |
649 | .flags = IORESOURCE_MEM, | |
650 | }, | |
651 | IRQ(19), | |
652 | }; | |
653 | ||
654 | DEFINE_DEV(at32_pm, 0); | |
655 | DEFINE_DEV(at32ap700x_rtc, 0); | |
656 | DEFINE_DEV(at32_wdt, 0); | |
657 | DEFINE_DEV(at32_eic, 0); | |
658 | ||
659 | /* | |
660 | * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this | |
661 | * is always running. | |
662 | */ | |
663 | static struct clk at32_pm_pclk = { | |
188ff65d | 664 | .name = "pclk", |
7a5b8059 | 665 | .dev = &at32_pm0_device.dev, |
188ff65d HS |
666 | .parent = &pbb_clk, |
667 | .mode = pbb_clk_mode, | |
668 | .get_rate = pbb_clk_get_rate, | |
669 | .users = 1, | |
670 | .index = 0, | |
671 | }; | |
5f97f7f9 HS |
672 | |
673 | static struct resource intc0_resource[] = { | |
674 | PBMEM(0xfff00400), | |
675 | }; | |
676 | struct platform_device at32_intc0_device = { | |
677 | .name = "intc", | |
678 | .id = 0, | |
679 | .resource = intc0_resource, | |
680 | .num_resources = ARRAY_SIZE(intc0_resource), | |
681 | }; | |
682 | DEV_CLK(pclk, at32_intc0, pbb, 1); | |
683 | ||
684 | static struct clk ebi_clk = { | |
685 | .name = "ebi", | |
686 | .parent = &hsb_clk, | |
687 | .mode = hsb_clk_mode, | |
688 | .get_rate = hsb_clk_get_rate, | |
689 | .users = 1, | |
690 | }; | |
691 | static struct clk hramc_clk = { | |
692 | .name = "hramc", | |
693 | .parent = &hsb_clk, | |
694 | .mode = hsb_clk_mode, | |
695 | .get_rate = hsb_clk_get_rate, | |
696 | .users = 1, | |
188ff65d | 697 | .index = 3, |
5f97f7f9 | 698 | }; |
7951f188 HS |
699 | static struct clk sdramc_clk = { |
700 | .name = "sdramc_clk", | |
701 | .parent = &pbb_clk, | |
702 | .mode = pbb_clk_mode, | |
703 | .get_rate = pbb_clk_get_rate, | |
704 | .users = 1, | |
705 | .index = 14, | |
706 | }; | |
5f97f7f9 | 707 | |
bc157b75 HS |
708 | static struct resource smc0_resource[] = { |
709 | PBMEM(0xfff03400), | |
710 | }; | |
711 | DEFINE_DEV(smc, 0); | |
712 | DEV_CLK(pclk, smc0, pbb, 13); | |
713 | DEV_CLK(mck, smc0, hsb, 0); | |
714 | ||
5f97f7f9 HS |
715 | static struct platform_device pdc_device = { |
716 | .name = "pdc", | |
717 | .id = 0, | |
718 | }; | |
719 | DEV_CLK(hclk, pdc, hsb, 4); | |
720 | DEV_CLK(pclk, pdc, pba, 16); | |
721 | ||
722 | static struct clk pico_clk = { | |
723 | .name = "pico", | |
724 | .parent = &cpu_clk, | |
725 | .mode = cpu_clk_mode, | |
726 | .get_rate = cpu_clk_get_rate, | |
727 | .users = 1, | |
728 | }; | |
729 | ||
9c8f8e75 HS |
730 | /* -------------------------------------------------------------------- |
731 | * HMATRIX | |
732 | * -------------------------------------------------------------------- */ | |
733 | ||
b47eb409 | 734 | struct clk at32_hmatrix_clk = { |
9c8f8e75 HS |
735 | .name = "hmatrix_clk", |
736 | .parent = &pbb_clk, | |
737 | .mode = pbb_clk_mode, | |
738 | .get_rate = pbb_clk_get_rate, | |
739 | .index = 2, | |
740 | .users = 1, | |
741 | }; | |
9c8f8e75 HS |
742 | |
743 | /* | |
744 | * Set bits in the HMATRIX Special Function Register (SFR) used by the | |
745 | * External Bus Interface (EBI). This can be used to enable special | |
746 | * features like CompactFlash support, NAND Flash support, etc. on | |
747 | * certain chipselects. | |
748 | */ | |
749 | static inline void set_ebi_sfr_bits(u32 mask) | |
750 | { | |
b47eb409 | 751 | hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask); |
9c8f8e75 HS |
752 | } |
753 | ||
7760989e | 754 | /* -------------------------------------------------------------------- |
e723ff66 | 755 | * Timer/Counter (TC) |
7760989e | 756 | * -------------------------------------------------------------------- */ |
e723ff66 DB |
757 | |
758 | static struct resource at32_tcb0_resource[] = { | |
7760989e HCE |
759 | PBMEM(0xfff00c00), |
760 | IRQ(22), | |
761 | }; | |
e723ff66 DB |
762 | static struct platform_device at32_tcb0_device = { |
763 | .name = "atmel_tcb", | |
7760989e | 764 | .id = 0, |
e723ff66 DB |
765 | .resource = at32_tcb0_resource, |
766 | .num_resources = ARRAY_SIZE(at32_tcb0_resource), | |
767 | }; | |
768 | DEV_CLK(t0_clk, at32_tcb0, pbb, 3); | |
769 | ||
770 | static struct resource at32_tcb1_resource[] = { | |
771 | PBMEM(0xfff01000), | |
772 | IRQ(23), | |
773 | }; | |
774 | static struct platform_device at32_tcb1_device = { | |
775 | .name = "atmel_tcb", | |
776 | .id = 1, | |
777 | .resource = at32_tcb1_resource, | |
778 | .num_resources = ARRAY_SIZE(at32_tcb1_resource), | |
7760989e | 779 | }; |
e723ff66 | 780 | DEV_CLK(t0_clk, at32_tcb1, pbb, 4); |
7760989e | 781 | |
5f97f7f9 HS |
782 | /* -------------------------------------------------------------------- |
783 | * PIO | |
784 | * -------------------------------------------------------------------- */ | |
785 | ||
786 | static struct resource pio0_resource[] = { | |
787 | PBMEM(0xffe02800), | |
788 | IRQ(13), | |
789 | }; | |
790 | DEFINE_DEV(pio, 0); | |
791 | DEV_CLK(mck, pio0, pba, 10); | |
792 | ||
793 | static struct resource pio1_resource[] = { | |
794 | PBMEM(0xffe02c00), | |
795 | IRQ(14), | |
796 | }; | |
797 | DEFINE_DEV(pio, 1); | |
798 | DEV_CLK(mck, pio1, pba, 11); | |
799 | ||
800 | static struct resource pio2_resource[] = { | |
801 | PBMEM(0xffe03000), | |
802 | IRQ(15), | |
803 | }; | |
804 | DEFINE_DEV(pio, 2); | |
805 | DEV_CLK(mck, pio2, pba, 12); | |
806 | ||
807 | static struct resource pio3_resource[] = { | |
808 | PBMEM(0xffe03400), | |
809 | IRQ(16), | |
810 | }; | |
811 | DEFINE_DEV(pio, 3); | |
812 | DEV_CLK(mck, pio3, pba, 13); | |
813 | ||
7f9f4678 HS |
814 | static struct resource pio4_resource[] = { |
815 | PBMEM(0xffe03800), | |
816 | IRQ(17), | |
817 | }; | |
818 | DEFINE_DEV(pio, 4); | |
819 | DEV_CLK(mck, pio4, pba, 14); | |
820 | ||
e82c6106 | 821 | static int __init system_device_init(void) |
5f97f7f9 | 822 | { |
7a5b8059 | 823 | platform_device_register(&at32_pm0_device); |
5f97f7f9 | 824 | platform_device_register(&at32_intc0_device); |
7a5b8059 HS |
825 | platform_device_register(&at32ap700x_rtc0_device); |
826 | platform_device_register(&at32_wdt0_device); | |
827 | platform_device_register(&at32_eic0_device); | |
bc157b75 | 828 | platform_device_register(&smc0_device); |
5f97f7f9 | 829 | platform_device_register(&pdc_device); |
3bfb1d20 | 830 | platform_device_register(&dw_dmac0_device); |
5f97f7f9 | 831 | |
e723ff66 DB |
832 | platform_device_register(&at32_tcb0_device); |
833 | platform_device_register(&at32_tcb1_device); | |
7760989e | 834 | |
5f97f7f9 HS |
835 | platform_device_register(&pio0_device); |
836 | platform_device_register(&pio1_device); | |
837 | platform_device_register(&pio2_device); | |
838 | platform_device_register(&pio3_device); | |
7f9f4678 | 839 | platform_device_register(&pio4_device); |
e82c6106 HS |
840 | |
841 | return 0; | |
5f97f7f9 | 842 | } |
e82c6106 | 843 | core_initcall(system_device_init); |
5f97f7f9 | 844 | |
d86d314f HCE |
845 | /* -------------------------------------------------------------------- |
846 | * PSIF | |
847 | * -------------------------------------------------------------------- */ | |
848 | static struct resource atmel_psif0_resource[] __initdata = { | |
849 | { | |
850 | .start = 0xffe03c00, | |
851 | .end = 0xffe03cff, | |
852 | .flags = IORESOURCE_MEM, | |
853 | }, | |
854 | IRQ(18), | |
855 | }; | |
856 | static struct clk atmel_psif0_pclk = { | |
857 | .name = "pclk", | |
858 | .parent = &pba_clk, | |
859 | .mode = pba_clk_mode, | |
860 | .get_rate = pba_clk_get_rate, | |
861 | .index = 15, | |
862 | }; | |
863 | ||
864 | static struct resource atmel_psif1_resource[] __initdata = { | |
865 | { | |
866 | .start = 0xffe03d00, | |
867 | .end = 0xffe03dff, | |
868 | .flags = IORESOURCE_MEM, | |
869 | }, | |
870 | IRQ(18), | |
871 | }; | |
872 | static struct clk atmel_psif1_pclk = { | |
873 | .name = "pclk", | |
874 | .parent = &pba_clk, | |
875 | .mode = pba_clk_mode, | |
876 | .get_rate = pba_clk_get_rate, | |
877 | .index = 15, | |
878 | }; | |
879 | ||
880 | struct platform_device *__init at32_add_device_psif(unsigned int id) | |
881 | { | |
882 | struct platform_device *pdev; | |
caf18f19 | 883 | u32 pin_mask; |
d86d314f HCE |
884 | |
885 | if (!(id == 0 || id == 1)) | |
886 | return NULL; | |
887 | ||
888 | pdev = platform_device_alloc("atmel_psif", id); | |
889 | if (!pdev) | |
890 | return NULL; | |
891 | ||
892 | switch (id) { | |
893 | case 0: | |
caf18f19 JM |
894 | pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */ |
895 | ||
d86d314f HCE |
896 | if (platform_device_add_resources(pdev, atmel_psif0_resource, |
897 | ARRAY_SIZE(atmel_psif0_resource))) | |
898 | goto err_add_resources; | |
899 | atmel_psif0_pclk.dev = &pdev->dev; | |
caf18f19 | 900 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); |
d86d314f HCE |
901 | break; |
902 | case 1: | |
caf18f19 JM |
903 | pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */ |
904 | ||
d86d314f HCE |
905 | if (platform_device_add_resources(pdev, atmel_psif1_resource, |
906 | ARRAY_SIZE(atmel_psif1_resource))) | |
907 | goto err_add_resources; | |
908 | atmel_psif1_pclk.dev = &pdev->dev; | |
caf18f19 | 909 | select_peripheral(PIOB, pin_mask, PERIPH_A, 0); |
d86d314f HCE |
910 | break; |
911 | default: | |
912 | return NULL; | |
913 | } | |
914 | ||
915 | platform_device_add(pdev); | |
916 | return pdev; | |
917 | ||
918 | err_add_resources: | |
919 | platform_device_put(pdev); | |
920 | return NULL; | |
921 | } | |
922 | ||
5f97f7f9 HS |
923 | /* -------------------------------------------------------------------- |
924 | * USART | |
925 | * -------------------------------------------------------------------- */ | |
926 | ||
75d35213 HS |
927 | static struct atmel_uart_data atmel_usart0_data = { |
928 | .use_dma_tx = 1, | |
929 | .use_dma_rx = 1, | |
930 | }; | |
1e8ea802 | 931 | static struct resource atmel_usart0_resource[] = { |
5f97f7f9 | 932 | PBMEM(0xffe00c00), |
a3d912c8 | 933 | IRQ(6), |
5f97f7f9 | 934 | }; |
75d35213 | 935 | DEFINE_DEV_DATA(atmel_usart, 0); |
80f76c54 | 936 | DEV_CLK(usart, atmel_usart0, pba, 3); |
5f97f7f9 | 937 | |
75d35213 HS |
938 | static struct atmel_uart_data atmel_usart1_data = { |
939 | .use_dma_tx = 1, | |
940 | .use_dma_rx = 1, | |
941 | }; | |
1e8ea802 | 942 | static struct resource atmel_usart1_resource[] = { |
5f97f7f9 HS |
943 | PBMEM(0xffe01000), |
944 | IRQ(7), | |
945 | }; | |
75d35213 | 946 | DEFINE_DEV_DATA(atmel_usart, 1); |
1e8ea802 | 947 | DEV_CLK(usart, atmel_usart1, pba, 4); |
5f97f7f9 | 948 | |
75d35213 HS |
949 | static struct atmel_uart_data atmel_usart2_data = { |
950 | .use_dma_tx = 1, | |
951 | .use_dma_rx = 1, | |
952 | }; | |
1e8ea802 | 953 | static struct resource atmel_usart2_resource[] = { |
5f97f7f9 HS |
954 | PBMEM(0xffe01400), |
955 | IRQ(8), | |
956 | }; | |
75d35213 | 957 | DEFINE_DEV_DATA(atmel_usart, 2); |
1e8ea802 | 958 | DEV_CLK(usart, atmel_usart2, pba, 5); |
5f97f7f9 | 959 | |
75d35213 HS |
960 | static struct atmel_uart_data atmel_usart3_data = { |
961 | .use_dma_tx = 1, | |
962 | .use_dma_rx = 1, | |
963 | }; | |
1e8ea802 | 964 | static struct resource atmel_usart3_resource[] = { |
5f97f7f9 HS |
965 | PBMEM(0xffe01800), |
966 | IRQ(9), | |
967 | }; | |
75d35213 | 968 | DEFINE_DEV_DATA(atmel_usart, 3); |
1e8ea802 | 969 | DEV_CLK(usart, atmel_usart3, pba, 6); |
5f97f7f9 | 970 | |
bf4861cf | 971 | static inline void configure_usart0_pins(int flags) |
5f97f7f9 | 972 | { |
caf18f19 | 973 | u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */ |
bf4861cf PM |
974 | if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 6); |
975 | if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 7); | |
976 | if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 10); | |
caf18f19 | 977 | |
10546263 | 978 | select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); |
5f97f7f9 HS |
979 | } |
980 | ||
bf4861cf | 981 | static inline void configure_usart1_pins(int flags) |
5f97f7f9 | 982 | { |
caf18f19 | 983 | u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */ |
bf4861cf PM |
984 | if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 19); |
985 | if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 20); | |
986 | if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 16); | |
caf18f19 | 987 | |
10546263 | 988 | select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP); |
5f97f7f9 HS |
989 | } |
990 | ||
bf4861cf | 991 | static inline void configure_usart2_pins(int flags) |
5f97f7f9 | 992 | { |
caf18f19 | 993 | u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */ |
bf4861cf PM |
994 | if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 30); |
995 | if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 29); | |
996 | if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 28); | |
caf18f19 | 997 | |
10546263 | 998 | select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); |
5f97f7f9 HS |
999 | } |
1000 | ||
bf4861cf | 1001 | static inline void configure_usart3_pins(int flags) |
5f97f7f9 | 1002 | { |
caf18f19 | 1003 | u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */ |
bf4861cf PM |
1004 | if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 16); |
1005 | if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 15); | |
1006 | if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 19); | |
caf18f19 | 1007 | |
10546263 | 1008 | select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); |
5f97f7f9 HS |
1009 | } |
1010 | ||
a3d912c8 | 1011 | static struct platform_device *__initdata at32_usarts[4]; |
c194588d | 1012 | |
bf4861cf | 1013 | void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags) |
5f97f7f9 HS |
1014 | { |
1015 | struct platform_device *pdev; | |
1016 | ||
c194588d | 1017 | switch (hw_id) { |
5f97f7f9 | 1018 | case 0: |
1e8ea802 | 1019 | pdev = &atmel_usart0_device; |
bf4861cf | 1020 | configure_usart0_pins(flags); |
5f97f7f9 HS |
1021 | break; |
1022 | case 1: | |
1e8ea802 | 1023 | pdev = &atmel_usart1_device; |
bf4861cf | 1024 | configure_usart1_pins(flags); |
5f97f7f9 HS |
1025 | break; |
1026 | case 2: | |
1e8ea802 | 1027 | pdev = &atmel_usart2_device; |
bf4861cf | 1028 | configure_usart2_pins(flags); |
5f97f7f9 HS |
1029 | break; |
1030 | case 3: | |
1e8ea802 | 1031 | pdev = &atmel_usart3_device; |
bf4861cf | 1032 | configure_usart3_pins(flags); |
5f97f7f9 HS |
1033 | break; |
1034 | default: | |
c194588d | 1035 | return; |
75d35213 HS |
1036 | } |
1037 | ||
1038 | if (PXSEG(pdev->resource[0].start) == P4SEG) { | |
1039 | /* Addresses in the P4 segment are permanently mapped 1:1 */ | |
1040 | struct atmel_uart_data *data = pdev->dev.platform_data; | |
1041 | data->regs = (void __iomem *)pdev->resource[0].start; | |
5f97f7f9 HS |
1042 | } |
1043 | ||
c194588d HS |
1044 | pdev->id = line; |
1045 | at32_usarts[line] = pdev; | |
5f97f7f9 HS |
1046 | } |
1047 | ||
1048 | struct platform_device *__init at32_add_device_usart(unsigned int id) | |
1049 | { | |
c194588d HS |
1050 | platform_device_register(at32_usarts[id]); |
1051 | return at32_usarts[id]; | |
5f97f7f9 HS |
1052 | } |
1053 | ||
73e2798b | 1054 | struct platform_device *atmel_default_console_device; |
5f97f7f9 HS |
1055 | |
1056 | void __init at32_setup_serial_console(unsigned int usart_id) | |
1057 | { | |
c194588d | 1058 | atmel_default_console_device = at32_usarts[usart_id]; |
5f97f7f9 HS |
1059 | } |
1060 | ||
1061 | /* -------------------------------------------------------------------- | |
1062 | * Ethernet | |
1063 | * -------------------------------------------------------------------- */ | |
1064 | ||
438ff3f3 | 1065 | #ifdef CONFIG_CPU_AT32AP7000 |
5f97f7f9 HS |
1066 | static struct eth_platform_data macb0_data; |
1067 | static struct resource macb0_resource[] = { | |
1068 | PBMEM(0xfff01800), | |
1069 | IRQ(25), | |
1070 | }; | |
1071 | DEFINE_DEV_DATA(macb, 0); | |
1072 | DEV_CLK(hclk, macb0, hsb, 8); | |
1073 | DEV_CLK(pclk, macb0, pbb, 6); | |
1074 | ||
cfcb3a89 HS |
1075 | static struct eth_platform_data macb1_data; |
1076 | static struct resource macb1_resource[] = { | |
1077 | PBMEM(0xfff01c00), | |
1078 | IRQ(26), | |
1079 | }; | |
1080 | DEFINE_DEV_DATA(macb, 1); | |
1081 | DEV_CLK(hclk, macb1, hsb, 9); | |
1082 | DEV_CLK(pclk, macb1, pbb, 7); | |
1083 | ||
5f97f7f9 HS |
1084 | struct platform_device *__init |
1085 | at32_add_device_eth(unsigned int id, struct eth_platform_data *data) | |
1086 | { | |
1087 | struct platform_device *pdev; | |
caf18f19 | 1088 | u32 pin_mask; |
5f97f7f9 HS |
1089 | |
1090 | switch (id) { | |
1091 | case 0: | |
1092 | pdev = &macb0_device; | |
1093 | ||
caf18f19 JM |
1094 | pin_mask = (1 << 3); /* TXD0 */ |
1095 | pin_mask |= (1 << 4); /* TXD1 */ | |
1096 | pin_mask |= (1 << 7); /* TXEN */ | |
1097 | pin_mask |= (1 << 8); /* TXCK */ | |
1098 | pin_mask |= (1 << 9); /* RXD0 */ | |
1099 | pin_mask |= (1 << 10); /* RXD1 */ | |
1100 | pin_mask |= (1 << 13); /* RXER */ | |
1101 | pin_mask |= (1 << 15); /* RXDV */ | |
1102 | pin_mask |= (1 << 16); /* MDC */ | |
1103 | pin_mask |= (1 << 17); /* MDIO */ | |
5f97f7f9 HS |
1104 | |
1105 | if (!data->is_rmii) { | |
caf18f19 JM |
1106 | pin_mask |= (1 << 0); /* COL */ |
1107 | pin_mask |= (1 << 1); /* CRS */ | |
1108 | pin_mask |= (1 << 2); /* TXER */ | |
1109 | pin_mask |= (1 << 5); /* TXD2 */ | |
1110 | pin_mask |= (1 << 6); /* TXD3 */ | |
1111 | pin_mask |= (1 << 11); /* RXD2 */ | |
1112 | pin_mask |= (1 << 12); /* RXD3 */ | |
1113 | pin_mask |= (1 << 14); /* RXCK */ | |
198f2935 | 1114 | #ifndef CONFIG_BOARD_MIMC200 |
caf18f19 | 1115 | pin_mask |= (1 << 18); /* SPD */ |
198f2935 | 1116 | #endif |
5f97f7f9 | 1117 | } |
caf18f19 JM |
1118 | |
1119 | select_peripheral(PIOC, pin_mask, PERIPH_A, 0); | |
1120 | ||
5f97f7f9 HS |
1121 | break; |
1122 | ||
cfcb3a89 HS |
1123 | case 1: |
1124 | pdev = &macb1_device; | |
1125 | ||
caf18f19 JM |
1126 | pin_mask = (1 << 13); /* TXD0 */ |
1127 | pin_mask |= (1 << 14); /* TXD1 */ | |
1128 | pin_mask |= (1 << 11); /* TXEN */ | |
1129 | pin_mask |= (1 << 12); /* TXCK */ | |
1130 | pin_mask |= (1 << 10); /* RXD0 */ | |
1131 | pin_mask |= (1 << 6); /* RXD1 */ | |
1132 | pin_mask |= (1 << 5); /* RXER */ | |
1133 | pin_mask |= (1 << 4); /* RXDV */ | |
1134 | pin_mask |= (1 << 3); /* MDC */ | |
1135 | pin_mask |= (1 << 2); /* MDIO */ | |
1136 | ||
198f2935 | 1137 | #ifndef CONFIG_BOARD_MIMC200 |
caf18f19 JM |
1138 | if (!data->is_rmii) |
1139 | pin_mask |= (1 << 15); /* SPD */ | |
198f2935 | 1140 | #endif |
caf18f19 JM |
1141 | |
1142 | select_peripheral(PIOD, pin_mask, PERIPH_B, 0); | |
cfcb3a89 HS |
1143 | |
1144 | if (!data->is_rmii) { | |
caf18f19 JM |
1145 | pin_mask = (1 << 19); /* COL */ |
1146 | pin_mask |= (1 << 23); /* CRS */ | |
1147 | pin_mask |= (1 << 26); /* TXER */ | |
1148 | pin_mask |= (1 << 27); /* TXD2 */ | |
1149 | pin_mask |= (1 << 28); /* TXD3 */ | |
1150 | pin_mask |= (1 << 29); /* RXD2 */ | |
1151 | pin_mask |= (1 << 30); /* RXD3 */ | |
1152 | pin_mask |= (1 << 24); /* RXCK */ | |
1153 | ||
1154 | select_peripheral(PIOC, pin_mask, PERIPH_B, 0); | |
cfcb3a89 HS |
1155 | } |
1156 | break; | |
1157 | ||
5f97f7f9 HS |
1158 | default: |
1159 | return NULL; | |
1160 | } | |
1161 | ||
1162 | memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data)); | |
1163 | platform_device_register(pdev); | |
1164 | ||
1165 | return pdev; | |
1166 | } | |
438ff3f3 | 1167 | #endif |
5f97f7f9 HS |
1168 | |
1169 | /* -------------------------------------------------------------------- | |
1170 | * SPI | |
1171 | * -------------------------------------------------------------------- */ | |
3d60ee1b | 1172 | static struct resource atmel_spi0_resource[] = { |
5f97f7f9 HS |
1173 | PBMEM(0xffe00000), |
1174 | IRQ(3), | |
1175 | }; | |
3d60ee1b HS |
1176 | DEFINE_DEV(atmel_spi, 0); |
1177 | DEV_CLK(spi_clk, atmel_spi0, pba, 0); | |
1178 | ||
1179 | static struct resource atmel_spi1_resource[] = { | |
1180 | PBMEM(0xffe00400), | |
1181 | IRQ(4), | |
1182 | }; | |
1183 | DEFINE_DEV(atmel_spi, 1); | |
1184 | DEV_CLK(spi_clk, atmel_spi1, pba, 1); | |
5f97f7f9 | 1185 | |
9a596a62 | 1186 | static void __init |
41d8ca45 HS |
1187 | at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, |
1188 | unsigned int n, const u8 *pins) | |
5f97f7f9 | 1189 | { |
41d8ca45 HS |
1190 | unsigned int pin, mode; |
1191 | ||
1192 | for (; n; n--, b++) { | |
1193 | b->bus_num = bus_num; | |
1194 | if (b->chip_select >= 4) | |
1195 | continue; | |
1196 | pin = (unsigned)b->controller_data; | |
1197 | if (!pin) { | |
1198 | pin = pins[b->chip_select]; | |
1199 | b->controller_data = (void *)pin; | |
1200 | } | |
1201 | mode = AT32_GPIOF_OUTPUT; | |
1202 | if (!(b->mode & SPI_CS_HIGH)) | |
1203 | mode |= AT32_GPIOF_HIGH; | |
1204 | at32_select_gpio(pin, mode); | |
1205 | } | |
1206 | } | |
1207 | ||
1208 | struct platform_device *__init | |
1209 | at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n) | |
1210 | { | |
1211 | /* | |
1212 | * Manage the chipselects as GPIOs, normally using the same pins | |
1213 | * the SPI controller expects; but boards can use other pins. | |
1214 | */ | |
1215 | static u8 __initdata spi0_pins[] = | |
1216 | { GPIO_PIN_PA(3), GPIO_PIN_PA(4), | |
1217 | GPIO_PIN_PA(5), GPIO_PIN_PA(20), }; | |
1218 | static u8 __initdata spi1_pins[] = | |
1219 | { GPIO_PIN_PB(2), GPIO_PIN_PB(3), | |
1220 | GPIO_PIN_PB(4), GPIO_PIN_PA(27), }; | |
5f97f7f9 | 1221 | struct platform_device *pdev; |
caf18f19 | 1222 | u32 pin_mask; |
5f97f7f9 HS |
1223 | |
1224 | switch (id) { | |
1225 | case 0: | |
3d60ee1b | 1226 | pdev = &atmel_spi0_device; |
caf18f19 JM |
1227 | pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */ |
1228 | ||
9c2baf78 | 1229 | /* pullup MISO so a level is always defined */ |
caf18f19 JM |
1230 | select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP); |
1231 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); | |
1232 | ||
41d8ca45 | 1233 | at32_spi_setup_slaves(0, b, n, spi0_pins); |
3d60ee1b HS |
1234 | break; |
1235 | ||
1236 | case 1: | |
1237 | pdev = &atmel_spi1_device; | |
caf18f19 JM |
1238 | pin_mask = (1 << 1) | (1 << 5); /* MOSI */ |
1239 | ||
9c2baf78 | 1240 | /* pullup MISO so a level is always defined */ |
caf18f19 JM |
1241 | select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP); |
1242 | select_peripheral(PIOB, pin_mask, PERIPH_B, 0); | |
1243 | ||
41d8ca45 | 1244 | at32_spi_setup_slaves(1, b, n, spi1_pins); |
5f97f7f9 HS |
1245 | break; |
1246 | ||
1247 | default: | |
1248 | return NULL; | |
1249 | } | |
1250 | ||
41d8ca45 | 1251 | spi_register_board_info(b, n); |
5f97f7f9 HS |
1252 | platform_device_register(pdev); |
1253 | return pdev; | |
1254 | } | |
1255 | ||
2042c1c4 HS |
1256 | /* -------------------------------------------------------------------- |
1257 | * TWI | |
1258 | * -------------------------------------------------------------------- */ | |
1259 | static struct resource atmel_twi0_resource[] __initdata = { | |
1260 | PBMEM(0xffe00800), | |
1261 | IRQ(5), | |
1262 | }; | |
1263 | static struct clk atmel_twi0_pclk = { | |
1264 | .name = "twi_pclk", | |
1265 | .parent = &pba_clk, | |
1266 | .mode = pba_clk_mode, | |
1267 | .get_rate = pba_clk_get_rate, | |
1268 | .index = 2, | |
1269 | }; | |
1270 | ||
040b28fc BN |
1271 | struct platform_device *__init at32_add_device_twi(unsigned int id, |
1272 | struct i2c_board_info *b, | |
1273 | unsigned int n) | |
2042c1c4 HS |
1274 | { |
1275 | struct platform_device *pdev; | |
caf18f19 | 1276 | u32 pin_mask; |
2042c1c4 HS |
1277 | |
1278 | if (id != 0) | |
1279 | return NULL; | |
1280 | ||
1281 | pdev = platform_device_alloc("atmel_twi", id); | |
1282 | if (!pdev) | |
1283 | return NULL; | |
1284 | ||
1285 | if (platform_device_add_resources(pdev, atmel_twi0_resource, | |
1286 | ARRAY_SIZE(atmel_twi0_resource))) | |
1287 | goto err_add_resources; | |
1288 | ||
caf18f19 JM |
1289 | pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */ |
1290 | ||
1291 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); | |
2042c1c4 HS |
1292 | |
1293 | atmel_twi0_pclk.dev = &pdev->dev; | |
1294 | ||
040b28fc BN |
1295 | if (b) |
1296 | i2c_register_board_info(id, b, n); | |
1297 | ||
2042c1c4 HS |
1298 | platform_device_add(pdev); |
1299 | return pdev; | |
1300 | ||
1301 | err_add_resources: | |
1302 | platform_device_put(pdev); | |
1303 | return NULL; | |
1304 | } | |
1305 | ||
1306 | /* -------------------------------------------------------------------- | |
1307 | * MMC | |
1308 | * -------------------------------------------------------------------- */ | |
1309 | static struct resource atmel_mci0_resource[] __initdata = { | |
1310 | PBMEM(0xfff02400), | |
1311 | IRQ(28), | |
1312 | }; | |
1313 | static struct clk atmel_mci0_pclk = { | |
1314 | .name = "mci_clk", | |
1315 | .parent = &pbb_clk, | |
1316 | .mode = pbb_clk_mode, | |
1317 | .get_rate = pbb_clk_get_rate, | |
1318 | .index = 9, | |
1319 | }; | |
1320 | ||
7d2be074 HS |
1321 | struct platform_device *__init |
1322 | at32_add_device_mci(unsigned int id, struct mci_platform_data *data) | |
2042c1c4 | 1323 | { |
7d2be074 | 1324 | struct platform_device *pdev; |
2635d1ba | 1325 | struct mci_dma_slave *slave; |
caf18f19 JM |
1326 | u32 pioa_mask; |
1327 | u32 piob_mask; | |
2042c1c4 | 1328 | |
6b918657 HS |
1329 | if (id != 0 || !data) |
1330 | return NULL; | |
1331 | ||
1332 | /* Must have at least one usable slot */ | |
1333 | if (!data->slot[0].bus_width && !data->slot[1].bus_width) | |
2042c1c4 HS |
1334 | return NULL; |
1335 | ||
1336 | pdev = platform_device_alloc("atmel_mci", id); | |
1337 | if (!pdev) | |
7d2be074 | 1338 | goto fail; |
2042c1c4 HS |
1339 | |
1340 | if (platform_device_add_resources(pdev, atmel_mci0_resource, | |
1341 | ARRAY_SIZE(atmel_mci0_resource))) | |
7d2be074 HS |
1342 | goto fail; |
1343 | ||
2635d1ba NF |
1344 | slave = kzalloc(sizeof(struct mci_dma_slave), GFP_KERNEL); |
1345 | ||
1346 | slave->sdata.dma_dev = &dw_dmac0_device.dev; | |
1347 | slave->sdata.reg_width = DW_DMA_SLAVE_WIDTH_32BIT; | |
1348 | slave->sdata.cfg_hi = (DWC_CFGH_SRC_PER(0) | |
65e8b083 | 1349 | | DWC_CFGH_DST_PER(1)); |
2635d1ba | 1350 | slave->sdata.cfg_lo &= ~(DWC_CFGL_HS_DST_POL |
65e8b083 HS |
1351 | | DWC_CFGL_HS_SRC_POL); |
1352 | ||
2635d1ba NF |
1353 | data->dma_slave = slave; |
1354 | ||
7d2be074 HS |
1355 | if (platform_device_add_data(pdev, data, |
1356 | sizeof(struct mci_platform_data))) | |
1357 | goto fail; | |
2042c1c4 | 1358 | |
6b918657 | 1359 | /* CLK line is common to both slots */ |
caf18f19 | 1360 | pioa_mask = 1 << 10; |
6b918657 HS |
1361 | |
1362 | switch (data->slot[0].bus_width) { | |
1363 | case 4: | |
caf18f19 JM |
1364 | pioa_mask |= 1 << 13; /* DATA1 */ |
1365 | pioa_mask |= 1 << 14; /* DATA2 */ | |
1366 | pioa_mask |= 1 << 15; /* DATA3 */ | |
6b918657 HS |
1367 | /* fall through */ |
1368 | case 1: | |
caf18f19 JM |
1369 | pioa_mask |= 1 << 11; /* CMD */ |
1370 | pioa_mask |= 1 << 12; /* DATA0 */ | |
6b918657 HS |
1371 | |
1372 | if (gpio_is_valid(data->slot[0].detect_pin)) | |
1373 | at32_select_gpio(data->slot[0].detect_pin, 0); | |
1374 | if (gpio_is_valid(data->slot[0].wp_pin)) | |
1375 | at32_select_gpio(data->slot[0].wp_pin, 0); | |
1376 | break; | |
1377 | case 0: | |
1378 | /* Slot is unused */ | |
1379 | break; | |
1380 | default: | |
1381 | goto fail; | |
1382 | } | |
1383 | ||
caf18f19 JM |
1384 | select_peripheral(PIOA, pioa_mask, PERIPH_A, 0); |
1385 | piob_mask = 0; | |
1386 | ||
6b918657 HS |
1387 | switch (data->slot[1].bus_width) { |
1388 | case 4: | |
caf18f19 JM |
1389 | piob_mask |= 1 << 8; /* DATA1 */ |
1390 | piob_mask |= 1 << 9; /* DATA2 */ | |
1391 | piob_mask |= 1 << 10; /* DATA3 */ | |
6b918657 HS |
1392 | /* fall through */ |
1393 | case 1: | |
caf18f19 JM |
1394 | piob_mask |= 1 << 6; /* CMD */ |
1395 | piob_mask |= 1 << 7; /* DATA0 */ | |
1396 | select_peripheral(PIOB, piob_mask, PERIPH_B, 0); | |
6b918657 HS |
1397 | |
1398 | if (gpio_is_valid(data->slot[1].detect_pin)) | |
1399 | at32_select_gpio(data->slot[1].detect_pin, 0); | |
1400 | if (gpio_is_valid(data->slot[1].wp_pin)) | |
1401 | at32_select_gpio(data->slot[1].wp_pin, 0); | |
1402 | break; | |
1403 | case 0: | |
1404 | /* Slot is unused */ | |
1405 | break; | |
1406 | default: | |
1407 | if (!data->slot[0].bus_width) | |
1408 | goto fail; | |
1409 | ||
1410 | data->slot[1].bus_width = 0; | |
1411 | break; | |
1412 | } | |
7d2be074 | 1413 | |
2042c1c4 HS |
1414 | atmel_mci0_pclk.dev = &pdev->dev; |
1415 | ||
1416 | platform_device_add(pdev); | |
1417 | return pdev; | |
1418 | ||
7d2be074 | 1419 | fail: |
2635d1ba NF |
1420 | data->dma_slave = NULL; |
1421 | kfree(slave); | |
2042c1c4 HS |
1422 | platform_device_put(pdev); |
1423 | return NULL; | |
1424 | } | |
1425 | ||
5f97f7f9 HS |
1426 | /* -------------------------------------------------------------------- |
1427 | * LCDC | |
1428 | * -------------------------------------------------------------------- */ | |
438ff3f3 | 1429 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af HS |
1430 | static struct atmel_lcdfb_info atmel_lcdfb0_data; |
1431 | static struct resource atmel_lcdfb0_resource[] = { | |
5f97f7f9 HS |
1432 | { |
1433 | .start = 0xff000000, | |
1434 | .end = 0xff000fff, | |
1435 | .flags = IORESOURCE_MEM, | |
1436 | }, | |
1437 | IRQ(1), | |
d0a2b7af HS |
1438 | { |
1439 | /* Placeholder for pre-allocated fb memory */ | |
1440 | .start = 0x00000000, | |
1441 | .end = 0x00000000, | |
1442 | .flags = 0, | |
1443 | }, | |
5f97f7f9 | 1444 | }; |
d0a2b7af HS |
1445 | DEFINE_DEV_DATA(atmel_lcdfb, 0); |
1446 | DEV_CLK(hck1, atmel_lcdfb0, hsb, 7); | |
1447 | static struct clk atmel_lcdfb0_pixclk = { | |
1448 | .name = "lcdc_clk", | |
1449 | .dev = &atmel_lcdfb0_device.dev, | |
5f97f7f9 HS |
1450 | .mode = genclk_mode, |
1451 | .get_rate = genclk_get_rate, | |
1452 | .set_rate = genclk_set_rate, | |
1453 | .set_parent = genclk_set_parent, | |
1454 | .index = 7, | |
1455 | }; | |
1456 | ||
1457 | struct platform_device *__init | |
d0a2b7af | 1458 | at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, |
47882cf6 | 1459 | unsigned long fbmem_start, unsigned long fbmem_len, |
70664124 | 1460 | u64 pin_mask) |
5f97f7f9 HS |
1461 | { |
1462 | struct platform_device *pdev; | |
d0a2b7af HS |
1463 | struct atmel_lcdfb_info *info; |
1464 | struct fb_monspecs *monspecs; | |
1465 | struct fb_videomode *modedb; | |
1466 | unsigned int modedb_size; | |
caf18f19 | 1467 | u32 portc_mask, portd_mask, porte_mask; |
d0a2b7af HS |
1468 | |
1469 | /* | |
1470 | * Do a deep copy of the fb data, monspecs and modedb. Make | |
1471 | * sure all allocations are done before setting up the | |
1472 | * portmux. | |
1473 | */ | |
1474 | monspecs = kmemdup(data->default_monspecs, | |
1475 | sizeof(struct fb_monspecs), GFP_KERNEL); | |
1476 | if (!monspecs) | |
1477 | return NULL; | |
1478 | ||
1479 | modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len; | |
1480 | modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL); | |
1481 | if (!modedb) | |
1482 | goto err_dup_modedb; | |
1483 | monspecs->modedb = modedb; | |
5f97f7f9 HS |
1484 | |
1485 | switch (id) { | |
1486 | case 0: | |
d0a2b7af | 1487 | pdev = &atmel_lcdfb0_device; |
47882cf6 | 1488 | |
70664124 JM |
1489 | if (pin_mask == 0ULL) |
1490 | /* Default to "full" lcdc control signals and 24bit */ | |
1491 | pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL; | |
1492 | ||
1493 | /* LCDC on port C */ | |
60900656 | 1494 | portc_mask = pin_mask & 0xfff80000; |
caf18f19 | 1495 | select_peripheral(PIOC, portc_mask, PERIPH_A, 0); |
70664124 JM |
1496 | |
1497 | /* LCDC on port D */ | |
caf18f19 JM |
1498 | portd_mask = pin_mask & 0x0003ffff; |
1499 | select_peripheral(PIOD, portd_mask, PERIPH_A, 0); | |
70664124 JM |
1500 | |
1501 | /* LCDC on port E */ | |
caf18f19 JM |
1502 | porte_mask = (pin_mask >> 32) & 0x0007ffff; |
1503 | select_peripheral(PIOE, porte_mask, PERIPH_B, 0); | |
5f97f7f9 | 1504 | |
d0a2b7af HS |
1505 | clk_set_parent(&atmel_lcdfb0_pixclk, &pll0); |
1506 | clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0)); | |
5f97f7f9 HS |
1507 | break; |
1508 | ||
1509 | default: | |
d0a2b7af | 1510 | goto err_invalid_id; |
5f97f7f9 HS |
1511 | } |
1512 | ||
d0a2b7af HS |
1513 | if (fbmem_len) { |
1514 | pdev->resource[2].start = fbmem_start; | |
1515 | pdev->resource[2].end = fbmem_start + fbmem_len - 1; | |
1516 | pdev->resource[2].flags = IORESOURCE_MEM; | |
1517 | } | |
1518 | ||
1519 | info = pdev->dev.platform_data; | |
1520 | memcpy(info, data, sizeof(struct atmel_lcdfb_info)); | |
1521 | info->default_monspecs = monspecs; | |
5f97f7f9 HS |
1522 | |
1523 | platform_device_register(pdev); | |
1524 | return pdev; | |
d0a2b7af HS |
1525 | |
1526 | err_invalid_id: | |
1527 | kfree(modedb); | |
1528 | err_dup_modedb: | |
1529 | kfree(monspecs); | |
1530 | return NULL; | |
5f97f7f9 | 1531 | } |
438ff3f3 | 1532 | #endif |
5f97f7f9 | 1533 | |
9a1e8eb1 DB |
1534 | /* -------------------------------------------------------------------- |
1535 | * PWM | |
1536 | * -------------------------------------------------------------------- */ | |
1537 | static struct resource atmel_pwm0_resource[] __initdata = { | |
1538 | PBMEM(0xfff01400), | |
1539 | IRQ(24), | |
1540 | }; | |
1541 | static struct clk atmel_pwm0_mck = { | |
8405996f | 1542 | .name = "pwm_clk", |
9a1e8eb1 DB |
1543 | .parent = &pbb_clk, |
1544 | .mode = pbb_clk_mode, | |
1545 | .get_rate = pbb_clk_get_rate, | |
1546 | .index = 5, | |
1547 | }; | |
1548 | ||
1549 | struct platform_device *__init at32_add_device_pwm(u32 mask) | |
1550 | { | |
1551 | struct platform_device *pdev; | |
caf18f19 | 1552 | u32 pin_mask; |
9a1e8eb1 DB |
1553 | |
1554 | if (!mask) | |
1555 | return NULL; | |
1556 | ||
1557 | pdev = platform_device_alloc("atmel_pwm", 0); | |
1558 | if (!pdev) | |
1559 | return NULL; | |
1560 | ||
1561 | if (platform_device_add_resources(pdev, atmel_pwm0_resource, | |
1562 | ARRAY_SIZE(atmel_pwm0_resource))) | |
1563 | goto out_free_pdev; | |
1564 | ||
1565 | if (platform_device_add_data(pdev, &mask, sizeof(mask))) | |
1566 | goto out_free_pdev; | |
1567 | ||
caf18f19 | 1568 | pin_mask = 0; |
9a1e8eb1 | 1569 | if (mask & (1 << 0)) |
caf18f19 | 1570 | pin_mask |= (1 << 28); |
9a1e8eb1 | 1571 | if (mask & (1 << 1)) |
caf18f19 JM |
1572 | pin_mask |= (1 << 29); |
1573 | if (pin_mask > 0) | |
1574 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); | |
1575 | ||
1576 | pin_mask = 0; | |
9a1e8eb1 | 1577 | if (mask & (1 << 2)) |
caf18f19 | 1578 | pin_mask |= (1 << 21); |
9a1e8eb1 | 1579 | if (mask & (1 << 3)) |
caf18f19 JM |
1580 | pin_mask |= (1 << 22); |
1581 | if (pin_mask > 0) | |
1582 | select_peripheral(PIOA, pin_mask, PERIPH_B, 0); | |
9a1e8eb1 DB |
1583 | |
1584 | atmel_pwm0_mck.dev = &pdev->dev; | |
1585 | ||
1586 | platform_device_add(pdev); | |
1587 | ||
1588 | return pdev; | |
1589 | ||
1590 | out_free_pdev: | |
1591 | platform_device_put(pdev); | |
1592 | return NULL; | |
1593 | } | |
1594 | ||
9cf6cf58 HCE |
1595 | /* -------------------------------------------------------------------- |
1596 | * SSC | |
1597 | * -------------------------------------------------------------------- */ | |
1598 | static struct resource ssc0_resource[] = { | |
1599 | PBMEM(0xffe01c00), | |
1600 | IRQ(10), | |
1601 | }; | |
1602 | DEFINE_DEV(ssc, 0); | |
1603 | DEV_CLK(pclk, ssc0, pba, 7); | |
1604 | ||
1605 | static struct resource ssc1_resource[] = { | |
1606 | PBMEM(0xffe02000), | |
1607 | IRQ(11), | |
1608 | }; | |
1609 | DEFINE_DEV(ssc, 1); | |
1610 | DEV_CLK(pclk, ssc1, pba, 8); | |
1611 | ||
1612 | static struct resource ssc2_resource[] = { | |
1613 | PBMEM(0xffe02400), | |
1614 | IRQ(12), | |
1615 | }; | |
1616 | DEFINE_DEV(ssc, 2); | |
1617 | DEV_CLK(pclk, ssc2, pba, 9); | |
1618 | ||
1619 | struct platform_device *__init | |
1620 | at32_add_device_ssc(unsigned int id, unsigned int flags) | |
1621 | { | |
1622 | struct platform_device *pdev; | |
caf18f19 | 1623 | u32 pin_mask = 0; |
9cf6cf58 HCE |
1624 | |
1625 | switch (id) { | |
1626 | case 0: | |
1627 | pdev = &ssc0_device; | |
1628 | if (flags & ATMEL_SSC_RF) | |
caf18f19 | 1629 | pin_mask |= (1 << 21); /* RF */ |
9cf6cf58 | 1630 | if (flags & ATMEL_SSC_RK) |
caf18f19 | 1631 | pin_mask |= (1 << 22); /* RK */ |
9cf6cf58 | 1632 | if (flags & ATMEL_SSC_TK) |
caf18f19 | 1633 | pin_mask |= (1 << 23); /* TK */ |
9cf6cf58 | 1634 | if (flags & ATMEL_SSC_TF) |
caf18f19 | 1635 | pin_mask |= (1 << 24); /* TF */ |
9cf6cf58 | 1636 | if (flags & ATMEL_SSC_TD) |
caf18f19 | 1637 | pin_mask |= (1 << 25); /* TD */ |
9cf6cf58 | 1638 | if (flags & ATMEL_SSC_RD) |
caf18f19 JM |
1639 | pin_mask |= (1 << 26); /* RD */ |
1640 | ||
1641 | if (pin_mask > 0) | |
1642 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); | |
1643 | ||
9cf6cf58 HCE |
1644 | break; |
1645 | case 1: | |
1646 | pdev = &ssc1_device; | |
1647 | if (flags & ATMEL_SSC_RF) | |
caf18f19 | 1648 | pin_mask |= (1 << 0); /* RF */ |
9cf6cf58 | 1649 | if (flags & ATMEL_SSC_RK) |
caf18f19 | 1650 | pin_mask |= (1 << 1); /* RK */ |
9cf6cf58 | 1651 | if (flags & ATMEL_SSC_TK) |
caf18f19 | 1652 | pin_mask |= (1 << 2); /* TK */ |
9cf6cf58 | 1653 | if (flags & ATMEL_SSC_TF) |
caf18f19 | 1654 | pin_mask |= (1 << 3); /* TF */ |
9cf6cf58 | 1655 | if (flags & ATMEL_SSC_TD) |
caf18f19 | 1656 | pin_mask |= (1 << 4); /* TD */ |
9cf6cf58 | 1657 | if (flags & ATMEL_SSC_RD) |
caf18f19 JM |
1658 | pin_mask |= (1 << 5); /* RD */ |
1659 | ||
1660 | if (pin_mask > 0) | |
1661 | select_peripheral(PIOA, pin_mask, PERIPH_B, 0); | |
1662 | ||
9cf6cf58 HCE |
1663 | break; |
1664 | case 2: | |
1665 | pdev = &ssc2_device; | |
1666 | if (flags & ATMEL_SSC_TD) | |
caf18f19 | 1667 | pin_mask |= (1 << 13); /* TD */ |
9cf6cf58 | 1668 | if (flags & ATMEL_SSC_RD) |
caf18f19 | 1669 | pin_mask |= (1 << 14); /* RD */ |
9cf6cf58 | 1670 | if (flags & ATMEL_SSC_TK) |
caf18f19 | 1671 | pin_mask |= (1 << 15); /* TK */ |
9cf6cf58 | 1672 | if (flags & ATMEL_SSC_TF) |
caf18f19 | 1673 | pin_mask |= (1 << 16); /* TF */ |
9cf6cf58 | 1674 | if (flags & ATMEL_SSC_RF) |
caf18f19 | 1675 | pin_mask |= (1 << 17); /* RF */ |
9cf6cf58 | 1676 | if (flags & ATMEL_SSC_RK) |
caf18f19 JM |
1677 | pin_mask |= (1 << 18); /* RK */ |
1678 | ||
1679 | if (pin_mask > 0) | |
1680 | select_peripheral(PIOB, pin_mask, PERIPH_A, 0); | |
1681 | ||
9cf6cf58 HCE |
1682 | break; |
1683 | default: | |
1684 | return NULL; | |
1685 | } | |
1686 | ||
1687 | platform_device_register(pdev); | |
1688 | return pdev; | |
1689 | } | |
1690 | ||
6fcf0615 HS |
1691 | /* -------------------------------------------------------------------- |
1692 | * USB Device Controller | |
1693 | * -------------------------------------------------------------------- */ | |
1694 | static struct resource usba0_resource[] __initdata = { | |
1695 | { | |
1696 | .start = 0xff300000, | |
1697 | .end = 0xff3fffff, | |
1698 | .flags = IORESOURCE_MEM, | |
1699 | }, { | |
1700 | .start = 0xfff03000, | |
1701 | .end = 0xfff033ff, | |
1702 | .flags = IORESOURCE_MEM, | |
1703 | }, | |
1704 | IRQ(31), | |
1705 | }; | |
1706 | static struct clk usba0_pclk = { | |
1707 | .name = "pclk", | |
1708 | .parent = &pbb_clk, | |
1709 | .mode = pbb_clk_mode, | |
1710 | .get_rate = pbb_clk_get_rate, | |
1711 | .index = 12, | |
1712 | }; | |
1713 | static struct clk usba0_hclk = { | |
1714 | .name = "hclk", | |
1715 | .parent = &hsb_clk, | |
1716 | .mode = hsb_clk_mode, | |
1717 | .get_rate = hsb_clk_get_rate, | |
1718 | .index = 6, | |
1719 | }; | |
1720 | ||
8d855317 SP |
1721 | #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ |
1722 | [idx] = { \ | |
1723 | .name = nam, \ | |
1724 | .index = idx, \ | |
1725 | .fifo_size = maxpkt, \ | |
1726 | .nr_banks = maxbk, \ | |
1727 | .can_dma = dma, \ | |
1728 | .can_isoc = isoc, \ | |
1729 | } | |
1730 | ||
1731 | static struct usba_ep_data at32_usba_ep[] __initdata = { | |
1732 | EP("ep0", 0, 64, 1, 0, 0), | |
1733 | EP("ep1", 1, 512, 2, 1, 1), | |
1734 | EP("ep2", 2, 512, 2, 1, 1), | |
1735 | EP("ep3-int", 3, 64, 3, 1, 0), | |
1736 | EP("ep4-int", 4, 64, 3, 1, 0), | |
1737 | EP("ep5", 5, 1024, 3, 1, 1), | |
1738 | EP("ep6", 6, 1024, 3, 1, 1), | |
1739 | }; | |
1740 | ||
1741 | #undef EP | |
1742 | ||
6fcf0615 HS |
1743 | struct platform_device *__init |
1744 | at32_add_device_usba(unsigned int id, struct usba_platform_data *data) | |
1745 | { | |
8d855317 SP |
1746 | /* |
1747 | * pdata doesn't have room for any endpoints, so we need to | |
1748 | * append room for the ones we need right after it. | |
1749 | */ | |
1750 | struct { | |
1751 | struct usba_platform_data pdata; | |
1752 | struct usba_ep_data ep[7]; | |
1753 | } usba_data; | |
6fcf0615 HS |
1754 | struct platform_device *pdev; |
1755 | ||
1756 | if (id != 0) | |
1757 | return NULL; | |
1758 | ||
1759 | pdev = platform_device_alloc("atmel_usba_udc", 0); | |
1760 | if (!pdev) | |
1761 | return NULL; | |
1762 | ||
1763 | if (platform_device_add_resources(pdev, usba0_resource, | |
1764 | ARRAY_SIZE(usba0_resource))) | |
1765 | goto out_free_pdev; | |
1766 | ||
8d855317 SP |
1767 | if (data) |
1768 | usba_data.pdata.vbus_pin = data->vbus_pin; | |
1769 | else | |
1770 | usba_data.pdata.vbus_pin = -EINVAL; | |
6fcf0615 | 1771 | |
8d855317 SP |
1772 | data = &usba_data.pdata; |
1773 | data->num_ep = ARRAY_SIZE(at32_usba_ep); | |
1774 | memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep)); | |
1775 | ||
1776 | if (platform_device_add_data(pdev, data, sizeof(usba_data))) | |
1777 | goto out_free_pdev; | |
1778 | ||
9477ab2b | 1779 | if (gpio_is_valid(data->vbus_pin)) |
8d855317 | 1780 | at32_select_gpio(data->vbus_pin, 0); |
6fcf0615 HS |
1781 | |
1782 | usba0_pclk.dev = &pdev->dev; | |
1783 | usba0_hclk.dev = &pdev->dev; | |
1784 | ||
1785 | platform_device_add(pdev); | |
1786 | ||
1787 | return pdev; | |
1788 | ||
1789 | out_free_pdev: | |
1790 | platform_device_put(pdev); | |
1791 | return NULL; | |
1792 | } | |
1793 | ||
48021bd9 | 1794 | /* -------------------------------------------------------------------- |
eaf5f925 | 1795 | * IDE / CompactFlash |
48021bd9 | 1796 | * -------------------------------------------------------------------- */ |
438ff3f3 | 1797 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001) |
eaf5f925 | 1798 | static struct resource at32_smc_cs4_resource[] __initdata = { |
48021bd9 KNG |
1799 | { |
1800 | .start = 0x04000000, | |
1801 | .end = 0x07ffffff, | |
1802 | .flags = IORESOURCE_MEM, | |
1803 | }, | |
1804 | IRQ(~0UL), /* Magic IRQ will be overridden */ | |
1805 | }; | |
eaf5f925 HS |
1806 | static struct resource at32_smc_cs5_resource[] __initdata = { |
1807 | { | |
1808 | .start = 0x20000000, | |
1809 | .end = 0x23ffffff, | |
1810 | .flags = IORESOURCE_MEM, | |
1811 | }, | |
1812 | IRQ(~0UL), /* Magic IRQ will be overridden */ | |
1813 | }; | |
48021bd9 | 1814 | |
eaf5f925 HS |
1815 | static int __init at32_init_ide_or_cf(struct platform_device *pdev, |
1816 | unsigned int cs, unsigned int extint) | |
48021bd9 | 1817 | { |
eaf5f925 | 1818 | static unsigned int extint_pin_map[4] __initdata = { |
caf18f19 JM |
1819 | (1 << 25), |
1820 | (1 << 26), | |
1821 | (1 << 27), | |
1822 | (1 << 28), | |
eaf5f925 HS |
1823 | }; |
1824 | static bool common_pins_initialized __initdata = false; | |
48021bd9 | 1825 | unsigned int extint_pin; |
eaf5f925 | 1826 | int ret; |
caf18f19 | 1827 | u32 pin_mask; |
48021bd9 | 1828 | |
eaf5f925 HS |
1829 | if (extint >= ARRAY_SIZE(extint_pin_map)) |
1830 | return -EINVAL; | |
1831 | extint_pin = extint_pin_map[extint]; | |
1832 | ||
1833 | switch (cs) { | |
1834 | case 4: | |
1835 | ret = platform_device_add_resources(pdev, | |
1836 | at32_smc_cs4_resource, | |
1837 | ARRAY_SIZE(at32_smc_cs4_resource)); | |
1838 | if (ret) | |
1839 | return ret; | |
1840 | ||
caf18f19 JM |
1841 | /* NCS4 -> OE_N */ |
1842 | select_peripheral(PIOE, (1 << 21), PERIPH_A, 0); | |
b47eb409 | 1843 | hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE); |
48021bd9 | 1844 | break; |
eaf5f925 HS |
1845 | case 5: |
1846 | ret = platform_device_add_resources(pdev, | |
1847 | at32_smc_cs5_resource, | |
1848 | ARRAY_SIZE(at32_smc_cs5_resource)); | |
1849 | if (ret) | |
1850 | return ret; | |
1851 | ||
caf18f19 JM |
1852 | /* NCS5 -> OE_N */ |
1853 | select_peripheral(PIOE, (1 << 22), PERIPH_A, 0); | |
b47eb409 | 1854 | hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE); |
48021bd9 KNG |
1855 | break; |
1856 | default: | |
eaf5f925 | 1857 | return -EINVAL; |
48021bd9 KNG |
1858 | } |
1859 | ||
eaf5f925 | 1860 | if (!common_pins_initialized) { |
caf18f19 JM |
1861 | pin_mask = (1 << 19); /* CFCE1 -> CS0_N */ |
1862 | pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */ | |
1863 | pin_mask |= (1 << 23); /* CFRNW -> DIR */ | |
1864 | pin_mask |= (1 << 24); /* NWAIT <- IORDY */ | |
1865 | ||
1866 | select_peripheral(PIOE, pin_mask, PERIPH_A, 0); | |
1867 | ||
eaf5f925 | 1868 | common_pins_initialized = true; |
48021bd9 KNG |
1869 | } |
1870 | ||
caf18f19 | 1871 | select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH); |
48021bd9 KNG |
1872 | |
1873 | pdev->resource[1].start = EIM_IRQ_BASE + extint; | |
1874 | pdev->resource[1].end = pdev->resource[1].start; | |
1875 | ||
eaf5f925 HS |
1876 | return 0; |
1877 | } | |
48021bd9 | 1878 | |
eaf5f925 HS |
1879 | struct platform_device *__init |
1880 | at32_add_device_ide(unsigned int id, unsigned int extint, | |
1881 | struct ide_platform_data *data) | |
1882 | { | |
1883 | struct platform_device *pdev; | |
1884 | ||
1885 | pdev = platform_device_alloc("at32_ide", id); | |
1886 | if (!pdev) | |
1887 | goto fail; | |
1888 | ||
1889 | if (platform_device_add_data(pdev, data, | |
1890 | sizeof(struct ide_platform_data))) | |
1891 | goto fail; | |
1892 | ||
1893 | if (at32_init_ide_or_cf(pdev, data->cs, extint)) | |
1894 | goto fail; | |
1895 | ||
1896 | platform_device_add(pdev); | |
1897 | return pdev; | |
1898 | ||
1899 | fail: | |
1900 | platform_device_put(pdev); | |
1901 | return NULL; | |
1902 | } | |
1903 | ||
1904 | struct platform_device *__init | |
1905 | at32_add_device_cf(unsigned int id, unsigned int extint, | |
1906 | struct cf_platform_data *data) | |
1907 | { | |
1908 | struct platform_device *pdev; | |
1909 | ||
1910 | pdev = platform_device_alloc("at32_cf", id); | |
1911 | if (!pdev) | |
1912 | goto fail; | |
48021bd9 | 1913 | |
eaf5f925 HS |
1914 | if (platform_device_add_data(pdev, data, |
1915 | sizeof(struct cf_platform_data))) | |
1916 | goto fail; | |
1917 | ||
1918 | if (at32_init_ide_or_cf(pdev, data->cs, extint)) | |
1919 | goto fail; | |
1920 | ||
3c26e170 | 1921 | if (gpio_is_valid(data->detect_pin)) |
eaf5f925 | 1922 | at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH); |
3c26e170 | 1923 | if (gpio_is_valid(data->reset_pin)) |
eaf5f925 | 1924 | at32_select_gpio(data->reset_pin, 0); |
3c26e170 | 1925 | if (gpio_is_valid(data->vcc_pin)) |
eaf5f925 HS |
1926 | at32_select_gpio(data->vcc_pin, 0); |
1927 | /* READY is used as extint, so we can't select it as gpio */ | |
1928 | ||
1929 | platform_device_add(pdev); | |
48021bd9 | 1930 | return pdev; |
eaf5f925 HS |
1931 | |
1932 | fail: | |
1933 | platform_device_put(pdev); | |
1934 | return NULL; | |
48021bd9 | 1935 | } |
438ff3f3 | 1936 | #endif |
48021bd9 | 1937 | |
62090a08 HS |
1938 | /* -------------------------------------------------------------------- |
1939 | * NAND Flash / SmartMedia | |
1940 | * -------------------------------------------------------------------- */ | |
1941 | static struct resource smc_cs3_resource[] __initdata = { | |
1942 | { | |
1943 | .start = 0x0c000000, | |
1944 | .end = 0x0fffffff, | |
1945 | .flags = IORESOURCE_MEM, | |
1946 | }, { | |
1947 | .start = 0xfff03c00, | |
1948 | .end = 0xfff03fff, | |
1949 | .flags = IORESOURCE_MEM, | |
1950 | }, | |
1951 | }; | |
1952 | ||
1953 | struct platform_device *__init | |
1954 | at32_add_device_nand(unsigned int id, struct atmel_nand_data *data) | |
1955 | { | |
1956 | struct platform_device *pdev; | |
1957 | ||
1958 | if (id != 0 || !data) | |
1959 | return NULL; | |
1960 | ||
1961 | pdev = platform_device_alloc("atmel_nand", id); | |
1962 | if (!pdev) | |
1963 | goto fail; | |
1964 | ||
1965 | if (platform_device_add_resources(pdev, smc_cs3_resource, | |
1966 | ARRAY_SIZE(smc_cs3_resource))) | |
1967 | goto fail; | |
1968 | ||
1969 | if (platform_device_add_data(pdev, data, | |
1970 | sizeof(struct atmel_nand_data))) | |
1971 | goto fail; | |
1972 | ||
b47eb409 | 1973 | hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE); |
62090a08 HS |
1974 | if (data->enable_pin) |
1975 | at32_select_gpio(data->enable_pin, | |
1976 | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH); | |
1977 | if (data->rdy_pin) | |
1978 | at32_select_gpio(data->rdy_pin, 0); | |
1979 | if (data->det_pin) | |
1980 | at32_select_gpio(data->det_pin, 0); | |
1981 | ||
1982 | platform_device_add(pdev); | |
1983 | return pdev; | |
1984 | ||
1985 | fail: | |
1986 | platform_device_put(pdev); | |
1987 | return NULL; | |
1988 | } | |
1989 | ||
2042c1c4 HS |
1990 | /* -------------------------------------------------------------------- |
1991 | * AC97C | |
1992 | * -------------------------------------------------------------------- */ | |
1993 | static struct resource atmel_ac97c0_resource[] __initdata = { | |
1994 | PBMEM(0xfff02800), | |
1995 | IRQ(29), | |
1996 | }; | |
1997 | static struct clk atmel_ac97c0_pclk = { | |
1998 | .name = "pclk", | |
1999 | .parent = &pbb_clk, | |
2000 | .mode = pbb_clk_mode, | |
2001 | .get_rate = pbb_clk_get_rate, | |
2002 | .index = 10, | |
2003 | }; | |
2004 | ||
218df4a2 | 2005 | struct platform_device *__init |
2f47c8c5 HCE |
2006 | at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data, |
2007 | unsigned int flags) | |
2042c1c4 | 2008 | { |
2f47c8c5 HCE |
2009 | struct platform_device *pdev; |
2010 | struct dw_dma_slave *rx_dws; | |
2011 | struct dw_dma_slave *tx_dws; | |
2012 | struct ac97c_platform_data _data; | |
2013 | u32 pin_mask; | |
2042c1c4 HS |
2014 | |
2015 | if (id != 0) | |
2016 | return NULL; | |
2017 | ||
2018 | pdev = platform_device_alloc("atmel_ac97c", id); | |
2019 | if (!pdev) | |
2020 | return NULL; | |
2021 | ||
2022 | if (platform_device_add_resources(pdev, atmel_ac97c0_resource, | |
2023 | ARRAY_SIZE(atmel_ac97c0_resource))) | |
2f47c8c5 | 2024 | goto out_free_resources; |
218df4a2 HCE |
2025 | |
2026 | if (!data) { | |
2027 | data = &_data; | |
2028 | memset(data, 0, sizeof(struct ac97c_platform_data)); | |
2f47c8c5 HCE |
2029 | data->reset_pin = -ENODEV; |
2030 | } | |
2031 | ||
2032 | rx_dws = &data->rx_dws; | |
2033 | tx_dws = &data->tx_dws; | |
2034 | ||
2035 | /* Check if DMA slave interface for capture should be configured. */ | |
2036 | if (flags & AC97C_CAPTURE) { | |
2037 | rx_dws->dma_dev = &dw_dmac0_device.dev; | |
2038 | rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT; | |
2039 | rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3); | |
2040 | rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); | |
218df4a2 HCE |
2041 | } |
2042 | ||
2f47c8c5 HCE |
2043 | /* Check if DMA slave interface for playback should be configured. */ |
2044 | if (flags & AC97C_PLAYBACK) { | |
2045 | tx_dws->dma_dev = &dw_dmac0_device.dev; | |
2046 | tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT; | |
2047 | tx_dws->cfg_hi = DWC_CFGH_DST_PER(4); | |
2048 | tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); | |
2049 | } | |
2042c1c4 | 2050 | |
218df4a2 HCE |
2051 | if (platform_device_add_data(pdev, data, |
2052 | sizeof(struct ac97c_platform_data))) | |
2f47c8c5 | 2053 | goto out_free_resources; |
218df4a2 | 2054 | |
2f47c8c5 HCE |
2055 | /* SDO | SYNC | SCLK | SDI */ |
2056 | pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23); | |
caf18f19 JM |
2057 | |
2058 | select_peripheral(PIOB, pin_mask, PERIPH_B, 0); | |
218df4a2 | 2059 | |
2f47c8c5 HCE |
2060 | if (gpio_is_valid(data->reset_pin)) |
2061 | at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT | |
2062 | | AT32_GPIOF_HIGH); | |
2042c1c4 HS |
2063 | |
2064 | atmel_ac97c0_pclk.dev = &pdev->dev; | |
2065 | ||
2066 | platform_device_add(pdev); | |
2067 | return pdev; | |
2068 | ||
2f47c8c5 | 2069 | out_free_resources: |
2042c1c4 HS |
2070 | platform_device_put(pdev); |
2071 | return NULL; | |
2072 | } | |
2073 | ||
2074 | /* -------------------------------------------------------------------- | |
2075 | * ABDAC | |
2076 | * -------------------------------------------------------------------- */ | |
2077 | static struct resource abdac0_resource[] __initdata = { | |
2078 | PBMEM(0xfff02000), | |
2079 | IRQ(27), | |
2080 | }; | |
2081 | static struct clk abdac0_pclk = { | |
2082 | .name = "pclk", | |
2083 | .parent = &pbb_clk, | |
2084 | .mode = pbb_clk_mode, | |
2085 | .get_rate = pbb_clk_get_rate, | |
2086 | .index = 8, | |
2087 | }; | |
2088 | static struct clk abdac0_sample_clk = { | |
2089 | .name = "sample_clk", | |
2090 | .mode = genclk_mode, | |
2091 | .get_rate = genclk_get_rate, | |
2092 | .set_rate = genclk_set_rate, | |
2093 | .set_parent = genclk_set_parent, | |
2094 | .index = 6, | |
2095 | }; | |
2096 | ||
6b0c9351 HCE |
2097 | struct platform_device *__init |
2098 | at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data) | |
2042c1c4 | 2099 | { |
6b0c9351 HCE |
2100 | struct platform_device *pdev; |
2101 | struct dw_dma_slave *dws; | |
2102 | u32 pin_mask; | |
2042c1c4 | 2103 | |
6b0c9351 | 2104 | if (id != 0 || !data) |
2042c1c4 HS |
2105 | return NULL; |
2106 | ||
6b0c9351 | 2107 | pdev = platform_device_alloc("atmel_abdac", id); |
2042c1c4 HS |
2108 | if (!pdev) |
2109 | return NULL; | |
2110 | ||
2111 | if (platform_device_add_resources(pdev, abdac0_resource, | |
2112 | ARRAY_SIZE(abdac0_resource))) | |
6b0c9351 HCE |
2113 | goto out_free_resources; |
2114 | ||
2115 | dws = &data->dws; | |
2116 | ||
2117 | dws->dma_dev = &dw_dmac0_device.dev; | |
2118 | dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT; | |
2119 | dws->cfg_hi = DWC_CFGH_DST_PER(2); | |
2120 | dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); | |
2121 | ||
2122 | if (platform_device_add_data(pdev, data, | |
2123 | sizeof(struct atmel_abdac_pdata))) | |
2124 | goto out_free_resources; | |
2042c1c4 | 2125 | |
caf18f19 JM |
2126 | pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */ |
2127 | pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */ | |
2128 | ||
2129 | select_peripheral(PIOB, pin_mask, PERIPH_A, 0); | |
2042c1c4 HS |
2130 | |
2131 | abdac0_pclk.dev = &pdev->dev; | |
2132 | abdac0_sample_clk.dev = &pdev->dev; | |
2133 | ||
2134 | platform_device_add(pdev); | |
2135 | return pdev; | |
2136 | ||
6b0c9351 | 2137 | out_free_resources: |
2042c1c4 HS |
2138 | platform_device_put(pdev); |
2139 | return NULL; | |
2140 | } | |
2141 | ||
7a5fe238 HS |
2142 | /* -------------------------------------------------------------------- |
2143 | * GCLK | |
2144 | * -------------------------------------------------------------------- */ | |
2145 | static struct clk gclk0 = { | |
2146 | .name = "gclk0", | |
2147 | .mode = genclk_mode, | |
2148 | .get_rate = genclk_get_rate, | |
2149 | .set_rate = genclk_set_rate, | |
2150 | .set_parent = genclk_set_parent, | |
2151 | .index = 0, | |
2152 | }; | |
2153 | static struct clk gclk1 = { | |
2154 | .name = "gclk1", | |
2155 | .mode = genclk_mode, | |
2156 | .get_rate = genclk_get_rate, | |
2157 | .set_rate = genclk_set_rate, | |
2158 | .set_parent = genclk_set_parent, | |
2159 | .index = 1, | |
2160 | }; | |
2161 | static struct clk gclk2 = { | |
2162 | .name = "gclk2", | |
2163 | .mode = genclk_mode, | |
2164 | .get_rate = genclk_get_rate, | |
2165 | .set_rate = genclk_set_rate, | |
2166 | .set_parent = genclk_set_parent, | |
2167 | .index = 2, | |
2168 | }; | |
2169 | static struct clk gclk3 = { | |
2170 | .name = "gclk3", | |
2171 | .mode = genclk_mode, | |
2172 | .get_rate = genclk_get_rate, | |
2173 | .set_rate = genclk_set_rate, | |
2174 | .set_parent = genclk_set_parent, | |
2175 | .index = 3, | |
2176 | }; | |
2177 | static struct clk gclk4 = { | |
2178 | .name = "gclk4", | |
2179 | .mode = genclk_mode, | |
2180 | .get_rate = genclk_get_rate, | |
2181 | .set_rate = genclk_set_rate, | |
2182 | .set_parent = genclk_set_parent, | |
2183 | .index = 4, | |
2184 | }; | |
2185 | ||
300bb762 | 2186 | static __initdata struct clk *init_clocks[] = { |
5f97f7f9 HS |
2187 | &osc32k, |
2188 | &osc0, | |
2189 | &osc1, | |
2190 | &pll0, | |
2191 | &pll1, | |
2192 | &cpu_clk, | |
2193 | &hsb_clk, | |
2194 | &pba_clk, | |
2195 | &pbb_clk, | |
7a5b8059 | 2196 | &at32_pm_pclk, |
5f97f7f9 | 2197 | &at32_intc0_pclk, |
b47eb409 | 2198 | &at32_hmatrix_clk, |
5f97f7f9 HS |
2199 | &ebi_clk, |
2200 | &hramc_clk, | |
7951f188 | 2201 | &sdramc_clk, |
bc157b75 HS |
2202 | &smc0_pclk, |
2203 | &smc0_mck, | |
5f97f7f9 HS |
2204 | &pdc_hclk, |
2205 | &pdc_pclk, | |
3bfb1d20 | 2206 | &dw_dmac0_hclk, |
5f97f7f9 HS |
2207 | &pico_clk, |
2208 | &pio0_mck, | |
2209 | &pio1_mck, | |
2210 | &pio2_mck, | |
2211 | &pio3_mck, | |
7f9f4678 | 2212 | &pio4_mck, |
e723ff66 DB |
2213 | &at32_tcb0_t0_clk, |
2214 | &at32_tcb1_t0_clk, | |
d86d314f HCE |
2215 | &atmel_psif0_pclk, |
2216 | &atmel_psif1_pclk, | |
1e8ea802 HS |
2217 | &atmel_usart0_usart, |
2218 | &atmel_usart1_usart, | |
2219 | &atmel_usart2_usart, | |
2220 | &atmel_usart3_usart, | |
9a1e8eb1 | 2221 | &atmel_pwm0_mck, |
438ff3f3 | 2222 | #if defined(CONFIG_CPU_AT32AP7000) |
5f97f7f9 HS |
2223 | &macb0_hclk, |
2224 | &macb0_pclk, | |
cfcb3a89 HS |
2225 | &macb1_hclk, |
2226 | &macb1_pclk, | |
438ff3f3 | 2227 | #endif |
3d60ee1b HS |
2228 | &atmel_spi0_spi_clk, |
2229 | &atmel_spi1_spi_clk, | |
2042c1c4 HS |
2230 | &atmel_twi0_pclk, |
2231 | &atmel_mci0_pclk, | |
438ff3f3 | 2232 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af HS |
2233 | &atmel_lcdfb0_hck1, |
2234 | &atmel_lcdfb0_pixclk, | |
438ff3f3 | 2235 | #endif |
9cf6cf58 HCE |
2236 | &ssc0_pclk, |
2237 | &ssc1_pclk, | |
2238 | &ssc2_pclk, | |
6fcf0615 HS |
2239 | &usba0_hclk, |
2240 | &usba0_pclk, | |
2042c1c4 HS |
2241 | &atmel_ac97c0_pclk, |
2242 | &abdac0_pclk, | |
2243 | &abdac0_sample_clk, | |
7a5fe238 HS |
2244 | &gclk0, |
2245 | &gclk1, | |
2246 | &gclk2, | |
2247 | &gclk3, | |
2248 | &gclk4, | |
5f97f7f9 | 2249 | }; |
5f97f7f9 | 2250 | |
65033ed7 | 2251 | void __init setup_platform(void) |
5f97f7f9 | 2252 | { |
5f97f7f9 HS |
2253 | u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0; |
2254 | int i; | |
2255 | ||
9e58e185 | 2256 | if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) { |
5f97f7f9 | 2257 | main_clock = &pll0; |
9e58e185 HCE |
2258 | cpu_clk.parent = &pll0; |
2259 | } else { | |
5f97f7f9 | 2260 | main_clock = &osc0; |
9e58e185 HCE |
2261 | cpu_clk.parent = &osc0; |
2262 | } | |
5f97f7f9 | 2263 | |
7a5b8059 | 2264 | if (pm_readl(PLL0) & PM_BIT(PLLOSC)) |
5f97f7f9 | 2265 | pll0.parent = &osc1; |
7a5b8059 | 2266 | if (pm_readl(PLL1) & PM_BIT(PLLOSC)) |
5f97f7f9 HS |
2267 | pll1.parent = &osc1; |
2268 | ||
7a5fe238 HS |
2269 | genclk_init_parent(&gclk0); |
2270 | genclk_init_parent(&gclk1); | |
2271 | genclk_init_parent(&gclk2); | |
2272 | genclk_init_parent(&gclk3); | |
2273 | genclk_init_parent(&gclk4); | |
438ff3f3 | 2274 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af | 2275 | genclk_init_parent(&atmel_lcdfb0_pixclk); |
438ff3f3 | 2276 | #endif |
2042c1c4 | 2277 | genclk_init_parent(&abdac0_sample_clk); |
7a5fe238 | 2278 | |
5f97f7f9 | 2279 | /* |
300bb762 AR |
2280 | * Build initial dynamic clock list by registering all clocks |
2281 | * from the array. | |
2282 | * At the same time, turn on all clocks that have at least one | |
2283 | * user already, and turn off everything else. We only do this | |
2284 | * for module clocks, and even though it isn't particularly | |
2285 | * pretty to check the address of the mode function, it should | |
2286 | * do the trick... | |
5f97f7f9 | 2287 | */ |
300bb762 AR |
2288 | for (i = 0; i < ARRAY_SIZE(init_clocks); i++) { |
2289 | struct clk *clk = init_clocks[i]; | |
2290 | ||
2291 | /* first, register clock */ | |
2292 | at32_clk_register(clk); | |
5f97f7f9 | 2293 | |
188ff65d HS |
2294 | if (clk->users == 0) |
2295 | continue; | |
2296 | ||
5f97f7f9 HS |
2297 | if (clk->mode == &cpu_clk_mode) |
2298 | cpu_mask |= 1 << clk->index; | |
2299 | else if (clk->mode == &hsb_clk_mode) | |
2300 | hsb_mask |= 1 << clk->index; | |
2301 | else if (clk->mode == &pba_clk_mode) | |
2302 | pba_mask |= 1 << clk->index; | |
2303 | else if (clk->mode == &pbb_clk_mode) | |
2304 | pbb_mask |= 1 << clk->index; | |
2305 | } | |
2306 | ||
7a5b8059 HS |
2307 | pm_writel(CPU_MASK, cpu_mask); |
2308 | pm_writel(HSB_MASK, hsb_mask); | |
2309 | pm_writel(PBA_MASK, pba_mask); | |
2310 | pm_writel(PBB_MASK, pbb_mask); | |
65033ed7 HS |
2311 | |
2312 | /* Initialize the port muxes */ | |
2313 | at32_init_pio(&pio0_device); | |
2314 | at32_init_pio(&pio1_device); | |
2315 | at32_init_pio(&pio2_device); | |
2316 | at32_init_pio(&pio3_device); | |
2317 | at32_init_pio(&pio4_device); | |
5f97f7f9 | 2318 | } |
b83d6ee1 HS |
2319 | |
2320 | struct gen_pool *sram_pool; | |
2321 | ||
2322 | static int __init sram_init(void) | |
2323 | { | |
2324 | struct gen_pool *pool; | |
2325 | ||
2326 | /* 1KiB granularity */ | |
2327 | pool = gen_pool_create(10, -1); | |
2328 | if (!pool) | |
2329 | goto fail; | |
2330 | ||
2331 | if (gen_pool_add(pool, 0x24000000, 0x8000, -1)) | |
2332 | goto err_pool_add; | |
2333 | ||
2334 | sram_pool = pool; | |
2335 | return 0; | |
2336 | ||
2337 | err_pool_add: | |
2338 | gen_pool_destroy(pool); | |
2339 | fail: | |
2340 | pr_err("Failed to create SRAM pool\n"); | |
2341 | return -ENOMEM; | |
2342 | } | |
2343 | core_initcall(sram_init); |