ARM: at91: at91sam9x5cm/dt: add leds support
[linux-2.6-block.git] / arch / avr32 / boards / atstk1000 / atstk1002.c
CommitLineData
5f97f7f9 1/*
e150d6e7 2 * ATSTK1002/ATSTK1006 daughterboard-specific init code
5f97f7f9 3 *
e150d6e7 4 * Copyright (C) 2005-2007 Atmel Corporation
5f97f7f9
HS
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
c164b901
HS
10#include <linux/clk.h>
11#include <linux/etherdevice.h>
5f97f7f9 12#include <linux/init.h>
a6f92f3d 13#include <linux/kernel.h>
c164b901 14#include <linux/platform_device.h>
a6f92f3d
HS
15#include <linux/string.h>
16#include <linux/types.h>
3d60ee1b 17#include <linux/spi/spi.h>
1c2f1737 18#include <linux/spi/at73c213.h>
c42aa775 19#include <linux/atmel-mci.h>
5f97f7f9 20
d0a2b7af
HS
21#include <video/atmel_lcdc.h>
22
c164b901 23#include <asm/io.h>
a6f92f3d 24#include <asm/setup.h>
3c26e170 25
3663b736
HS
26#include <mach/at32ap700x.h>
27#include <mach/board.h>
28#include <mach/init.h>
29#include <mach/portmux.h>
5f97f7f9 30
d0a2b7af 31#include "atstk1000.h"
a3d912c8 32
60ed7951
A
33/* Oscillator frequencies. These are board specific */
34unsigned long at32_board_osc_rates[3] = {
35 [0] = 32768, /* 32.768 kHz on RTC osc */
36 [1] = 20000000, /* 20 MHz on osc0 */
37 [2] = 12000000, /* 12 MHz on osc1 */
38};
a3d912c8 39
e150d6e7
HS
40/*
41 * The ATSTK1006 daughterboard is very similar to the ATSTK1002. Both
42 * have the AT32AP7000 chip on board; the difference is that the
43 * STK1006 has 128 MB SDRAM (the STK1002 uses the 8 MB SDRAM chip on
44 * the STK1000 motherboard) and 256 MB NAND flash (the STK1002 has
45 * none.)
46 *
47 * The RAM difference is handled by the boot loader, so the only
48 * difference we end up handling here is the NAND flash.
49 */
50#ifdef CONFIG_BOARD_ATSTK1006
51#include <linux/mtd/partitions.h>
3663b736 52#include <mach/smc.h>
e150d6e7
HS
53
54static struct smc_timing nand_timing __initdata = {
55 .ncs_read_setup = 0,
56 .nrd_setup = 10,
57 .ncs_write_setup = 0,
58 .nwe_setup = 10,
59
60 .ncs_read_pulse = 30,
61 .nrd_pulse = 15,
62 .ncs_write_pulse = 30,
63 .nwe_pulse = 15,
64
65 .read_cycle = 30,
66 .write_cycle = 30,
67
68 .ncs_read_recover = 0,
69 .nrd_recover = 15,
70 .ncs_write_recover = 0,
71 /* WE# high -> RE# low min 60 ns */
72 .nwe_recover = 50,
73};
74
75static struct smc_config nand_config __initdata = {
76 .bus_width = 1,
77 .nrd_controlled = 1,
78 .nwe_controlled = 1,
79 .nwait_mode = 0,
80 .byte_write = 0,
81 .tdf_cycles = 2,
82 .tdf_mode = 0,
83};
84
85static struct mtd_partition nand_partitions[] = {
86 {
87 .name = "main",
88 .offset = 0x00000000,
89 .size = MTDPART_SIZ_FULL,
90 },
91};
92
33f197a6 93static struct atmel_nand_data atstk1006_nand_data __initdata = {
e150d6e7
HS
94 .cle = 21,
95 .ale = 22,
96 .rdy_pin = GPIO_PIN_PB(30),
97 .enable_pin = GPIO_PIN_PB(29),
1754aab9
DES
98 .parts = nand_partitions,
99 .num_parts = ARRAY_SIZE(num_partitions),
e150d6e7
HS
100};
101#endif
102
c164b901
HS
103struct eth_addr {
104 u8 addr[6];
105};
106
107static struct eth_addr __initdata hw_addr[2];
84e0cdb0 108static struct macb_platform_data __initdata eth_data[2] = {
587ca761
HS
109 {
110 /*
111 * The MDIO pullups on STK1000 are a bit too weak for
112 * the autodetection to work properly, so we have to
113 * mask out everything but the correct address.
114 */
115 .phy_mask = ~(1U << 16),
116 },
117 {
118 .phy_mask = ~(1U << 17),
119 },
120};
5f97f7f9 121
64d81052 122#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
1c2f1737
HCE
123static struct at73c213_board_info at73c213_data = {
124 .ssc_id = 0,
125 .shortname = "AVR32 STK1000 external DAC",
126};
127#endif
1c2f1737 128
78693e47 129#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
41d8ca45 130static struct spi_board_info spi0_board_info[] __initdata = {
64d81052 131#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
1c2f1737
HCE
132 {
133 /* AT73C213 */
134 .modalias = "at73c213",
135 .max_speed_hz = 200000,
136 .chip_select = 0,
137 .mode = SPI_MODE_1,
138 .platform_data = &at73c213_data,
139 },
140#endif
3d60ee1b 141 {
41d8ca45 142 /* QVGA display */
3d60ee1b 143 .modalias = "ltv350qv",
3d60ee1b 144 .max_speed_hz = 16000000,
3d60ee1b 145 .chip_select = 1,
2fdfe8d9 146 .mode = SPI_MODE_3,
3d60ee1b
HS
147 },
148};
a8e93ed8
DB
149#endif
150
78693e47 151#ifdef CONFIG_BOARD_ATSTK100X_SPI1
a8e93ed8
DB
152static struct spi_board_info spi1_board_info[] __initdata = { {
153 /* patch in custom entries here */
154} };
155#endif
3d60ee1b 156
c164b901
HS
157/*
158 * The next two functions should go away as the boot loader is
159 * supposed to initialize the macb address registers with a valid
160 * ethernet address. But we need to keep it around for a while until
161 * we can be reasonably sure the boot loader does this.
162 *
163 * The phy_id is ignored as the driver will probe for it.
164 */
a6f92f3d
HS
165static int __init parse_tag_ethernet(struct tag *tag)
166{
167 int i;
168
169 i = tag->u.ethernet.mac_index;
c164b901
HS
170 if (i < ARRAY_SIZE(hw_addr))
171 memcpy(hw_addr[i].addr, tag->u.ethernet.hw_address,
172 sizeof(hw_addr[i].addr));
173
a6f92f3d
HS
174 return 0;
175}
176__tagtable(ATAG_ETHERNET, parse_tag_ethernet);
177
c164b901
HS
178static void __init set_hw_addr(struct platform_device *pdev)
179{
180 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
181 const u8 *addr;
182 void __iomem *regs;
183 struct clk *pclk;
184
185 if (!res)
186 return;
187 if (pdev->id >= ARRAY_SIZE(hw_addr))
188 return;
189
190 addr = hw_addr[pdev->id].addr;
191 if (!is_valid_ether_addr(addr))
192 return;
193
194 /*
195 * Since this is board-specific code, we'll cheat and use the
196 * physical address directly as we happen to know that it's
197 * the same as the virtual address.
198 */
199 regs = (void __iomem __force *)res->start;
200 pclk = clk_get(&pdev->dev, "pclk");
36b471e0 201 if (IS_ERR(pclk))
c164b901
HS
202 return;
203
204 clk_enable(pclk);
205 __raw_writel((addr[3] << 24) | (addr[2] << 16)
206 | (addr[1] << 8) | addr[0], regs + 0x98);
207 __raw_writel((addr[5] << 8) | addr[4], regs + 0x9c);
208 clk_disable(pclk);
209 clk_put(pclk);
210}
211
64d81052
HS
212#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
213static void __init atstk1002_setup_extdac(void)
1c2f1737
HCE
214{
215 struct clk *gclk;
216 struct clk *pll;
217
218 gclk = clk_get(NULL, "gclk0");
219 if (IS_ERR(gclk))
220 goto err_gclk;
221 pll = clk_get(NULL, "pll0");
222 if (IS_ERR(pll))
223 goto err_pll;
224
225 if (clk_set_parent(gclk, pll)) {
226 pr_debug("STK1000: failed to set pll0 as parent for DAC clock\n");
227 goto err_set_clk;
228 }
229
caf18f19 230 at32_select_periph(GPIO_PIOA_BASE, (1 << 30), GPIO_PERIPH_A, 0);
64d81052 231 at73c213_data.dac_clk = gclk;
1c2f1737
HCE
232
233err_set_clk:
234 clk_put(pll);
235err_pll:
236 clk_put(gclk);
237err_gclk:
238 return;
239}
64d81052
HS
240#else
241static void __init atstk1002_setup_extdac(void)
242{
243
244}
245#endif /* CONFIG_BOARD_ATSTK1000_EXTDAC */
1c2f1737 246
c194588d
HS
247void __init setup_board(void)
248{
78693e47 249#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
bf4861cf 250 at32_map_usart(0, 1, 0); /* USART 0/B: /dev/ttyS1, IRDA */
a8e93ed8 251#else
bf4861cf 252 at32_map_usart(1, 0, 0); /* USART 1/A: /dev/ttyS0, DB9 */
a3d912c8
DB
253#endif
254 /* USART 2/unused: expansion connector */
bf4861cf 255 at32_map_usart(3, 2, 0); /* USART 3/C: /dev/ttyS2, DB9 */
c194588d
HS
256
257 at32_setup_serial_console(0);
258}
259
3c26e170
DB
260#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
261
6b918657
HS
262static struct mci_platform_data __initdata mci0_data = {
263 .slot[0] = {
264 .bus_width = 4,
265
3c26e170
DB
266/* MMC card detect requires MACB0 *NOT* be used */
267#ifdef CONFIG_BOARD_ATSTK1002_SW6_CUSTOM
6b918657
HS
268 .detect_pin = GPIO_PIN_PC(14), /* gpio30/sdcd */
269 .wp_pin = GPIO_PIN_PC(15), /* gpio31/sdwp */
3c26e170 270#else
6b918657
HS
271 .detect_pin = -ENODEV,
272 .wp_pin = -ENODEV,
3c26e170 273#endif /* SW6 for sd{cd,wp} routing */
6b918657
HS
274 },
275};
3c26e170
DB
276
277#endif /* SW2 for MMC signal routing */
278
5f97f7f9
HS
279static int __init atstk1002_init(void)
280{
7f9f4678
HS
281 /*
282 * ATSTK1000 uses 32-bit SDRAM interface. Reserve the
283 * SDRAM-specific pins so that nobody messes with them.
284 */
adde42b5 285 at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
7f9f4678 286
e150d6e7
HS
287#ifdef CONFIG_BOARD_ATSTK1006
288 smc_set_timing(&nand_config, &nand_timing);
289 smc_set_configuration(3, &nand_config);
290 at32_add_device_nand(0, &atstk1006_nand_data);
291#endif
292
78693e47 293#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
c194588d 294 at32_add_device_usart(1);
a8e93ed8
DB
295#else
296 at32_add_device_usart(0);
a3d912c8 297#endif
c194588d 298 at32_add_device_usart(2);
5f97f7f9 299
d4003ba0 300#ifndef CONFIG_BOARD_ATSTK1002_SW6_CUSTOM
c164b901 301 set_hw_addr(at32_add_device_eth(0, &eth_data[0]));
d4003ba0 302#endif
78693e47 303#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
41d8ca45 304 at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
a8e93ed8 305#endif
78693e47 306#ifdef CONFIG_BOARD_ATSTK100X_SPI1
a8e93ed8
DB
307 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
308#endif
7fb61a7b 309#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
6eb3ebe0 310 at32_add_device_mci(0, &mci0_data);
7d2be074 311#endif
a8e93ed8
DB
312#ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM
313 set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
314#else
d0a2b7af 315 at32_add_device_lcdc(0, &atstk1000_lcdc_data,
70664124
JM
316 fbmem_start, fbmem_size,
317 ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL);
a8e93ed8 318#endif
6fcf0615 319 at32_add_device_usba(0, NULL);
78693e47 320#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
95a42267
HCE
321 at32_add_device_ssc(0, ATMEL_SSC_TX);
322#endif
5f97f7f9 323
f4c41b26 324 atstk1000_setup_j2_leds();
64d81052 325 atstk1002_setup_extdac();
1c2f1737 326
5f97f7f9
HS
327 return 0;
328}
329postcore_initcall(atstk1002_init);