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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1d18c47c CM |
2 | /* |
3 | * Based on arch/arm/mm/fault.c | |
4 | * | |
5 | * Copyright (C) 1995 Linus Torvalds | |
6 | * Copyright (C) 1995-2004 Russell King | |
7 | * Copyright (C) 2012 ARM Ltd. | |
1d18c47c CM |
8 | */ |
9 | ||
d44f1b8d | 10 | #include <linux/acpi.h> |
42f91093 | 11 | #include <linux/bitfield.h> |
0edfa839 | 12 | #include <linux/extable.h> |
1d18c47c CM |
13 | #include <linux/signal.h> |
14 | #include <linux/mm.h> | |
15 | #include <linux/hardirq.h> | |
16 | #include <linux/init.h> | |
4291e9ee | 17 | #include <linux/kasan.h> |
1d18c47c CM |
18 | #include <linux/kprobes.h> |
19 | #include <linux/uaccess.h> | |
20 | #include <linux/page-flags.h> | |
3f07c014 | 21 | #include <linux/sched/signal.h> |
b17b0153 | 22 | #include <linux/sched/debug.h> |
1d18c47c CM |
23 | #include <linux/highmem.h> |
24 | #include <linux/perf_event.h> | |
7209c868 | 25 | #include <linux/preempt.h> |
e7c600f1 | 26 | #include <linux/hugetlb.h> |
1d18c47c | 27 | |
d44f1b8d | 28 | #include <asm/acpi.h> |
7209c868 | 29 | #include <asm/bug.h> |
3bbf7157 | 30 | #include <asm/cmpxchg.h> |
338d4f49 | 31 | #include <asm/cpufeature.h> |
1d18c47c | 32 | #include <asm/exception.h> |
9a0c0328 | 33 | #include <asm/daifflags.h> |
1d18c47c | 34 | #include <asm/debug-monitors.h> |
9141300a | 35 | #include <asm/esr.h> |
b6e43c0e | 36 | #include <asm/kprobes.h> |
98c970da | 37 | #include <asm/mte.h> |
bfe29874 | 38 | #include <asm/processor.h> |
338d4f49 | 39 | #include <asm/sysreg.h> |
1d18c47c | 40 | #include <asm/system_misc.h> |
1d18c47c | 41 | #include <asm/tlbflush.h> |
92ff0674 | 42 | #include <asm/traps.h> |
1d18c47c | 43 | |
09a6adf5 | 44 | struct fault_info { |
dceec3ff | 45 | int (*fn)(unsigned long far, unsigned int esr, |
09a6adf5 VK |
46 | struct pt_regs *regs); |
47 | int sig; | |
48 | int code; | |
49 | const char *name; | |
50 | }; | |
51 | ||
52 | static const struct fault_info fault_info[]; | |
359048f9 | 53 | static struct fault_info debug_fault_info[]; |
09a6adf5 VK |
54 | |
55 | static inline const struct fault_info *esr_to_fault_info(unsigned int esr) | |
56 | { | |
00bbd5d9 | 57 | return fault_info + (esr & ESR_ELx_FSC); |
09a6adf5 | 58 | } |
3495386b | 59 | |
359048f9 AK |
60 | static inline const struct fault_info *esr_to_debug_fault_info(unsigned int esr) |
61 | { | |
62 | return debug_fault_info + DBG_ESR_EVT(esr); | |
63 | } | |
64 | ||
1f9b8936 JT |
65 | static void data_abort_decode(unsigned int esr) |
66 | { | |
67 | pr_alert("Data abort info:\n"); | |
68 | ||
69 | if (esr & ESR_ELx_ISV) { | |
70 | pr_alert(" Access size = %u byte(s)\n", | |
71 | 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT)); | |
72 | pr_alert(" SSE = %lu, SRT = %lu\n", | |
73 | (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT, | |
74 | (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT); | |
75 | pr_alert(" SF = %lu, AR = %lu\n", | |
76 | (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT, | |
77 | (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT); | |
78 | } else { | |
0a6de8b8 | 79 | pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK); |
1f9b8936 JT |
80 | } |
81 | ||
82 | pr_alert(" CM = %lu, WnR = %lu\n", | |
83 | (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT, | |
84 | (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT); | |
85 | } | |
86 | ||
1f9b8936 JT |
87 | static void mem_abort_decode(unsigned int esr) |
88 | { | |
89 | pr_alert("Mem abort info:\n"); | |
90 | ||
42dbf54e | 91 | pr_alert(" ESR = 0x%08x\n", esr); |
2951d5ef MC |
92 | pr_alert(" EC = 0x%02lx: %s, IL = %u bits\n", |
93 | ESR_ELx_EC(esr), esr_get_class_string(esr), | |
1f9b8936 JT |
94 | (esr & ESR_ELx_IL) ? 32 : 16); |
95 | pr_alert(" SET = %lu, FnV = %lu\n", | |
96 | (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT, | |
97 | (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT); | |
98 | pr_alert(" EA = %lu, S1PTW = %lu\n", | |
99 | (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT, | |
100 | (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT); | |
101 | ||
102 | if (esr_is_data_abort(esr)) | |
103 | data_abort_decode(esr); | |
104 | } | |
105 | ||
e4365f96 MR |
106 | static inline unsigned long mm_to_pgd_phys(struct mm_struct *mm) |
107 | { | |
108 | /* Either init_pg_dir or swapper_pg_dir */ | |
109 | if (mm == &init_mm) | |
110 | return __pa_symbol(mm->pgd); | |
111 | ||
112 | return (unsigned long)virt_to_phys(mm->pgd); | |
113 | } | |
114 | ||
1d18c47c | 115 | /* |
67ce16ec | 116 | * Dump out the page tables associated with 'addr' in the currently active mm. |
1d18c47c | 117 | */ |
7048a597 | 118 | static void show_pte(unsigned long addr) |
1d18c47c | 119 | { |
67ce16ec | 120 | struct mm_struct *mm; |
20a004e7 WD |
121 | pgd_t *pgdp; |
122 | pgd_t pgd; | |
1d18c47c | 123 | |
356607f2 | 124 | if (is_ttbr0_addr(addr)) { |
67ce16ec KM |
125 | /* TTBR0 */ |
126 | mm = current->active_mm; | |
127 | if (mm == &init_mm) { | |
128 | pr_alert("[%016lx] user address but active_mm is swapper\n", | |
129 | addr); | |
130 | return; | |
131 | } | |
356607f2 | 132 | } else if (is_ttbr1_addr(addr)) { |
67ce16ec | 133 | /* TTBR1 */ |
1d18c47c | 134 | mm = &init_mm; |
67ce16ec KM |
135 | } else { |
136 | pr_alert("[%016lx] address between user and kernel address ranges\n", | |
137 | addr); | |
138 | return; | |
139 | } | |
1d18c47c | 140 | |
5383cc6e | 141 | pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n", |
1eb34b6e | 142 | mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K, |
e4365f96 | 143 | vabits_actual, mm_to_pgd_phys(mm)); |
20a004e7 WD |
144 | pgdp = pgd_offset(mm, addr); |
145 | pgd = READ_ONCE(*pgdp); | |
146 | pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd)); | |
1d18c47c CM |
147 | |
148 | do { | |
e9f63768 | 149 | p4d_t *p4dp, p4d; |
20a004e7 WD |
150 | pud_t *pudp, pud; |
151 | pmd_t *pmdp, pmd; | |
152 | pte_t *ptep, pte; | |
1d18c47c | 153 | |
20a004e7 | 154 | if (pgd_none(pgd) || pgd_bad(pgd)) |
1d18c47c CM |
155 | break; |
156 | ||
e9f63768 MR |
157 | p4dp = p4d_offset(pgdp, addr); |
158 | p4d = READ_ONCE(*p4dp); | |
159 | pr_cont(", p4d=%016llx", p4d_val(p4d)); | |
160 | if (p4d_none(p4d) || p4d_bad(p4d)) | |
161 | break; | |
162 | ||
163 | pudp = pud_offset(p4dp, addr); | |
20a004e7 WD |
164 | pud = READ_ONCE(*pudp); |
165 | pr_cont(", pud=%016llx", pud_val(pud)); | |
166 | if (pud_none(pud) || pud_bad(pud)) | |
1d18c47c CM |
167 | break; |
168 | ||
20a004e7 WD |
169 | pmdp = pmd_offset(pudp, addr); |
170 | pmd = READ_ONCE(*pmdp); | |
171 | pr_cont(", pmd=%016llx", pmd_val(pmd)); | |
172 | if (pmd_none(pmd) || pmd_bad(pmd)) | |
1d18c47c CM |
173 | break; |
174 | ||
20a004e7 WD |
175 | ptep = pte_offset_map(pmdp, addr); |
176 | pte = READ_ONCE(*ptep); | |
177 | pr_cont(", pte=%016llx", pte_val(pte)); | |
178 | pte_unmap(ptep); | |
1d18c47c CM |
179 | } while(0); |
180 | ||
6ef4fb38 | 181 | pr_cont("\n"); |
1d18c47c CM |
182 | } |
183 | ||
66dbd6e6 CM |
184 | /* |
185 | * This function sets the access flags (dirty, accessed), as well as write | |
186 | * permission, and only to a more permissive setting. | |
187 | * | |
188 | * It needs to cope with hardware update of the accessed/dirty state by other | |
189 | * agents in the system and can safely skip the __sync_icache_dcache() call as, | |
190 | * like set_pte_at(), the PTE is never changed from no-exec to exec here. | |
191 | * | |
192 | * Returns whether or not the PTE actually changed. | |
193 | */ | |
194 | int ptep_set_access_flags(struct vm_area_struct *vma, | |
195 | unsigned long address, pte_t *ptep, | |
196 | pte_t entry, int dirty) | |
197 | { | |
3bbf7157 | 198 | pteval_t old_pteval, pteval; |
20a004e7 | 199 | pte_t pte = READ_ONCE(*ptep); |
66dbd6e6 | 200 | |
20a004e7 | 201 | if (pte_same(pte, entry)) |
66dbd6e6 CM |
202 | return 0; |
203 | ||
204 | /* only preserve the access flags and write permission */ | |
73e86cb0 | 205 | pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY; |
66dbd6e6 CM |
206 | |
207 | /* | |
208 | * Setting the flags must be done atomically to avoid racing with the | |
6d332747 CM |
209 | * hardware update of the access/dirty state. The PTE_RDONLY bit must |
210 | * be set to the most permissive (lowest value) of *ptep and entry | |
211 | * (calculated as: a & b == ~(~a | ~b)). | |
66dbd6e6 | 212 | */ |
6d332747 | 213 | pte_val(entry) ^= PTE_RDONLY; |
20a004e7 | 214 | pteval = pte_val(pte); |
3bbf7157 CM |
215 | do { |
216 | old_pteval = pteval; | |
217 | pteval ^= PTE_RDONLY; | |
218 | pteval |= pte_val(entry); | |
219 | pteval ^= PTE_RDONLY; | |
220 | pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval); | |
221 | } while (pteval != old_pteval); | |
66dbd6e6 | 222 | |
6a1bdb17 WD |
223 | /* Invalidate a stale read-only entry */ |
224 | if (dirty) | |
225 | flush_tlb_page(vma, address); | |
66dbd6e6 CM |
226 | return 1; |
227 | } | |
66dbd6e6 | 228 | |
9adeb8e7 LA |
229 | static bool is_el1_instruction_abort(unsigned int esr) |
230 | { | |
231 | return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; | |
232 | } | |
233 | ||
dbfe3828 AK |
234 | static inline bool is_el1_permission_fault(unsigned long addr, unsigned int esr, |
235 | struct pt_regs *regs) | |
b824b930 SB |
236 | { |
237 | unsigned int ec = ESR_ELx_EC(esr); | |
238 | unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE; | |
239 | ||
240 | if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR) | |
241 | return false; | |
242 | ||
243 | if (fsc_type == ESR_ELx_FSC_PERM) | |
244 | return true; | |
245 | ||
356607f2 | 246 | if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan()) |
b824b930 SB |
247 | return fsc_type == ESR_ELx_FSC_FAULT && |
248 | (regs->pstate & PSR_PAN_BIT); | |
249 | ||
250 | return false; | |
251 | } | |
252 | ||
42f91093 WD |
253 | static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr, |
254 | unsigned int esr, | |
255 | struct pt_regs *regs) | |
256 | { | |
257 | unsigned long flags; | |
258 | u64 par, dfsc; | |
259 | ||
260 | if (ESR_ELx_EC(esr) != ESR_ELx_EC_DABT_CUR || | |
261 | (esr & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT) | |
262 | return false; | |
263 | ||
264 | local_irq_save(flags); | |
265 | asm volatile("at s1e1r, %0" :: "r" (addr)); | |
266 | isb(); | |
96d389ca | 267 | par = read_sysreg_par(); |
42f91093 WD |
268 | local_irq_restore(flags); |
269 | ||
38137335 MR |
270 | /* |
271 | * If we now have a valid translation, treat the translation fault as | |
272 | * spurious. | |
273 | */ | |
42f91093 | 274 | if (!(par & SYS_PAR_EL1_F)) |
38137335 | 275 | return true; |
42f91093 WD |
276 | |
277 | /* | |
278 | * If we got a different type of fault from the AT instruction, | |
279 | * treat the translation fault as spurious. | |
280 | */ | |
308c5156 | 281 | dfsc = FIELD_GET(SYS_PAR_EL1_FST, par); |
42f91093 WD |
282 | return (dfsc & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT; |
283 | } | |
284 | ||
c870f14e MR |
285 | static void die_kernel_fault(const char *msg, unsigned long addr, |
286 | unsigned int esr, struct pt_regs *regs) | |
287 | { | |
288 | bust_spinlocks(1); | |
289 | ||
290 | pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg, | |
291 | addr); | |
292 | ||
293 | mem_abort_decode(esr); | |
294 | ||
295 | show_pte(addr); | |
296 | die("Oops", regs, esr); | |
297 | bust_spinlocks(0); | |
298 | do_exit(SIGKILL); | |
299 | } | |
300 | ||
4291e9ee | 301 | #ifdef CONFIG_KASAN_HW_TAGS |
98c970da VF |
302 | static void report_tag_fault(unsigned long addr, unsigned int esr, |
303 | struct pt_regs *regs) | |
304 | { | |
4291e9ee AK |
305 | bool is_write = ((esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT) != 0; |
306 | ||
307 | /* | |
308 | * SAS bits aren't set for all faults reported in EL1, so we can't | |
309 | * find out access size. | |
310 | */ | |
311 | kasan_report(addr, 0, is_write, regs->pc); | |
98c970da | 312 | } |
4291e9ee AK |
313 | #else |
314 | /* Tag faults aren't enabled without CONFIG_KASAN_HW_TAGS. */ | |
315 | static inline void report_tag_fault(unsigned long addr, unsigned int esr, | |
316 | struct pt_regs *regs) { } | |
317 | #endif | |
98c970da VF |
318 | |
319 | static void do_tag_recovery(unsigned long addr, unsigned int esr, | |
320 | struct pt_regs *regs) | |
321 | { | |
322 | static bool reported; | |
323 | ||
324 | if (!READ_ONCE(reported)) { | |
325 | report_tag_fault(addr, esr, regs); | |
326 | WRITE_ONCE(reported, true); | |
327 | } | |
328 | ||
329 | /* | |
330 | * Disable MTE Tag Checking on the local CPU for the current EL. | |
331 | * It will be done lazily on the other CPUs when they will hit a | |
332 | * tag fault. | |
333 | */ | |
334 | sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, SCTLR_ELx_TCF_NONE); | |
335 | isb(); | |
336 | } | |
337 | ||
338 | static bool is_el1_mte_sync_tag_check_fault(unsigned int esr) | |
339 | { | |
340 | unsigned int ec = ESR_ELx_EC(esr); | |
341 | unsigned int fsc = esr & ESR_ELx_FSC; | |
342 | ||
343 | if (ec != ESR_ELx_EC_DABT_CUR) | |
344 | return false; | |
345 | ||
346 | if (fsc == ESR_ELx_FSC_MTE) | |
347 | return true; | |
348 | ||
349 | return false; | |
350 | } | |
351 | ||
67ce16ec KM |
352 | static void __do_kernel_fault(unsigned long addr, unsigned int esr, |
353 | struct pt_regs *regs) | |
1d18c47c | 354 | { |
b824b930 SB |
355 | const char *msg; |
356 | ||
1d18c47c CM |
357 | /* |
358 | * Are we prepared to handle this kernel fault? | |
9adeb8e7 | 359 | * We are almost certainly not prepared to handle instruction faults. |
1d18c47c | 360 | */ |
9adeb8e7 | 361 | if (!is_el1_instruction_abort(esr) && fixup_exception(regs)) |
1d18c47c CM |
362 | return; |
363 | ||
42f91093 WD |
364 | if (WARN_RATELIMIT(is_spurious_el1_translation_fault(addr, esr, regs), |
365 | "Ignoring spurious kernel translation fault at virtual address %016lx\n", addr)) | |
366 | return; | |
367 | ||
98c970da VF |
368 | if (is_el1_mte_sync_tag_check_fault(esr)) { |
369 | do_tag_recovery(addr, esr, regs); | |
370 | ||
371 | return; | |
372 | } | |
373 | ||
dbfe3828 | 374 | if (is_el1_permission_fault(addr, esr, regs)) { |
b824b930 SB |
375 | if (esr & ESR_ELx_WNR) |
376 | msg = "write to read-only memory"; | |
e44ec4a3 XZ |
377 | else if (is_el1_instruction_abort(esr)) |
378 | msg = "execute from non-executable memory"; | |
b824b930 SB |
379 | else |
380 | msg = "read from unreadable memory"; | |
381 | } else if (addr < PAGE_SIZE) { | |
382 | msg = "NULL pointer dereference"; | |
383 | } else { | |
384 | msg = "paging request"; | |
385 | } | |
386 | ||
c870f14e | 387 | die_kernel_fault(msg, addr, esr, regs); |
1d18c47c CM |
388 | } |
389 | ||
f29ad209 | 390 | static void set_thread_esr(unsigned long address, unsigned int esr) |
1d18c47c | 391 | { |
f29ad209 | 392 | current->thread.fault_address = address; |
cc198460 PM |
393 | |
394 | /* | |
395 | * If the faulting address is in the kernel, we must sanitize the ESR. | |
396 | * From userspace's point of view, kernel-only mappings don't exist | |
397 | * at all, so we report them as level 0 translation faults. | |
398 | * (This is not quite the way that "no mapping there at all" behaves: | |
399 | * an alignment fault not caused by the memory type would take | |
400 | * precedence over translation fault for a real access to empty | |
401 | * space. Unfortunately we can't easily distinguish "alignment fault | |
402 | * not caused by memory type" from "alignment fault caused by memory | |
403 | * type", so we ignore this wrinkle and just return the translation | |
404 | * fault.) | |
405 | */ | |
356607f2 | 406 | if (!is_ttbr0_addr(current->thread.fault_address)) { |
cc198460 PM |
407 | switch (ESR_ELx_EC(esr)) { |
408 | case ESR_ELx_EC_DABT_LOW: | |
409 | /* | |
410 | * These bits provide only information about the | |
411 | * faulting instruction, which userspace knows already. | |
412 | * We explicitly clear bits which are architecturally | |
413 | * RES0 in case they are given meanings in future. | |
414 | * We always report the ESR as if the fault was taken | |
415 | * to EL1 and so ISV and the bits in ISS[23:14] are | |
416 | * clear. (In fact it always will be a fault to EL1.) | |
417 | */ | |
418 | esr &= ESR_ELx_EC_MASK | ESR_ELx_IL | | |
419 | ESR_ELx_CM | ESR_ELx_WNR; | |
420 | esr |= ESR_ELx_FSC_FAULT; | |
421 | break; | |
422 | case ESR_ELx_EC_IABT_LOW: | |
423 | /* | |
424 | * Claim a level 0 translation fault. | |
425 | * All other bits are architecturally RES0 for faults | |
426 | * reported with that DFSC value, so we clear them. | |
427 | */ | |
428 | esr &= ESR_ELx_EC_MASK | ESR_ELx_IL; | |
429 | esr |= ESR_ELx_FSC_FAULT; | |
430 | break; | |
431 | default: | |
432 | /* | |
433 | * This should never happen (entry.S only brings us | |
434 | * into this code for insn and data aborts from a lower | |
435 | * exception level). Fail safe by not providing an ESR | |
436 | * context record at all. | |
437 | */ | |
438 | WARN(1, "ESR 0x%x is not DABT or IABT from EL0\n", esr); | |
439 | esr = 0; | |
440 | break; | |
441 | } | |
442 | } | |
443 | ||
92ff0674 | 444 | current->thread.fault_code = esr; |
1d18c47c CM |
445 | } |
446 | ||
dceec3ff PC |
447 | static void do_bad_area(unsigned long far, unsigned int esr, |
448 | struct pt_regs *regs) | |
1d18c47c | 449 | { |
dceec3ff PC |
450 | unsigned long addr = untagged_addr(far); |
451 | ||
1d18c47c CM |
452 | /* |
453 | * If we are in kernel mode at this point, we have no context to | |
454 | * handle this fault with. | |
455 | */ | |
09a6adf5 | 456 | if (user_mode(regs)) { |
92ff0674 | 457 | const struct fault_info *inf = esr_to_fault_info(esr); |
3eb0f519 | 458 | |
effb093a | 459 | set_thread_esr(addr, esr); |
dceec3ff | 460 | arm64_force_sig_fault(inf->sig, inf->code, far, inf->name); |
92ff0674 | 461 | } else { |
67ce16ec | 462 | __do_kernel_fault(addr, esr, regs); |
92ff0674 | 463 | } |
1d18c47c CM |
464 | } |
465 | ||
466 | #define VM_FAULT_BADMAP 0x010000 | |
467 | #define VM_FAULT_BADACCESS 0x020000 | |
468 | ||
50a7ca3c | 469 | static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr, |
6a1bb025 PX |
470 | unsigned int mm_flags, unsigned long vm_flags, |
471 | struct pt_regs *regs) | |
1d18c47c | 472 | { |
4745224b | 473 | struct vm_area_struct *vma = find_vma(mm, addr); |
1d18c47c | 474 | |
1d18c47c | 475 | if (unlikely(!vma)) |
4745224b | 476 | return VM_FAULT_BADMAP; |
1d18c47c CM |
477 | |
478 | /* | |
479 | * Ok, we have a good vm_area for this memory access, so we can handle | |
480 | * it. | |
481 | */ | |
4745224b AK |
482 | if (unlikely(vma->vm_start > addr)) { |
483 | if (!(vma->vm_flags & VM_GROWSDOWN)) | |
484 | return VM_FAULT_BADMAP; | |
485 | if (expand_stack(vma, addr)) | |
486 | return VM_FAULT_BADMAP; | |
487 | } | |
488 | ||
db6f4106 WD |
489 | /* |
490 | * Check that the permissions on the VMA allow for the fault which | |
cab15ce6 | 491 | * occurred. |
db6f4106 | 492 | */ |
4745224b AK |
493 | if (!(vma->vm_flags & vm_flags)) |
494 | return VM_FAULT_BADACCESS; | |
6a1bb025 | 495 | return handle_mm_fault(vma, addr & PAGE_MASK, mm_flags, regs); |
1d18c47c CM |
496 | } |
497 | ||
541ec870 MR |
498 | static bool is_el0_instruction_abort(unsigned int esr) |
499 | { | |
500 | return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; | |
501 | } | |
502 | ||
c49bd02f AK |
503 | /* |
504 | * Note: not valid for EL1 DC IVAC, but we never use that such that it | |
505 | * should fault. EL0 cannot issue DC IVAC (undef). | |
506 | */ | |
507 | static bool is_write_abort(unsigned int esr) | |
508 | { | |
509 | return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM); | |
510 | } | |
511 | ||
dceec3ff | 512 | static int __kprobes do_page_fault(unsigned long far, unsigned int esr, |
1d18c47c CM |
513 | struct pt_regs *regs) |
514 | { | |
2d2837fa | 515 | const struct fault_info *inf; |
61681036 | 516 | struct mm_struct *mm = current->mm; |
6a1bb025 | 517 | vm_fault_t fault; |
6cb4d9a2 | 518 | unsigned long vm_flags = VM_ACCESS_FLAGS; |
dde16072 | 519 | unsigned int mm_flags = FAULT_FLAG_DEFAULT; |
dceec3ff | 520 | unsigned long addr = untagged_addr(far); |
db6f4106 | 521 | |
b98cca44 | 522 | if (kprobe_page_fault(regs, esr)) |
2dd0e8d2 SP |
523 | return 0; |
524 | ||
1d18c47c CM |
525 | /* |
526 | * If we're in an interrupt or have no user context, we must not take | |
527 | * the fault. | |
528 | */ | |
70ffdb93 | 529 | if (faulthandler_disabled() || !mm) |
1d18c47c CM |
530 | goto no_context; |
531 | ||
759496ba JW |
532 | if (user_mode(regs)) |
533 | mm_flags |= FAULT_FLAG_USER; | |
534 | ||
541ec870 | 535 | if (is_el0_instruction_abort(esr)) { |
759496ba | 536 | vm_flags = VM_EXEC; |
01de1776 | 537 | mm_flags |= FAULT_FLAG_INSTRUCTION; |
c49bd02f | 538 | } else if (is_write_abort(esr)) { |
759496ba JW |
539 | vm_flags = VM_WRITE; |
540 | mm_flags |= FAULT_FLAG_WRITE; | |
541 | } | |
542 | ||
356607f2 | 543 | if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) { |
9adeb8e7 | 544 | if (is_el1_instruction_abort(esr)) |
c870f14e MR |
545 | die_kernel_fault("execution of user memory", |
546 | addr, esr, regs); | |
9adeb8e7 | 547 | |
57f4959b | 548 | if (!search_exception_tables(regs->pc)) |
c870f14e MR |
549 | die_kernel_fault("access to user memory outside uaccess routines", |
550 | addr, esr, regs); | |
57f4959b | 551 | } |
338d4f49 | 552 | |
0e3a9026 PA |
553 | perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); |
554 | ||
1d18c47c CM |
555 | /* |
556 | * As per x86, we may deadlock here. However, since the kernel only | |
557 | * validly references user space from well defined areas of the code, | |
558 | * we can bug out early if this is from code which shouldn't. | |
559 | */ | |
d8ed45c5 | 560 | if (!mmap_read_trylock(mm)) { |
1d18c47c CM |
561 | if (!user_mode(regs) && !search_exception_tables(regs->pc)) |
562 | goto no_context; | |
563 | retry: | |
d8ed45c5 | 564 | mmap_read_lock(mm); |
1d18c47c CM |
565 | } else { |
566 | /* | |
567 | * The above down_read_trylock() might have succeeded in which | |
568 | * case, we'll have missed the might_sleep() from down_read(). | |
569 | */ | |
570 | might_sleep(); | |
571 | #ifdef CONFIG_DEBUG_VM | |
a0509313 | 572 | if (!user_mode(regs) && !search_exception_tables(regs->pc)) { |
d8ed45c5 | 573 | mmap_read_unlock(mm); |
1d18c47c | 574 | goto no_context; |
a0509313 | 575 | } |
1d18c47c CM |
576 | #endif |
577 | } | |
578 | ||
6a1bb025 | 579 | fault = __do_page_fault(mm, addr, mm_flags, vm_flags, regs); |
1d18c47c | 580 | |
b502f038 PX |
581 | /* Quick path to respond to signals */ |
582 | if (fault_signal_pending(fault, regs)) { | |
583 | if (!user_mode(regs)) | |
584 | goto no_context; | |
585 | return 0; | |
586 | } | |
0e3a9026 | 587 | |
b502f038 | 588 | if (fault & VM_FAULT_RETRY) { |
0e3a9026 | 589 | if (mm_flags & FAULT_FLAG_ALLOW_RETRY) { |
0e3a9026 PA |
590 | mm_flags |= FAULT_FLAG_TRIED; |
591 | goto retry; | |
592 | } | |
593 | } | |
d8ed45c5 | 594 | mmap_read_unlock(mm); |
1d18c47c CM |
595 | |
596 | /* | |
0e3a9026 | 597 | * Handle the "normal" (no error) case first. |
1d18c47c | 598 | */ |
0e3a9026 | 599 | if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP | |
6a1bb025 | 600 | VM_FAULT_BADACCESS)))) |
1d18c47c CM |
601 | return 0; |
602 | ||
87134102 JW |
603 | /* |
604 | * If we are in kernel mode at this point, we have no context to | |
605 | * handle this fault with. | |
606 | */ | |
607 | if (!user_mode(regs)) | |
608 | goto no_context; | |
609 | ||
1d18c47c CM |
610 | if (fault & VM_FAULT_OOM) { |
611 | /* | |
612 | * We ran out of memory, call the OOM killer, and return to | |
613 | * userspace (which will retry the fault, or kill us if we got | |
614 | * oom-killed). | |
615 | */ | |
616 | pagefault_out_of_memory(); | |
617 | return 0; | |
618 | } | |
619 | ||
2d2837fa | 620 | inf = esr_to_fault_info(esr); |
559d8d91 | 621 | set_thread_esr(addr, esr); |
1d18c47c CM |
622 | if (fault & VM_FAULT_SIGBUS) { |
623 | /* | |
624 | * We had some memory, but were unable to successfully fix up | |
625 | * this page fault. | |
626 | */ | |
dceec3ff | 627 | arm64_force_sig_fault(SIGBUS, BUS_ADRERR, far, inf->name); |
9ea3a974 EB |
628 | } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) { |
629 | unsigned int lsb; | |
630 | ||
631 | lsb = PAGE_SHIFT; | |
632 | if (fault & VM_FAULT_HWPOISON_LARGE) | |
633 | lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); | |
92ff0674 | 634 | |
dceec3ff | 635 | arm64_force_sig_mceerr(BUS_MCEERR_AR, far, lsb, inf->name); |
1d18c47c CM |
636 | } else { |
637 | /* | |
638 | * Something tried to access memory that isn't in our memory | |
639 | * map. | |
640 | */ | |
feca355b EB |
641 | arm64_force_sig_fault(SIGSEGV, |
642 | fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR, | |
dceec3ff | 643 | far, inf->name); |
1d18c47c CM |
644 | } |
645 | ||
1d18c47c CM |
646 | return 0; |
647 | ||
648 | no_context: | |
67ce16ec | 649 | __do_kernel_fault(addr, esr, regs); |
1d18c47c CM |
650 | return 0; |
651 | } | |
652 | ||
dceec3ff | 653 | static int __kprobes do_translation_fault(unsigned long far, |
1d18c47c CM |
654 | unsigned int esr, |
655 | struct pt_regs *regs) | |
656 | { | |
dceec3ff PC |
657 | unsigned long addr = untagged_addr(far); |
658 | ||
356607f2 | 659 | if (is_ttbr0_addr(addr)) |
dceec3ff | 660 | return do_page_fault(far, esr, regs); |
1d18c47c | 661 | |
dceec3ff | 662 | do_bad_area(far, esr, regs); |
1d18c47c CM |
663 | return 0; |
664 | } | |
665 | ||
dceec3ff | 666 | static int do_alignment_fault(unsigned long far, unsigned int esr, |
52d7523d EL |
667 | struct pt_regs *regs) |
668 | { | |
dceec3ff | 669 | do_bad_area(far, esr, regs); |
52d7523d EL |
670 | return 0; |
671 | } | |
672 | ||
dceec3ff | 673 | static int do_bad(unsigned long far, unsigned int esr, struct pt_regs *regs) |
1d18c47c | 674 | { |
f67d5c4f | 675 | return 1; /* "fault" */ |
1d18c47c CM |
676 | } |
677 | ||
dceec3ff | 678 | static int do_sea(unsigned long far, unsigned int esr, struct pt_regs *regs) |
32015c23 | 679 | { |
32015c23 | 680 | const struct fault_info *inf; |
dceec3ff | 681 | unsigned long siaddr; |
32015c23 TB |
682 | |
683 | inf = esr_to_fault_info(esr); | |
32015c23 | 684 | |
8fcc4ae6 JM |
685 | if (user_mode(regs) && apei_claim_sea(regs) == 0) { |
686 | /* | |
687 | * APEI claimed this as a firmware-first notification. | |
688 | * Some processing deferred to task_work before ret_to_user(). | |
689 | */ | |
690 | return 0; | |
691 | } | |
7edda088 | 692 | |
dceec3ff PC |
693 | if (esr & ESR_ELx_FnV) { |
694 | siaddr = 0; | |
695 | } else { | |
696 | /* | |
697 | * The architecture specifies that the tag bits of FAR_EL1 are | |
698 | * UNKNOWN for synchronous external aborts. Mask them out now | |
699 | * so that userspace doesn't see them. | |
700 | */ | |
701 | siaddr = untagged_addr(far); | |
702 | } | |
6fa998e8 | 703 | arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr); |
32015c23 | 704 | |
faa75e14 | 705 | return 0; |
32015c23 TB |
706 | } |
707 | ||
dceec3ff | 708 | static int do_tag_check_fault(unsigned long far, unsigned int esr, |
637ec831 VF |
709 | struct pt_regs *regs) |
710 | { | |
dceec3ff PC |
711 | /* |
712 | * The architecture specifies that bits 63:60 of FAR_EL1 are UNKNOWN for tag | |
713 | * check faults. Mask them out now so that userspace doesn't see them. | |
714 | */ | |
715 | far &= (1UL << 60) - 1; | |
716 | do_bad_area(far, esr, regs); | |
637ec831 VF |
717 | return 0; |
718 | } | |
719 | ||
09a6adf5 | 720 | static const struct fault_info fault_info[] = { |
af40ff68 DM |
721 | { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" }, |
722 | { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" }, | |
723 | { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" }, | |
724 | { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" }, | |
7f73f7ae | 725 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" }, |
1d18c47c CM |
726 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" }, |
727 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" }, | |
760bfb47 | 728 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" }, |
af40ff68 | 729 | { do_bad, SIGKILL, SI_KERNEL, "unknown 8" }, |
084bd298 SC |
730 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" }, |
731 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" }, | |
1d18c47c | 732 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" }, |
af40ff68 | 733 | { do_bad, SIGKILL, SI_KERNEL, "unknown 12" }, |
084bd298 SC |
734 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, |
735 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, | |
1d18c47c | 736 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, |
af40ff68 | 737 | { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" }, |
637ec831 | 738 | { do_tag_check_fault, SIGSEGV, SEGV_MTESERR, "synchronous tag check fault" }, |
af40ff68 DM |
739 | { do_bad, SIGKILL, SI_KERNEL, "unknown 18" }, |
740 | { do_bad, SIGKILL, SI_KERNEL, "unknown 19" }, | |
741 | { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" }, | |
742 | { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" }, | |
743 | { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" }, | |
744 | { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" }, | |
745 | { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented | |
746 | { do_bad, SIGKILL, SI_KERNEL, "unknown 25" }, | |
747 | { do_bad, SIGKILL, SI_KERNEL, "unknown 26" }, | |
748 | { do_bad, SIGKILL, SI_KERNEL, "unknown 27" }, | |
749 | { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented | |
750 | { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented | |
751 | { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented | |
752 | { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented | |
753 | { do_bad, SIGKILL, SI_KERNEL, "unknown 32" }, | |
52d7523d | 754 | { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, |
af40ff68 DM |
755 | { do_bad, SIGKILL, SI_KERNEL, "unknown 34" }, |
756 | { do_bad, SIGKILL, SI_KERNEL, "unknown 35" }, | |
757 | { do_bad, SIGKILL, SI_KERNEL, "unknown 36" }, | |
758 | { do_bad, SIGKILL, SI_KERNEL, "unknown 37" }, | |
759 | { do_bad, SIGKILL, SI_KERNEL, "unknown 38" }, | |
760 | { do_bad, SIGKILL, SI_KERNEL, "unknown 39" }, | |
761 | { do_bad, SIGKILL, SI_KERNEL, "unknown 40" }, | |
762 | { do_bad, SIGKILL, SI_KERNEL, "unknown 41" }, | |
763 | { do_bad, SIGKILL, SI_KERNEL, "unknown 42" }, | |
764 | { do_bad, SIGKILL, SI_KERNEL, "unknown 43" }, | |
765 | { do_bad, SIGKILL, SI_KERNEL, "unknown 44" }, | |
766 | { do_bad, SIGKILL, SI_KERNEL, "unknown 45" }, | |
767 | { do_bad, SIGKILL, SI_KERNEL, "unknown 46" }, | |
768 | { do_bad, SIGKILL, SI_KERNEL, "unknown 47" }, | |
769 | { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" }, | |
770 | { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" }, | |
771 | { do_bad, SIGKILL, SI_KERNEL, "unknown 50" }, | |
772 | { do_bad, SIGKILL, SI_KERNEL, "unknown 51" }, | |
773 | { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" }, | |
774 | { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" }, | |
775 | { do_bad, SIGKILL, SI_KERNEL, "unknown 54" }, | |
776 | { do_bad, SIGKILL, SI_KERNEL, "unknown 55" }, | |
777 | { do_bad, SIGKILL, SI_KERNEL, "unknown 56" }, | |
778 | { do_bad, SIGKILL, SI_KERNEL, "unknown 57" }, | |
779 | { do_bad, SIGKILL, SI_KERNEL, "unknown 58" }, | |
780 | { do_bad, SIGKILL, SI_KERNEL, "unknown 59" }, | |
781 | { do_bad, SIGKILL, SI_KERNEL, "unknown 60" }, | |
782 | { do_bad, SIGKILL, SI_KERNEL, "section domain fault" }, | |
783 | { do_bad, SIGKILL, SI_KERNEL, "page domain fault" }, | |
784 | { do_bad, SIGKILL, SI_KERNEL, "unknown 63" }, | |
1d18c47c CM |
785 | }; |
786 | ||
dceec3ff | 787 | void do_mem_abort(unsigned long far, unsigned int esr, struct pt_regs *regs) |
1d18c47c | 788 | { |
09a6adf5 | 789 | const struct fault_info *inf = esr_to_fault_info(esr); |
dceec3ff | 790 | unsigned long addr = untagged_addr(far); |
1d18c47c | 791 | |
dceec3ff | 792 | if (!inf->fn(far, esr, regs)) |
1d18c47c CM |
793 | return; |
794 | ||
1049c308 WD |
795 | if (!user_mode(regs)) { |
796 | pr_alert("Unhandled fault at 0x%016lx\n", addr); | |
797 | mem_abort_decode(esr); | |
80b6eb04 | 798 | show_pte(addr); |
1049c308 | 799 | } |
42dbf54e | 800 | |
dceec3ff PC |
801 | /* |
802 | * At this point we have an unrecognized fault type whose tag bits may | |
803 | * have been defined as UNKNOWN. Therefore we only expose the untagged | |
804 | * address to the signal handler. | |
805 | */ | |
806 | arm64_notify_die(inf->name, regs, inf->sig, inf->code, addr, esr); | |
1d18c47c | 807 | } |
b6e43c0e | 808 | NOKPROBE_SYMBOL(do_mem_abort); |
1d18c47c | 809 | |
afa7c0e5 | 810 | void do_el0_irq_bp_hardening(void) |
30d88c0e WD |
811 | { |
812 | /* PC has already been checked in entry.S */ | |
813 | arm64_apply_bp_hardening(); | |
814 | } | |
b6e43c0e | 815 | NOKPROBE_SYMBOL(do_el0_irq_bp_hardening); |
30d88c0e | 816 | |
afa7c0e5 | 817 | void do_sp_pc_abort(unsigned long addr, unsigned int esr, struct pt_regs *regs) |
1d18c47c | 818 | { |
dceec3ff PC |
819 | arm64_notify_die("SP/PC alignment exception", regs, SIGBUS, BUS_ADRALN, |
820 | addr, esr); | |
1d18c47c | 821 | } |
b6e43c0e | 822 | NOKPROBE_SYMBOL(do_sp_pc_abort); |
1d18c47c | 823 | |
9fb7410f DM |
824 | int __init early_brk64(unsigned long addr, unsigned int esr, |
825 | struct pt_regs *regs); | |
826 | ||
827 | /* | |
828 | * __refdata because early_brk64 is __init, but the reference to it is | |
829 | * clobbered at arch_initcall time. | |
830 | * See traps.c and debug-monitors.c:debug_traps_init(). | |
831 | */ | |
832 | static struct fault_info __refdata debug_fault_info[] = { | |
1d18c47c CM |
833 | { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" }, |
834 | { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" }, | |
835 | { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" }, | |
af40ff68 | 836 | { do_bad, SIGKILL, SI_KERNEL, "unknown 3" }, |
1d18c47c | 837 | { do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" }, |
af40ff68 | 838 | { do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" }, |
9fb7410f | 839 | { early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" }, |
af40ff68 | 840 | { do_bad, SIGKILL, SI_KERNEL, "unknown 7" }, |
1d18c47c CM |
841 | }; |
842 | ||
843 | void __init hook_debug_fault_code(int nr, | |
844 | int (*fn)(unsigned long, unsigned int, struct pt_regs *), | |
845 | int sig, int code, const char *name) | |
846 | { | |
847 | BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info)); | |
848 | ||
849 | debug_fault_info[nr].fn = fn; | |
850 | debug_fault_info[nr].sig = sig; | |
851 | debug_fault_info[nr].code = code; | |
852 | debug_fault_info[nr].name = name; | |
853 | } | |
854 | ||
d8bb6718 MH |
855 | /* |
856 | * In debug exception context, we explicitly disable preemption despite | |
857 | * having interrupts disabled. | |
858 | * This serves two purposes: it makes it much less likely that we would | |
859 | * accidentally schedule in exception context and it will force a warning | |
860 | * if we somehow manage to schedule by accident. | |
861 | */ | |
862 | static void debug_exception_enter(struct pt_regs *regs) | |
863 | { | |
d8bb6718 MH |
864 | preempt_disable(); |
865 | ||
866 | /* This code is a bit fragile. Test it. */ | |
867 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "exception_enter didn't work"); | |
868 | } | |
869 | NOKPROBE_SYMBOL(debug_exception_enter); | |
870 | ||
871 | static void debug_exception_exit(struct pt_regs *regs) | |
872 | { | |
873 | preempt_enable_no_resched(); | |
d8bb6718 MH |
874 | } |
875 | NOKPROBE_SYMBOL(debug_exception_exit); | |
876 | ||
969f5ea6 WD |
877 | #ifdef CONFIG_ARM64_ERRATUM_1463225 |
878 | DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); | |
879 | ||
b6e43c0e | 880 | static int cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) |
969f5ea6 WD |
881 | { |
882 | if (user_mode(regs)) | |
883 | return 0; | |
884 | ||
885 | if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa)) | |
886 | return 0; | |
887 | ||
888 | /* | |
889 | * We've taken a dummy step exception from the kernel to ensure | |
890 | * that interrupts are re-enabled on the syscall path. Return back | |
891 | * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions | |
892 | * masked so that we can safely restore the mdscr and get on with | |
893 | * handling the syscall. | |
894 | */ | |
895 | regs->pstate |= PSR_D_BIT; | |
896 | return 1; | |
897 | } | |
898 | #else | |
b6e43c0e | 899 | static int cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) |
969f5ea6 WD |
900 | { |
901 | return 0; | |
902 | } | |
903 | #endif /* CONFIG_ARM64_ERRATUM_1463225 */ | |
b6e43c0e | 904 | NOKPROBE_SYMBOL(cortex_a76_erratum_1463225_debug_handler); |
969f5ea6 | 905 | |
afa7c0e5 JM |
906 | void do_debug_exception(unsigned long addr_if_watchpoint, unsigned int esr, |
907 | struct pt_regs *regs) | |
1d18c47c | 908 | { |
359048f9 | 909 | const struct fault_info *inf = esr_to_debug_fault_info(esr); |
b9a4b9d0 | 910 | unsigned long pc = instruction_pointer(regs); |
1d18c47c | 911 | |
969f5ea6 WD |
912 | if (cortex_a76_erratum_1463225_debug_handler(regs)) |
913 | return; | |
914 | ||
d8bb6718 | 915 | debug_exception_enter(regs); |
1d18c47c | 916 | |
b9a4b9d0 | 917 | if (user_mode(regs) && !is_ttbr0_addr(pc)) |
5dfc6ed2 WD |
918 | arm64_apply_bp_hardening(); |
919 | ||
52c6d145 | 920 | if (inf->fn(addr_if_watchpoint, esr, regs)) { |
dceec3ff | 921 | arm64_notify_die(inf->name, regs, inf->sig, inf->code, pc, esr); |
6afedcd2 | 922 | } |
1d18c47c | 923 | |
d8bb6718 | 924 | debug_exception_exit(regs); |
1d18c47c | 925 | } |
2dd0e8d2 | 926 | NOKPROBE_SYMBOL(do_debug_exception); |