Commit | Line | Data |
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1d18c47c CM |
1 | /* |
2 | * Based on arch/arm/mm/fault.c | |
3 | * | |
4 | * Copyright (C) 1995 Linus Torvalds | |
5 | * Copyright (C) 1995-2004 Russell King | |
6 | * Copyright (C) 2012 ARM Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
0edfa839 | 21 | #include <linux/extable.h> |
1d18c47c CM |
22 | #include <linux/signal.h> |
23 | #include <linux/mm.h> | |
24 | #include <linux/hardirq.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/kprobes.h> | |
27 | #include <linux/uaccess.h> | |
28 | #include <linux/page-flags.h> | |
3f07c014 | 29 | #include <linux/sched/signal.h> |
b17b0153 | 30 | #include <linux/sched/debug.h> |
1d18c47c CM |
31 | #include <linux/highmem.h> |
32 | #include <linux/perf_event.h> | |
7209c868 | 33 | #include <linux/preempt.h> |
e7c600f1 | 34 | #include <linux/hugetlb.h> |
1d18c47c | 35 | |
7209c868 | 36 | #include <asm/bug.h> |
3bbf7157 | 37 | #include <asm/cmpxchg.h> |
338d4f49 | 38 | #include <asm/cpufeature.h> |
1d18c47c CM |
39 | #include <asm/exception.h> |
40 | #include <asm/debug-monitors.h> | |
9141300a | 41 | #include <asm/esr.h> |
338d4f49 | 42 | #include <asm/sysreg.h> |
1d18c47c CM |
43 | #include <asm/system_misc.h> |
44 | #include <asm/pgtable.h> | |
45 | #include <asm/tlbflush.h> | |
92ff0674 | 46 | #include <asm/traps.h> |
1d18c47c | 47 | |
7edda088 TB |
48 | #include <acpi/ghes.h> |
49 | ||
09a6adf5 VK |
50 | struct fault_info { |
51 | int (*fn)(unsigned long addr, unsigned int esr, | |
52 | struct pt_regs *regs); | |
53 | int sig; | |
54 | int code; | |
55 | const char *name; | |
56 | }; | |
57 | ||
58 | static const struct fault_info fault_info[]; | |
59 | ||
60 | static inline const struct fault_info *esr_to_fault_info(unsigned int esr) | |
61 | { | |
62 | return fault_info + (esr & 63); | |
63 | } | |
3495386b | 64 | |
2dd0e8d2 SP |
65 | #ifdef CONFIG_KPROBES |
66 | static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) | |
67 | { | |
68 | int ret = 0; | |
69 | ||
70 | /* kprobe_running() needs smp_processor_id() */ | |
71 | if (!user_mode(regs)) { | |
72 | preempt_disable(); | |
73 | if (kprobe_running() && kprobe_fault_handler(regs, esr)) | |
74 | ret = 1; | |
75 | preempt_enable(); | |
76 | } | |
77 | ||
78 | return ret; | |
79 | } | |
80 | #else | |
81 | static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) | |
82 | { | |
83 | return 0; | |
84 | } | |
85 | #endif | |
86 | ||
1f9b8936 JT |
87 | static void data_abort_decode(unsigned int esr) |
88 | { | |
89 | pr_alert("Data abort info:\n"); | |
90 | ||
91 | if (esr & ESR_ELx_ISV) { | |
92 | pr_alert(" Access size = %u byte(s)\n", | |
93 | 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT)); | |
94 | pr_alert(" SSE = %lu, SRT = %lu\n", | |
95 | (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT, | |
96 | (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT); | |
97 | pr_alert(" SF = %lu, AR = %lu\n", | |
98 | (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT, | |
99 | (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT); | |
100 | } else { | |
0a6de8b8 | 101 | pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK); |
1f9b8936 JT |
102 | } |
103 | ||
104 | pr_alert(" CM = %lu, WnR = %lu\n", | |
105 | (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT, | |
106 | (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT); | |
107 | } | |
108 | ||
1f9b8936 JT |
109 | static void mem_abort_decode(unsigned int esr) |
110 | { | |
111 | pr_alert("Mem abort info:\n"); | |
112 | ||
42dbf54e | 113 | pr_alert(" ESR = 0x%08x\n", esr); |
1f9b8936 JT |
114 | pr_alert(" Exception class = %s, IL = %u bits\n", |
115 | esr_get_class_string(esr), | |
116 | (esr & ESR_ELx_IL) ? 32 : 16); | |
117 | pr_alert(" SET = %lu, FnV = %lu\n", | |
118 | (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT, | |
119 | (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT); | |
120 | pr_alert(" EA = %lu, S1PTW = %lu\n", | |
121 | (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT, | |
122 | (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT); | |
123 | ||
124 | if (esr_is_data_abort(esr)) | |
125 | data_abort_decode(esr); | |
126 | } | |
127 | ||
1d18c47c | 128 | /* |
67ce16ec | 129 | * Dump out the page tables associated with 'addr' in the currently active mm. |
1d18c47c | 130 | */ |
67ce16ec | 131 | void show_pte(unsigned long addr) |
1d18c47c | 132 | { |
67ce16ec | 133 | struct mm_struct *mm; |
20a004e7 WD |
134 | pgd_t *pgdp; |
135 | pgd_t pgd; | |
1d18c47c | 136 | |
67ce16ec KM |
137 | if (addr < TASK_SIZE) { |
138 | /* TTBR0 */ | |
139 | mm = current->active_mm; | |
140 | if (mm == &init_mm) { | |
141 | pr_alert("[%016lx] user address but active_mm is swapper\n", | |
142 | addr); | |
143 | return; | |
144 | } | |
145 | } else if (addr >= VA_START) { | |
146 | /* TTBR1 */ | |
1d18c47c | 147 | mm = &init_mm; |
67ce16ec KM |
148 | } else { |
149 | pr_alert("[%016lx] address between user and kernel address ranges\n", | |
150 | addr); | |
151 | return; | |
152 | } | |
1d18c47c | 153 | |
20a004e7 | 154 | pr_alert("%s pgtable: %luk pages, %u-bit VAs, pgdp = %p\n", |
1eb34b6e WD |
155 | mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K, |
156 | VA_BITS, mm->pgd); | |
20a004e7 WD |
157 | pgdp = pgd_offset(mm, addr); |
158 | pgd = READ_ONCE(*pgdp); | |
159 | pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd)); | |
1d18c47c CM |
160 | |
161 | do { | |
20a004e7 WD |
162 | pud_t *pudp, pud; |
163 | pmd_t *pmdp, pmd; | |
164 | pte_t *ptep, pte; | |
1d18c47c | 165 | |
20a004e7 | 166 | if (pgd_none(pgd) || pgd_bad(pgd)) |
1d18c47c CM |
167 | break; |
168 | ||
20a004e7 WD |
169 | pudp = pud_offset(pgdp, addr); |
170 | pud = READ_ONCE(*pudp); | |
171 | pr_cont(", pud=%016llx", pud_val(pud)); | |
172 | if (pud_none(pud) || pud_bad(pud)) | |
1d18c47c CM |
173 | break; |
174 | ||
20a004e7 WD |
175 | pmdp = pmd_offset(pudp, addr); |
176 | pmd = READ_ONCE(*pmdp); | |
177 | pr_cont(", pmd=%016llx", pmd_val(pmd)); | |
178 | if (pmd_none(pmd) || pmd_bad(pmd)) | |
1d18c47c CM |
179 | break; |
180 | ||
20a004e7 WD |
181 | ptep = pte_offset_map(pmdp, addr); |
182 | pte = READ_ONCE(*ptep); | |
183 | pr_cont(", pte=%016llx", pte_val(pte)); | |
184 | pte_unmap(ptep); | |
1d18c47c CM |
185 | } while(0); |
186 | ||
6ef4fb38 | 187 | pr_cont("\n"); |
1d18c47c CM |
188 | } |
189 | ||
66dbd6e6 CM |
190 | /* |
191 | * This function sets the access flags (dirty, accessed), as well as write | |
192 | * permission, and only to a more permissive setting. | |
193 | * | |
194 | * It needs to cope with hardware update of the accessed/dirty state by other | |
195 | * agents in the system and can safely skip the __sync_icache_dcache() call as, | |
196 | * like set_pte_at(), the PTE is never changed from no-exec to exec here. | |
197 | * | |
198 | * Returns whether or not the PTE actually changed. | |
199 | */ | |
200 | int ptep_set_access_flags(struct vm_area_struct *vma, | |
201 | unsigned long address, pte_t *ptep, | |
202 | pte_t entry, int dirty) | |
203 | { | |
3bbf7157 | 204 | pteval_t old_pteval, pteval; |
20a004e7 | 205 | pte_t pte = READ_ONCE(*ptep); |
66dbd6e6 | 206 | |
20a004e7 | 207 | if (pte_same(pte, entry)) |
66dbd6e6 CM |
208 | return 0; |
209 | ||
210 | /* only preserve the access flags and write permission */ | |
73e86cb0 | 211 | pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY; |
66dbd6e6 CM |
212 | |
213 | /* | |
214 | * Setting the flags must be done atomically to avoid racing with the | |
6d332747 CM |
215 | * hardware update of the access/dirty state. The PTE_RDONLY bit must |
216 | * be set to the most permissive (lowest value) of *ptep and entry | |
217 | * (calculated as: a & b == ~(~a | ~b)). | |
66dbd6e6 | 218 | */ |
6d332747 | 219 | pte_val(entry) ^= PTE_RDONLY; |
20a004e7 | 220 | pteval = pte_val(pte); |
3bbf7157 CM |
221 | do { |
222 | old_pteval = pteval; | |
223 | pteval ^= PTE_RDONLY; | |
224 | pteval |= pte_val(entry); | |
225 | pteval ^= PTE_RDONLY; | |
226 | pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval); | |
227 | } while (pteval != old_pteval); | |
66dbd6e6 CM |
228 | |
229 | flush_tlb_fix_spurious_fault(vma, address); | |
230 | return 1; | |
231 | } | |
66dbd6e6 | 232 | |
9adeb8e7 LA |
233 | static bool is_el1_instruction_abort(unsigned int esr) |
234 | { | |
235 | return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; | |
236 | } | |
237 | ||
969e61ba MR |
238 | static inline bool is_el1_permission_fault(unsigned int esr, |
239 | struct pt_regs *regs, | |
240 | unsigned long addr) | |
b824b930 SB |
241 | { |
242 | unsigned int ec = ESR_ELx_EC(esr); | |
243 | unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE; | |
244 | ||
245 | if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR) | |
246 | return false; | |
247 | ||
248 | if (fsc_type == ESR_ELx_FSC_PERM) | |
249 | return true; | |
250 | ||
51369e39 | 251 | if (addr < TASK_SIZE && system_uses_ttbr0_pan()) |
b824b930 SB |
252 | return fsc_type == ESR_ELx_FSC_FAULT && |
253 | (regs->pstate & PSR_PAN_BIT); | |
254 | ||
255 | return false; | |
256 | } | |
257 | ||
c870f14e MR |
258 | static void die_kernel_fault(const char *msg, unsigned long addr, |
259 | unsigned int esr, struct pt_regs *regs) | |
260 | { | |
261 | bust_spinlocks(1); | |
262 | ||
263 | pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg, | |
264 | addr); | |
265 | ||
266 | mem_abort_decode(esr); | |
267 | ||
268 | show_pte(addr); | |
269 | die("Oops", regs, esr); | |
270 | bust_spinlocks(0); | |
271 | do_exit(SIGKILL); | |
272 | } | |
273 | ||
67ce16ec KM |
274 | static void __do_kernel_fault(unsigned long addr, unsigned int esr, |
275 | struct pt_regs *regs) | |
1d18c47c | 276 | { |
b824b930 SB |
277 | const char *msg; |
278 | ||
1d18c47c CM |
279 | /* |
280 | * Are we prepared to handle this kernel fault? | |
9adeb8e7 | 281 | * We are almost certainly not prepared to handle instruction faults. |
1d18c47c | 282 | */ |
9adeb8e7 | 283 | if (!is_el1_instruction_abort(esr) && fixup_exception(regs)) |
1d18c47c CM |
284 | return; |
285 | ||
969e61ba | 286 | if (is_el1_permission_fault(esr, regs, addr)) { |
b824b930 SB |
287 | if (esr & ESR_ELx_WNR) |
288 | msg = "write to read-only memory"; | |
289 | else | |
290 | msg = "read from unreadable memory"; | |
291 | } else if (addr < PAGE_SIZE) { | |
292 | msg = "NULL pointer dereference"; | |
293 | } else { | |
294 | msg = "paging request"; | |
295 | } | |
296 | ||
c870f14e | 297 | die_kernel_fault(msg, addr, esr, regs); |
1d18c47c CM |
298 | } |
299 | ||
f29ad209 | 300 | static void set_thread_esr(unsigned long address, unsigned int esr) |
1d18c47c | 301 | { |
f29ad209 | 302 | current->thread.fault_address = address; |
cc198460 PM |
303 | |
304 | /* | |
305 | * If the faulting address is in the kernel, we must sanitize the ESR. | |
306 | * From userspace's point of view, kernel-only mappings don't exist | |
307 | * at all, so we report them as level 0 translation faults. | |
308 | * (This is not quite the way that "no mapping there at all" behaves: | |
309 | * an alignment fault not caused by the memory type would take | |
310 | * precedence over translation fault for a real access to empty | |
311 | * space. Unfortunately we can't easily distinguish "alignment fault | |
312 | * not caused by memory type" from "alignment fault caused by memory | |
313 | * type", so we ignore this wrinkle and just return the translation | |
314 | * fault.) | |
315 | */ | |
316 | if (current->thread.fault_address >= TASK_SIZE) { | |
317 | switch (ESR_ELx_EC(esr)) { | |
318 | case ESR_ELx_EC_DABT_LOW: | |
319 | /* | |
320 | * These bits provide only information about the | |
321 | * faulting instruction, which userspace knows already. | |
322 | * We explicitly clear bits which are architecturally | |
323 | * RES0 in case they are given meanings in future. | |
324 | * We always report the ESR as if the fault was taken | |
325 | * to EL1 and so ISV and the bits in ISS[23:14] are | |
326 | * clear. (In fact it always will be a fault to EL1.) | |
327 | */ | |
328 | esr &= ESR_ELx_EC_MASK | ESR_ELx_IL | | |
329 | ESR_ELx_CM | ESR_ELx_WNR; | |
330 | esr |= ESR_ELx_FSC_FAULT; | |
331 | break; | |
332 | case ESR_ELx_EC_IABT_LOW: | |
333 | /* | |
334 | * Claim a level 0 translation fault. | |
335 | * All other bits are architecturally RES0 for faults | |
336 | * reported with that DFSC value, so we clear them. | |
337 | */ | |
338 | esr &= ESR_ELx_EC_MASK | ESR_ELx_IL; | |
339 | esr |= ESR_ELx_FSC_FAULT; | |
340 | break; | |
341 | default: | |
342 | /* | |
343 | * This should never happen (entry.S only brings us | |
344 | * into this code for insn and data aborts from a lower | |
345 | * exception level). Fail safe by not providing an ESR | |
346 | * context record at all. | |
347 | */ | |
348 | WARN(1, "ESR 0x%x is not DABT or IABT from EL0\n", esr); | |
349 | esr = 0; | |
350 | break; | |
351 | } | |
352 | } | |
353 | ||
92ff0674 | 354 | current->thread.fault_code = esr; |
f29ad209 EB |
355 | } |
356 | ||
59f67e16 | 357 | static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs) |
1d18c47c | 358 | { |
1d18c47c CM |
359 | /* |
360 | * If we are in kernel mode at this point, we have no context to | |
361 | * handle this fault with. | |
362 | */ | |
09a6adf5 | 363 | if (user_mode(regs)) { |
92ff0674 | 364 | const struct fault_info *inf = esr_to_fault_info(esr); |
3eb0f519 EB |
365 | struct siginfo si; |
366 | ||
367 | clear_siginfo(&si); | |
368 | si.si_signo = inf->sig; | |
369 | si.si_code = inf->code; | |
370 | si.si_addr = (void __user *)addr; | |
92ff0674 | 371 | |
effb093a EB |
372 | set_thread_esr(addr, esr); |
373 | arm64_force_sig_info(&si, inf->name); | |
92ff0674 | 374 | } else { |
67ce16ec | 375 | __do_kernel_fault(addr, esr, regs); |
92ff0674 | 376 | } |
1d18c47c CM |
377 | } |
378 | ||
379 | #define VM_FAULT_BADMAP 0x010000 | |
380 | #define VM_FAULT_BADACCESS 0x020000 | |
381 | ||
50a7ca3c | 382 | static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr, |
db6f4106 | 383 | unsigned int mm_flags, unsigned long vm_flags, |
1d18c47c CM |
384 | struct task_struct *tsk) |
385 | { | |
386 | struct vm_area_struct *vma; | |
50a7ca3c | 387 | vm_fault_t fault; |
1d18c47c CM |
388 | |
389 | vma = find_vma(mm, addr); | |
390 | fault = VM_FAULT_BADMAP; | |
391 | if (unlikely(!vma)) | |
392 | goto out; | |
393 | if (unlikely(vma->vm_start > addr)) | |
394 | goto check_stack; | |
395 | ||
396 | /* | |
397 | * Ok, we have a good vm_area for this memory access, so we can handle | |
398 | * it. | |
399 | */ | |
400 | good_area: | |
db6f4106 WD |
401 | /* |
402 | * Check that the permissions on the VMA allow for the fault which | |
cab15ce6 | 403 | * occurred. |
db6f4106 WD |
404 | */ |
405 | if (!(vma->vm_flags & vm_flags)) { | |
1d18c47c CM |
406 | fault = VM_FAULT_BADACCESS; |
407 | goto out; | |
408 | } | |
409 | ||
dcddffd4 | 410 | return handle_mm_fault(vma, addr & PAGE_MASK, mm_flags); |
1d18c47c CM |
411 | |
412 | check_stack: | |
413 | if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr)) | |
414 | goto good_area; | |
415 | out: | |
416 | return fault; | |
417 | } | |
418 | ||
541ec870 MR |
419 | static bool is_el0_instruction_abort(unsigned int esr) |
420 | { | |
421 | return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; | |
422 | } | |
423 | ||
1d18c47c CM |
424 | static int __kprobes do_page_fault(unsigned long addr, unsigned int esr, |
425 | struct pt_regs *regs) | |
426 | { | |
2d2837fa | 427 | const struct fault_info *inf; |
1d18c47c CM |
428 | struct task_struct *tsk; |
429 | struct mm_struct *mm; | |
92ff0674 | 430 | struct siginfo si; |
50a7ca3c | 431 | vm_fault_t fault, major = 0; |
cab15ce6 | 432 | unsigned long vm_flags = VM_READ | VM_WRITE; |
db6f4106 WD |
433 | unsigned int mm_flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; |
434 | ||
2dd0e8d2 SP |
435 | if (notify_page_fault(regs, esr)) |
436 | return 0; | |
437 | ||
1d18c47c CM |
438 | tsk = current; |
439 | mm = tsk->mm; | |
440 | ||
1d18c47c CM |
441 | /* |
442 | * If we're in an interrupt or have no user context, we must not take | |
443 | * the fault. | |
444 | */ | |
70ffdb93 | 445 | if (faulthandler_disabled() || !mm) |
1d18c47c CM |
446 | goto no_context; |
447 | ||
759496ba JW |
448 | if (user_mode(regs)) |
449 | mm_flags |= FAULT_FLAG_USER; | |
450 | ||
541ec870 | 451 | if (is_el0_instruction_abort(esr)) { |
759496ba | 452 | vm_flags = VM_EXEC; |
aed40e01 | 453 | } else if ((esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM)) { |
759496ba JW |
454 | vm_flags = VM_WRITE; |
455 | mm_flags |= FAULT_FLAG_WRITE; | |
456 | } | |
457 | ||
969e61ba | 458 | if (addr < TASK_SIZE && is_el1_permission_fault(esr, regs, addr)) { |
e19a6ee2 JM |
459 | /* regs->orig_addr_limit may be 0 if we entered from EL0 */ |
460 | if (regs->orig_addr_limit == KERNEL_DS) | |
c870f14e MR |
461 | die_kernel_fault("access to user memory with fs=KERNEL_DS", |
462 | addr, esr, regs); | |
70544196 | 463 | |
9adeb8e7 | 464 | if (is_el1_instruction_abort(esr)) |
c870f14e MR |
465 | die_kernel_fault("execution of user memory", |
466 | addr, esr, regs); | |
9adeb8e7 | 467 | |
57f4959b | 468 | if (!search_exception_tables(regs->pc)) |
c870f14e MR |
469 | die_kernel_fault("access to user memory outside uaccess routines", |
470 | addr, esr, regs); | |
57f4959b | 471 | } |
338d4f49 | 472 | |
0e3a9026 PA |
473 | perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); |
474 | ||
1d18c47c CM |
475 | /* |
476 | * As per x86, we may deadlock here. However, since the kernel only | |
477 | * validly references user space from well defined areas of the code, | |
478 | * we can bug out early if this is from code which shouldn't. | |
479 | */ | |
480 | if (!down_read_trylock(&mm->mmap_sem)) { | |
481 | if (!user_mode(regs) && !search_exception_tables(regs->pc)) | |
482 | goto no_context; | |
483 | retry: | |
484 | down_read(&mm->mmap_sem); | |
485 | } else { | |
486 | /* | |
487 | * The above down_read_trylock() might have succeeded in which | |
488 | * case, we'll have missed the might_sleep() from down_read(). | |
489 | */ | |
490 | might_sleep(); | |
491 | #ifdef CONFIG_DEBUG_VM | |
492 | if (!user_mode(regs) && !search_exception_tables(regs->pc)) | |
493 | goto no_context; | |
494 | #endif | |
495 | } | |
496 | ||
db6f4106 | 497 | fault = __do_page_fault(mm, addr, mm_flags, vm_flags, tsk); |
0e3a9026 | 498 | major |= fault & VM_FAULT_MAJOR; |
1d18c47c | 499 | |
0e3a9026 PA |
500 | if (fault & VM_FAULT_RETRY) { |
501 | /* | |
502 | * If we need to retry but a fatal signal is pending, | |
503 | * handle the signal first. We do not need to release | |
504 | * the mmap_sem because it would already be released | |
505 | * in __lock_page_or_retry in mm/filemap.c. | |
506 | */ | |
289d07a2 MR |
507 | if (fatal_signal_pending(current)) { |
508 | if (!user_mode(regs)) | |
509 | goto no_context; | |
0e3a9026 | 510 | return 0; |
289d07a2 | 511 | } |
0e3a9026 PA |
512 | |
513 | /* | |
514 | * Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk of | |
515 | * starvation. | |
516 | */ | |
517 | if (mm_flags & FAULT_FLAG_ALLOW_RETRY) { | |
518 | mm_flags &= ~FAULT_FLAG_ALLOW_RETRY; | |
519 | mm_flags |= FAULT_FLAG_TRIED; | |
520 | goto retry; | |
521 | } | |
522 | } | |
523 | up_read(&mm->mmap_sem); | |
1d18c47c CM |
524 | |
525 | /* | |
0e3a9026 | 526 | * Handle the "normal" (no error) case first. |
1d18c47c | 527 | */ |
0e3a9026 PA |
528 | if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP | |
529 | VM_FAULT_BADACCESS)))) { | |
530 | /* | |
531 | * Major/minor page fault accounting is only done | |
532 | * once. If we go through a retry, it is extremely | |
533 | * likely that the page will be found in page cache at | |
534 | * that point. | |
535 | */ | |
536 | if (major) { | |
1d18c47c CM |
537 | tsk->maj_flt++; |
538 | perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, | |
539 | addr); | |
540 | } else { | |
541 | tsk->min_flt++; | |
542 | perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, | |
543 | addr); | |
544 | } | |
1d18c47c | 545 | |
1d18c47c | 546 | return 0; |
0e3a9026 | 547 | } |
1d18c47c | 548 | |
87134102 JW |
549 | /* |
550 | * If we are in kernel mode at this point, we have no context to | |
551 | * handle this fault with. | |
552 | */ | |
553 | if (!user_mode(regs)) | |
554 | goto no_context; | |
555 | ||
1d18c47c CM |
556 | if (fault & VM_FAULT_OOM) { |
557 | /* | |
558 | * We ran out of memory, call the OOM killer, and return to | |
559 | * userspace (which will retry the fault, or kill us if we got | |
560 | * oom-killed). | |
561 | */ | |
562 | pagefault_out_of_memory(); | |
563 | return 0; | |
564 | } | |
565 | ||
2d2837fa | 566 | inf = esr_to_fault_info(esr); |
559d8d91 | 567 | set_thread_esr(addr, esr); |
1d18c47c CM |
568 | if (fault & VM_FAULT_SIGBUS) { |
569 | /* | |
570 | * We had some memory, but were unable to successfully fix up | |
571 | * this page fault. | |
572 | */ | |
aefab2b4 | 573 | clear_siginfo(&si); |
92ff0674 WD |
574 | si.si_signo = SIGBUS; |
575 | si.si_code = BUS_ADRERR; | |
aefab2b4 | 576 | si.si_addr = (void __user *)addr; |
2d2837fa | 577 | arm64_force_sig_info(&si, inf->name); |
9ea3a974 EB |
578 | } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) { |
579 | unsigned int lsb; | |
580 | ||
581 | lsb = PAGE_SHIFT; | |
582 | if (fault & VM_FAULT_HWPOISON_LARGE) | |
583 | lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); | |
92ff0674 | 584 | |
aefab2b4 | 585 | clear_siginfo(&si); |
92ff0674 WD |
586 | si.si_signo = SIGBUS; |
587 | si.si_code = BUS_MCEERR_AR; | |
aefab2b4 | 588 | si.si_addr = (void __user *)addr; |
9ea3a974 | 589 | si.si_addr_lsb = lsb; |
2d2837fa | 590 | arm64_force_sig_info(&si, inf->name); |
1d18c47c CM |
591 | } else { |
592 | /* | |
593 | * Something tried to access memory that isn't in our memory | |
594 | * map. | |
595 | */ | |
aefab2b4 | 596 | clear_siginfo(&si); |
92ff0674 WD |
597 | si.si_signo = SIGSEGV; |
598 | si.si_code = fault == VM_FAULT_BADACCESS ? | |
599 | SEGV_ACCERR : SEGV_MAPERR; | |
aefab2b4 | 600 | si.si_addr = (void __user *)addr; |
2d2837fa | 601 | arm64_force_sig_info(&si, inf->name); |
1d18c47c CM |
602 | } |
603 | ||
1d18c47c CM |
604 | return 0; |
605 | ||
606 | no_context: | |
67ce16ec | 607 | __do_kernel_fault(addr, esr, regs); |
1d18c47c CM |
608 | return 0; |
609 | } | |
610 | ||
1d18c47c CM |
611 | static int __kprobes do_translation_fault(unsigned long addr, |
612 | unsigned int esr, | |
613 | struct pt_regs *regs) | |
614 | { | |
615 | if (addr < TASK_SIZE) | |
616 | return do_page_fault(addr, esr, regs); | |
617 | ||
618 | do_bad_area(addr, esr, regs); | |
619 | return 0; | |
620 | } | |
621 | ||
52d7523d EL |
622 | static int do_alignment_fault(unsigned long addr, unsigned int esr, |
623 | struct pt_regs *regs) | |
624 | { | |
625 | do_bad_area(addr, esr, regs); | |
626 | return 0; | |
627 | } | |
628 | ||
1d18c47c CM |
629 | static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) |
630 | { | |
f67d5c4f | 631 | return 1; /* "fault" */ |
1d18c47c CM |
632 | } |
633 | ||
32015c23 TB |
634 | static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) |
635 | { | |
32015c23 | 636 | const struct fault_info *inf; |
6fa998e8 | 637 | void __user *siaddr; |
32015c23 TB |
638 | |
639 | inf = esr_to_fault_info(esr); | |
32015c23 | 640 | |
7edda088 TB |
641 | /* |
642 | * Synchronous aborts may interrupt code which had interrupts masked. | |
643 | * Before calling out into the wider kernel tell the interested | |
644 | * subsystems. | |
645 | */ | |
646 | if (IS_ENABLED(CONFIG_ACPI_APEI_SEA)) { | |
647 | if (interrupts_enabled(regs)) | |
648 | nmi_enter(); | |
649 | ||
faa75e14 | 650 | ghes_notify_sea(); |
7edda088 TB |
651 | |
652 | if (interrupts_enabled(regs)) | |
653 | nmi_exit(); | |
654 | } | |
655 | ||
32015c23 | 656 | if (esr & ESR_ELx_FnV) |
6fa998e8 | 657 | siaddr = NULL; |
32015c23 | 658 | else |
6fa998e8 EB |
659 | siaddr = (void __user *)addr; |
660 | arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr); | |
32015c23 | 661 | |
faa75e14 | 662 | return 0; |
32015c23 TB |
663 | } |
664 | ||
09a6adf5 | 665 | static const struct fault_info fault_info[] = { |
af40ff68 DM |
666 | { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" }, |
667 | { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" }, | |
668 | { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" }, | |
669 | { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" }, | |
7f73f7ae | 670 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" }, |
1d18c47c CM |
671 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" }, |
672 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" }, | |
760bfb47 | 673 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" }, |
af40ff68 | 674 | { do_bad, SIGKILL, SI_KERNEL, "unknown 8" }, |
084bd298 SC |
675 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" }, |
676 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" }, | |
1d18c47c | 677 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" }, |
af40ff68 | 678 | { do_bad, SIGKILL, SI_KERNEL, "unknown 12" }, |
084bd298 SC |
679 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, |
680 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, | |
1d18c47c | 681 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, |
af40ff68 DM |
682 | { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" }, |
683 | { do_bad, SIGKILL, SI_KERNEL, "unknown 17" }, | |
684 | { do_bad, SIGKILL, SI_KERNEL, "unknown 18" }, | |
685 | { do_bad, SIGKILL, SI_KERNEL, "unknown 19" }, | |
686 | { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" }, | |
687 | { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" }, | |
688 | { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" }, | |
689 | { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" }, | |
690 | { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented | |
691 | { do_bad, SIGKILL, SI_KERNEL, "unknown 25" }, | |
692 | { do_bad, SIGKILL, SI_KERNEL, "unknown 26" }, | |
693 | { do_bad, SIGKILL, SI_KERNEL, "unknown 27" }, | |
694 | { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented | |
695 | { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented | |
696 | { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented | |
697 | { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented | |
698 | { do_bad, SIGKILL, SI_KERNEL, "unknown 32" }, | |
52d7523d | 699 | { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, |
af40ff68 DM |
700 | { do_bad, SIGKILL, SI_KERNEL, "unknown 34" }, |
701 | { do_bad, SIGKILL, SI_KERNEL, "unknown 35" }, | |
702 | { do_bad, SIGKILL, SI_KERNEL, "unknown 36" }, | |
703 | { do_bad, SIGKILL, SI_KERNEL, "unknown 37" }, | |
704 | { do_bad, SIGKILL, SI_KERNEL, "unknown 38" }, | |
705 | { do_bad, SIGKILL, SI_KERNEL, "unknown 39" }, | |
706 | { do_bad, SIGKILL, SI_KERNEL, "unknown 40" }, | |
707 | { do_bad, SIGKILL, SI_KERNEL, "unknown 41" }, | |
708 | { do_bad, SIGKILL, SI_KERNEL, "unknown 42" }, | |
709 | { do_bad, SIGKILL, SI_KERNEL, "unknown 43" }, | |
710 | { do_bad, SIGKILL, SI_KERNEL, "unknown 44" }, | |
711 | { do_bad, SIGKILL, SI_KERNEL, "unknown 45" }, | |
712 | { do_bad, SIGKILL, SI_KERNEL, "unknown 46" }, | |
713 | { do_bad, SIGKILL, SI_KERNEL, "unknown 47" }, | |
714 | { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" }, | |
715 | { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" }, | |
716 | { do_bad, SIGKILL, SI_KERNEL, "unknown 50" }, | |
717 | { do_bad, SIGKILL, SI_KERNEL, "unknown 51" }, | |
718 | { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" }, | |
719 | { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" }, | |
720 | { do_bad, SIGKILL, SI_KERNEL, "unknown 54" }, | |
721 | { do_bad, SIGKILL, SI_KERNEL, "unknown 55" }, | |
722 | { do_bad, SIGKILL, SI_KERNEL, "unknown 56" }, | |
723 | { do_bad, SIGKILL, SI_KERNEL, "unknown 57" }, | |
724 | { do_bad, SIGKILL, SI_KERNEL, "unknown 58" }, | |
725 | { do_bad, SIGKILL, SI_KERNEL, "unknown 59" }, | |
726 | { do_bad, SIGKILL, SI_KERNEL, "unknown 60" }, | |
727 | { do_bad, SIGKILL, SI_KERNEL, "section domain fault" }, | |
728 | { do_bad, SIGKILL, SI_KERNEL, "page domain fault" }, | |
729 | { do_bad, SIGKILL, SI_KERNEL, "unknown 63" }, | |
1d18c47c CM |
730 | }; |
731 | ||
621f48e4 TB |
732 | int handle_guest_sea(phys_addr_t addr, unsigned int esr) |
733 | { | |
1035a078 | 734 | return ghes_notify_sea(); |
621f48e4 TB |
735 | } |
736 | ||
1d18c47c CM |
737 | asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, |
738 | struct pt_regs *regs) | |
739 | { | |
09a6adf5 | 740 | const struct fault_info *inf = esr_to_fault_info(esr); |
1d18c47c CM |
741 | |
742 | if (!inf->fn(addr, esr, regs)) | |
743 | return; | |
744 | ||
1049c308 WD |
745 | if (!user_mode(regs)) { |
746 | pr_alert("Unhandled fault at 0x%016lx\n", addr); | |
747 | mem_abort_decode(esr); | |
80b6eb04 | 748 | show_pte(addr); |
1049c308 | 749 | } |
42dbf54e | 750 | |
6fa998e8 EB |
751 | arm64_notify_die(inf->name, regs, |
752 | inf->sig, inf->code, (void __user *)addr, esr); | |
1d18c47c CM |
753 | } |
754 | ||
30d88c0e WD |
755 | asmlinkage void __exception do_el0_irq_bp_hardening(void) |
756 | { | |
757 | /* PC has already been checked in entry.S */ | |
758 | arm64_apply_bp_hardening(); | |
759 | } | |
760 | ||
0f15adbb WD |
761 | asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, |
762 | unsigned int esr, | |
763 | struct pt_regs *regs) | |
764 | { | |
765 | /* | |
766 | * We've taken an instruction abort from userspace and not yet | |
767 | * re-enabled IRQs. If the address is a kernel address, apply | |
768 | * BP hardening prior to enabling IRQs and pre-emption. | |
769 | */ | |
770 | if (addr > TASK_SIZE) | |
771 | arm64_apply_bp_hardening(); | |
772 | ||
773 | local_irq_enable(); | |
774 | do_mem_abort(addr, esr, regs); | |
775 | } | |
776 | ||
777 | ||
1d18c47c CM |
778 | asmlinkage void __exception do_sp_pc_abort(unsigned long addr, |
779 | unsigned int esr, | |
780 | struct pt_regs *regs) | |
781 | { | |
5dfc6ed2 WD |
782 | if (user_mode(regs)) { |
783 | if (instruction_pointer(regs) > TASK_SIZE) | |
784 | arm64_apply_bp_hardening(); | |
785 | local_irq_enable(); | |
786 | } | |
787 | ||
6fa998e8 EB |
788 | arm64_notify_die("SP/PC alignment exception", regs, |
789 | SIGBUS, BUS_ADRALN, (void __user *)addr, esr); | |
1d18c47c CM |
790 | } |
791 | ||
9fb7410f DM |
792 | int __init early_brk64(unsigned long addr, unsigned int esr, |
793 | struct pt_regs *regs); | |
794 | ||
795 | /* | |
796 | * __refdata because early_brk64 is __init, but the reference to it is | |
797 | * clobbered at arch_initcall time. | |
798 | * See traps.c and debug-monitors.c:debug_traps_init(). | |
799 | */ | |
800 | static struct fault_info __refdata debug_fault_info[] = { | |
1d18c47c CM |
801 | { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" }, |
802 | { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" }, | |
803 | { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" }, | |
af40ff68 | 804 | { do_bad, SIGKILL, SI_KERNEL, "unknown 3" }, |
1d18c47c | 805 | { do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" }, |
af40ff68 | 806 | { do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" }, |
9fb7410f | 807 | { early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" }, |
af40ff68 | 808 | { do_bad, SIGKILL, SI_KERNEL, "unknown 7" }, |
1d18c47c CM |
809 | }; |
810 | ||
811 | void __init hook_debug_fault_code(int nr, | |
812 | int (*fn)(unsigned long, unsigned int, struct pt_regs *), | |
813 | int sig, int code, const char *name) | |
814 | { | |
815 | BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info)); | |
816 | ||
817 | debug_fault_info[nr].fn = fn; | |
818 | debug_fault_info[nr].sig = sig; | |
819 | debug_fault_info[nr].code = code; | |
820 | debug_fault_info[nr].name = name; | |
821 | } | |
822 | ||
823 | asmlinkage int __exception do_debug_exception(unsigned long addr, | |
824 | unsigned int esr, | |
825 | struct pt_regs *regs) | |
826 | { | |
827 | const struct fault_info *inf = debug_fault_info + DBG_ESR_EVT(esr); | |
6afedcd2 | 828 | int rv; |
1d18c47c | 829 | |
6afedcd2 JM |
830 | /* |
831 | * Tell lockdep we disabled irqs in entry.S. Do nothing if they were | |
832 | * already disabled to preserve the last enabled/disabled addresses. | |
833 | */ | |
834 | if (interrupts_enabled(regs)) | |
835 | trace_hardirqs_off(); | |
1d18c47c | 836 | |
5dfc6ed2 WD |
837 | if (user_mode(regs) && instruction_pointer(regs) > TASK_SIZE) |
838 | arm64_apply_bp_hardening(); | |
839 | ||
6afedcd2 JM |
840 | if (!inf->fn(addr, esr, regs)) { |
841 | rv = 1; | |
842 | } else { | |
6fa998e8 EB |
843 | arm64_notify_die(inf->name, regs, |
844 | inf->sig, inf->code, (void __user *)addr, esr); | |
6afedcd2 JM |
845 | rv = 0; |
846 | } | |
1d18c47c | 847 | |
6afedcd2 JM |
848 | if (interrupts_enabled(regs)) |
849 | trace_hardirqs_on(); | |
1d18c47c | 850 | |
6afedcd2 | 851 | return rv; |
1d18c47c | 852 | } |
2dd0e8d2 | 853 | NOKPROBE_SYMBOL(do_debug_exception); |
338d4f49 JM |
854 | |
855 | #ifdef CONFIG_ARM64_PAN | |
c0cda3b8 | 856 | void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) |
338d4f49 | 857 | { |
7209c868 JM |
858 | /* |
859 | * We modify PSTATE. This won't work from irq context as the PSTATE | |
860 | * is discarded once we return from the exception. | |
861 | */ | |
862 | WARN_ON_ONCE(in_interrupt()); | |
863 | ||
25be597a | 864 | sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); |
7209c868 | 865 | asm(SET_PSTATE_PAN(1)); |
338d4f49 JM |
866 | } |
867 | #endif /* CONFIG_ARM64_PAN */ |