[linux-2.6-block.git] / arch / arm64 / kvm / sys_regs.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2012,2013 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * Derived from arch/arm/kvm/coproc.h
 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
 * Authors: Christoffer Dall <c.dall@virtualopensystems.com>
 */

#ifndef __ARM64_KVM_SYS_REGS_LOCAL_H__
#define __ARM64_KVM_SYS_REGS_LOCAL_H__

#include <linux/bsearch.h>

#define reg_to_encoding(x)						\
	sys_reg((u32)(x)->Op0, (u32)(x)->Op1,				\
		(u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)

struct sys_reg_params {
	u8	Op0;
	u8	Op1;
	u8	CRn;
	u8	CRm;
	u8	Op2;
	u64	regval;
	bool	is_write;
};

#define esr_sys64_to_params(esr)                                               \
	((struct sys_reg_params){ .Op0 = ((esr) >> 20) & 3,                    \
				  .Op1 = ((esr) >> 14) & 0x7,                  \
				  .CRn = ((esr) >> 10) & 0xf,                  \
				  .CRm = ((esr) >> 1) & 0xf,                   \
				  .Op2 = ((esr) >> 17) & 0x7,                  \
				  .is_write = !((esr) & 1) })

#define esr_cp1x_32_to_params(esr)						\
	((struct sys_reg_params){ .Op1 = ((esr) >> 14) & 0x7,			\
				  .CRn = ((esr) >> 10) & 0xf,			\
				  .CRm = ((esr) >> 1) & 0xf,			\
				  .Op2 = ((esr) >> 17) & 0x7,			\
				  .is_write = !((esr) & 1) })

struct sys_reg_desc {
	/* Sysreg string for debug */
	const char *name;

	enum {
		AA32_DIRECT,
		AA32_LO,
		AA32_HI,
	} aarch32_map;

	/* MRS/MSR instruction which accesses it. */
	u8	Op0;
	u8	Op1;
	u8	CRn;
	u8	CRm;
	u8	Op2;

	/* Trapped access from guest, if non-NULL. */
	bool (*access)(struct kvm_vcpu *,
		       struct sys_reg_params *,
		       const struct sys_reg_desc *);

	/* Initialization for vcpu. */
	void (*reset)(struct kvm_vcpu *, const struct sys_reg_desc *);

	/* Index into sys_reg[], or 0 if we don't need to save it. */
	int reg;

	/* Value (usually reset value) */
	u64 val;

	/* Custom get/set_user functions, fallback to generic if NULL */
	int (*get_user)(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
			const struct kvm_one_reg *reg, void __user *uaddr);
	int (*set_user)(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
			const struct kvm_one_reg *reg, void __user *uaddr);

	/* Return mask of REG_* runtime visibility overrides */
	unsigned int (*visibility)(const struct kvm_vcpu *vcpu,
				   const struct sys_reg_desc *rd);
};

#define REG_HIDDEN		(1 << 0) /* hidden from userspace and guest */
#define REG_RAZ			(1 << 1) /* RAZ from userspace and guest */

static __printf(2, 3)
inline void print_sys_reg_msg(const struct sys_reg_params *p,
				       char *fmt, ...)
{
	va_list va;

	va_start(va, fmt);
	/* Look, we even formatted it for you to paste into the table! */
	kvm_pr_unimpl("%pV { Op0(%2u), Op1(%2u), CRn(%2u), CRm(%2u), Op2(%2u), func_%s },\n",
		      &(struct va_format){ fmt, &va },
		      p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read");
	va_end(va);
}

static inline void print_sys_reg_instr(const struct sys_reg_params *p)
{
	/* GCC warns on an empty format string */
	print_sys_reg_msg(p, "%s", "");
}

static inline bool ignore_write(struct kvm_vcpu *vcpu,
				const struct sys_reg_params *p)
{
	return true;
}

static inline bool read_zero(struct kvm_vcpu *vcpu,
			     struct sys_reg_params *p)
{
	p->regval = 0;
	return true;
}

/* Reset functions */
static inline void reset_unknown(struct kvm_vcpu *vcpu,
				 const struct sys_reg_desc *r)
{
	BUG_ON(!r->reg);
	BUG_ON(r->reg >= NR_SYS_REGS);
	__vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
}

static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
	BUG_ON(!r->reg);
	BUG_ON(r->reg >= NR_SYS_REGS);
	__vcpu_sys_reg(vcpu, r->reg) = r->val;
}

static inline bool sysreg_hidden(const struct kvm_vcpu *vcpu,
				 const struct sys_reg_desc *r)
{
	if (likely(!r->visibility))
		return false;

	return r->visibility(vcpu, r) & REG_HIDDEN;
}

static inline bool sysreg_visible_as_raz(const struct kvm_vcpu *vcpu,
					 const struct sys_reg_desc *r)
{
	if (likely(!r->visibility))
		return false;

	return r->visibility(vcpu, r) & REG_RAZ;
}

static inline int cmp_sys_reg(const struct sys_reg_desc *i1,
			      const struct sys_reg_desc *i2)
{
	BUG_ON(i1 == i2);
	if (!i1)
		return 1;
	else if (!i2)
		return -1;
	if (i1->Op0 != i2->Op0)
		return i1->Op0 - i2->Op0;
	if (i1->Op1 != i2->Op1)
		return i1->Op1 - i2->Op1;
	if (i1->CRn != i2->CRn)
		return i1->CRn - i2->CRn;
	if (i1->CRm != i2->CRm)
		return i1->CRm - i2->CRm;
	return i1->Op2 - i2->Op2;
}

static inline int match_sys_reg(const void *key, const void *elt)
{
	const unsigned long pval = (unsigned long)key;
	const struct sys_reg_desc *r = elt;

	return pval - reg_to_encoding(r);
}

static inline const struct sys_reg_desc *
find_reg(const struct sys_reg_params *params, const struct sys_reg_desc table[],
	 unsigned int num)
{
	unsigned long pval = reg_to_encoding(params);

	return __inline_bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
}

const struct sys_reg_desc *find_reg_by_id(u64 id,
					  struct sys_reg_params *params,
					  const struct sys_reg_desc table[],
					  unsigned int num);

#define AA32(_x)	.aarch32_map = AA32_##_x
#define Op0(_x) 	.Op0 = _x
#define Op1(_x) 	.Op1 = _x
#define CRn(_x)		.CRn = _x
#define CRm(_x) 	.CRm = _x
#define Op2(_x) 	.Op2 = _x

#define SYS_DESC(reg)					\
	.name = #reg,					\
	Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)),	\
	CRn(sys_reg_CRn(reg)), CRm(sys_reg_CRm(reg)),	\
	Op2(sys_reg_Op2(reg))

#endif /* __ARM64_KVM_SYS_REGS_LOCAL_H__ */
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
7c8c5e6a MZ	2	/*
	3	* Copyright (C) 2012,2013 - ARM Ltd
	4	* Author: Marc Zyngier <marc.zyngier@arm.com>
	5	*
	6	* Derived from arch/arm/kvm/coproc.h
	7	* Copyright (C) 2012 - Virtual Open Systems and Columbia University
	8	* Authors: Christoffer Dall <c.dall@virtualopensystems.com>
7c8c5e6a MZ	9	*/
	10
	11	#ifndef __ARM64_KVM_SYS_REGS_LOCAL_H__
	12	#define __ARM64_KVM_SYS_REGS_LOCAL_H__
	13
f76f89e2 FT	14	#include <linux/bsearch.h>
	15
	16	#define reg_to_encoding(x) \
	17	sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
	18	(u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
	19
7c8c5e6a MZ	20	struct sys_reg_params {
	21	u8 Op0;
	22	u8 Op1;
	23	u8 CRn;
	24	u8 CRm;
	25	u8 Op2;
2ec5be3d	26	u64 regval;
7c8c5e6a MZ	27	bool is_write;
	28	};
	29
f76f89e2 FT	30	#define esr_sys64_to_params(esr) \
	31	((struct sys_reg_params){ .Op0 = ((esr) >> 20) & 3, \
	32	.Op1 = ((esr) >> 14) & 0x7, \
	33	.CRn = ((esr) >> 10) & 0xf, \
	34	.CRm = ((esr) >> 1) & 0xf, \
	35	.Op2 = ((esr) >> 17) & 0x7, \
	36	.is_write = !((esr) & 1) })
	37
e6519766 OU	38	#define esr_cp1x_32_to_params(esr) \
	39	((struct sys_reg_params){ .Op1 = ((esr) >> 14) & 0x7, \
	40	.CRn = ((esr) >> 10) & 0xf, \
	41	.CRm = ((esr) >> 1) & 0xf, \
	42	.Op2 = ((esr) >> 17) & 0x7, \
	43	.is_write = !((esr) & 1) })
	44
7c8c5e6a	45	struct sys_reg_desc {
599d79dc MZ	46	/* Sysreg string for debug */
	47	const char *name;
	48
6ed6750f	49	enum {
a9e192cd	50	AA32_DIRECT,
6ed6750f MZ	51	AA32_LO,
	52	AA32_HI,
	53	} aarch32_map;
	54
7c8c5e6a MZ	55	/* MRS/MSR instruction which accesses it. */
	56	u8 Op0;
	57	u8 Op1;
	58	u8 CRn;
	59	u8 CRm;
	60	u8 Op2;
	61
	62	/* Trapped access from guest, if non-NULL. */
	63	bool (access)(struct kvm_vcpu ,
3fec037d	64	struct sys_reg_params *,
7c8c5e6a MZ	65	const struct sys_reg_desc *);
	66
	67	/* Initialization for vcpu. */
	68	void (reset)(struct kvm_vcpu , const struct sys_reg_desc *);
	69
	70	/* Index into sys_reg[], or 0 if we don't need to save it. */
	71	int reg;
	72
	73	/* Value (usually reset value) */
	74	u64 val;
84e690bf AB	75
	76	/* Custom get/set_user functions, fallback to generic if NULL */
	77	int (get_user)(struct kvm_vcpu vcpu, const struct sys_reg_desc *rd,
	78	const struct kvm_one_reg reg, void __user uaddr);
	79	int (set_user)(struct kvm_vcpu vcpu, const struct sys_reg_desc *rd,
	80	const struct kvm_one_reg reg, void __user uaddr);
7f34e409 DM	81
	82	/* Return mask of REG_* runtime visibility overrides */
	83	unsigned int (visibility)(const struct kvm_vcpu vcpu,
	84	const struct sys_reg_desc *rd);
7c8c5e6a MZ	85	};
7c8c5e6a MZ	86
01fe5ace	87	#define REG_HIDDEN (1 << 0) /* hidden from userspace and guest */
912dee57	88	#define REG_RAZ (1 << 1) /* RAZ from userspace and guest */
7f34e409	89
bf4b96bb MR	90	static __printf(2, 3)
	91	inline void print_sys_reg_msg(const struct sys_reg_params *p,
	92	char *fmt, ...)
7c8c5e6a	93	{
bf4b96bb MR	94	va_list va;
	95
	96	va_start(va, fmt);
7c8c5e6a	97	/* Look, we even formatted it for you to paste into the table! */
bf4b96bb MR	98	kvm_pr_unimpl("%pV { Op0(%2u), Op1(%2u), CRn(%2u), CRm(%2u), Op2(%2u), func_%s },\n",
bf4b96bb MR	99	&(struct va_format){ fmt, &va },
7c8c5e6a	100	p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read");
bf4b96bb MR	101	va_end(va);
	102	}
	103
	104	static inline void print_sys_reg_instr(const struct sys_reg_params *p)
	105	{
	106	/* GCC warns on an empty format string */
	107	print_sys_reg_msg(p, "%s", "");
7c8c5e6a MZ	108	}
	109
	110	static inline bool ignore_write(struct kvm_vcpu *vcpu,
	111	const struct sys_reg_params *p)
	112	{
	113	return true;
	114	}
	115
	116	static inline bool read_zero(struct kvm_vcpu *vcpu,
3fec037d	117	struct sys_reg_params *p)
7c8c5e6a	118	{
2ec5be3d	119	p->regval = 0;
7c8c5e6a MZ	120	return true;
	121	}
	122
7c8c5e6a MZ	123	/* Reset functions */
	124	static inline void reset_unknown(struct kvm_vcpu *vcpu,
	125	const struct sys_reg_desc *r)
	126	{
	127	BUG_ON(!r->reg);
	128	BUG_ON(r->reg >= NR_SYS_REGS);
8d404c4c	129	__vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
7c8c5e6a MZ	130	}
	131
	132	static inline void reset_val(struct kvm_vcpu vcpu, const struct sys_reg_desc r)
	133	{
	134	BUG_ON(!r->reg);
	135	BUG_ON(r->reg >= NR_SYS_REGS);
8d404c4c	136	__vcpu_sys_reg(vcpu, r->reg) = r->val;
7c8c5e6a MZ	137	}
7c8c5e6a MZ	138
01fe5ace AJ	139	static inline bool sysreg_hidden(const struct kvm_vcpu *vcpu,
01fe5ace AJ	140	const struct sys_reg_desc *r)
7f34e409 DM	141	{
	142	if (likely(!r->visibility))
	143	return false;
	144
01fe5ace	145	return r->visibility(vcpu, r) & REG_HIDDEN;
7f34e409 DM	146	}
7f34e409 DM	147
912dee57 AJ	148	static inline bool sysreg_visible_as_raz(const struct kvm_vcpu *vcpu,
	149	const struct sys_reg_desc *r)
	150	{
	151	if (likely(!r->visibility))
	152	return false;
	153
	154	return r->visibility(vcpu, r) & REG_RAZ;
	155	}
	156
7c8c5e6a MZ	157	static inline int cmp_sys_reg(const struct sys_reg_desc *i1,
	158	const struct sys_reg_desc *i2)
	159	{
	160	BUG_ON(i1 == i2);
	161	if (!i1)
	162	return 1;
	163	else if (!i2)
	164	return -1;
	165	if (i1->Op0 != i2->Op0)
	166	return i1->Op0 - i2->Op0;
	167	if (i1->Op1 != i2->Op1)
	168	return i1->Op1 - i2->Op1;
	169	if (i1->CRn != i2->CRn)
	170	return i1->CRn - i2->CRn;
	171	if (i1->CRm != i2->CRm)
	172	return i1->CRm - i2->CRm;
	173	return i1->Op2 - i2->Op2;
	174	}
	175
f76f89e2 FT	176	static inline int match_sys_reg(const void key, const void elt)
	177	{
	178	const unsigned long pval = (unsigned long)key;
	179	const struct sys_reg_desc *r = elt;
	180
	181	return pval - reg_to_encoding(r);
	182	}
	183
	184	static inline const struct sys_reg_desc *
	185	find_reg(const struct sys_reg_params *params, const struct sys_reg_desc table[],
	186	unsigned int num)
	187	{
	188	unsigned long pval = reg_to_encoding(params);
	189
	190	return __inline_bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
	191	}
	192
4b927b94 VK	193	const struct sys_reg_desc *find_reg_by_id(u64 id,
	194	struct sys_reg_params *params,
	195	const struct sys_reg_desc table[],
	196	unsigned int num);
7c8c5e6a	197
6ed6750f	198	#define AA32(_x) .aarch32_map = AA32_##_x
7c8c5e6a MZ	199	#define Op0(_x) .Op0 = _x
	200	#define Op1(_x) .Op1 = _x
	201	#define CRn(_x) .CRn = _x
	202	#define CRm(_x) .CRm = _x
	203	#define Op2(_x) .Op2 = _x
	204
8db5d8f1	205	#define SYS_DESC(reg) \
599d79dc	206	.name = #reg, \
8db5d8f1 MR	207	Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \
	208	CRn(sys_reg_CRn(reg)), CRm(sys_reg_CRm(reg)), \
	209	Op2(sys_reg_Op2(reg))
	210
7c8c5e6a	211	#endif /* __ARM64_KVM_SYS_REGS_LOCAL_H__ */