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KVM: arm64: Introduce MTE VM feature
[linux-2.6-block.git] / arch / arm64 / kvm / sys_regs.c
CommitLineData
caab277b 1// SPDX-License-Identifier: GPL-2.0-only
7c8c5e6a
MZ		 2/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
7c8c5e6a
MZ		 10 */
11
c8857935 12#include <linux/bitfield.h>
623eefa8 13#include <linux/bsearch.h>
7c8c5e6a 14#include <linux/kvm_host.h>
c6d01a94 15#include <linux/mm.h>
07d79fe7 16#include <linux/printk.h>
7c8c5e6a 17#include <linux/uaccess.h>
c6d01a94 18
7c8c5e6a
MZ		 19#include <asm/cacheflush.h>
20#include <asm/cputype.h>
0c557ed4 21#include <asm/debug-monitors.h>
c6d01a94
MR		 22#include <asm/esr.h>
23#include <asm/kvm_arm.h>
c6d01a94 24#include <asm/kvm_emulate.h>
d47533da 25#include <asm/kvm_hyp.h>
c6d01a94 26#include <asm/kvm_mmu.h>
ab946834 27#include <asm/perf_event.h>
1f3d8699 28#include <asm/sysreg.h>
c6d01a94 29
7c8c5e6a
MZ		 30#include <trace/events/kvm.h>
31
32#include "sys_regs.h"
33
eef8c85a
AB		 34#include "trace.h"
35
7c8c5e6a 36/*
656012c7 37 * All of this file is extremely similar to the ARM coproc.c, but the
7c8c5e6a
MZ		 38 * types are different. My gut feeling is that it should be pretty
39 * easy to merge, but that would be an ABI breakage -- again. VFP
40 * would also need to be abstracted.
62a89c44
MZ		 41 *
42 * For AArch32, we only take care of what is being trapped. Anything
43 * that has to do with init and userspace access has to go via the
44 * 64bit interface.
7c8c5e6a
MZ		 45 */
46
7ba8b438
AE		 47#define reg_to_encoding(x) \
48 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
49 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
50
7b5b4df1 51static bool read_from_write_only(struct kvm_vcpu *vcpu,
e7f1d1ee
MZ		 52 struct sys_reg_params *params,
53 const struct sys_reg_desc *r)
7b5b4df1
MZ		 54{
55 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
56 print_sys_reg_instr(params);
57 kvm_inject_undefined(vcpu);
58 return false;
59}
60
7b1dba1f
MZ		 61static bool write_to_read_only(struct kvm_vcpu *vcpu,
62 struct sys_reg_params *params,
63 const struct sys_reg_desc *r)
64{
65 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
66 print_sys_reg_instr(params);
67 kvm_inject_undefined(vcpu);
68 return false;
69}
70
7ea90bdd
MZ		 71u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
72{
73 u64 val = 0x8badf00d8badf00d;
74
75 if (vcpu->arch.sysregs_loaded_on_cpu &&
76 __vcpu_read_sys_reg_from_cpu(reg, &val))
77 return val;
78
79 return __vcpu_sys_reg(vcpu, reg);
80}
81
82void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
83{
84 if (vcpu->arch.sysregs_loaded_on_cpu &&
85 __vcpu_write_sys_reg_to_cpu(val, reg))
86 return;
87
d47533da
CD		 88 __vcpu_sys_reg(vcpu, reg) = val;
89}
90
7c8c5e6a
MZ		 91/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
92static u32 cache_levels;
93
94/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
c73a4416 95#define CSSELR_MAX 14
7c8c5e6a
MZ		 96
97/* Which cache CCSIDR represents depends on CSSELR value. */
98static u32 get_ccsidr(u32 csselr)
99{
100 u32 ccsidr;
101
102 /* Make sure noone else changes CSSELR during this! */
103 local_irq_disable();
1f3d8699 104 write_sysreg(csselr, csselr_el1);
7c8c5e6a 105 isb();
1f3d8699 106 ccsidr = read_sysreg(ccsidr_el1);
7c8c5e6a
MZ		 107 local_irq_enable();
108
109 return ccsidr;
110}
111
3c1e7165
MZ		 112/*
113 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
114 */
7c8c5e6a 115static bool access_dcsw(struct kvm_vcpu *vcpu,
3fec037d 116 struct sys_reg_params *p,
7c8c5e6a
MZ		 117 const struct sys_reg_desc *r)
118{
7c8c5e6a 119 if (!p->is_write)
e7f1d1ee 120 return read_from_write_only(vcpu, p, r);
7c8c5e6a 121
09605e94
MZ		 122 /*
123 * Only track S/W ops if we don't have FWB. It still indicates
124 * that the guest is a bit broken (S/W operations should only
125 * be done by firmware, knowing that there is only a single
126 * CPU left in the system, and certainly not from non-secure
127 * software).
128 */
129 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
130 kvm_set_way_flush(vcpu);
131
7c8c5e6a
MZ		 132 return true;
133}
134
b1ea1d76
MZ		 135static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
136{
137 switch (r->aarch32_map) {
138 case AA32_LO:
139 *mask = GENMASK_ULL(31, 0);
140 *shift = 0;
141 break;
142 case AA32_HI:
143 *mask = GENMASK_ULL(63, 32);
144 *shift = 32;
145 break;
146 default:
147 *mask = GENMASK_ULL(63, 0);
148 *shift = 0;
149 break;
150 }
151}
152
4d44923b
MZ		 153/*
154 * Generic accessor for VM registers. Only called as long as HCR_TVM
3c1e7165
MZ		 155 * is set. If the guest enables the MMU, we stop trapping the VM
156 * sys_regs and leave it in complete control of the caches.
4d44923b
MZ		 157 */
158static bool access_vm_reg(struct kvm_vcpu *vcpu,
3fec037d 159 struct sys_reg_params *p,
4d44923b
MZ		 160 const struct sys_reg_desc *r)
161{
3c1e7165 162 bool was_enabled = vcpu_has_cache_enabled(vcpu);
b1ea1d76 163 u64 val, mask, shift;
4d44923b
MZ		 164
165 BUG_ON(!p->is_write);
166
b1ea1d76 167 get_access_mask(r, &mask, &shift);
52f6c4f0 168
b1ea1d76
MZ		 169 if (~mask) {
170 val = vcpu_read_sys_reg(vcpu, r->reg);
171 val &= ~mask;
dedf97e8 172 } else {
b1ea1d76 173 val = 0;
dedf97e8 174 }
b1ea1d76
MZ		 175
176 val |= (p->regval & (mask >> shift)) << shift;
177 vcpu_write_sys_reg(vcpu, val, r->reg);
f0a3eaff 178
3c1e7165 179 kvm_toggle_cache(vcpu, was_enabled);
4d44923b
MZ		 180 return true;
181}
182
af473829
JM		 183static bool access_actlr(struct kvm_vcpu *vcpu,
184 struct sys_reg_params *p,
185 const struct sys_reg_desc *r)
186{
b1ea1d76
MZ		 187 u64 mask, shift;
188
af473829
JM		 189 if (p->is_write)
190 return ignore_write(vcpu, p);
191
b1ea1d76
MZ		 192 get_access_mask(r, &mask, &shift);
193 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
af473829
JM		 194
195 return true;
196}
197
6d52f35a
AP		 198/*
199 * Trap handler for the GICv3 SGI generation system register.
200 * Forward the request to the VGIC emulation.
201 * The cp15_64 code makes sure this automatically works
202 * for both AArch64 and AArch32 accesses.
203 */
204static bool access_gic_sgi(struct kvm_vcpu *vcpu,
3fec037d 205 struct sys_reg_params *p,
6d52f35a
AP		 206 const struct sys_reg_desc *r)
207{
03bd646d
MZ		 208 bool g1;
209
6d52f35a 210 if (!p->is_write)
e7f1d1ee 211 return read_from_write_only(vcpu, p, r);
6d52f35a 212
03bd646d
MZ		 213 /*
214 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
215 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
216 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
217 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
218 * group.
219 */
50f30453 220 if (p->Op0 == 0) { /* AArch32 */
03bd646d
MZ		 221 switch (p->Op1) {
222 default: /* Keep GCC quiet */
223 case 0: /* ICC_SGI1R */
224 g1 = true;
225 break;
226 case 1: /* ICC_ASGI1R */
227 case 2: /* ICC_SGI0R */
228 g1 = false;
229 break;
230 }
50f30453 231 } else { /* AArch64 */
03bd646d
MZ		 232 switch (p->Op2) {
233 default: /* Keep GCC quiet */
234 case 5: /* ICC_SGI1R_EL1 */
235 g1 = true;
236 break;
237 case 6: /* ICC_ASGI1R_EL1 */
238 case 7: /* ICC_SGI0R_EL1 */
239 g1 = false;
240 break;
241 }
242 }
243
244 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
6d52f35a
AP		 245
246 return true;
247}
248
b34f2bcb
MZ		 249static bool access_gic_sre(struct kvm_vcpu *vcpu,
250 struct sys_reg_params *p,
251 const struct sys_reg_desc *r)
252{
253 if (p->is_write)
254 return ignore_write(vcpu, p);
255
256 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
257 return true;
258}
259
7609c125 260static bool trap_raz_wi(struct kvm_vcpu *vcpu,
3fec037d 261 struct sys_reg_params *p,
7609c125 262 const struct sys_reg_desc *r)
7c8c5e6a
MZ		 263{
264 if (p->is_write)
265 return ignore_write(vcpu, p);
266 else
267 return read_zero(vcpu, p);
268}
269
22925521
MZ		 270/*
271 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
272 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
273 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
274 * treat it separately.
275 */
276static bool trap_loregion(struct kvm_vcpu *vcpu,
277 struct sys_reg_params *p,
278 const struct sys_reg_desc *r)
cc33c4e2 279{
22925521 280 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
7ba8b438 281 u32 sr = reg_to_encoding(r);
22925521
MZ		 282
283 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
284 kvm_inject_undefined(vcpu);
285 return false;
286 }
287
288 if (p->is_write && sr == SYS_LORID_EL1)
289 return write_to_read_only(vcpu, p, r);
290
291 return trap_raz_wi(vcpu, p, r);
cc33c4e2
MR		 292}
293
0c557ed4 294static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
3fec037d 295 struct sys_reg_params *p,
0c557ed4
MZ		 296 const struct sys_reg_desc *r)
297{
298 if (p->is_write) {
299 return ignore_write(vcpu, p);
300 } else {
2ec5be3d 301 p->regval = (1 << 3);
0c557ed4
MZ		 302 return true;
303 }
304}
305
306static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
3fec037d 307 struct sys_reg_params *p,
0c557ed4
MZ		 308 const struct sys_reg_desc *r)
309{
310 if (p->is_write) {
311 return ignore_write(vcpu, p);
312 } else {
1f3d8699 313 p->regval = read_sysreg(dbgauthstatus_el1);
0c557ed4
MZ		 314 return true;
315 }
316}
317
318/*
319 * We want to avoid world-switching all the DBG registers all the
320 * time:
321 *
322 * - If we've touched any debug register, it is likely that we're
323 * going to touch more of them. It then makes sense to disable the
324 * traps and start doing the save/restore dance
325 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
326 * then mandatory to save/restore the registers, as the guest
327 * depends on them.
328 *
329 * For this, we use a DIRTY bit, indicating the guest has modified the
330 * debug registers, used as follow:
331 *
332 * On guest entry:
333 * - If the dirty bit is set (because we're coming back from trapping),
334 * disable the traps, save host registers, restore guest registers.
335 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
336 * set the dirty bit, disable the traps, save host registers,
337 * restore guest registers.
338 * - Otherwise, enable the traps
339 *
340 * On guest exit:
341 * - If the dirty bit is set, save guest registers, restore host
342 * registers and clear the dirty bit. This ensure that the host can
343 * now use the debug registers.
344 */
345static bool trap_debug_regs(struct kvm_vcpu *vcpu,
3fec037d 346 struct sys_reg_params *p,
0c557ed4
MZ		 347 const struct sys_reg_desc *r)
348{
349 if (p->is_write) {
8d404c4c 350 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
fa89d31c 351 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
0c557ed4 352 } else {
8d404c4c 353 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
0c557ed4
MZ		 354 }
355
2ec5be3d 356 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
eef8c85a 357
0c557ed4
MZ		 358 return true;
359}
360
84e690bf
AB		 361/*
362 * reg_to_dbg/dbg_to_reg
363 *
364 * A 32 bit write to a debug register leave top bits alone
365 * A 32 bit read from a debug register only returns the bottom bits
366 *
367 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
368 * hyp.S code switches between host and guest values in future.
369 */
281243cb
MZ		 370static void reg_to_dbg(struct kvm_vcpu *vcpu,
371 struct sys_reg_params *p,
1da42c34 372 const struct sys_reg_desc *rd,
281243cb 373 u64 *dbg_reg)
84e690bf 374{
1da42c34 375 u64 mask, shift, val;
84e690bf 376
1da42c34 377 get_access_mask(rd, &mask, &shift);
84e690bf 378
1da42c34
MZ		 379 val = *dbg_reg;
380 val &= ~mask;
381 val |= (p->regval & (mask >> shift)) << shift;
84e690bf 382 *dbg_reg = val;
1da42c34 383
fa89d31c 384 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
84e690bf
AB		 385}
386
281243cb
MZ		 387static void dbg_to_reg(struct kvm_vcpu *vcpu,
388 struct sys_reg_params *p,
1da42c34 389 const struct sys_reg_desc *rd,
281243cb 390 u64 *dbg_reg)
84e690bf 391{
1da42c34
MZ		 392 u64 mask, shift;
393
394 get_access_mask(rd, &mask, &shift);
395 p->regval = (*dbg_reg & mask) >> shift;
84e690bf
AB		 396}
397
281243cb
MZ		 398static bool trap_bvr(struct kvm_vcpu *vcpu,
399 struct sys_reg_params *p,
400 const struct sys_reg_desc *rd)
84e690bf 401{
cb853ded 402 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
84e690bf
AB		 403
404 if (p->is_write)
1da42c34 405 reg_to_dbg(vcpu, p, rd, dbg_reg);
84e690bf 406 else
1da42c34 407 dbg_to_reg(vcpu, p, rd, dbg_reg);
84e690bf 408
cb853ded 409 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
eef8c85a 410
84e690bf
AB		 411 return true;
412}
413
414static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
415 const struct kvm_one_reg *reg, void __user *uaddr)
416{
cb853ded 417 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
84e690bf 418
1713e5aa 419 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 420 return -EFAULT;
421 return 0;
422}
423
424static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
425 const struct kvm_one_reg *reg, void __user *uaddr)
426{
cb853ded 427 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
84e690bf
AB		 428
429 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
430 return -EFAULT;
431 return 0;
432}
433
281243cb
MZ		 434static void reset_bvr(struct kvm_vcpu *vcpu,
435 const struct sys_reg_desc *rd)
84e690bf 436{
cb853ded 437 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
84e690bf
AB		 438}
439
281243cb
MZ		 440static bool trap_bcr(struct kvm_vcpu *vcpu,
441 struct sys_reg_params *p,
442 const struct sys_reg_desc *rd)
84e690bf 443{
cb853ded 444 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
84e690bf
AB		 445
446 if (p->is_write)
1da42c34 447 reg_to_dbg(vcpu, p, rd, dbg_reg);
84e690bf 448 else
1da42c34 449 dbg_to_reg(vcpu, p, rd, dbg_reg);
84e690bf 450
cb853ded 451 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
eef8c85a 452
84e690bf
AB		 453 return true;
454}
455
456static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
457 const struct kvm_one_reg *reg, void __user *uaddr)
458{
cb853ded 459 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
84e690bf 460
1713e5aa 461 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 462 return -EFAULT;
463
464 return 0;
465}
466
467static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
468 const struct kvm_one_reg *reg, void __user *uaddr)
469{
cb853ded 470 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
84e690bf
AB		 471
472 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
473 return -EFAULT;
474 return 0;
475}
476
281243cb
MZ		 477static void reset_bcr(struct kvm_vcpu *vcpu,
478 const struct sys_reg_desc *rd)
84e690bf 479{
cb853ded 480 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
84e690bf
AB		 481}
482
281243cb
MZ		 483static bool trap_wvr(struct kvm_vcpu *vcpu,
484 struct sys_reg_params *p,
485 const struct sys_reg_desc *rd)
84e690bf 486{
cb853ded 487 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
84e690bf
AB		 488
489 if (p->is_write)
1da42c34 490 reg_to_dbg(vcpu, p, rd, dbg_reg);
84e690bf 491 else
1da42c34 492 dbg_to_reg(vcpu, p, rd, dbg_reg);
84e690bf 493
cb853ded
MZ		 494 trace_trap_reg(__func__, rd->CRm, p->is_write,
495 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
eef8c85a 496
84e690bf
AB		 497 return true;
498}
499
500static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
501 const struct kvm_one_reg *reg, void __user *uaddr)
502{
cb853ded 503 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
84e690bf 504
1713e5aa 505 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 506 return -EFAULT;
507 return 0;
508}
509
510static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
511 const struct kvm_one_reg *reg, void __user *uaddr)
512{
cb853ded 513 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
84e690bf
AB		 514
515 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
516 return -EFAULT;
517 return 0;
518}
519
281243cb
MZ		 520static void reset_wvr(struct kvm_vcpu *vcpu,
521 const struct sys_reg_desc *rd)
84e690bf 522{
cb853ded 523 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
84e690bf
AB		 524}
525
281243cb
MZ		 526static bool trap_wcr(struct kvm_vcpu *vcpu,
527 struct sys_reg_params *p,
528 const struct sys_reg_desc *rd)
84e690bf 529{
cb853ded 530 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
84e690bf
AB		 531
532 if (p->is_write)
1da42c34 533 reg_to_dbg(vcpu, p, rd, dbg_reg);
84e690bf 534 else
1da42c34 535 dbg_to_reg(vcpu, p, rd, dbg_reg);
84e690bf 536
cb853ded 537 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
eef8c85a 538
84e690bf
AB		 539 return true;
540}
541
542static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
543 const struct kvm_one_reg *reg, void __user *uaddr)
544{
cb853ded 545 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
84e690bf 546
1713e5aa 547 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 548 return -EFAULT;
549 return 0;
550}
551
552static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
553 const struct kvm_one_reg *reg, void __user *uaddr)
554{
cb853ded 555 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
84e690bf
AB		 556
557 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
558 return -EFAULT;
559 return 0;
560}
561
281243cb
MZ		 562static void reset_wcr(struct kvm_vcpu *vcpu,
563 const struct sys_reg_desc *rd)
84e690bf 564{
cb853ded 565 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
84e690bf
AB		 566}
567
7c8c5e6a
MZ		 568static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
569{
8d404c4c
CD		 570 u64 amair = read_sysreg(amair_el1);
571 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
7c8c5e6a
MZ		 572}
573
af473829
JM		 574static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
575{
576 u64 actlr = read_sysreg(actlr_el1);
577 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
578}
579
7c8c5e6a
MZ		 580static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
581{
4429fc64
AP		 582 u64 mpidr;
583
7c8c5e6a 584 /*
4429fc64
AP		 585 * Map the vcpu_id into the first three affinity level fields of
586 * the MPIDR. We limit the number of VCPUs in level 0 due to a
587 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
588 * of the GICv3 to be able to address each CPU directly when
589 * sending IPIs.
7c8c5e6a 590 */
4429fc64
AP		 591 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
592 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
593 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
8d404c4c 594 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
7c8c5e6a
MZ		 595}
596
11663111
MZ		 597static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
598 const struct sys_reg_desc *r)
599{
600 if (kvm_vcpu_has_pmu(vcpu))
601 return 0;
602
603 return REG_HIDDEN;
604}
605
ab946834
SZ		 606static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
607{
608 u64 pmcr, val;
609
2a5f1b67
MZ		 610 /* No PMU available, PMCR_EL0 may UNDEF... */
611 if (!kvm_arm_support_pmu_v3())
612 return;
613
1f3d8699
MR		 614 pmcr = read_sysreg(pmcr_el0);
615 /*
616 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
ab946834
SZ		 617 * except PMCR.E resetting to zero.
618 */
619 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
620 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
6f163714
MZ		 621 if (!system_supports_32bit_el0())
622 val |= ARMV8_PMU_PMCR_LC;
03fdfb26 623 __vcpu_sys_reg(vcpu, r->reg) = val;
ab946834
SZ		 624}
625
6c007036 626static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
d692b8ad 627{
8d404c4c 628 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
7ded92e2 629 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
d692b8ad 630
24d5950f
MZ		 631 if (!enabled)
632 kvm_inject_undefined(vcpu);
d692b8ad 633
6c007036 634 return !enabled;
d692b8ad
SZ		 635}
636
6c007036 637static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
d692b8ad 638{
6c007036
MZ		 639 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
640}
d692b8ad 641
6c007036
MZ		 642static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
643{
644 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 645}
646
647static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
648{
6c007036 649 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 650}
651
652static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
653{
6c007036 654 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 655}
656
ab946834
SZ		 657static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
658 const struct sys_reg_desc *r)
659{
660 u64 val;
661
d692b8ad
SZ		 662 if (pmu_access_el0_disabled(vcpu))
663 return false;
664
ab946834
SZ		 665 if (p->is_write) {
666 /* Only update writeable bits of PMCR */
8d404c4c 667 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
ab946834
SZ		 668 val &= ~ARMV8_PMU_PMCR_MASK;
669 val |= p->regval & ARMV8_PMU_PMCR_MASK;
6f163714
MZ		 670 if (!system_supports_32bit_el0())
671 val |= ARMV8_PMU_PMCR_LC;
8d404c4c 672 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
76993739 673 kvm_pmu_handle_pmcr(vcpu, val);
435e53fb 674 kvm_vcpu_pmu_restore_guest(vcpu);
ab946834
SZ		 675 } else {
676 /* PMCR.P & PMCR.C are RAZ */
8d404c4c 677 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
ab946834
SZ		 678 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
679 p->regval = val;
680 }
681
682 return true;
683}
684
3965c3ce
SZ		 685static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
686 const struct sys_reg_desc *r)
687{
d692b8ad
SZ		 688 if (pmu_access_event_counter_el0_disabled(vcpu))
689 return false;
690
3965c3ce 691 if (p->is_write)
8d404c4c 692 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
3965c3ce
SZ		 693 else
694 /* return PMSELR.SEL field */
8d404c4c 695 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
3965c3ce
SZ		 696 & ARMV8_PMU_COUNTER_MASK;
697
698 return true;
699}
700
a86b5505
SZ		 701static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
702 const struct sys_reg_desc *r)
703{
99b6a401 704 u64 pmceid, mask, shift;
a86b5505 705
a86b5505
SZ		 706 BUG_ON(p->is_write);
707
d692b8ad
SZ		 708 if (pmu_access_el0_disabled(vcpu))
709 return false;
710
99b6a401
MZ		 711 get_access_mask(r, &mask, &shift);
712
88865bec 713 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
99b6a401
MZ		 714 pmceid &= mask;
715 pmceid >>= shift;
a86b5505
SZ		 716
717 p->regval = pmceid;
718
719 return true;
720}
721
051ff581
SZ		 722static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
723{
724 u64 pmcr, val;
725
8d404c4c 726 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
051ff581 727 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
24d5950f
MZ		 728 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
729 kvm_inject_undefined(vcpu);
051ff581 730 return false;
24d5950f 731 }
051ff581
SZ		 732
733 return true;
734}
735
736static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
737 struct sys_reg_params *p,
738 const struct sys_reg_desc *r)
739{
a3da9358 740 u64 idx = ~0UL;
051ff581
SZ		 741
742 if (r->CRn == 9 && r->CRm == 13) {
743 if (r->Op2 == 2) {
744 /* PMXEVCNTR_EL0 */
d692b8ad
SZ		 745 if (pmu_access_event_counter_el0_disabled(vcpu))
746 return false;
747
8d404c4c 748 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
051ff581
SZ		 749 & ARMV8_PMU_COUNTER_MASK;
750 } else if (r->Op2 == 0) {
751 /* PMCCNTR_EL0 */
d692b8ad
SZ		 752 if (pmu_access_cycle_counter_el0_disabled(vcpu))
753 return false;
754
051ff581 755 idx = ARMV8_PMU_CYCLE_IDX;
051ff581 756 }
9e3f7a29
WH		 757 } else if (r->CRn == 0 && r->CRm == 9) {
758 /* PMCCNTR */
759 if (pmu_access_event_counter_el0_disabled(vcpu))
760 return false;
761
762 idx = ARMV8_PMU_CYCLE_IDX;
051ff581
SZ		 763 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
764 /* PMEVCNTRn_EL0 */
d692b8ad
SZ		 765 if (pmu_access_event_counter_el0_disabled(vcpu))
766 return false;
767
051ff581 768 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
051ff581
SZ		 769 }
770
a3da9358
MZ		 771 /* Catch any decoding mistake */
772 WARN_ON(idx == ~0UL);
773
051ff581
SZ		 774 if (!pmu_counter_idx_valid(vcpu, idx))
775 return false;
776
d692b8ad
SZ		 777 if (p->is_write) {
778 if (pmu_access_el0_disabled(vcpu))
779 return false;
780
051ff581 781 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
d692b8ad 782 } else {
051ff581 783 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
d692b8ad 784 }
051ff581
SZ		 785
786 return true;
787}
788
9feb21ac
SZ		 789static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
790 const struct sys_reg_desc *r)
791{
792 u64 idx, reg;
793
d692b8ad
SZ		 794 if (pmu_access_el0_disabled(vcpu))
795 return false;
796
9feb21ac
SZ		 797 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
798 /* PMXEVTYPER_EL0 */
8d404c4c 799 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
9feb21ac
SZ		 800 reg = PMEVTYPER0_EL0 + idx;
801 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
802 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
803 if (idx == ARMV8_PMU_CYCLE_IDX)
804 reg = PMCCFILTR_EL0;
805 else
806 /* PMEVTYPERn_EL0 */
807 reg = PMEVTYPER0_EL0 + idx;
808 } else {
809 BUG();
810 }
811
812 if (!pmu_counter_idx_valid(vcpu, idx))
813 return false;
814
815 if (p->is_write) {
816 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
8d404c4c 817 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
435e53fb 818 kvm_vcpu_pmu_restore_guest(vcpu);
9feb21ac 819 } else {
8d404c4c 820 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
9feb21ac
SZ		 821 }
822
823 return true;
824}
825
96b0eebc
SZ		 826static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
827 const struct sys_reg_desc *r)
828{
829 u64 val, mask;
830
d692b8ad
SZ		 831 if (pmu_access_el0_disabled(vcpu))
832 return false;
833
96b0eebc
SZ		 834 mask = kvm_pmu_valid_counter_mask(vcpu);
835 if (p->is_write) {
836 val = p->regval & mask;
837 if (r->Op2 & 0x1) {
838 /* accessing PMCNTENSET_EL0 */
8d404c4c 839 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
418e5ca8 840 kvm_pmu_enable_counter_mask(vcpu, val);
435e53fb 841 kvm_vcpu_pmu_restore_guest(vcpu);
96b0eebc
SZ		 842 } else {
843 /* accessing PMCNTENCLR_EL0 */
8d404c4c 844 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
418e5ca8 845 kvm_pmu_disable_counter_mask(vcpu, val);
96b0eebc
SZ		 846 }
847 } else {
8d404c4c 848 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
96b0eebc
SZ		 849 }
850
851 return true;
852}
853
9db52c78
SZ		 854static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
855 const struct sys_reg_desc *r)
856{
857 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
858
b0737e99 859 if (check_pmu_access_disabled(vcpu, 0))
d692b8ad
SZ		 860 return false;
861
9db52c78
SZ		 862 if (p->is_write) {
863 u64 val = p->regval & mask;
864
865 if (r->Op2 & 0x1)
866 /* accessing PMINTENSET_EL1 */
8d404c4c 867 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
9db52c78
SZ		 868 else
869 /* accessing PMINTENCLR_EL1 */
8d404c4c 870 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
9db52c78 871 } else {
8d404c4c 872 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
9db52c78
SZ		 873 }
874
875 return true;
876}
877
76d883c4
SZ		 878static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
879 const struct sys_reg_desc *r)
880{
881 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
882
d692b8ad
SZ		 883 if (pmu_access_el0_disabled(vcpu))
884 return false;
885
76d883c4
SZ		 886 if (p->is_write) {
887 if (r->CRm & 0x2)
888 /* accessing PMOVSSET_EL0 */
8d404c4c 889 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
76d883c4
SZ		 890 else
891 /* accessing PMOVSCLR_EL0 */
8d404c4c 892 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
76d883c4 893 } else {
8d404c4c 894 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
76d883c4
SZ		 895 }
896
897 return true;
898}
899
7a0adc70
SZ		 900static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
901 const struct sys_reg_desc *r)
902{
903 u64 mask;
904
e0443230 905 if (!p->is_write)
e7f1d1ee 906 return read_from_write_only(vcpu, p, r);
e0443230 907
d692b8ad
SZ		 908 if (pmu_write_swinc_el0_disabled(vcpu))
909 return false;
910
e0443230
MZ		 911 mask = kvm_pmu_valid_counter_mask(vcpu);
912 kvm_pmu_software_increment(vcpu, p->regval & mask);
913 return true;
7a0adc70
SZ		 914}
915
d692b8ad
SZ		 916static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
917 const struct sys_reg_desc *r)
918{
d692b8ad 919 if (p->is_write) {
9008c235
MZ		 920 if (!vcpu_mode_priv(vcpu)) {
921 kvm_inject_undefined(vcpu);
d692b8ad 922 return false;
9008c235 923 }
d692b8ad 924
8d404c4c
CD		 925 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
926 p->regval & ARMV8_PMU_USERENR_MASK;
d692b8ad 927 } else {
8d404c4c 928 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
d692b8ad
SZ		 929 & ARMV8_PMU_USERENR_MASK;
930 }
931
932 return true;
933}
934
0c557ed4
MZ		 935/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
936#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
ee1b64e6 937 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
03fdfb26 938 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
ee1b64e6 939 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
03fdfb26 940 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
ee1b64e6 941 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
03fdfb26 942 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
ee1b64e6 943 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
03fdfb26 944 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
0c557ed4 945
11663111
MZ		 946#define PMU_SYS_REG(r) \
947 SYS_DESC(r), .reset = reset_unknown, .visibility = pmu_visibility
948
051ff581
SZ		 949/* Macro to expand the PMEVCNTRn_EL0 register */
950#define PMU_PMEVCNTR_EL0(n) \
11663111
MZ		 951 { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \
952 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
051ff581 953
9feb21ac
SZ		 954/* Macro to expand the PMEVTYPERn_EL0 register */
955#define PMU_PMEVTYPER_EL0(n) \
11663111
MZ		 956 { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \
957 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
9feb21ac 958
338b1793
MZ		 959static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
960 const struct sys_reg_desc *r)
4fcdf106
IV		 961{
962 kvm_inject_undefined(vcpu);
963
964 return false;
965}
966
967/* Macro to expand the AMU counter and type registers*/
338b1793
MZ		 968#define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
969#define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
970#define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
971#define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
384b40ca
MR		 972
973static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
974 const struct sys_reg_desc *rd)
975{
01fe5ace 976 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
384b40ca
MR		 977}
978
338b1793
MZ		 979/*
980 * If we land here on a PtrAuth access, that is because we didn't
981 * fixup the access on exit by allowing the PtrAuth sysregs. The only
982 * way this happens is when the guest does not have PtrAuth support
983 * enabled.
984 */
384b40ca 985#define __PTRAUTH_KEY(k) \
338b1793 986 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
384b40ca
MR		 987 .visibility = ptrauth_visibility}
988
989#define PTRAUTH_KEY(k) \
990 __PTRAUTH_KEY(k ## KEYLO_EL1), \
991 __PTRAUTH_KEY(k ## KEYHI_EL1)
992
84135d3d
AP		 993static bool access_arch_timer(struct kvm_vcpu *vcpu,
994 struct sys_reg_params *p,
995 const struct sys_reg_desc *r)
c9a3c58f 996{
84135d3d
AP		 997 enum kvm_arch_timers tmr;
998 enum kvm_arch_timer_regs treg;
999 u64 reg = reg_to_encoding(r);
7b6b4631 1000
84135d3d
AP		 1001 switch (reg) {
1002 case SYS_CNTP_TVAL_EL0:
1003 case SYS_AARCH32_CNTP_TVAL:
1004 tmr = TIMER_PTIMER;
1005 treg = TIMER_REG_TVAL;
1006 break;
1007 case SYS_CNTP_CTL_EL0:
1008 case SYS_AARCH32_CNTP_CTL:
1009 tmr = TIMER_PTIMER;
1010 treg = TIMER_REG_CTL;
1011 break;
1012 case SYS_CNTP_CVAL_EL0:
1013 case SYS_AARCH32_CNTP_CVAL:
1014 tmr = TIMER_PTIMER;
1015 treg = TIMER_REG_CVAL;
1016 break;
1017 default:
1018 BUG();
c1b135af 1019 }
7b6b4631 1020
7b6b4631 1021 if (p->is_write)
84135d3d 1022 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
7b6b4631 1023 else
84135d3d 1024 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
7b6b4631 1025
c9a3c58f
JL		 1026 return true;
1027}
1028
c8857935
MZ		 1029#define FEATURE(x) (GENMASK_ULL(x##_SHIFT + 3, x##_SHIFT))
1030
93390c0a 1031/* Read a sanitised cpufeature ID register by sys_reg_desc */
1c199913
DM		 1032static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1033 struct sys_reg_desc const *r, bool raz)
93390c0a 1034{
7ba8b438 1035 u32 id = reg_to_encoding(r);
07d79fe7 1036 u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
93390c0a 1037
c8857935
MZ		 1038 switch (id) {
1039 case SYS_ID_AA64PFR0_EL1:
4fcdf106 1040 if (!vcpu_has_sve(vcpu))
c8857935
MZ		 1041 val &= ~FEATURE(ID_AA64PFR0_SVE);
1042 val &= ~FEATURE(ID_AA64PFR0_AMU);
1043 val &= ~FEATURE(ID_AA64PFR0_CSV2);
1044 val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
1045 val &= ~FEATURE(ID_AA64PFR0_CSV3);
1046 val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
1047 break;
1048 case SYS_ID_AA64PFR1_EL1:
1049 val &= ~FEATURE(ID_AA64PFR1_MTE);
ea7fc1bb
SP		 1050 if (kvm_has_mte(vcpu->kvm)) {
1051 u64 pfr, mte;
1052
1053 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
1054 mte = cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR1_MTE_SHIFT);
1055 val |= FIELD_PREP(FEATURE(ID_AA64PFR1_MTE), mte);
1056 }
c8857935
MZ		 1057 break;
1058 case SYS_ID_AA64ISAR1_EL1:
1059 if (!vcpu_has_ptrauth(vcpu))
1060 val &= ~(FEATURE(ID_AA64ISAR1_APA) |
1061 FEATURE(ID_AA64ISAR1_API) |
1062 FEATURE(ID_AA64ISAR1_GPA) |
1063 FEATURE(ID_AA64ISAR1_GPI));
1064 break;
1065 case SYS_ID_AA64DFR0_EL1:
94893fc9
MZ		 1066 /* Limit debug to ARMv8.0 */
1067 val &= ~FEATURE(ID_AA64DFR0_DEBUGVER);
1068 val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6);
46081078 1069 /* Limit guests to PMUv3 for ARMv8.4 */
c854188e 1070 val = cpuid_feature_cap_perfmon_field(val,
c8857935 1071 ID_AA64DFR0_PMUVER_SHIFT,
46081078 1072 kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0);
96f4f680
AE		 1073 /* Hide SPE from guests */
1074 val &= ~FEATURE(ID_AA64DFR0_PMSVER);
c8857935
MZ		 1075 break;
1076 case SYS_ID_DFR0_EL1:
46081078 1077 /* Limit guests to PMUv3 for ARMv8.4 */
c854188e 1078 val = cpuid_feature_cap_perfmon_field(val,
cb959146 1079 ID_DFR0_PERFMON_SHIFT,
46081078 1080 kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
c8857935 1081 break;
07d79fe7
DM		 1082 }
1083
1084 return val;
93390c0a
DM		 1085}
1086
912dee57
AJ		 1087static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1088 const struct sys_reg_desc *r)
1089{
7ba8b438 1090 u32 id = reg_to_encoding(r);
c512298e
AJ		 1091
1092 switch (id) {
1093 case SYS_ID_AA64ZFR0_EL1:
1094 if (!vcpu_has_sve(vcpu))
1095 return REG_RAZ;
1096 break;
1097 }
1098
912dee57
AJ		 1099 return 0;
1100}
1101
93390c0a
DM		 1102/* cpufeature ID register access trap handlers */
1103
1104static bool __access_id_reg(struct kvm_vcpu *vcpu,
1105 struct sys_reg_params *p,
1106 const struct sys_reg_desc *r,
1107 bool raz)
1108{
1109 if (p->is_write)
1110 return write_to_read_only(vcpu, p, r);
1111
1c199913 1112 p->regval = read_id_reg(vcpu, r, raz);
93390c0a
DM		 1113 return true;
1114}
1115
1116static bool access_id_reg(struct kvm_vcpu *vcpu,
1117 struct sys_reg_params *p,
1118 const struct sys_reg_desc *r)
1119{
912dee57
AJ		 1120 bool raz = sysreg_visible_as_raz(vcpu, r);
1121
1122 return __access_id_reg(vcpu, p, r, raz);
93390c0a
DM		 1123}
1124
1125static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1126 struct sys_reg_params *p,
1127 const struct sys_reg_desc *r)
1128{
1129 return __access_id_reg(vcpu, p, r, true);
1130}
1131
1132static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1133static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1134static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1135
73433762
DM		 1136/* Visibility overrides for SVE-specific control registers */
1137static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1138 const struct sys_reg_desc *rd)
1139{
1140 if (vcpu_has_sve(vcpu))
1141 return 0;
1142
01fe5ace 1143 return REG_HIDDEN;
73433762
DM		 1144}
1145
23711a5e
MZ		 1146static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1147 const struct sys_reg_desc *rd,
1148 const struct kvm_one_reg *reg, void __user *uaddr)
1149{
1150 const u64 id = sys_reg_to_index(rd);
4f1df628 1151 u8 csv2, csv3;
23711a5e
MZ		 1152 int err;
1153 u64 val;
23711a5e
MZ		 1154
1155 err = reg_from_user(&val, uaddr, id);
1156 if (err)
1157 return err;
1158
1159 /*
1160 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
1161 * it doesn't promise more than what is actually provided (the
1162 * guest could otherwise be covered in ectoplasmic residue).
1163 */
1164 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT);
1165 if (csv2 > 1 ||
1166 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED))
1167 return -EINVAL;
1168
4f1df628
MZ		 1169 /* Same thing for CSV3 */
1170 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV3_SHIFT);
1171 if (csv3 > 1 ||
1172 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
1173 return -EINVAL;
1174
1175 /* We can only differ with CSV[23], and anything else is an error */
23711a5e 1176 val ^= read_id_reg(vcpu, rd, false);
4f1df628
MZ		 1177 val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) |
1178 (0xFUL << ID_AA64PFR0_CSV3_SHIFT));
23711a5e
MZ		 1179 if (val)
1180 return -EINVAL;
1181
1182 vcpu->kvm->arch.pfr0_csv2 = csv2;
4f1df628 1183 vcpu->kvm->arch.pfr0_csv3 = csv3 ;
23711a5e
MZ		 1184
1185 return 0;
1186}
1187
93390c0a
DM		 1188/*
1189 * cpufeature ID register user accessors
1190 *
1191 * For now, these registers are immutable for userspace, so no values
1192 * are stored, and for set_id_reg() we don't allow the effective value
1193 * to be changed.
1194 */
1c199913
DM		 1195static int __get_id_reg(const struct kvm_vcpu *vcpu,
1196 const struct sys_reg_desc *rd, void __user *uaddr,
93390c0a
DM		 1197 bool raz)
1198{
1199 const u64 id = sys_reg_to_index(rd);
1c199913 1200 const u64 val = read_id_reg(vcpu, rd, raz);
93390c0a
DM		 1201
1202 return reg_to_user(uaddr, &val, id);
1203}
1204
1c199913
DM		 1205static int __set_id_reg(const struct kvm_vcpu *vcpu,
1206 const struct sys_reg_desc *rd, void __user *uaddr,
93390c0a
DM		 1207 bool raz)
1208{
1209 const u64 id = sys_reg_to_index(rd);
1210 int err;
1211 u64 val;
1212
1213 err = reg_from_user(&val, uaddr, id);
1214 if (err)
1215 return err;
1216
1217 /* This is what we mean by invariant: you can't change it. */
1c199913 1218 if (val != read_id_reg(vcpu, rd, raz))
93390c0a
DM		 1219 return -EINVAL;
1220
1221 return 0;
1222}
1223
1224static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1225 const struct kvm_one_reg *reg, void __user *uaddr)
1226{
912dee57
AJ		 1227 bool raz = sysreg_visible_as_raz(vcpu, rd);
1228
1229 return __get_id_reg(vcpu, rd, uaddr, raz);
93390c0a
DM		 1230}
1231
1232static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1233 const struct kvm_one_reg *reg, void __user *uaddr)
1234{
912dee57
AJ		 1235 bool raz = sysreg_visible_as_raz(vcpu, rd);
1236
1237 return __set_id_reg(vcpu, rd, uaddr, raz);
93390c0a
DM		 1238}
1239
1240static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1241 const struct kvm_one_reg *reg, void __user *uaddr)
1242{
1c199913 1243 return __get_id_reg(vcpu, rd, uaddr, true);
93390c0a
DM		 1244}
1245
1246static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1247 const struct kvm_one_reg *reg, void __user *uaddr)
1248{
1c199913 1249 return __set_id_reg(vcpu, rd, uaddr, true);
93390c0a
DM		 1250}
1251
f7f2b15c
AB		 1252static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1253 const struct sys_reg_desc *r)
1254{
1255 if (p->is_write)
1256 return write_to_read_only(vcpu, p, r);
1257
1258 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1259 return true;
1260}
1261
1262static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1263 const struct sys_reg_desc *r)
1264{
1265 if (p->is_write)
1266 return write_to_read_only(vcpu, p, r);
1267
1268 p->regval = read_sysreg(clidr_el1);
1269 return true;
1270}
1271
1272static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1273 const struct sys_reg_desc *r)
1274{
7c582bf4
JM		 1275 int reg = r->reg;
1276
f7f2b15c 1277 if (p->is_write)
7c582bf4 1278 vcpu_write_sys_reg(vcpu, p->regval, reg);
f7f2b15c 1279 else
7c582bf4 1280 p->regval = vcpu_read_sys_reg(vcpu, reg);
f7f2b15c
AB		 1281 return true;
1282}
1283
1284static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1285 const struct sys_reg_desc *r)
1286{
1287 u32 csselr;
1288
1289 if (p->is_write)
1290 return write_to_read_only(vcpu, p, r);
1291
1292 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1293 p->regval = get_ccsidr(csselr);
793acf87
AB		 1294
1295 /*
1296 * Guests should not be doing cache operations by set/way at all, and
1297 * for this reason, we trap them and attempt to infer the intent, so
1298 * that we can flush the entire guest's address space at the appropriate
1299 * time.
1300 * To prevent this trapping from causing performance problems, let's
1301 * expose the geometry of all data and unified caches (which are
1302 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1303 * [If guests should attempt to infer aliasing properties from the
1304 * geometry (which is not permitted by the architecture), they would
1305 * only do so for virtually indexed caches.]
1306 */
1307 if (!(csselr & 1)) // data or unified cache
1308 p->regval &= ~GENMASK(27, 3);
f7f2b15c
AB		 1309 return true;
1310}
1311
93390c0a
DM		 1312/* sys_reg_desc initialiser for known cpufeature ID registers */
1313#define ID_SANITISED(name) { \
1314 SYS_DESC(SYS_##name), \
1315 .access = access_id_reg, \
1316 .get_user = get_id_reg, \
1317 .set_user = set_id_reg, \
912dee57 1318 .visibility = id_visibility, \
93390c0a
DM		 1319}
1320
1321/*
1322 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1323 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1324 * (1 <= crm < 8, 0 <= Op2 < 8).
1325 */
1326#define ID_UNALLOCATED(crm, op2) { \
1327 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1328 .access = access_raz_id_reg, \
1329 .get_user = get_raz_id_reg, \
1330 .set_user = set_raz_id_reg, \
1331}
1332
1333/*
1334 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1335 * For now, these are exposed just like unallocated ID regs: they appear
1336 * RAZ for the guest.
1337 */
1338#define ID_HIDDEN(name) { \
1339 SYS_DESC(SYS_##name), \
1340 .access = access_raz_id_reg, \
1341 .get_user = get_raz_id_reg, \
1342 .set_user = set_raz_id_reg, \
1343}
1344
7c8c5e6a
MZ		 1345/*
1346 * Architected system registers.
1347 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
7609c125 1348 *
0c557ed4
MZ		 1349 * Debug handling: We do trap most, if not all debug related system
1350 * registers. The implementation is good enough to ensure that a guest
1351 * can use these with minimal performance degradation. The drawback is
1352 * that we don't implement any of the external debug, none of the
1353 * OSlock protocol. This should be revisited if we ever encounter a
1354 * more demanding guest...
7c8c5e6a
MZ		 1355 */
1356static const struct sys_reg_desc sys_reg_descs[] = {
7606e078
MR		 1357 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1358 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1359 { SYS_DESC(SYS_DC_CISW), access_dcsw },
7c8c5e6a 1360
0c557ed4
MZ		 1361 DBG_BCR_BVR_WCR_WVR_EL1(0),
1362 DBG_BCR_BVR_WCR_WVR_EL1(1),
ee1b64e6
MR		 1363 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1364 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
0c557ed4
MZ		 1365 DBG_BCR_BVR_WCR_WVR_EL1(2),
1366 DBG_BCR_BVR_WCR_WVR_EL1(3),
1367 DBG_BCR_BVR_WCR_WVR_EL1(4),
1368 DBG_BCR_BVR_WCR_WVR_EL1(5),
1369 DBG_BCR_BVR_WCR_WVR_EL1(6),
1370 DBG_BCR_BVR_WCR_WVR_EL1(7),
1371 DBG_BCR_BVR_WCR_WVR_EL1(8),
1372 DBG_BCR_BVR_WCR_WVR_EL1(9),
1373 DBG_BCR_BVR_WCR_WVR_EL1(10),
1374 DBG_BCR_BVR_WCR_WVR_EL1(11),
1375 DBG_BCR_BVR_WCR_WVR_EL1(12),
1376 DBG_BCR_BVR_WCR_WVR_EL1(13),
1377 DBG_BCR_BVR_WCR_WVR_EL1(14),
1378 DBG_BCR_BVR_WCR_WVR_EL1(15),
1379
ee1b64e6
MR		 1380 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1381 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1382 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1383 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1384 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1385 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1386 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1387 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1388
1389 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1390 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1391 // DBGDTR[TR]X_EL0 share the same encoding
1392 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1393
1394 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
62a89c44 1395
851050a5 1396 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
93390c0a
DM		 1397
1398 /*
1399 * ID regs: all ID_SANITISED() entries here must have corresponding
1400 * entries in arm64_ftr_regs[].
1401 */
1402
1403 /* AArch64 mappings of the AArch32 ID registers */
1404 /* CRm=1 */
1405 ID_SANITISED(ID_PFR0_EL1),
1406 ID_SANITISED(ID_PFR1_EL1),
1407 ID_SANITISED(ID_DFR0_EL1),
1408 ID_HIDDEN(ID_AFR0_EL1),
1409 ID_SANITISED(ID_MMFR0_EL1),
1410 ID_SANITISED(ID_MMFR1_EL1),
1411 ID_SANITISED(ID_MMFR2_EL1),
1412 ID_SANITISED(ID_MMFR3_EL1),
1413
1414 /* CRm=2 */
1415 ID_SANITISED(ID_ISAR0_EL1),
1416 ID_SANITISED(ID_ISAR1_EL1),
1417 ID_SANITISED(ID_ISAR2_EL1),
1418 ID_SANITISED(ID_ISAR3_EL1),
1419 ID_SANITISED(ID_ISAR4_EL1),
1420 ID_SANITISED(ID_ISAR5_EL1),
1421 ID_SANITISED(ID_MMFR4_EL1),
8e3747be 1422 ID_SANITISED(ID_ISAR6_EL1),
93390c0a
DM		 1423
1424 /* CRm=3 */
1425 ID_SANITISED(MVFR0_EL1),
1426 ID_SANITISED(MVFR1_EL1),
1427 ID_SANITISED(MVFR2_EL1),
1428 ID_UNALLOCATED(3,3),
16824085 1429 ID_SANITISED(ID_PFR2_EL1),
dd35ec07 1430 ID_HIDDEN(ID_DFR1_EL1),
152accf8 1431 ID_SANITISED(ID_MMFR5_EL1),
93390c0a
DM		 1432 ID_UNALLOCATED(3,7),
1433
1434 /* AArch64 ID registers */
1435 /* CRm=4 */
23711a5e
MZ		 1436 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
1437 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
93390c0a
DM		 1438 ID_SANITISED(ID_AA64PFR1_EL1),
1439 ID_UNALLOCATED(4,2),
1440 ID_UNALLOCATED(4,3),
c512298e 1441 ID_SANITISED(ID_AA64ZFR0_EL1),
93390c0a
DM		 1442 ID_UNALLOCATED(4,5),
1443 ID_UNALLOCATED(4,6),
1444 ID_UNALLOCATED(4,7),
1445
1446 /* CRm=5 */
1447 ID_SANITISED(ID_AA64DFR0_EL1),
1448 ID_SANITISED(ID_AA64DFR1_EL1),
1449 ID_UNALLOCATED(5,2),
1450 ID_UNALLOCATED(5,3),
1451 ID_HIDDEN(ID_AA64AFR0_EL1),
1452 ID_HIDDEN(ID_AA64AFR1_EL1),
1453 ID_UNALLOCATED(5,6),
1454 ID_UNALLOCATED(5,7),
1455
1456 /* CRm=6 */
1457 ID_SANITISED(ID_AA64ISAR0_EL1),
1458 ID_SANITISED(ID_AA64ISAR1_EL1),
1459 ID_UNALLOCATED(6,2),
1460 ID_UNALLOCATED(6,3),
1461 ID_UNALLOCATED(6,4),
1462 ID_UNALLOCATED(6,5),
1463 ID_UNALLOCATED(6,6),
1464 ID_UNALLOCATED(6,7),
1465
1466 /* CRm=7 */
1467 ID_SANITISED(ID_AA64MMFR0_EL1),
1468 ID_SANITISED(ID_AA64MMFR1_EL1),
1469 ID_SANITISED(ID_AA64MMFR2_EL1),
1470 ID_UNALLOCATED(7,3),
1471 ID_UNALLOCATED(7,4),
1472 ID_UNALLOCATED(7,5),
1473 ID_UNALLOCATED(7,6),
1474 ID_UNALLOCATED(7,7),
1475
851050a5 1476 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
af473829 1477 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
851050a5 1478 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
2ac638fc 1479
338b1793
MZ		 1480 { SYS_DESC(SYS_RGSR_EL1), undef_access },
1481 { SYS_DESC(SYS_GCR_EL1), undef_access },
2ac638fc 1482
73433762 1483 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
cc427cbb 1484 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
851050a5
MR		 1485 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1486 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1487 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1488
384b40ca
MR		 1489 PTRAUTH_KEY(APIA),
1490 PTRAUTH_KEY(APIB),
1491 PTRAUTH_KEY(APDA),
1492 PTRAUTH_KEY(APDB),
1493 PTRAUTH_KEY(APGA),
1494
851050a5
MR		 1495 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1496 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1497 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
558daf69
DG		 1498
1499 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1500 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1501 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1502 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1503 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1504 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1505 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1506 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1507
338b1793
MZ		 1508 { SYS_DESC(SYS_TFSR_EL1), undef_access },
1509 { SYS_DESC(SYS_TFSRE0_EL1), undef_access },
2ac638fc 1510
851050a5
MR		 1511 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1512 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
7c8c5e6a 1513
13611bc8
AE		 1514 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
1515 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
1516 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
1517 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
1518 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
1519 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
1520 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
1521 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
1522 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
1523 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
1524 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
1525 /* PMBIDR_EL1 is not trapped */
1526
11663111
MZ		 1527 { PMU_SYS_REG(SYS_PMINTENSET_EL1),
1528 .access = access_pminten, .reg = PMINTENSET_EL1 },
1529 { PMU_SYS_REG(SYS_PMINTENCLR_EL1),
1530 .access = access_pminten, .reg = PMINTENSET_EL1 },
46081078 1531 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
7c8c5e6a 1532
851050a5
MR		 1533 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1534 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
7c8c5e6a 1535
22925521
MZ		 1536 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1537 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1538 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1539 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1540 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
cc33c4e2 1541
851050a5 1542 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
c773ae2b 1543 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
db7dedd0 1544
7b1dba1f 1545 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
e7f1d1ee 1546 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
7b1dba1f 1547 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
e7f1d1ee 1548 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
7b1dba1f 1549 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
e804d208 1550 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
03bd646d
MZ		 1551 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1552 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
7b1dba1f 1553 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
e7f1d1ee 1554 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
7b1dba1f 1555 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
e804d208 1556 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
db7dedd0 1557
851050a5
MR		 1558 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1559 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
7c8c5e6a 1560
ed4ffaf4
MZ		 1561 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
1562
851050a5 1563 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
7c8c5e6a 1564
f7f2b15c
AB		 1565 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1566 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1567 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1568 { SYS_DESC(SYS_CTR_EL0), access_ctr },
7c8c5e6a 1569
11663111
MZ		 1570 { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr,
1571 .reset = reset_pmcr, .reg = PMCR_EL0 },
1572 { PMU_SYS_REG(SYS_PMCNTENSET_EL0),
1573 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1574 { PMU_SYS_REG(SYS_PMCNTENCLR_EL0),
1575 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1576 { PMU_SYS_REG(SYS_PMOVSCLR_EL0),
1577 .access = access_pmovs, .reg = PMOVSSET_EL0 },
1578 { PMU_SYS_REG(SYS_PMSWINC_EL0),
1579 .access = access_pmswinc, .reg = PMSWINC_EL0 },
1580 { PMU_SYS_REG(SYS_PMSELR_EL0),
1581 .access = access_pmselr, .reg = PMSELR_EL0 },
1582 { PMU_SYS_REG(SYS_PMCEID0_EL0),
1583 .access = access_pmceid, .reset = NULL },
1584 { PMU_SYS_REG(SYS_PMCEID1_EL0),
1585 .access = access_pmceid, .reset = NULL },
1586 { PMU_SYS_REG(SYS_PMCCNTR_EL0),
1587 .access = access_pmu_evcntr, .reg = PMCCNTR_EL0 },
1588 { PMU_SYS_REG(SYS_PMXEVTYPER_EL0),
1589 .access = access_pmu_evtyper, .reset = NULL },
1590 { PMU_SYS_REG(SYS_PMXEVCNTR_EL0),
1591 .access = access_pmu_evcntr, .reset = NULL },
174ed3e4
MR		 1592 /*
1593 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
d692b8ad
SZ		 1594 * in 32bit mode. Here we choose to reset it as zero for consistency.
1595 */
11663111
MZ		 1596 { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr,
1597 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
1598 { PMU_SYS_REG(SYS_PMOVSSET_EL0),
1599 .access = access_pmovs, .reg = PMOVSSET_EL0 },
7c8c5e6a 1600
851050a5
MR		 1601 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1602 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
4fcdf106 1603
ed4ffaf4
MZ		 1604 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
1605
338b1793
MZ		 1606 { SYS_DESC(SYS_AMCR_EL0), undef_access },
1607 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
1608 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
1609 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
1610 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
1611 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
1612 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
1613 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
4fcdf106
IV		 1614 AMU_AMEVCNTR0_EL0(0),
1615 AMU_AMEVCNTR0_EL0(1),
1616 AMU_AMEVCNTR0_EL0(2),
1617 AMU_AMEVCNTR0_EL0(3),
1618 AMU_AMEVCNTR0_EL0(4),
1619 AMU_AMEVCNTR0_EL0(5),
1620 AMU_AMEVCNTR0_EL0(6),
1621 AMU_AMEVCNTR0_EL0(7),
1622 AMU_AMEVCNTR0_EL0(8),
1623 AMU_AMEVCNTR0_EL0(9),
1624 AMU_AMEVCNTR0_EL0(10),
1625 AMU_AMEVCNTR0_EL0(11),
1626 AMU_AMEVCNTR0_EL0(12),
1627 AMU_AMEVCNTR0_EL0(13),
1628 AMU_AMEVCNTR0_EL0(14),
1629 AMU_AMEVCNTR0_EL0(15),
493cf9b7
VM		 1630 AMU_AMEVTYPER0_EL0(0),
1631 AMU_AMEVTYPER0_EL0(1),
1632 AMU_AMEVTYPER0_EL0(2),
1633 AMU_AMEVTYPER0_EL0(3),
1634 AMU_AMEVTYPER0_EL0(4),
1635 AMU_AMEVTYPER0_EL0(5),
1636 AMU_AMEVTYPER0_EL0(6),
1637 AMU_AMEVTYPER0_EL0(7),
1638 AMU_AMEVTYPER0_EL0(8),
1639 AMU_AMEVTYPER0_EL0(9),
1640 AMU_AMEVTYPER0_EL0(10),
1641 AMU_AMEVTYPER0_EL0(11),
1642 AMU_AMEVTYPER0_EL0(12),
1643 AMU_AMEVTYPER0_EL0(13),
1644 AMU_AMEVTYPER0_EL0(14),
1645 AMU_AMEVTYPER0_EL0(15),
4fcdf106
IV		 1646 AMU_AMEVCNTR1_EL0(0),
1647 AMU_AMEVCNTR1_EL0(1),
1648 AMU_AMEVCNTR1_EL0(2),
1649 AMU_AMEVCNTR1_EL0(3),
1650 AMU_AMEVCNTR1_EL0(4),
1651 AMU_AMEVCNTR1_EL0(5),
1652 AMU_AMEVCNTR1_EL0(6),
1653 AMU_AMEVCNTR1_EL0(7),
1654 AMU_AMEVCNTR1_EL0(8),
1655 AMU_AMEVCNTR1_EL0(9),
1656 AMU_AMEVCNTR1_EL0(10),
1657 AMU_AMEVCNTR1_EL0(11),
1658 AMU_AMEVCNTR1_EL0(12),
1659 AMU_AMEVCNTR1_EL0(13),
1660 AMU_AMEVCNTR1_EL0(14),
1661 AMU_AMEVCNTR1_EL0(15),
493cf9b7
VM		 1662 AMU_AMEVTYPER1_EL0(0),
1663 AMU_AMEVTYPER1_EL0(1),
1664 AMU_AMEVTYPER1_EL0(2),
1665 AMU_AMEVTYPER1_EL0(3),
1666 AMU_AMEVTYPER1_EL0(4),
1667 AMU_AMEVTYPER1_EL0(5),
1668 AMU_AMEVTYPER1_EL0(6),
1669 AMU_AMEVTYPER1_EL0(7),
1670 AMU_AMEVTYPER1_EL0(8),
1671 AMU_AMEVTYPER1_EL0(9),
1672 AMU_AMEVTYPER1_EL0(10),
1673 AMU_AMEVTYPER1_EL0(11),
1674 AMU_AMEVTYPER1_EL0(12),
1675 AMU_AMEVTYPER1_EL0(13),
1676 AMU_AMEVTYPER1_EL0(14),
1677 AMU_AMEVTYPER1_EL0(15),
62a89c44 1678
84135d3d
AP		 1679 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1680 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1681 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
c9a3c58f 1682
051ff581
SZ		 1683 /* PMEVCNTRn_EL0 */
1684 PMU_PMEVCNTR_EL0(0),
1685 PMU_PMEVCNTR_EL0(1),
1686 PMU_PMEVCNTR_EL0(2),
1687 PMU_PMEVCNTR_EL0(3),
1688 PMU_PMEVCNTR_EL0(4),
1689 PMU_PMEVCNTR_EL0(5),
1690 PMU_PMEVCNTR_EL0(6),
1691 PMU_PMEVCNTR_EL0(7),
1692 PMU_PMEVCNTR_EL0(8),
1693 PMU_PMEVCNTR_EL0(9),
1694 PMU_PMEVCNTR_EL0(10),
1695 PMU_PMEVCNTR_EL0(11),
1696 PMU_PMEVCNTR_EL0(12),
1697 PMU_PMEVCNTR_EL0(13),
1698 PMU_PMEVCNTR_EL0(14),
1699 PMU_PMEVCNTR_EL0(15),
1700 PMU_PMEVCNTR_EL0(16),
1701 PMU_PMEVCNTR_EL0(17),
1702 PMU_PMEVCNTR_EL0(18),
1703 PMU_PMEVCNTR_EL0(19),
1704 PMU_PMEVCNTR_EL0(20),
1705 PMU_PMEVCNTR_EL0(21),
1706 PMU_PMEVCNTR_EL0(22),
1707 PMU_PMEVCNTR_EL0(23),
1708 PMU_PMEVCNTR_EL0(24),
1709 PMU_PMEVCNTR_EL0(25),
1710 PMU_PMEVCNTR_EL0(26),
1711 PMU_PMEVCNTR_EL0(27),
1712 PMU_PMEVCNTR_EL0(28),
1713 PMU_PMEVCNTR_EL0(29),
1714 PMU_PMEVCNTR_EL0(30),
9feb21ac
SZ		 1715 /* PMEVTYPERn_EL0 */
1716 PMU_PMEVTYPER_EL0(0),
1717 PMU_PMEVTYPER_EL0(1),
1718 PMU_PMEVTYPER_EL0(2),
1719 PMU_PMEVTYPER_EL0(3),
1720 PMU_PMEVTYPER_EL0(4),
1721 PMU_PMEVTYPER_EL0(5),
1722 PMU_PMEVTYPER_EL0(6),
1723 PMU_PMEVTYPER_EL0(7),
1724 PMU_PMEVTYPER_EL0(8),
1725 PMU_PMEVTYPER_EL0(9),
1726 PMU_PMEVTYPER_EL0(10),
1727 PMU_PMEVTYPER_EL0(11),
1728 PMU_PMEVTYPER_EL0(12),
1729 PMU_PMEVTYPER_EL0(13),
1730 PMU_PMEVTYPER_EL0(14),
1731 PMU_PMEVTYPER_EL0(15),
1732 PMU_PMEVTYPER_EL0(16),
1733 PMU_PMEVTYPER_EL0(17),
1734 PMU_PMEVTYPER_EL0(18),
1735 PMU_PMEVTYPER_EL0(19),
1736 PMU_PMEVTYPER_EL0(20),
1737 PMU_PMEVTYPER_EL0(21),
1738 PMU_PMEVTYPER_EL0(22),
1739 PMU_PMEVTYPER_EL0(23),
1740 PMU_PMEVTYPER_EL0(24),
1741 PMU_PMEVTYPER_EL0(25),
1742 PMU_PMEVTYPER_EL0(26),
1743 PMU_PMEVTYPER_EL0(27),
1744 PMU_PMEVTYPER_EL0(28),
1745 PMU_PMEVTYPER_EL0(29),
1746 PMU_PMEVTYPER_EL0(30),
174ed3e4
MR		 1747 /*
1748 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
9feb21ac
SZ		 1749 * in 32bit mode. Here we choose to reset it as zero for consistency.
1750 */
11663111
MZ		 1751 { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper,
1752 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
051ff581 1753
851050a5
MR		 1754 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1755 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
c88b0936 1756 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
62a89c44
MZ		 1757};
1758
8c358b29 1759static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
3fec037d 1760 struct sys_reg_params *p,
bdfb4b38
MZ		 1761 const struct sys_reg_desc *r)
1762{
1763 if (p->is_write) {
1764 return ignore_write(vcpu, p);
1765 } else {
46823dd1
DM		 1766 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1767 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
28c5dcb2 1768 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
bdfb4b38 1769
2ec5be3d
PF		 1770 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1771 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1772 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
bea7e97f 1773 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12));
bdfb4b38
MZ		 1774 return true;
1775 }
1776}
1777
1da42c34
MZ		 1778/*
1779 * AArch32 debug register mappings
84e690bf
AB		 1780 *
1781 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1782 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1783 *
1da42c34
MZ		 1784 * None of the other registers share their location, so treat them as
1785 * if they were 64bit.
84e690bf 1786 */
1da42c34
MZ		 1787#define DBG_BCR_BVR_WCR_WVR(n) \
1788 /* DBGBVRn */ \
1789 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1790 /* DBGBCRn */ \
1791 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1792 /* DBGWVRn */ \
1793 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1794 /* DBGWCRn */ \
84e690bf
AB		 1795 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1796
1da42c34
MZ		 1797#define DBGBXVR(n) \
1798 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
bdfb4b38
MZ		 1799
1800/*
1801 * Trapped cp14 registers. We generally ignore most of the external
1802 * debug, on the principle that they don't really make sense to a
84e690bf 1803 * guest. Revisit this one day, would this principle change.
bdfb4b38 1804 */
72564016 1805static const struct sys_reg_desc cp14_regs[] = {
8c358b29
AE		 1806 /* DBGDIDR */
1807 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
bdfb4b38
MZ		 1808 /* DBGDTRRXext */
1809 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1810
1811 DBG_BCR_BVR_WCR_WVR(0),
1812 /* DBGDSCRint */
1813 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1814 DBG_BCR_BVR_WCR_WVR(1),
1815 /* DBGDCCINT */
1da42c34 1816 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
bdfb4b38 1817 /* DBGDSCRext */
1da42c34 1818 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
bdfb4b38
MZ		 1819 DBG_BCR_BVR_WCR_WVR(2),
1820 /* DBGDTR[RT]Xint */
1821 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1822 /* DBGDTR[RT]Xext */
1823 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1824 DBG_BCR_BVR_WCR_WVR(3),
1825 DBG_BCR_BVR_WCR_WVR(4),
1826 DBG_BCR_BVR_WCR_WVR(5),
1827 /* DBGWFAR */
1828 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1829 /* DBGOSECCR */
1830 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1831 DBG_BCR_BVR_WCR_WVR(6),
1832 /* DBGVCR */
1da42c34 1833 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
bdfb4b38
MZ		 1834 DBG_BCR_BVR_WCR_WVR(7),
1835 DBG_BCR_BVR_WCR_WVR(8),
1836 DBG_BCR_BVR_WCR_WVR(9),
1837 DBG_BCR_BVR_WCR_WVR(10),
1838 DBG_BCR_BVR_WCR_WVR(11),
1839 DBG_BCR_BVR_WCR_WVR(12),
1840 DBG_BCR_BVR_WCR_WVR(13),
1841 DBG_BCR_BVR_WCR_WVR(14),
1842 DBG_BCR_BVR_WCR_WVR(15),
1843
1844 /* DBGDRAR (32bit) */
1845 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1846
1847 DBGBXVR(0),
1848 /* DBGOSLAR */
1849 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1850 DBGBXVR(1),
1851 /* DBGOSLSR */
1852 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1853 DBGBXVR(2),
1854 DBGBXVR(3),
1855 /* DBGOSDLR */
1856 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1857 DBGBXVR(4),
1858 /* DBGPRCR */
1859 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1860 DBGBXVR(5),
1861 DBGBXVR(6),
1862 DBGBXVR(7),
1863 DBGBXVR(8),
1864 DBGBXVR(9),
1865 DBGBXVR(10),
1866 DBGBXVR(11),
1867 DBGBXVR(12),
1868 DBGBXVR(13),
1869 DBGBXVR(14),
1870 DBGBXVR(15),
1871
1872 /* DBGDSAR (32bit) */
1873 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1874
1875 /* DBGDEVID2 */
1876 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1877 /* DBGDEVID1 */
1878 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1879 /* DBGDEVID */
1880 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1881 /* DBGCLAIMSET */
1882 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1883 /* DBGCLAIMCLR */
1884 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1885 /* DBGAUTHSTATUS */
1886 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
72564016
MZ		 1887};
1888
a9866ba0
MZ		 1889/* Trapped cp14 64bit registers */
1890static const struct sys_reg_desc cp14_64_regs[] = {
bdfb4b38
MZ		 1891 /* DBGDRAR (64bit) */
1892 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1893
1894 /* DBGDSAR (64bit) */
1895 { Op1( 0), CRm( 2), .access = trap_raz_wi },
a9866ba0
MZ		 1896};
1897
051ff581
SZ		 1898/* Macro to expand the PMEVCNTRn register */
1899#define PMU_PMEVCNTR(n) \
1900 /* PMEVCNTRn */ \
1901 { Op1(0), CRn(0b1110), \
1902 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1903 access_pmu_evcntr }
1904
9feb21ac
SZ		 1905/* Macro to expand the PMEVTYPERn register */
1906#define PMU_PMEVTYPER(n) \
1907 /* PMEVTYPERn */ \
1908 { Op1(0), CRn(0b1110), \
1909 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1910 access_pmu_evtyper }
1911
4d44923b
MZ		 1912/*
1913 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1914 * depending on the way they are accessed (as a 32bit or a 64bit
1915 * register).
1916 */
62a89c44 1917static const struct sys_reg_desc cp15_regs[] = {
f7f2b15c 1918 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
b1ea1d76
MZ		 1919 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
1920 /* ACTLR */
1921 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
1922 /* ACTLR2 */
1923 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
1924 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
1925 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
1926 /* TTBCR */
1927 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
1928 /* TTBCR2 */
1929 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
1930 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
1931 /* DFSR */
1932 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
1933 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
1934 /* ADFSR */
1935 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
1936 /* AIFSR */
1937 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
1938 /* DFAR */
1939 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
1940 /* IFAR */
1941 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
4d44923b 1942
62a89c44
MZ		 1943 /*
1944 * DC{C,I,CI}SW operations:
1945 */
1946 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1947 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1948 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
4d44923b 1949
7609c125 1950 /* PMU */
ab946834 1951 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
96b0eebc
SZ		 1952 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1953 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
76d883c4 1954 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
7a0adc70 1955 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
3965c3ce 1956 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
99b6a401
MZ		 1957 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1958 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
051ff581 1959 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
9feb21ac 1960 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
051ff581 1961 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
d692b8ad 1962 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
9db52c78
SZ		 1963 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1964 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
76d883c4 1965 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
99b6a401
MZ		 1966 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid },
1967 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid },
46081078
MZ		 1968 /* PMMIR */
1969 { Op1( 0), CRn( 9), CRm(14), Op2( 6), trap_raz_wi },
4d44923b 1970
b1ea1d76
MZ		 1971 /* PRRR/MAIR0 */
1972 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
1973 /* NMRR/MAIR1 */
1974 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
1975 /* AMAIR0 */
1976 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
1977 /* AMAIR1 */
1978 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
db7dedd0
CD		 1979
1980 /* ICC_SRE */
f7f6f2d9 1981 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
db7dedd0 1982
b1ea1d76 1983 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
051ff581 1984
84135d3d
AP		 1985 /* Arch Tmers */
1986 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
1987 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
eac137b4 1988
051ff581
SZ		 1989 /* PMEVCNTRn */
1990 PMU_PMEVCNTR(0),
1991 PMU_PMEVCNTR(1),
1992 PMU_PMEVCNTR(2),
1993 PMU_PMEVCNTR(3),
1994 PMU_PMEVCNTR(4),
1995 PMU_PMEVCNTR(5),
1996 PMU_PMEVCNTR(6),
1997 PMU_PMEVCNTR(7),
1998 PMU_PMEVCNTR(8),
1999 PMU_PMEVCNTR(9),
2000 PMU_PMEVCNTR(10),
2001 PMU_PMEVCNTR(11),
2002 PMU_PMEVCNTR(12),
2003 PMU_PMEVCNTR(13),
2004 PMU_PMEVCNTR(14),
2005 PMU_PMEVCNTR(15),
2006 PMU_PMEVCNTR(16),
2007 PMU_PMEVCNTR(17),
2008 PMU_PMEVCNTR(18),
2009 PMU_PMEVCNTR(19),
2010 PMU_PMEVCNTR(20),
2011 PMU_PMEVCNTR(21),
2012 PMU_PMEVCNTR(22),
2013 PMU_PMEVCNTR(23),
2014 PMU_PMEVCNTR(24),
2015 PMU_PMEVCNTR(25),
2016 PMU_PMEVCNTR(26),
2017 PMU_PMEVCNTR(27),
2018 PMU_PMEVCNTR(28),
2019 PMU_PMEVCNTR(29),
2020 PMU_PMEVCNTR(30),
9feb21ac
SZ		 2021 /* PMEVTYPERn */
2022 PMU_PMEVTYPER(0),
2023 PMU_PMEVTYPER(1),
2024 PMU_PMEVTYPER(2),
2025 PMU_PMEVTYPER(3),
2026 PMU_PMEVTYPER(4),
2027 PMU_PMEVTYPER(5),
2028 PMU_PMEVTYPER(6),
2029 PMU_PMEVTYPER(7),
2030 PMU_PMEVTYPER(8),
2031 PMU_PMEVTYPER(9),
2032 PMU_PMEVTYPER(10),
2033 PMU_PMEVTYPER(11),
2034 PMU_PMEVTYPER(12),
2035 PMU_PMEVTYPER(13),
2036 PMU_PMEVTYPER(14),
2037 PMU_PMEVTYPER(15),
2038 PMU_PMEVTYPER(16),
2039 PMU_PMEVTYPER(17),
2040 PMU_PMEVTYPER(18),
2041 PMU_PMEVTYPER(19),
2042 PMU_PMEVTYPER(20),
2043 PMU_PMEVTYPER(21),
2044 PMU_PMEVTYPER(22),
2045 PMU_PMEVTYPER(23),
2046 PMU_PMEVTYPER(24),
2047 PMU_PMEVTYPER(25),
2048 PMU_PMEVTYPER(26),
2049 PMU_PMEVTYPER(27),
2050 PMU_PMEVTYPER(28),
2051 PMU_PMEVTYPER(29),
2052 PMU_PMEVTYPER(30),
2053 /* PMCCFILTR */
2054 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
f7f2b15c
AB		 2055
2056 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2057 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
b1ea1d76 2058 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
a9866ba0
MZ		 2059};
2060
2061static const struct sys_reg_desc cp15_64_regs[] = {
b1ea1d76 2062 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
051ff581 2063 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
03bd646d 2064 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
b1ea1d76 2065 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
03bd646d
MZ		 2066 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2067 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
84135d3d 2068 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
7c8c5e6a
MZ		 2069};
2070
bb44a8db
MZ		 2071static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2072 bool is_32)
2073{
2074 unsigned int i;
2075
2076 for (i = 0; i < n; i++) {
2077 if (!is_32 && table[i].reg && !table[i].reset) {
2078 kvm_err("sys_reg table %p entry %d has lacks reset\n",
2079 table, i);
2080 return 1;
2081 }
2082
2083 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2084 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2085 return 1;
2086 }
2087 }
2088
2089 return 0;
2090}
2091
623eefa8
MZ		 2092static int match_sys_reg(const void *key, const void *elt)
2093{
2094 const unsigned long pval = (unsigned long)key;
2095 const struct sys_reg_desc *r = elt;
2096
09838de9 2097 return pval - reg_to_encoding(r);
623eefa8
MZ		 2098}
2099
7c8c5e6a
MZ		 2100static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
2101 const struct sys_reg_desc table[],
2102 unsigned int num)
2103{
09838de9 2104 unsigned long pval = reg_to_encoding(params);
623eefa8
MZ		 2105
2106 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
7c8c5e6a
MZ		 2107}
2108
74cc7e0c 2109int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
62a89c44
MZ		 2110{
2111 kvm_inject_undefined(vcpu);
2112 return 1;
2113}
2114
e70b9522
MZ		 2115static void perform_access(struct kvm_vcpu *vcpu,
2116 struct sys_reg_params *params,
2117 const struct sys_reg_desc *r)
2118{
599d79dc
MZ		 2119 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2120
7f34e409 2121 /* Check for regs disabled by runtime config */
01fe5ace 2122 if (sysreg_hidden(vcpu, r)) {
7f34e409
DM		 2123 kvm_inject_undefined(vcpu);
2124 return;
2125 }
2126
e70b9522
MZ		 2127 /*
2128 * Not having an accessor means that we have configured a trap
2129 * that we don't know how to handle. This certainly qualifies
2130 * as a gross bug that should be fixed right away.
2131 */
2132 BUG_ON(!r->access);
2133
2134 /* Skip instruction if instructed so */
2135 if (likely(r->access(vcpu, params, r)))
cdb5e02e 2136 kvm_incr_pc(vcpu);
e70b9522
MZ		 2137}
2138
72564016
MZ		 2139/*
2140 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2141 * call the corresponding trap handler.
2142 *
2143 * @params: pointer to the descriptor of the access
2144 * @table: array of trap descriptors
2145 * @num: size of the trap descriptor array
2146 *
2147 * Return 0 if the access has been handled, and -1 if not.
2148 */
2149static int emulate_cp(struct kvm_vcpu *vcpu,
3fec037d 2150 struct sys_reg_params *params,
72564016
MZ		 2151 const struct sys_reg_desc *table,
2152 size_t num)
62a89c44 2153{
72564016 2154 const struct sys_reg_desc *r;
62a89c44 2155
72564016
MZ		 2156 if (!table)
2157 return -1; /* Not handled */
62a89c44 2158
62a89c44 2159 r = find_reg(params, table, num);
62a89c44 2160
72564016 2161 if (r) {
e70b9522
MZ		 2162 perform_access(vcpu, params, r);
2163 return 0;
72564016
MZ		 2164 }
2165
2166 /* Not handled */
2167 return -1;
2168}
2169
2170static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2171 struct sys_reg_params *params)
2172{
3a949f4c 2173 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
40c4f8d2 2174 int cp = -1;
72564016 2175
3a949f4c 2176 switch (esr_ec) {
c6d01a94
MR		 2177 case ESR_ELx_EC_CP15_32:
2178 case ESR_ELx_EC_CP15_64:
72564016
MZ		 2179 cp = 15;
2180 break;
c6d01a94
MR		 2181 case ESR_ELx_EC_CP14_MR:
2182 case ESR_ELx_EC_CP14_64:
72564016
MZ		 2183 cp = 14;
2184 break;
2185 default:
40c4f8d2 2186 WARN_ON(1);
62a89c44
MZ		 2187 }
2188
bf4b96bb
MR		 2189 print_sys_reg_msg(params,
2190 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2191 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
62a89c44
MZ		 2192 kvm_inject_undefined(vcpu);
2193}
2194
2195/**
7769db90 2196 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
62a89c44
MZ		 2197 * @vcpu: The VCPU pointer
2198 * @run: The kvm_run struct
2199 */
72564016
MZ		 2200static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2201 const struct sys_reg_desc *global,
dcaffa7b 2202 size_t nr_global)
62a89c44
MZ		 2203{
2204 struct sys_reg_params params;
3a949f4c 2205 u32 esr = kvm_vcpu_get_esr(vcpu);
c667186f 2206 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3a949f4c 2207 int Rt2 = (esr >> 10) & 0x1f;
62a89c44 2208
3a949f4c
GS		 2209 params.CRm = (esr >> 1) & 0xf;
2210 params.is_write = ((esr & 1) == 0);
62a89c44
MZ		 2211
2212 params.Op0 = 0;
3a949f4c 2213 params.Op1 = (esr >> 16) & 0xf;
62a89c44
MZ		 2214 params.Op2 = 0;
2215 params.CRn = 0;
2216
2217 /*
2ec5be3d 2218 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
62a89c44
MZ		 2219 * backends between AArch32 and AArch64, we get away with it.
2220 */
2221 if (params.is_write) {
2ec5be3d
PF		 2222 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2223 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
62a89c44
MZ		 2224 }
2225
b6b7a806 2226 /*
dcaffa7b 2227 * If the table contains a handler, handle the
b6b7a806
MZ		 2228 * potential register operation in the case of a read and return
2229 * with success.
2230 */
dcaffa7b 2231 if (!emulate_cp(vcpu, &params, global, nr_global)) {
b6b7a806
MZ		 2232 /* Split up the value between registers for the read side */
2233 if (!params.is_write) {
2234 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2235 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2236 }
62a89c44 2237
b6b7a806 2238 return 1;
62a89c44
MZ		 2239 }
2240
b6b7a806 2241 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 2242 return 1;
2243}
2244
2245/**
7769db90 2246 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
62a89c44
MZ		 2247 * @vcpu: The VCPU pointer
2248 * @run: The kvm_run struct
2249 */
72564016
MZ		 2250static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2251 const struct sys_reg_desc *global,
dcaffa7b 2252 size_t nr_global)
62a89c44
MZ		 2253{
2254 struct sys_reg_params params;
3a949f4c 2255 u32 esr = kvm_vcpu_get_esr(vcpu);
c667186f 2256 int Rt = kvm_vcpu_sys_get_rt(vcpu);
62a89c44 2257
3a949f4c 2258 params.CRm = (esr >> 1) & 0xf;
2ec5be3d 2259 params.regval = vcpu_get_reg(vcpu, Rt);
3a949f4c
GS		 2260 params.is_write = ((esr & 1) == 0);
2261 params.CRn = (esr >> 10) & 0xf;
62a89c44 2262 params.Op0 = 0;
3a949f4c
GS		 2263 params.Op1 = (esr >> 14) & 0x7;
2264 params.Op2 = (esr >> 17) & 0x7;
62a89c44 2265
dcaffa7b 2266 if (!emulate_cp(vcpu, &params, global, nr_global)) {
2ec5be3d
PF		 2267 if (!params.is_write)
2268 vcpu_set_reg(vcpu, Rt, params.regval);
72564016 2269 return 1;
2ec5be3d 2270 }
72564016
MZ		 2271
2272 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 2273 return 1;
2274}
2275
74cc7e0c 2276int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
72564016 2277{
dcaffa7b 2278 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
72564016
MZ		 2279}
2280
74cc7e0c 2281int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
72564016 2282{
dcaffa7b 2283 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
72564016
MZ		 2284}
2285
74cc7e0c 2286int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
72564016 2287{
dcaffa7b 2288 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
72564016
MZ		 2289}
2290
74cc7e0c 2291int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
72564016 2292{
dcaffa7b 2293 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs));
72564016
MZ		 2294}
2295
54ad68b7
MR		 2296static bool is_imp_def_sys_reg(struct sys_reg_params *params)
2297{
2298 // See ARM DDI 0487E.a, section D12.3.2
2299 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
2300}
2301
7c8c5e6a 2302static int emulate_sys_reg(struct kvm_vcpu *vcpu,
3fec037d 2303 struct sys_reg_params *params)
7c8c5e6a 2304{
dcaffa7b 2305 const struct sys_reg_desc *r;
7c8c5e6a 2306
dcaffa7b 2307 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
7c8c5e6a
MZ		 2308
2309 if (likely(r)) {
e70b9522 2310 perform_access(vcpu, params, r);
54ad68b7
MR		 2311 } else if (is_imp_def_sys_reg(params)) {
2312 kvm_inject_undefined(vcpu);
7c8c5e6a 2313 } else {
bf4b96bb
MR		 2314 print_sys_reg_msg(params,
2315 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
2316 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
e70b9522 2317 kvm_inject_undefined(vcpu);
7c8c5e6a 2318 }
7c8c5e6a
MZ		 2319 return 1;
2320}
2321
750ed566
JM		 2322/**
2323 * kvm_reset_sys_regs - sets system registers to reset value
2324 * @vcpu: The VCPU pointer
2325 *
2326 * This function finds the right table above and sets the registers on the
2327 * virtual CPU struct to their architecturally defined reset values.
2328 */
2329void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
7c8c5e6a
MZ		 2330{
2331 unsigned long i;
2332
750ed566
JM		 2333 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++)
2334 if (sys_reg_descs[i].reset)
2335 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]);
7c8c5e6a
MZ		 2336}
2337
2338/**
2339 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2340 * @vcpu: The VCPU pointer
7c8c5e6a 2341 */
74cc7e0c 2342int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
7c8c5e6a
MZ		 2343{
2344 struct sys_reg_params params;
3a949f4c 2345 unsigned long esr = kvm_vcpu_get_esr(vcpu);
c667186f 2346 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2ec5be3d 2347 int ret;
7c8c5e6a 2348
eef8c85a
AB		 2349 trace_kvm_handle_sys_reg(esr);
2350
7c8c5e6a
MZ		 2351 params.Op0 = (esr >> 20) & 3;
2352 params.Op1 = (esr >> 14) & 0x7;
2353 params.CRn = (esr >> 10) & 0xf;
2354 params.CRm = (esr >> 1) & 0xf;
2355 params.Op2 = (esr >> 17) & 0x7;
2ec5be3d 2356 params.regval = vcpu_get_reg(vcpu, Rt);
7c8c5e6a
MZ		 2357 params.is_write = !(esr & 1);
2358
2ec5be3d
PF		 2359 ret = emulate_sys_reg(vcpu, &params);
2360
2361 if (!params.is_write)
2362 vcpu_set_reg(vcpu, Rt, params.regval);
2363 return ret;
7c8c5e6a
MZ		 2364}
2365
2366/******************************************************************************
2367 * Userspace API
2368 *****************************************************************************/
2369
2370static bool index_to_params(u64 id, struct sys_reg_params *params)
2371{
2372 switch (id & KVM_REG_SIZE_MASK) {
2373 case KVM_REG_SIZE_U64:
2374 /* Any unused index bits means it's not valid. */
2375 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2376 | KVM_REG_ARM_COPROC_MASK
2377 | KVM_REG_ARM64_SYSREG_OP0_MASK
2378 | KVM_REG_ARM64_SYSREG_OP1_MASK
2379 | KVM_REG_ARM64_SYSREG_CRN_MASK
2380 | KVM_REG_ARM64_SYSREG_CRM_MASK
2381 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2382 return false;
2383 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2384 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2385 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2386 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2387 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2388 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2389 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2390 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2391 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2392 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2393 return true;
2394 default:
2395 return false;
2396 }
2397}
2398
4b927b94
VK		 2399const struct sys_reg_desc *find_reg_by_id(u64 id,
2400 struct sys_reg_params *params,
2401 const struct sys_reg_desc table[],
2402 unsigned int num)
2403{
2404 if (!index_to_params(id, params))
2405 return NULL;
2406
2407 return find_reg(params, table, num);
2408}
2409
7c8c5e6a
MZ		 2410/* Decode an index value, and find the sys_reg_desc entry. */
2411static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2412 u64 id)
2413{
dcaffa7b 2414 const struct sys_reg_desc *r;
7c8c5e6a
MZ		 2415 struct sys_reg_params params;
2416
2417 /* We only do sys_reg for now. */
2418 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2419 return NULL;
2420
1ce74e96
WD		 2421 if (!index_to_params(id, &params))
2422 return NULL;
2423
dcaffa7b 2424 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
7c8c5e6a 2425
93390c0a
DM		 2426 /* Not saved in the sys_reg array and not otherwise accessible? */
2427 if (r && !(r->reg || r->get_user))
7c8c5e6a
MZ		 2428 r = NULL;
2429
2430 return r;
2431}
2432
2433/*
2434 * These are the invariant sys_reg registers: we let the guest see the
2435 * host versions of these, so they're part of the guest state.
2436 *
2437 * A future CPU may provide a mechanism to present different values to
2438 * the guest, or a future kvm may trap them.
2439 */
2440
2441#define FUNCTION_INVARIANT(reg) \
2442 static void get_##reg(struct kvm_vcpu *v, \
2443 const struct sys_reg_desc *r) \
2444 { \
1f3d8699 2445 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
7c8c5e6a
MZ		 2446 }
2447
2448FUNCTION_INVARIANT(midr_el1)
7c8c5e6a 2449FUNCTION_INVARIANT(revidr_el1)
7c8c5e6a
MZ		 2450FUNCTION_INVARIANT(clidr_el1)
2451FUNCTION_INVARIANT(aidr_el1)
2452
f7f2b15c
AB		 2453static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2454{
2455 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2456}
2457
7c8c5e6a
MZ		 2458/* ->val is filled in by kvm_sys_reg_table_init() */
2459static struct sys_reg_desc invariant_sys_regs[] = {
0d449541
MR		 2460 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2461 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
0d449541
MR		 2462 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2463 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2464 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
7c8c5e6a
MZ		 2465};
2466
26c99af1 2467static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
7c8c5e6a 2468{
7c8c5e6a
MZ		 2469 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2470 return -EFAULT;
2471 return 0;
2472}
2473
26c99af1 2474static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
7c8c5e6a 2475{
7c8c5e6a
MZ		 2476 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2477 return -EFAULT;
2478 return 0;
2479}
2480
2481static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2482{
2483 struct sys_reg_params params;
2484 const struct sys_reg_desc *r;
2485
4b927b94
VK		 2486 r = find_reg_by_id(id, &params, invariant_sys_regs,
2487 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 2488 if (!r)
2489 return -ENOENT;
2490
2491 return reg_to_user(uaddr, &r->val, id);
2492}
2493
2494static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2495{
2496 struct sys_reg_params params;
2497 const struct sys_reg_desc *r;
2498 int err;
2499 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2500
4b927b94
VK		 2501 r = find_reg_by_id(id, &params, invariant_sys_regs,
2502 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 2503 if (!r)
2504 return -ENOENT;
2505
2506 err = reg_from_user(&val, uaddr, id);
2507 if (err)
2508 return err;
2509
2510 /* This is what we mean by invariant: you can't change it. */
2511 if (r->val != val)
2512 return -EINVAL;
2513
2514 return 0;
2515}
2516
2517static bool is_valid_cache(u32 val)
2518{
2519 u32 level, ctype;
2520
2521 if (val >= CSSELR_MAX)
18d45766 2522 return false;
7c8c5e6a
MZ		 2523
2524 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2525 level = (val >> 1);
2526 ctype = (cache_levels >> (level * 3)) & 7;
2527
2528 switch (ctype) {
2529 case 0: /* No cache */
2530 return false;
2531 case 1: /* Instruction cache only */
2532 return (val & 1);
2533 case 2: /* Data cache only */
2534 case 4: /* Unified cache */
2535 return !(val & 1);
2536 case 3: /* Separate instruction and data caches */
2537 return true;
2538 default: /* Reserved: we can't know instruction or data. */
2539 return false;
2540 }
2541}
2542
2543static int demux_c15_get(u64 id, void __user *uaddr)
2544{
2545 u32 val;
2546 u32 __user *uval = uaddr;
2547
2548 /* Fail if we have unknown bits set. */
2549 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2550 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2551 return -ENOENT;
2552
2553 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2554 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2555 if (KVM_REG_SIZE(id) != 4)
2556 return -ENOENT;
2557 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2558 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2559 if (!is_valid_cache(val))
2560 return -ENOENT;
2561
2562 return put_user(get_ccsidr(val), uval);
2563 default:
2564 return -ENOENT;
2565 }
2566}
2567
2568static int demux_c15_set(u64 id, void __user *uaddr)
2569{
2570 u32 val, newval;
2571 u32 __user *uval = uaddr;
2572
2573 /* Fail if we have unknown bits set. */
2574 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2575 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2576 return -ENOENT;
2577
2578 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2579 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2580 if (KVM_REG_SIZE(id) != 4)
2581 return -ENOENT;
2582 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2583 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2584 if (!is_valid_cache(val))
2585 return -ENOENT;
2586
2587 if (get_user(newval, uval))
2588 return -EFAULT;
2589
2590 /* This is also invariant: you can't change it. */
2591 if (newval != get_ccsidr(val))
2592 return -EINVAL;
2593 return 0;
2594 default:
2595 return -ENOENT;
2596 }
2597}
2598
2599int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2600{
2601 const struct sys_reg_desc *r;
2602 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2603
2604 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2605 return demux_c15_get(reg->id, uaddr);
2606
2607 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2608 return -ENOENT;
2609
2610 r = index_to_sys_reg_desc(vcpu, reg->id);
2611 if (!r)
2612 return get_invariant_sys_reg(reg->id, uaddr);
2613
7f34e409 2614 /* Check for regs disabled by runtime config */
01fe5ace 2615 if (sysreg_hidden(vcpu, r))
7f34e409
DM		 2616 return -ENOENT;
2617
84e690bf
AB		 2618 if (r->get_user)
2619 return (r->get_user)(vcpu, r, reg, uaddr);
2620
8d404c4c 2621 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
7c8c5e6a
MZ		 2622}
2623
2624int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2625{
2626 const struct sys_reg_desc *r;
2627 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2628
2629 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2630 return demux_c15_set(reg->id, uaddr);
2631
2632 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2633 return -ENOENT;
2634
2635 r = index_to_sys_reg_desc(vcpu, reg->id);
2636 if (!r)
2637 return set_invariant_sys_reg(reg->id, uaddr);
2638
7f34e409 2639 /* Check for regs disabled by runtime config */
01fe5ace 2640 if (sysreg_hidden(vcpu, r))
7f34e409
DM		 2641 return -ENOENT;
2642
84e690bf
AB		 2643 if (r->set_user)
2644 return (r->set_user)(vcpu, r, reg, uaddr);
2645
8d404c4c 2646 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
7c8c5e6a
MZ		 2647}
2648
2649static unsigned int num_demux_regs(void)
2650{
2651 unsigned int i, count = 0;
2652
2653 for (i = 0; i < CSSELR_MAX; i++)
2654 if (is_valid_cache(i))
2655 count++;
2656
2657 return count;
2658}
2659
2660static int write_demux_regids(u64 __user *uindices)
2661{
efd48cea 2662 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
7c8c5e6a
MZ		 2663 unsigned int i;
2664
2665 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2666 for (i = 0; i < CSSELR_MAX; i++) {
2667 if (!is_valid_cache(i))
2668 continue;
2669 if (put_user(val | i, uindices))
2670 return -EFAULT;
2671 uindices++;
2672 }
2673 return 0;
2674}
2675
2676static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2677{
2678 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2679 KVM_REG_ARM64_SYSREG |
2680 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2681 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2682 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2683 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2684 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2685}
2686
2687static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2688{
2689 if (!*uind)
2690 return true;
2691
2692 if (put_user(sys_reg_to_index(reg), *uind))
2693 return false;
2694
2695 (*uind)++;
2696 return true;
2697}
2698
7f34e409
DM		 2699static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2700 const struct sys_reg_desc *rd,
93390c0a
DM		 2701 u64 __user **uind,
2702 unsigned int *total)
2703{
2704 /*
2705 * Ignore registers we trap but don't save,
2706 * and for which no custom user accessor is provided.
2707 */
2708 if (!(rd->reg || rd->get_user))
2709 return 0;
2710
01fe5ace 2711 if (sysreg_hidden(vcpu, rd))
7f34e409
DM		 2712 return 0;
2713
93390c0a
DM		 2714 if (!copy_reg_to_user(rd, uind))
2715 return -EFAULT;
2716
2717 (*total)++;
2718 return 0;
2719}
2720
7c8c5e6a
MZ		 2721/* Assumed ordered tables, see kvm_sys_reg_table_init. */
2722static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2723{
dcaffa7b 2724 const struct sys_reg_desc *i2, *end2;
7c8c5e6a 2725 unsigned int total = 0;
93390c0a 2726 int err;
7c8c5e6a 2727
7c8c5e6a
MZ		 2728 i2 = sys_reg_descs;
2729 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2730
dcaffa7b
JM		 2731 while (i2 != end2) {
2732 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
93390c0a
DM		 2733 if (err)
2734 return err;
7c8c5e6a
MZ		 2735 }
2736 return total;
2737}
2738
2739unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2740{
2741 return ARRAY_SIZE(invariant_sys_regs)
2742 + num_demux_regs()
2743 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2744}
2745
2746int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2747{
2748 unsigned int i;
2749 int err;
2750
2751 /* Then give them all the invariant registers' indices. */
2752 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2753 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2754 return -EFAULT;
2755 uindices++;
2756 }
2757
2758 err = walk_sys_regs(vcpu, uindices);
2759 if (err < 0)
2760 return err;
2761 uindices += err;
2762
2763 return write_demux_regids(uindices);
2764}
2765
2766void kvm_sys_reg_table_init(void)
2767{
2768 unsigned int i;
2769 struct sys_reg_desc clidr;
2770
2771 /* Make sure tables are unique and in order. */
bb44a8db
MZ		 2772 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false));
2773 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true));
2774 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true));
2775 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true));
2776 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true));
2777 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false));
7c8c5e6a
MZ		 2778
2779 /* We abuse the reset function to overwrite the table itself. */
2780 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2781 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2782
2783 /*
2784 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2785 *
2786 * If software reads the Cache Type fields from Ctype1
2787 * upwards, once it has seen a value of 0b000, no caches
2788 * exist at further-out levels of the hierarchy. So, for
2789 * example, if Ctype3 is the first Cache Type field with a
2790 * value of 0b000, the values of Ctype4 to Ctype7 must be
2791 * ignored.
2792 */
2793 get_clidr_el1(NULL, &clidr); /* Ugly... */
2794 cache_levels = clidr.val;
2795 for (i = 0; i < 7; i++)
2796 if (((cache_levels >> (i*3)) & 7) == 0)
2797 break;
2798 /* Clear all higher bits. */
2799 cache_levels &= (1 << (i*3))-1;
2800}
Linux 6.x block layer and io_uring tree(s)