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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7c8c5e6a MZ |
2 | /* |
3 | * Copyright (C) 2012,2013 - ARM Ltd | |
4 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
5 | * | |
6 | * Derived from arch/arm/kvm/coproc.c: | |
7 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
8 | * Authors: Rusty Russell <rusty@rustcorp.com.au> | |
9 | * Christoffer Dall <c.dall@virtualopensystems.com> | |
7c8c5e6a MZ |
10 | */ |
11 | ||
c8857935 | 12 | #include <linux/bitfield.h> |
623eefa8 | 13 | #include <linux/bsearch.h> |
7c8c5e6a | 14 | #include <linux/kvm_host.h> |
c6d01a94 | 15 | #include <linux/mm.h> |
07d79fe7 | 16 | #include <linux/printk.h> |
7c8c5e6a | 17 | #include <linux/uaccess.h> |
c6d01a94 | 18 | |
7c8c5e6a MZ |
19 | #include <asm/cacheflush.h> |
20 | #include <asm/cputype.h> | |
0c557ed4 | 21 | #include <asm/debug-monitors.h> |
c6d01a94 MR |
22 | #include <asm/esr.h> |
23 | #include <asm/kvm_arm.h> | |
c6d01a94 | 24 | #include <asm/kvm_emulate.h> |
d47533da | 25 | #include <asm/kvm_hyp.h> |
c6d01a94 | 26 | #include <asm/kvm_mmu.h> |
ab946834 | 27 | #include <asm/perf_event.h> |
1f3d8699 | 28 | #include <asm/sysreg.h> |
c6d01a94 | 29 | |
7c8c5e6a MZ |
30 | #include <trace/events/kvm.h> |
31 | ||
32 | #include "sys_regs.h" | |
33 | ||
eef8c85a AB |
34 | #include "trace.h" |
35 | ||
7c8c5e6a | 36 | /* |
656012c7 | 37 | * All of this file is extremely similar to the ARM coproc.c, but the |
7c8c5e6a MZ |
38 | * types are different. My gut feeling is that it should be pretty |
39 | * easy to merge, but that would be an ABI breakage -- again. VFP | |
40 | * would also need to be abstracted. | |
62a89c44 MZ |
41 | * |
42 | * For AArch32, we only take care of what is being trapped. Anything | |
43 | * that has to do with init and userspace access has to go via the | |
44 | * 64bit interface. | |
7c8c5e6a MZ |
45 | */ |
46 | ||
f24adc65 OU |
47 | static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); |
48 | static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); | |
49 | static u64 sys_reg_to_index(const struct sys_reg_desc *reg); | |
50 | ||
7b5b4df1 | 51 | static bool read_from_write_only(struct kvm_vcpu *vcpu, |
e7f1d1ee MZ |
52 | struct sys_reg_params *params, |
53 | const struct sys_reg_desc *r) | |
7b5b4df1 MZ |
54 | { |
55 | WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); | |
56 | print_sys_reg_instr(params); | |
57 | kvm_inject_undefined(vcpu); | |
58 | return false; | |
59 | } | |
60 | ||
7b1dba1f MZ |
61 | static bool write_to_read_only(struct kvm_vcpu *vcpu, |
62 | struct sys_reg_params *params, | |
63 | const struct sys_reg_desc *r) | |
64 | { | |
65 | WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); | |
66 | print_sys_reg_instr(params); | |
67 | kvm_inject_undefined(vcpu); | |
68 | return false; | |
69 | } | |
70 | ||
7ea90bdd MZ |
71 | u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) |
72 | { | |
73 | u64 val = 0x8badf00d8badf00d; | |
74 | ||
75 | if (vcpu->arch.sysregs_loaded_on_cpu && | |
76 | __vcpu_read_sys_reg_from_cpu(reg, &val)) | |
77 | return val; | |
78 | ||
79 | return __vcpu_sys_reg(vcpu, reg); | |
80 | } | |
81 | ||
82 | void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) | |
83 | { | |
84 | if (vcpu->arch.sysregs_loaded_on_cpu && | |
85 | __vcpu_write_sys_reg_to_cpu(val, reg)) | |
86 | return; | |
87 | ||
d47533da CD |
88 | __vcpu_sys_reg(vcpu, reg) = val; |
89 | } | |
90 | ||
7c8c5e6a MZ |
91 | /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ |
92 | static u32 cache_levels; | |
93 | ||
94 | /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ | |
c73a4416 | 95 | #define CSSELR_MAX 14 |
7c8c5e6a MZ |
96 | |
97 | /* Which cache CCSIDR represents depends on CSSELR value. */ | |
98 | static u32 get_ccsidr(u32 csselr) | |
99 | { | |
100 | u32 ccsidr; | |
101 | ||
102 | /* Make sure noone else changes CSSELR during this! */ | |
103 | local_irq_disable(); | |
1f3d8699 | 104 | write_sysreg(csselr, csselr_el1); |
7c8c5e6a | 105 | isb(); |
1f3d8699 | 106 | ccsidr = read_sysreg(ccsidr_el1); |
7c8c5e6a MZ |
107 | local_irq_enable(); |
108 | ||
109 | return ccsidr; | |
110 | } | |
111 | ||
3c1e7165 MZ |
112 | /* |
113 | * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). | |
114 | */ | |
7c8c5e6a | 115 | static bool access_dcsw(struct kvm_vcpu *vcpu, |
3fec037d | 116 | struct sys_reg_params *p, |
7c8c5e6a MZ |
117 | const struct sys_reg_desc *r) |
118 | { | |
7c8c5e6a | 119 | if (!p->is_write) |
e7f1d1ee | 120 | return read_from_write_only(vcpu, p, r); |
7c8c5e6a | 121 | |
09605e94 MZ |
122 | /* |
123 | * Only track S/W ops if we don't have FWB. It still indicates | |
124 | * that the guest is a bit broken (S/W operations should only | |
125 | * be done by firmware, knowing that there is only a single | |
126 | * CPU left in the system, and certainly not from non-secure | |
127 | * software). | |
128 | */ | |
129 | if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) | |
130 | kvm_set_way_flush(vcpu); | |
131 | ||
7c8c5e6a MZ |
132 | return true; |
133 | } | |
134 | ||
b1ea1d76 MZ |
135 | static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) |
136 | { | |
137 | switch (r->aarch32_map) { | |
138 | case AA32_LO: | |
139 | *mask = GENMASK_ULL(31, 0); | |
140 | *shift = 0; | |
141 | break; | |
142 | case AA32_HI: | |
143 | *mask = GENMASK_ULL(63, 32); | |
144 | *shift = 32; | |
145 | break; | |
146 | default: | |
147 | *mask = GENMASK_ULL(63, 0); | |
148 | *shift = 0; | |
149 | break; | |
150 | } | |
151 | } | |
152 | ||
4d44923b MZ |
153 | /* |
154 | * Generic accessor for VM registers. Only called as long as HCR_TVM | |
3c1e7165 MZ |
155 | * is set. If the guest enables the MMU, we stop trapping the VM |
156 | * sys_regs and leave it in complete control of the caches. | |
4d44923b MZ |
157 | */ |
158 | static bool access_vm_reg(struct kvm_vcpu *vcpu, | |
3fec037d | 159 | struct sys_reg_params *p, |
4d44923b MZ |
160 | const struct sys_reg_desc *r) |
161 | { | |
3c1e7165 | 162 | bool was_enabled = vcpu_has_cache_enabled(vcpu); |
b1ea1d76 | 163 | u64 val, mask, shift; |
4d44923b MZ |
164 | |
165 | BUG_ON(!p->is_write); | |
166 | ||
b1ea1d76 | 167 | get_access_mask(r, &mask, &shift); |
52f6c4f0 | 168 | |
b1ea1d76 MZ |
169 | if (~mask) { |
170 | val = vcpu_read_sys_reg(vcpu, r->reg); | |
171 | val &= ~mask; | |
dedf97e8 | 172 | } else { |
b1ea1d76 | 173 | val = 0; |
dedf97e8 | 174 | } |
b1ea1d76 MZ |
175 | |
176 | val |= (p->regval & (mask >> shift)) << shift; | |
177 | vcpu_write_sys_reg(vcpu, val, r->reg); | |
f0a3eaff | 178 | |
3c1e7165 | 179 | kvm_toggle_cache(vcpu, was_enabled); |
4d44923b MZ |
180 | return true; |
181 | } | |
182 | ||
af473829 JM |
183 | static bool access_actlr(struct kvm_vcpu *vcpu, |
184 | struct sys_reg_params *p, | |
185 | const struct sys_reg_desc *r) | |
186 | { | |
b1ea1d76 MZ |
187 | u64 mask, shift; |
188 | ||
af473829 JM |
189 | if (p->is_write) |
190 | return ignore_write(vcpu, p); | |
191 | ||
b1ea1d76 MZ |
192 | get_access_mask(r, &mask, &shift); |
193 | p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; | |
af473829 JM |
194 | |
195 | return true; | |
196 | } | |
197 | ||
6d52f35a AP |
198 | /* |
199 | * Trap handler for the GICv3 SGI generation system register. | |
200 | * Forward the request to the VGIC emulation. | |
201 | * The cp15_64 code makes sure this automatically works | |
202 | * for both AArch64 and AArch32 accesses. | |
203 | */ | |
204 | static bool access_gic_sgi(struct kvm_vcpu *vcpu, | |
3fec037d | 205 | struct sys_reg_params *p, |
6d52f35a AP |
206 | const struct sys_reg_desc *r) |
207 | { | |
03bd646d MZ |
208 | bool g1; |
209 | ||
6d52f35a | 210 | if (!p->is_write) |
e7f1d1ee | 211 | return read_from_write_only(vcpu, p, r); |
6d52f35a | 212 | |
03bd646d MZ |
213 | /* |
214 | * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates | |
215 | * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, | |
216 | * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively | |
217 | * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure | |
218 | * group. | |
219 | */ | |
50f30453 | 220 | if (p->Op0 == 0) { /* AArch32 */ |
03bd646d MZ |
221 | switch (p->Op1) { |
222 | default: /* Keep GCC quiet */ | |
223 | case 0: /* ICC_SGI1R */ | |
224 | g1 = true; | |
225 | break; | |
226 | case 1: /* ICC_ASGI1R */ | |
227 | case 2: /* ICC_SGI0R */ | |
228 | g1 = false; | |
229 | break; | |
230 | } | |
50f30453 | 231 | } else { /* AArch64 */ |
03bd646d MZ |
232 | switch (p->Op2) { |
233 | default: /* Keep GCC quiet */ | |
234 | case 5: /* ICC_SGI1R_EL1 */ | |
235 | g1 = true; | |
236 | break; | |
237 | case 6: /* ICC_ASGI1R_EL1 */ | |
238 | case 7: /* ICC_SGI0R_EL1 */ | |
239 | g1 = false; | |
240 | break; | |
241 | } | |
242 | } | |
243 | ||
244 | vgic_v3_dispatch_sgi(vcpu, p->regval, g1); | |
6d52f35a AP |
245 | |
246 | return true; | |
247 | } | |
248 | ||
b34f2bcb MZ |
249 | static bool access_gic_sre(struct kvm_vcpu *vcpu, |
250 | struct sys_reg_params *p, | |
251 | const struct sys_reg_desc *r) | |
252 | { | |
253 | if (p->is_write) | |
254 | return ignore_write(vcpu, p); | |
255 | ||
256 | p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; | |
257 | return true; | |
258 | } | |
259 | ||
7609c125 | 260 | static bool trap_raz_wi(struct kvm_vcpu *vcpu, |
3fec037d | 261 | struct sys_reg_params *p, |
7609c125 | 262 | const struct sys_reg_desc *r) |
7c8c5e6a MZ |
263 | { |
264 | if (p->is_write) | |
265 | return ignore_write(vcpu, p); | |
266 | else | |
267 | return read_zero(vcpu, p); | |
268 | } | |
269 | ||
22925521 MZ |
270 | /* |
271 | * ARMv8.1 mandates at least a trivial LORegion implementation, where all the | |
272 | * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 | |
273 | * system, these registers should UNDEF. LORID_EL1 being a RO register, we | |
274 | * treat it separately. | |
275 | */ | |
276 | static bool trap_loregion(struct kvm_vcpu *vcpu, | |
277 | struct sys_reg_params *p, | |
278 | const struct sys_reg_desc *r) | |
cc33c4e2 | 279 | { |
22925521 | 280 | u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); |
7ba8b438 | 281 | u32 sr = reg_to_encoding(r); |
22925521 MZ |
282 | |
283 | if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { | |
284 | kvm_inject_undefined(vcpu); | |
285 | return false; | |
286 | } | |
287 | ||
288 | if (p->is_write && sr == SYS_LORID_EL1) | |
289 | return write_to_read_only(vcpu, p, r); | |
290 | ||
291 | return trap_raz_wi(vcpu, p, r); | |
cc33c4e2 MR |
292 | } |
293 | ||
f24adc65 OU |
294 | static bool trap_oslar_el1(struct kvm_vcpu *vcpu, |
295 | struct sys_reg_params *p, | |
296 | const struct sys_reg_desc *r) | |
297 | { | |
298 | u64 oslsr; | |
299 | ||
300 | if (!p->is_write) | |
301 | return read_from_write_only(vcpu, p, r); | |
302 | ||
303 | /* Forward the OSLK bit to OSLSR */ | |
304 | oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~SYS_OSLSR_OSLK; | |
305 | if (p->regval & SYS_OSLAR_OSLK) | |
306 | oslsr |= SYS_OSLSR_OSLK; | |
307 | ||
308 | __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; | |
309 | return true; | |
310 | } | |
311 | ||
0c557ed4 | 312 | static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, |
3fec037d | 313 | struct sys_reg_params *p, |
0c557ed4 MZ |
314 | const struct sys_reg_desc *r) |
315 | { | |
d42e2671 | 316 | if (p->is_write) |
e2ffceaa | 317 | return write_to_read_only(vcpu, p, r); |
d42e2671 OU |
318 | |
319 | p->regval = __vcpu_sys_reg(vcpu, r->reg); | |
320 | return true; | |
321 | } | |
322 | ||
323 | static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
324 | const struct kvm_one_reg *reg, void __user *uaddr) | |
325 | { | |
326 | u64 id = sys_reg_to_index(rd); | |
327 | u64 val; | |
328 | int err; | |
329 | ||
330 | err = reg_from_user(&val, uaddr, id); | |
331 | if (err) | |
332 | return err; | |
333 | ||
f24adc65 OU |
334 | /* |
335 | * The only modifiable bit is the OSLK bit. Refuse the write if | |
336 | * userspace attempts to change any other bit in the register. | |
337 | */ | |
338 | if ((val ^ rd->val) & ~SYS_OSLSR_OSLK) | |
d42e2671 OU |
339 | return -EINVAL; |
340 | ||
f24adc65 | 341 | __vcpu_sys_reg(vcpu, rd->reg) = val; |
d42e2671 | 342 | return 0; |
0c557ed4 MZ |
343 | } |
344 | ||
345 | static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, | |
3fec037d | 346 | struct sys_reg_params *p, |
0c557ed4 MZ |
347 | const struct sys_reg_desc *r) |
348 | { | |
349 | if (p->is_write) { | |
350 | return ignore_write(vcpu, p); | |
351 | } else { | |
1f3d8699 | 352 | p->regval = read_sysreg(dbgauthstatus_el1); |
0c557ed4 MZ |
353 | return true; |
354 | } | |
355 | } | |
356 | ||
357 | /* | |
358 | * We want to avoid world-switching all the DBG registers all the | |
359 | * time: | |
e6bc555c | 360 | * |
0c557ed4 MZ |
361 | * - If we've touched any debug register, it is likely that we're |
362 | * going to touch more of them. It then makes sense to disable the | |
363 | * traps and start doing the save/restore dance | |
364 | * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is | |
365 | * then mandatory to save/restore the registers, as the guest | |
366 | * depends on them. | |
e6bc555c | 367 | * |
0c557ed4 MZ |
368 | * For this, we use a DIRTY bit, indicating the guest has modified the |
369 | * debug registers, used as follow: | |
370 | * | |
371 | * On guest entry: | |
372 | * - If the dirty bit is set (because we're coming back from trapping), | |
373 | * disable the traps, save host registers, restore guest registers. | |
374 | * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), | |
375 | * set the dirty bit, disable the traps, save host registers, | |
376 | * restore guest registers. | |
377 | * - Otherwise, enable the traps | |
378 | * | |
379 | * On guest exit: | |
380 | * - If the dirty bit is set, save guest registers, restore host | |
381 | * registers and clear the dirty bit. This ensure that the host can | |
382 | * now use the debug registers. | |
383 | */ | |
384 | static bool trap_debug_regs(struct kvm_vcpu *vcpu, | |
3fec037d | 385 | struct sys_reg_params *p, |
0c557ed4 MZ |
386 | const struct sys_reg_desc *r) |
387 | { | |
388 | if (p->is_write) { | |
8d404c4c | 389 | vcpu_write_sys_reg(vcpu, p->regval, r->reg); |
fa89d31c | 390 | vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; |
0c557ed4 | 391 | } else { |
8d404c4c | 392 | p->regval = vcpu_read_sys_reg(vcpu, r->reg); |
0c557ed4 MZ |
393 | } |
394 | ||
2ec5be3d | 395 | trace_trap_reg(__func__, r->reg, p->is_write, p->regval); |
eef8c85a | 396 | |
0c557ed4 MZ |
397 | return true; |
398 | } | |
399 | ||
84e690bf AB |
400 | /* |
401 | * reg_to_dbg/dbg_to_reg | |
402 | * | |
403 | * A 32 bit write to a debug register leave top bits alone | |
404 | * A 32 bit read from a debug register only returns the bottom bits | |
405 | * | |
406 | * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the | |
407 | * hyp.S code switches between host and guest values in future. | |
408 | */ | |
281243cb MZ |
409 | static void reg_to_dbg(struct kvm_vcpu *vcpu, |
410 | struct sys_reg_params *p, | |
1da42c34 | 411 | const struct sys_reg_desc *rd, |
281243cb | 412 | u64 *dbg_reg) |
84e690bf | 413 | { |
1da42c34 | 414 | u64 mask, shift, val; |
84e690bf | 415 | |
1da42c34 | 416 | get_access_mask(rd, &mask, &shift); |
84e690bf | 417 | |
1da42c34 MZ |
418 | val = *dbg_reg; |
419 | val &= ~mask; | |
420 | val |= (p->regval & (mask >> shift)) << shift; | |
84e690bf | 421 | *dbg_reg = val; |
1da42c34 | 422 | |
fa89d31c | 423 | vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; |
84e690bf AB |
424 | } |
425 | ||
281243cb MZ |
426 | static void dbg_to_reg(struct kvm_vcpu *vcpu, |
427 | struct sys_reg_params *p, | |
1da42c34 | 428 | const struct sys_reg_desc *rd, |
281243cb | 429 | u64 *dbg_reg) |
84e690bf | 430 | { |
1da42c34 MZ |
431 | u64 mask, shift; |
432 | ||
433 | get_access_mask(rd, &mask, &shift); | |
434 | p->regval = (*dbg_reg & mask) >> shift; | |
84e690bf AB |
435 | } |
436 | ||
281243cb MZ |
437 | static bool trap_bvr(struct kvm_vcpu *vcpu, |
438 | struct sys_reg_params *p, | |
439 | const struct sys_reg_desc *rd) | |
84e690bf | 440 | { |
cb853ded | 441 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; |
84e690bf AB |
442 | |
443 | if (p->is_write) | |
1da42c34 | 444 | reg_to_dbg(vcpu, p, rd, dbg_reg); |
84e690bf | 445 | else |
1da42c34 | 446 | dbg_to_reg(vcpu, p, rd, dbg_reg); |
84e690bf | 447 | |
cb853ded | 448 | trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); |
eef8c85a | 449 | |
84e690bf AB |
450 | return true; |
451 | } | |
452 | ||
453 | static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
454 | const struct kvm_one_reg *reg, void __user *uaddr) | |
455 | { | |
cb853ded | 456 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; |
84e690bf | 457 | |
1713e5aa | 458 | if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) |
84e690bf AB |
459 | return -EFAULT; |
460 | return 0; | |
461 | } | |
462 | ||
463 | static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
464 | const struct kvm_one_reg *reg, void __user *uaddr) | |
465 | { | |
cb853ded | 466 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; |
84e690bf AB |
467 | |
468 | if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) | |
469 | return -EFAULT; | |
470 | return 0; | |
471 | } | |
472 | ||
281243cb MZ |
473 | static void reset_bvr(struct kvm_vcpu *vcpu, |
474 | const struct sys_reg_desc *rd) | |
84e690bf | 475 | { |
cb853ded | 476 | vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; |
84e690bf AB |
477 | } |
478 | ||
281243cb MZ |
479 | static bool trap_bcr(struct kvm_vcpu *vcpu, |
480 | struct sys_reg_params *p, | |
481 | const struct sys_reg_desc *rd) | |
84e690bf | 482 | { |
cb853ded | 483 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; |
84e690bf AB |
484 | |
485 | if (p->is_write) | |
1da42c34 | 486 | reg_to_dbg(vcpu, p, rd, dbg_reg); |
84e690bf | 487 | else |
1da42c34 | 488 | dbg_to_reg(vcpu, p, rd, dbg_reg); |
84e690bf | 489 | |
cb853ded | 490 | trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); |
eef8c85a | 491 | |
84e690bf AB |
492 | return true; |
493 | } | |
494 | ||
495 | static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
496 | const struct kvm_one_reg *reg, void __user *uaddr) | |
497 | { | |
cb853ded | 498 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; |
84e690bf | 499 | |
1713e5aa | 500 | if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) |
84e690bf AB |
501 | return -EFAULT; |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
507 | const struct kvm_one_reg *reg, void __user *uaddr) | |
508 | { | |
cb853ded | 509 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; |
84e690bf AB |
510 | |
511 | if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) | |
512 | return -EFAULT; | |
513 | return 0; | |
514 | } | |
515 | ||
281243cb MZ |
516 | static void reset_bcr(struct kvm_vcpu *vcpu, |
517 | const struct sys_reg_desc *rd) | |
84e690bf | 518 | { |
cb853ded | 519 | vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; |
84e690bf AB |
520 | } |
521 | ||
281243cb MZ |
522 | static bool trap_wvr(struct kvm_vcpu *vcpu, |
523 | struct sys_reg_params *p, | |
524 | const struct sys_reg_desc *rd) | |
84e690bf | 525 | { |
cb853ded | 526 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; |
84e690bf AB |
527 | |
528 | if (p->is_write) | |
1da42c34 | 529 | reg_to_dbg(vcpu, p, rd, dbg_reg); |
84e690bf | 530 | else |
1da42c34 | 531 | dbg_to_reg(vcpu, p, rd, dbg_reg); |
84e690bf | 532 | |
cb853ded MZ |
533 | trace_trap_reg(__func__, rd->CRm, p->is_write, |
534 | vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); | |
eef8c85a | 535 | |
84e690bf AB |
536 | return true; |
537 | } | |
538 | ||
539 | static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
540 | const struct kvm_one_reg *reg, void __user *uaddr) | |
541 | { | |
cb853ded | 542 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; |
84e690bf | 543 | |
1713e5aa | 544 | if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) |
84e690bf AB |
545 | return -EFAULT; |
546 | return 0; | |
547 | } | |
548 | ||
549 | static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
550 | const struct kvm_one_reg *reg, void __user *uaddr) | |
551 | { | |
cb853ded | 552 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; |
84e690bf AB |
553 | |
554 | if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) | |
555 | return -EFAULT; | |
556 | return 0; | |
557 | } | |
558 | ||
281243cb MZ |
559 | static void reset_wvr(struct kvm_vcpu *vcpu, |
560 | const struct sys_reg_desc *rd) | |
84e690bf | 561 | { |
cb853ded | 562 | vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; |
84e690bf AB |
563 | } |
564 | ||
281243cb MZ |
565 | static bool trap_wcr(struct kvm_vcpu *vcpu, |
566 | struct sys_reg_params *p, | |
567 | const struct sys_reg_desc *rd) | |
84e690bf | 568 | { |
cb853ded | 569 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; |
84e690bf AB |
570 | |
571 | if (p->is_write) | |
1da42c34 | 572 | reg_to_dbg(vcpu, p, rd, dbg_reg); |
84e690bf | 573 | else |
1da42c34 | 574 | dbg_to_reg(vcpu, p, rd, dbg_reg); |
84e690bf | 575 | |
cb853ded | 576 | trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); |
eef8c85a | 577 | |
84e690bf AB |
578 | return true; |
579 | } | |
580 | ||
581 | static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
582 | const struct kvm_one_reg *reg, void __user *uaddr) | |
583 | { | |
cb853ded | 584 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; |
84e690bf | 585 | |
1713e5aa | 586 | if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) |
84e690bf AB |
587 | return -EFAULT; |
588 | return 0; | |
589 | } | |
590 | ||
591 | static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
592 | const struct kvm_one_reg *reg, void __user *uaddr) | |
593 | { | |
cb853ded | 594 | __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; |
84e690bf AB |
595 | |
596 | if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) | |
597 | return -EFAULT; | |
598 | return 0; | |
599 | } | |
600 | ||
281243cb MZ |
601 | static void reset_wcr(struct kvm_vcpu *vcpu, |
602 | const struct sys_reg_desc *rd) | |
84e690bf | 603 | { |
cb853ded | 604 | vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; |
84e690bf AB |
605 | } |
606 | ||
7c8c5e6a MZ |
607 | static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
608 | { | |
8d404c4c CD |
609 | u64 amair = read_sysreg(amair_el1); |
610 | vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); | |
7c8c5e6a MZ |
611 | } |
612 | ||
af473829 JM |
613 | static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
614 | { | |
615 | u64 actlr = read_sysreg(actlr_el1); | |
616 | vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); | |
617 | } | |
618 | ||
7c8c5e6a MZ |
619 | static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
620 | { | |
4429fc64 AP |
621 | u64 mpidr; |
622 | ||
7c8c5e6a | 623 | /* |
4429fc64 AP |
624 | * Map the vcpu_id into the first three affinity level fields of |
625 | * the MPIDR. We limit the number of VCPUs in level 0 due to a | |
626 | * limitation to 16 CPUs in that level in the ICC_SGIxR registers | |
627 | * of the GICv3 to be able to address each CPU directly when | |
628 | * sending IPIs. | |
7c8c5e6a | 629 | */ |
4429fc64 AP |
630 | mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); |
631 | mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); | |
632 | mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); | |
8d404c4c | 633 | vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); |
7c8c5e6a MZ |
634 | } |
635 | ||
11663111 MZ |
636 | static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, |
637 | const struct sys_reg_desc *r) | |
638 | { | |
639 | if (kvm_vcpu_has_pmu(vcpu)) | |
640 | return 0; | |
641 | ||
642 | return REG_HIDDEN; | |
643 | } | |
644 | ||
0ab410a9 MZ |
645 | static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
646 | { | |
647 | u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); | |
648 | ||
649 | /* No PMU available, any PMU reg may UNDEF... */ | |
650 | if (!kvm_arm_support_pmu_v3()) | |
651 | return; | |
652 | ||
653 | n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; | |
654 | n &= ARMV8_PMU_PMCR_N_MASK; | |
655 | if (n) | |
656 | mask |= GENMASK(n - 1, 0); | |
657 | ||
658 | reset_unknown(vcpu, r); | |
659 | __vcpu_sys_reg(vcpu, r->reg) &= mask; | |
660 | } | |
661 | ||
662 | static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) | |
663 | { | |
664 | reset_unknown(vcpu, r); | |
665 | __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); | |
666 | } | |
667 | ||
668 | static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) | |
669 | { | |
670 | reset_unknown(vcpu, r); | |
671 | __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK; | |
672 | } | |
673 | ||
674 | static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) | |
675 | { | |
676 | reset_unknown(vcpu, r); | |
677 | __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK; | |
678 | } | |
679 | ||
ab946834 SZ |
680 | static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
681 | { | |
682 | u64 pmcr, val; | |
683 | ||
2a5f1b67 MZ |
684 | /* No PMU available, PMCR_EL0 may UNDEF... */ |
685 | if (!kvm_arm_support_pmu_v3()) | |
686 | return; | |
687 | ||
1f3d8699 MR |
688 | pmcr = read_sysreg(pmcr_el0); |
689 | /* | |
690 | * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN | |
ab946834 SZ |
691 | * except PMCR.E resetting to zero. |
692 | */ | |
693 | val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) | |
694 | | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); | |
6f163714 MZ |
695 | if (!system_supports_32bit_el0()) |
696 | val |= ARMV8_PMU_PMCR_LC; | |
03fdfb26 | 697 | __vcpu_sys_reg(vcpu, r->reg) = val; |
ab946834 SZ |
698 | } |
699 | ||
6c007036 | 700 | static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) |
d692b8ad | 701 | { |
8d404c4c | 702 | u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); |
7ded92e2 | 703 | bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); |
d692b8ad | 704 | |
24d5950f MZ |
705 | if (!enabled) |
706 | kvm_inject_undefined(vcpu); | |
d692b8ad | 707 | |
6c007036 | 708 | return !enabled; |
d692b8ad SZ |
709 | } |
710 | ||
6c007036 | 711 | static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) |
d692b8ad | 712 | { |
6c007036 MZ |
713 | return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); |
714 | } | |
d692b8ad | 715 | |
6c007036 MZ |
716 | static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) |
717 | { | |
718 | return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); | |
d692b8ad SZ |
719 | } |
720 | ||
721 | static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) | |
722 | { | |
6c007036 | 723 | return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); |
d692b8ad SZ |
724 | } |
725 | ||
726 | static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) | |
727 | { | |
6c007036 | 728 | return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); |
d692b8ad SZ |
729 | } |
730 | ||
ab946834 SZ |
731 | static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
732 | const struct sys_reg_desc *r) | |
733 | { | |
734 | u64 val; | |
735 | ||
d692b8ad SZ |
736 | if (pmu_access_el0_disabled(vcpu)) |
737 | return false; | |
738 | ||
ab946834 SZ |
739 | if (p->is_write) { |
740 | /* Only update writeable bits of PMCR */ | |
8d404c4c | 741 | val = __vcpu_sys_reg(vcpu, PMCR_EL0); |
ab946834 SZ |
742 | val &= ~ARMV8_PMU_PMCR_MASK; |
743 | val |= p->regval & ARMV8_PMU_PMCR_MASK; | |
6f163714 MZ |
744 | if (!system_supports_32bit_el0()) |
745 | val |= ARMV8_PMU_PMCR_LC; | |
8d404c4c | 746 | __vcpu_sys_reg(vcpu, PMCR_EL0) = val; |
76993739 | 747 | kvm_pmu_handle_pmcr(vcpu, val); |
435e53fb | 748 | kvm_vcpu_pmu_restore_guest(vcpu); |
ab946834 SZ |
749 | } else { |
750 | /* PMCR.P & PMCR.C are RAZ */ | |
8d404c4c | 751 | val = __vcpu_sys_reg(vcpu, PMCR_EL0) |
ab946834 SZ |
752 | & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); |
753 | p->regval = val; | |
754 | } | |
755 | ||
756 | return true; | |
757 | } | |
758 | ||
3965c3ce SZ |
759 | static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
760 | const struct sys_reg_desc *r) | |
761 | { | |
d692b8ad SZ |
762 | if (pmu_access_event_counter_el0_disabled(vcpu)) |
763 | return false; | |
764 | ||
3965c3ce | 765 | if (p->is_write) |
8d404c4c | 766 | __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; |
3965c3ce SZ |
767 | else |
768 | /* return PMSELR.SEL field */ | |
8d404c4c | 769 | p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) |
3965c3ce SZ |
770 | & ARMV8_PMU_COUNTER_MASK; |
771 | ||
772 | return true; | |
773 | } | |
774 | ||
a86b5505 SZ |
775 | static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
776 | const struct sys_reg_desc *r) | |
777 | { | |
99b6a401 | 778 | u64 pmceid, mask, shift; |
a86b5505 | 779 | |
a86b5505 SZ |
780 | BUG_ON(p->is_write); |
781 | ||
d692b8ad SZ |
782 | if (pmu_access_el0_disabled(vcpu)) |
783 | return false; | |
784 | ||
99b6a401 MZ |
785 | get_access_mask(r, &mask, &shift); |
786 | ||
88865bec | 787 | pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); |
99b6a401 MZ |
788 | pmceid &= mask; |
789 | pmceid >>= shift; | |
a86b5505 SZ |
790 | |
791 | p->regval = pmceid; | |
792 | ||
793 | return true; | |
794 | } | |
795 | ||
051ff581 SZ |
796 | static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) |
797 | { | |
798 | u64 pmcr, val; | |
799 | ||
8d404c4c | 800 | pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); |
051ff581 | 801 | val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; |
24d5950f MZ |
802 | if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { |
803 | kvm_inject_undefined(vcpu); | |
051ff581 | 804 | return false; |
24d5950f | 805 | } |
051ff581 SZ |
806 | |
807 | return true; | |
808 | } | |
809 | ||
810 | static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, | |
811 | struct sys_reg_params *p, | |
812 | const struct sys_reg_desc *r) | |
813 | { | |
a3da9358 | 814 | u64 idx = ~0UL; |
051ff581 SZ |
815 | |
816 | if (r->CRn == 9 && r->CRm == 13) { | |
817 | if (r->Op2 == 2) { | |
818 | /* PMXEVCNTR_EL0 */ | |
d692b8ad SZ |
819 | if (pmu_access_event_counter_el0_disabled(vcpu)) |
820 | return false; | |
821 | ||
8d404c4c | 822 | idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) |
051ff581 SZ |
823 | & ARMV8_PMU_COUNTER_MASK; |
824 | } else if (r->Op2 == 0) { | |
825 | /* PMCCNTR_EL0 */ | |
d692b8ad SZ |
826 | if (pmu_access_cycle_counter_el0_disabled(vcpu)) |
827 | return false; | |
828 | ||
051ff581 | 829 | idx = ARMV8_PMU_CYCLE_IDX; |
051ff581 | 830 | } |
9e3f7a29 WH |
831 | } else if (r->CRn == 0 && r->CRm == 9) { |
832 | /* PMCCNTR */ | |
833 | if (pmu_access_event_counter_el0_disabled(vcpu)) | |
834 | return false; | |
835 | ||
836 | idx = ARMV8_PMU_CYCLE_IDX; | |
051ff581 SZ |
837 | } else if (r->CRn == 14 && (r->CRm & 12) == 8) { |
838 | /* PMEVCNTRn_EL0 */ | |
d692b8ad SZ |
839 | if (pmu_access_event_counter_el0_disabled(vcpu)) |
840 | return false; | |
841 | ||
051ff581 | 842 | idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); |
051ff581 SZ |
843 | } |
844 | ||
a3da9358 MZ |
845 | /* Catch any decoding mistake */ |
846 | WARN_ON(idx == ~0UL); | |
847 | ||
051ff581 SZ |
848 | if (!pmu_counter_idx_valid(vcpu, idx)) |
849 | return false; | |
850 | ||
d692b8ad SZ |
851 | if (p->is_write) { |
852 | if (pmu_access_el0_disabled(vcpu)) | |
853 | return false; | |
854 | ||
051ff581 | 855 | kvm_pmu_set_counter_value(vcpu, idx, p->regval); |
d692b8ad | 856 | } else { |
051ff581 | 857 | p->regval = kvm_pmu_get_counter_value(vcpu, idx); |
d692b8ad | 858 | } |
051ff581 SZ |
859 | |
860 | return true; | |
861 | } | |
862 | ||
9feb21ac SZ |
863 | static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
864 | const struct sys_reg_desc *r) | |
865 | { | |
866 | u64 idx, reg; | |
867 | ||
d692b8ad SZ |
868 | if (pmu_access_el0_disabled(vcpu)) |
869 | return false; | |
870 | ||
9feb21ac SZ |
871 | if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { |
872 | /* PMXEVTYPER_EL0 */ | |
8d404c4c | 873 | idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; |
9feb21ac SZ |
874 | reg = PMEVTYPER0_EL0 + idx; |
875 | } else if (r->CRn == 14 && (r->CRm & 12) == 12) { | |
876 | idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); | |
877 | if (idx == ARMV8_PMU_CYCLE_IDX) | |
878 | reg = PMCCFILTR_EL0; | |
879 | else | |
880 | /* PMEVTYPERn_EL0 */ | |
881 | reg = PMEVTYPER0_EL0 + idx; | |
882 | } else { | |
883 | BUG(); | |
884 | } | |
885 | ||
886 | if (!pmu_counter_idx_valid(vcpu, idx)) | |
887 | return false; | |
888 | ||
889 | if (p->is_write) { | |
890 | kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); | |
8d404c4c | 891 | __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; |
435e53fb | 892 | kvm_vcpu_pmu_restore_guest(vcpu); |
9feb21ac | 893 | } else { |
8d404c4c | 894 | p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; |
9feb21ac SZ |
895 | } |
896 | ||
897 | return true; | |
898 | } | |
899 | ||
96b0eebc SZ |
900 | static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
901 | const struct sys_reg_desc *r) | |
902 | { | |
903 | u64 val, mask; | |
904 | ||
d692b8ad SZ |
905 | if (pmu_access_el0_disabled(vcpu)) |
906 | return false; | |
907 | ||
96b0eebc SZ |
908 | mask = kvm_pmu_valid_counter_mask(vcpu); |
909 | if (p->is_write) { | |
910 | val = p->regval & mask; | |
911 | if (r->Op2 & 0x1) { | |
912 | /* accessing PMCNTENSET_EL0 */ | |
8d404c4c | 913 | __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; |
418e5ca8 | 914 | kvm_pmu_enable_counter_mask(vcpu, val); |
435e53fb | 915 | kvm_vcpu_pmu_restore_guest(vcpu); |
96b0eebc SZ |
916 | } else { |
917 | /* accessing PMCNTENCLR_EL0 */ | |
8d404c4c | 918 | __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; |
418e5ca8 | 919 | kvm_pmu_disable_counter_mask(vcpu, val); |
96b0eebc SZ |
920 | } |
921 | } else { | |
f5eff400 | 922 | p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); |
96b0eebc SZ |
923 | } |
924 | ||
925 | return true; | |
926 | } | |
927 | ||
9db52c78 SZ |
928 | static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
929 | const struct sys_reg_desc *r) | |
930 | { | |
931 | u64 mask = kvm_pmu_valid_counter_mask(vcpu); | |
932 | ||
b0737e99 | 933 | if (check_pmu_access_disabled(vcpu, 0)) |
d692b8ad SZ |
934 | return false; |
935 | ||
9db52c78 SZ |
936 | if (p->is_write) { |
937 | u64 val = p->regval & mask; | |
938 | ||
939 | if (r->Op2 & 0x1) | |
940 | /* accessing PMINTENSET_EL1 */ | |
8d404c4c | 941 | __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; |
9db52c78 SZ |
942 | else |
943 | /* accessing PMINTENCLR_EL1 */ | |
8d404c4c | 944 | __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; |
9db52c78 | 945 | } else { |
f5eff400 | 946 | p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); |
9db52c78 SZ |
947 | } |
948 | ||
949 | return true; | |
950 | } | |
951 | ||
76d883c4 SZ |
952 | static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
953 | const struct sys_reg_desc *r) | |
954 | { | |
955 | u64 mask = kvm_pmu_valid_counter_mask(vcpu); | |
956 | ||
d692b8ad SZ |
957 | if (pmu_access_el0_disabled(vcpu)) |
958 | return false; | |
959 | ||
76d883c4 SZ |
960 | if (p->is_write) { |
961 | if (r->CRm & 0x2) | |
962 | /* accessing PMOVSSET_EL0 */ | |
8d404c4c | 963 | __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); |
76d883c4 SZ |
964 | else |
965 | /* accessing PMOVSCLR_EL0 */ | |
8d404c4c | 966 | __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); |
76d883c4 | 967 | } else { |
f5eff400 | 968 | p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); |
76d883c4 SZ |
969 | } |
970 | ||
971 | return true; | |
972 | } | |
973 | ||
7a0adc70 SZ |
974 | static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
975 | const struct sys_reg_desc *r) | |
976 | { | |
977 | u64 mask; | |
978 | ||
e0443230 | 979 | if (!p->is_write) |
e7f1d1ee | 980 | return read_from_write_only(vcpu, p, r); |
e0443230 | 981 | |
d692b8ad SZ |
982 | if (pmu_write_swinc_el0_disabled(vcpu)) |
983 | return false; | |
984 | ||
e0443230 MZ |
985 | mask = kvm_pmu_valid_counter_mask(vcpu); |
986 | kvm_pmu_software_increment(vcpu, p->regval & mask); | |
987 | return true; | |
7a0adc70 SZ |
988 | } |
989 | ||
d692b8ad SZ |
990 | static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
991 | const struct sys_reg_desc *r) | |
992 | { | |
d692b8ad | 993 | if (p->is_write) { |
9008c235 MZ |
994 | if (!vcpu_mode_priv(vcpu)) { |
995 | kvm_inject_undefined(vcpu); | |
d692b8ad | 996 | return false; |
9008c235 | 997 | } |
d692b8ad | 998 | |
8d404c4c CD |
999 | __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = |
1000 | p->regval & ARMV8_PMU_USERENR_MASK; | |
d692b8ad | 1001 | } else { |
8d404c4c | 1002 | p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) |
d692b8ad SZ |
1003 | & ARMV8_PMU_USERENR_MASK; |
1004 | } | |
1005 | ||
1006 | return true; | |
1007 | } | |
1008 | ||
0c557ed4 MZ |
1009 | /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ |
1010 | #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ | |
ee1b64e6 | 1011 | { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ |
03fdfb26 | 1012 | trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ |
ee1b64e6 | 1013 | { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ |
03fdfb26 | 1014 | trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ |
ee1b64e6 | 1015 | { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ |
03fdfb26 | 1016 | trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ |
ee1b64e6 | 1017 | { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ |
03fdfb26 | 1018 | trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } |
0c557ed4 | 1019 | |
11663111 | 1020 | #define PMU_SYS_REG(r) \ |
0ab410a9 | 1021 | SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility |
11663111 | 1022 | |
051ff581 SZ |
1023 | /* Macro to expand the PMEVCNTRn_EL0 register */ |
1024 | #define PMU_PMEVCNTR_EL0(n) \ | |
11663111 | 1025 | { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \ |
0ab410a9 | 1026 | .reset = reset_pmevcntr, \ |
11663111 | 1027 | .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } |
051ff581 | 1028 | |
9feb21ac SZ |
1029 | /* Macro to expand the PMEVTYPERn_EL0 register */ |
1030 | #define PMU_PMEVTYPER_EL0(n) \ | |
11663111 | 1031 | { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \ |
0ab410a9 | 1032 | .reset = reset_pmevtyper, \ |
11663111 | 1033 | .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } |
9feb21ac | 1034 | |
338b1793 MZ |
1035 | static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
1036 | const struct sys_reg_desc *r) | |
4fcdf106 IV |
1037 | { |
1038 | kvm_inject_undefined(vcpu); | |
1039 | ||
1040 | return false; | |
1041 | } | |
1042 | ||
1043 | /* Macro to expand the AMU counter and type registers*/ | |
338b1793 MZ |
1044 | #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } |
1045 | #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } | |
1046 | #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } | |
1047 | #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } | |
384b40ca MR |
1048 | |
1049 | static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, | |
1050 | const struct sys_reg_desc *rd) | |
1051 | { | |
01fe5ace | 1052 | return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; |
384b40ca MR |
1053 | } |
1054 | ||
338b1793 MZ |
1055 | /* |
1056 | * If we land here on a PtrAuth access, that is because we didn't | |
1057 | * fixup the access on exit by allowing the PtrAuth sysregs. The only | |
1058 | * way this happens is when the guest does not have PtrAuth support | |
1059 | * enabled. | |
1060 | */ | |
384b40ca | 1061 | #define __PTRAUTH_KEY(k) \ |
338b1793 | 1062 | { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ |
384b40ca MR |
1063 | .visibility = ptrauth_visibility} |
1064 | ||
1065 | #define PTRAUTH_KEY(k) \ | |
1066 | __PTRAUTH_KEY(k ## KEYLO_EL1), \ | |
1067 | __PTRAUTH_KEY(k ## KEYHI_EL1) | |
1068 | ||
84135d3d AP |
1069 | static bool access_arch_timer(struct kvm_vcpu *vcpu, |
1070 | struct sys_reg_params *p, | |
1071 | const struct sys_reg_desc *r) | |
c9a3c58f | 1072 | { |
84135d3d AP |
1073 | enum kvm_arch_timers tmr; |
1074 | enum kvm_arch_timer_regs treg; | |
1075 | u64 reg = reg_to_encoding(r); | |
7b6b4631 | 1076 | |
84135d3d AP |
1077 | switch (reg) { |
1078 | case SYS_CNTP_TVAL_EL0: | |
1079 | case SYS_AARCH32_CNTP_TVAL: | |
1080 | tmr = TIMER_PTIMER; | |
1081 | treg = TIMER_REG_TVAL; | |
1082 | break; | |
1083 | case SYS_CNTP_CTL_EL0: | |
1084 | case SYS_AARCH32_CNTP_CTL: | |
1085 | tmr = TIMER_PTIMER; | |
1086 | treg = TIMER_REG_CTL; | |
1087 | break; | |
1088 | case SYS_CNTP_CVAL_EL0: | |
1089 | case SYS_AARCH32_CNTP_CVAL: | |
1090 | tmr = TIMER_PTIMER; | |
1091 | treg = TIMER_REG_CVAL; | |
1092 | break; | |
1093 | default: | |
1094 | BUG(); | |
c1b135af | 1095 | } |
7b6b4631 | 1096 | |
7b6b4631 | 1097 | if (p->is_write) |
84135d3d | 1098 | kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); |
7b6b4631 | 1099 | else |
84135d3d | 1100 | p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); |
7b6b4631 | 1101 | |
c9a3c58f JL |
1102 | return true; |
1103 | } | |
1104 | ||
93390c0a | 1105 | /* Read a sanitised cpufeature ID register by sys_reg_desc */ |
1c199913 DM |
1106 | static u64 read_id_reg(const struct kvm_vcpu *vcpu, |
1107 | struct sys_reg_desc const *r, bool raz) | |
93390c0a | 1108 | { |
7ba8b438 | 1109 | u32 id = reg_to_encoding(r); |
00d5101b AE |
1110 | u64 val; |
1111 | ||
1112 | if (raz) | |
1113 | return 0; | |
1114 | ||
1115 | val = read_sanitised_ftr_reg(id); | |
93390c0a | 1116 | |
c8857935 MZ |
1117 | switch (id) { |
1118 | case SYS_ID_AA64PFR0_EL1: | |
4fcdf106 | 1119 | if (!vcpu_has_sve(vcpu)) |
f76f89e2 FT |
1120 | val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE); |
1121 | val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_AMU); | |
1122 | val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2); | |
1123 | val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); | |
1124 | val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3); | |
1125 | val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); | |
562e530f MZ |
1126 | if (irqchip_in_kernel(vcpu->kvm) && |
1127 | vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { | |
1128 | val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC); | |
1129 | val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), 1); | |
1130 | } | |
c8857935 MZ |
1131 | break; |
1132 | case SYS_ID_AA64PFR1_EL1: | |
16dd1fbb FT |
1133 | if (!kvm_has_mte(vcpu->kvm)) |
1134 | val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE); | |
c8857935 MZ |
1135 | break; |
1136 | case SYS_ID_AA64ISAR1_EL1: | |
1137 | if (!vcpu_has_ptrauth(vcpu)) | |
f76f89e2 FT |
1138 | val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | |
1139 | ARM64_FEATURE_MASK(ID_AA64ISAR1_API) | | |
1140 | ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) | | |
1141 | ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI)); | |
c8857935 | 1142 | break; |
def8c222 VM |
1143 | case SYS_ID_AA64ISAR2_EL1: |
1144 | if (!vcpu_has_ptrauth(vcpu)) | |
1145 | val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | | |
1146 | ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3)); | |
1147 | break; | |
c8857935 | 1148 | case SYS_ID_AA64DFR0_EL1: |
94893fc9 | 1149 | /* Limit debug to ARMv8.0 */ |
f76f89e2 FT |
1150 | val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER); |
1151 | val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6); | |
46081078 | 1152 | /* Limit guests to PMUv3 for ARMv8.4 */ |
c854188e | 1153 | val = cpuid_feature_cap_perfmon_field(val, |
c8857935 | 1154 | ID_AA64DFR0_PMUVER_SHIFT, |
46081078 | 1155 | kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0); |
96f4f680 | 1156 | /* Hide SPE from guests */ |
f76f89e2 | 1157 | val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER); |
c8857935 MZ |
1158 | break; |
1159 | case SYS_ID_DFR0_EL1: | |
46081078 | 1160 | /* Limit guests to PMUv3 for ARMv8.4 */ |
c854188e | 1161 | val = cpuid_feature_cap_perfmon_field(val, |
cb959146 | 1162 | ID_DFR0_PERFMON_SHIFT, |
46081078 | 1163 | kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0); |
c8857935 | 1164 | break; |
07d79fe7 DM |
1165 | } |
1166 | ||
1167 | return val; | |
93390c0a DM |
1168 | } |
1169 | ||
912dee57 AJ |
1170 | static unsigned int id_visibility(const struct kvm_vcpu *vcpu, |
1171 | const struct sys_reg_desc *r) | |
1172 | { | |
7ba8b438 | 1173 | u32 id = reg_to_encoding(r); |
c512298e AJ |
1174 | |
1175 | switch (id) { | |
1176 | case SYS_ID_AA64ZFR0_EL1: | |
1177 | if (!vcpu_has_sve(vcpu)) | |
1178 | return REG_RAZ; | |
1179 | break; | |
1180 | } | |
1181 | ||
912dee57 AJ |
1182 | return 0; |
1183 | } | |
1184 | ||
93390c0a DM |
1185 | /* cpufeature ID register access trap handlers */ |
1186 | ||
1187 | static bool __access_id_reg(struct kvm_vcpu *vcpu, | |
1188 | struct sys_reg_params *p, | |
1189 | const struct sys_reg_desc *r, | |
1190 | bool raz) | |
1191 | { | |
1192 | if (p->is_write) | |
1193 | return write_to_read_only(vcpu, p, r); | |
1194 | ||
1c199913 | 1195 | p->regval = read_id_reg(vcpu, r, raz); |
93390c0a DM |
1196 | return true; |
1197 | } | |
1198 | ||
1199 | static bool access_id_reg(struct kvm_vcpu *vcpu, | |
1200 | struct sys_reg_params *p, | |
1201 | const struct sys_reg_desc *r) | |
1202 | { | |
912dee57 AJ |
1203 | bool raz = sysreg_visible_as_raz(vcpu, r); |
1204 | ||
1205 | return __access_id_reg(vcpu, p, r, raz); | |
93390c0a DM |
1206 | } |
1207 | ||
1208 | static bool access_raz_id_reg(struct kvm_vcpu *vcpu, | |
1209 | struct sys_reg_params *p, | |
1210 | const struct sys_reg_desc *r) | |
1211 | { | |
1212 | return __access_id_reg(vcpu, p, r, true); | |
1213 | } | |
1214 | ||
73433762 DM |
1215 | /* Visibility overrides for SVE-specific control registers */ |
1216 | static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, | |
1217 | const struct sys_reg_desc *rd) | |
1218 | { | |
1219 | if (vcpu_has_sve(vcpu)) | |
1220 | return 0; | |
1221 | ||
01fe5ace | 1222 | return REG_HIDDEN; |
73433762 DM |
1223 | } |
1224 | ||
23711a5e MZ |
1225 | static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, |
1226 | const struct sys_reg_desc *rd, | |
1227 | const struct kvm_one_reg *reg, void __user *uaddr) | |
1228 | { | |
1229 | const u64 id = sys_reg_to_index(rd); | |
4f1df628 | 1230 | u8 csv2, csv3; |
23711a5e MZ |
1231 | int err; |
1232 | u64 val; | |
23711a5e MZ |
1233 | |
1234 | err = reg_from_user(&val, uaddr, id); | |
1235 | if (err) | |
1236 | return err; | |
1237 | ||
1238 | /* | |
1239 | * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as | |
1240 | * it doesn't promise more than what is actually provided (the | |
1241 | * guest could otherwise be covered in ectoplasmic residue). | |
1242 | */ | |
1243 | csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT); | |
1244 | if (csv2 > 1 || | |
1245 | (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED)) | |
1246 | return -EINVAL; | |
1247 | ||
4f1df628 MZ |
1248 | /* Same thing for CSV3 */ |
1249 | csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV3_SHIFT); | |
1250 | if (csv3 > 1 || | |
1251 | (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED)) | |
1252 | return -EINVAL; | |
1253 | ||
1254 | /* We can only differ with CSV[23], and anything else is an error */ | |
23711a5e | 1255 | val ^= read_id_reg(vcpu, rd, false); |
4f1df628 MZ |
1256 | val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) | |
1257 | (0xFUL << ID_AA64PFR0_CSV3_SHIFT)); | |
23711a5e MZ |
1258 | if (val) |
1259 | return -EINVAL; | |
1260 | ||
1261 | vcpu->kvm->arch.pfr0_csv2 = csv2; | |
4f1df628 | 1262 | vcpu->kvm->arch.pfr0_csv3 = csv3 ; |
23711a5e MZ |
1263 | |
1264 | return 0; | |
1265 | } | |
1266 | ||
93390c0a DM |
1267 | /* |
1268 | * cpufeature ID register user accessors | |
1269 | * | |
1270 | * For now, these registers are immutable for userspace, so no values | |
1271 | * are stored, and for set_id_reg() we don't allow the effective value | |
1272 | * to be changed. | |
1273 | */ | |
1c199913 DM |
1274 | static int __get_id_reg(const struct kvm_vcpu *vcpu, |
1275 | const struct sys_reg_desc *rd, void __user *uaddr, | |
93390c0a DM |
1276 | bool raz) |
1277 | { | |
1278 | const u64 id = sys_reg_to_index(rd); | |
1c199913 | 1279 | const u64 val = read_id_reg(vcpu, rd, raz); |
93390c0a DM |
1280 | |
1281 | return reg_to_user(uaddr, &val, id); | |
1282 | } | |
1283 | ||
1c199913 DM |
1284 | static int __set_id_reg(const struct kvm_vcpu *vcpu, |
1285 | const struct sys_reg_desc *rd, void __user *uaddr, | |
93390c0a DM |
1286 | bool raz) |
1287 | { | |
1288 | const u64 id = sys_reg_to_index(rd); | |
1289 | int err; | |
1290 | u64 val; | |
1291 | ||
1292 | err = reg_from_user(&val, uaddr, id); | |
1293 | if (err) | |
1294 | return err; | |
1295 | ||
1296 | /* This is what we mean by invariant: you can't change it. */ | |
1c199913 | 1297 | if (val != read_id_reg(vcpu, rd, raz)) |
93390c0a DM |
1298 | return -EINVAL; |
1299 | ||
1300 | return 0; | |
1301 | } | |
1302 | ||
1303 | static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
1304 | const struct kvm_one_reg *reg, void __user *uaddr) | |
1305 | { | |
912dee57 AJ |
1306 | bool raz = sysreg_visible_as_raz(vcpu, rd); |
1307 | ||
1308 | return __get_id_reg(vcpu, rd, uaddr, raz); | |
93390c0a DM |
1309 | } |
1310 | ||
1311 | static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
1312 | const struct kvm_one_reg *reg, void __user *uaddr) | |
1313 | { | |
912dee57 AJ |
1314 | bool raz = sysreg_visible_as_raz(vcpu, rd); |
1315 | ||
1316 | return __set_id_reg(vcpu, rd, uaddr, raz); | |
93390c0a DM |
1317 | } |
1318 | ||
93390c0a DM |
1319 | static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
1320 | const struct kvm_one_reg *reg, void __user *uaddr) | |
1321 | { | |
1c199913 | 1322 | return __set_id_reg(vcpu, rd, uaddr, true); |
93390c0a DM |
1323 | } |
1324 | ||
5a430976 AE |
1325 | static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
1326 | const struct kvm_one_reg *reg, void __user *uaddr) | |
1327 | { | |
1328 | const u64 id = sys_reg_to_index(rd); | |
1329 | const u64 val = 0; | |
1330 | ||
1331 | return reg_to_user(uaddr, &val, id); | |
1332 | } | |
1333 | ||
7a3ba309 MZ |
1334 | static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
1335 | const struct kvm_one_reg *reg, void __user *uaddr) | |
1336 | { | |
1337 | int err; | |
1338 | u64 val; | |
1339 | ||
1340 | /* Perform the access even if we are going to ignore the value */ | |
1341 | err = reg_from_user(&val, uaddr, sys_reg_to_index(rd)); | |
1342 | if (err) | |
1343 | return err; | |
1344 | ||
1345 | return 0; | |
1346 | } | |
1347 | ||
f7f2b15c AB |
1348 | static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
1349 | const struct sys_reg_desc *r) | |
1350 | { | |
1351 | if (p->is_write) | |
1352 | return write_to_read_only(vcpu, p, r); | |
1353 | ||
1354 | p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); | |
1355 | return true; | |
1356 | } | |
1357 | ||
1358 | static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, | |
1359 | const struct sys_reg_desc *r) | |
1360 | { | |
1361 | if (p->is_write) | |
1362 | return write_to_read_only(vcpu, p, r); | |
1363 | ||
1364 | p->regval = read_sysreg(clidr_el1); | |
1365 | return true; | |
1366 | } | |
1367 | ||
1368 | static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, | |
1369 | const struct sys_reg_desc *r) | |
1370 | { | |
7c582bf4 JM |
1371 | int reg = r->reg; |
1372 | ||
f7f2b15c | 1373 | if (p->is_write) |
7c582bf4 | 1374 | vcpu_write_sys_reg(vcpu, p->regval, reg); |
f7f2b15c | 1375 | else |
7c582bf4 | 1376 | p->regval = vcpu_read_sys_reg(vcpu, reg); |
f7f2b15c AB |
1377 | return true; |
1378 | } | |
1379 | ||
1380 | static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, | |
1381 | const struct sys_reg_desc *r) | |
1382 | { | |
1383 | u32 csselr; | |
1384 | ||
1385 | if (p->is_write) | |
1386 | return write_to_read_only(vcpu, p, r); | |
1387 | ||
1388 | csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); | |
1389 | p->regval = get_ccsidr(csselr); | |
793acf87 AB |
1390 | |
1391 | /* | |
1392 | * Guests should not be doing cache operations by set/way at all, and | |
1393 | * for this reason, we trap them and attempt to infer the intent, so | |
1394 | * that we can flush the entire guest's address space at the appropriate | |
1395 | * time. | |
1396 | * To prevent this trapping from causing performance problems, let's | |
1397 | * expose the geometry of all data and unified caches (which are | |
1398 | * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. | |
1399 | * [If guests should attempt to infer aliasing properties from the | |
1400 | * geometry (which is not permitted by the architecture), they would | |
1401 | * only do so for virtually indexed caches.] | |
1402 | */ | |
1403 | if (!(csselr & 1)) // data or unified cache | |
1404 | p->regval &= ~GENMASK(27, 3); | |
f7f2b15c AB |
1405 | return true; |
1406 | } | |
1407 | ||
e1f358b5 SP |
1408 | static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, |
1409 | const struct sys_reg_desc *rd) | |
1410 | { | |
673638f4 SP |
1411 | if (kvm_has_mte(vcpu->kvm)) |
1412 | return 0; | |
1413 | ||
e1f358b5 SP |
1414 | return REG_HIDDEN; |
1415 | } | |
1416 | ||
1417 | #define MTE_REG(name) { \ | |
1418 | SYS_DESC(SYS_##name), \ | |
1419 | .access = undef_access, \ | |
1420 | .reset = reset_unknown, \ | |
1421 | .reg = name, \ | |
1422 | .visibility = mte_visibility, \ | |
1423 | } | |
1424 | ||
93390c0a DM |
1425 | /* sys_reg_desc initialiser for known cpufeature ID registers */ |
1426 | #define ID_SANITISED(name) { \ | |
1427 | SYS_DESC(SYS_##name), \ | |
1428 | .access = access_id_reg, \ | |
1429 | .get_user = get_id_reg, \ | |
1430 | .set_user = set_id_reg, \ | |
912dee57 | 1431 | .visibility = id_visibility, \ |
93390c0a DM |
1432 | } |
1433 | ||
1434 | /* | |
1435 | * sys_reg_desc initialiser for architecturally unallocated cpufeature ID | |
1436 | * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 | |
1437 | * (1 <= crm < 8, 0 <= Op2 < 8). | |
1438 | */ | |
1439 | #define ID_UNALLOCATED(crm, op2) { \ | |
1440 | Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ | |
1441 | .access = access_raz_id_reg, \ | |
ebf6aa8c | 1442 | .get_user = get_raz_reg, \ |
93390c0a DM |
1443 | .set_user = set_raz_id_reg, \ |
1444 | } | |
1445 | ||
1446 | /* | |
1447 | * sys_reg_desc initialiser for known ID registers that we hide from guests. | |
1448 | * For now, these are exposed just like unallocated ID regs: they appear | |
1449 | * RAZ for the guest. | |
1450 | */ | |
1451 | #define ID_HIDDEN(name) { \ | |
1452 | SYS_DESC(SYS_##name), \ | |
1453 | .access = access_raz_id_reg, \ | |
ebf6aa8c | 1454 | .get_user = get_raz_reg, \ |
93390c0a DM |
1455 | .set_user = set_raz_id_reg, \ |
1456 | } | |
1457 | ||
7c8c5e6a MZ |
1458 | /* |
1459 | * Architected system registers. | |
1460 | * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 | |
7609c125 | 1461 | * |
0c557ed4 MZ |
1462 | * Debug handling: We do trap most, if not all debug related system |
1463 | * registers. The implementation is good enough to ensure that a guest | |
1464 | * can use these with minimal performance degradation. The drawback is | |
7dabf02f OU |
1465 | * that we don't implement any of the external debug architecture. |
1466 | * This should be revisited if we ever encounter a more demanding | |
1467 | * guest... | |
7c8c5e6a MZ |
1468 | */ |
1469 | static const struct sys_reg_desc sys_reg_descs[] = { | |
7606e078 MR |
1470 | { SYS_DESC(SYS_DC_ISW), access_dcsw }, |
1471 | { SYS_DESC(SYS_DC_CSW), access_dcsw }, | |
1472 | { SYS_DESC(SYS_DC_CISW), access_dcsw }, | |
7c8c5e6a | 1473 | |
0c557ed4 MZ |
1474 | DBG_BCR_BVR_WCR_WVR_EL1(0), |
1475 | DBG_BCR_BVR_WCR_WVR_EL1(1), | |
ee1b64e6 MR |
1476 | { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, |
1477 | { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, | |
0c557ed4 MZ |
1478 | DBG_BCR_BVR_WCR_WVR_EL1(2), |
1479 | DBG_BCR_BVR_WCR_WVR_EL1(3), | |
1480 | DBG_BCR_BVR_WCR_WVR_EL1(4), | |
1481 | DBG_BCR_BVR_WCR_WVR_EL1(5), | |
1482 | DBG_BCR_BVR_WCR_WVR_EL1(6), | |
1483 | DBG_BCR_BVR_WCR_WVR_EL1(7), | |
1484 | DBG_BCR_BVR_WCR_WVR_EL1(8), | |
1485 | DBG_BCR_BVR_WCR_WVR_EL1(9), | |
1486 | DBG_BCR_BVR_WCR_WVR_EL1(10), | |
1487 | DBG_BCR_BVR_WCR_WVR_EL1(11), | |
1488 | DBG_BCR_BVR_WCR_WVR_EL1(12), | |
1489 | DBG_BCR_BVR_WCR_WVR_EL1(13), | |
1490 | DBG_BCR_BVR_WCR_WVR_EL1(14), | |
1491 | DBG_BCR_BVR_WCR_WVR_EL1(15), | |
1492 | ||
ee1b64e6 | 1493 | { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, |
f24adc65 | 1494 | { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, |
d42e2671 OU |
1495 | { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, |
1496 | SYS_OSLSR_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, | |
ee1b64e6 MR |
1497 | { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, |
1498 | { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, | |
1499 | { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, | |
1500 | { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, | |
1501 | { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, | |
1502 | ||
1503 | { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, | |
1504 | { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, | |
1505 | // DBGDTR[TR]X_EL0 share the same encoding | |
1506 | { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, | |
1507 | ||
1508 | { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, | |
62a89c44 | 1509 | |
851050a5 | 1510 | { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, |
93390c0a DM |
1511 | |
1512 | /* | |
1513 | * ID regs: all ID_SANITISED() entries here must have corresponding | |
1514 | * entries in arm64_ftr_regs[]. | |
1515 | */ | |
1516 | ||
1517 | /* AArch64 mappings of the AArch32 ID registers */ | |
1518 | /* CRm=1 */ | |
1519 | ID_SANITISED(ID_PFR0_EL1), | |
1520 | ID_SANITISED(ID_PFR1_EL1), | |
1521 | ID_SANITISED(ID_DFR0_EL1), | |
1522 | ID_HIDDEN(ID_AFR0_EL1), | |
1523 | ID_SANITISED(ID_MMFR0_EL1), | |
1524 | ID_SANITISED(ID_MMFR1_EL1), | |
1525 | ID_SANITISED(ID_MMFR2_EL1), | |
1526 | ID_SANITISED(ID_MMFR3_EL1), | |
1527 | ||
1528 | /* CRm=2 */ | |
1529 | ID_SANITISED(ID_ISAR0_EL1), | |
1530 | ID_SANITISED(ID_ISAR1_EL1), | |
1531 | ID_SANITISED(ID_ISAR2_EL1), | |
1532 | ID_SANITISED(ID_ISAR3_EL1), | |
1533 | ID_SANITISED(ID_ISAR4_EL1), | |
1534 | ID_SANITISED(ID_ISAR5_EL1), | |
1535 | ID_SANITISED(ID_MMFR4_EL1), | |
8e3747be | 1536 | ID_SANITISED(ID_ISAR6_EL1), |
93390c0a DM |
1537 | |
1538 | /* CRm=3 */ | |
1539 | ID_SANITISED(MVFR0_EL1), | |
1540 | ID_SANITISED(MVFR1_EL1), | |
1541 | ID_SANITISED(MVFR2_EL1), | |
1542 | ID_UNALLOCATED(3,3), | |
16824085 | 1543 | ID_SANITISED(ID_PFR2_EL1), |
dd35ec07 | 1544 | ID_HIDDEN(ID_DFR1_EL1), |
152accf8 | 1545 | ID_SANITISED(ID_MMFR5_EL1), |
93390c0a DM |
1546 | ID_UNALLOCATED(3,7), |
1547 | ||
1548 | /* AArch64 ID registers */ | |
1549 | /* CRm=4 */ | |
23711a5e MZ |
1550 | { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg, |
1551 | .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, }, | |
93390c0a DM |
1552 | ID_SANITISED(ID_AA64PFR1_EL1), |
1553 | ID_UNALLOCATED(4,2), | |
1554 | ID_UNALLOCATED(4,3), | |
c512298e | 1555 | ID_SANITISED(ID_AA64ZFR0_EL1), |
93390c0a DM |
1556 | ID_UNALLOCATED(4,5), |
1557 | ID_UNALLOCATED(4,6), | |
1558 | ID_UNALLOCATED(4,7), | |
1559 | ||
1560 | /* CRm=5 */ | |
1561 | ID_SANITISED(ID_AA64DFR0_EL1), | |
1562 | ID_SANITISED(ID_AA64DFR1_EL1), | |
1563 | ID_UNALLOCATED(5,2), | |
1564 | ID_UNALLOCATED(5,3), | |
1565 | ID_HIDDEN(ID_AA64AFR0_EL1), | |
1566 | ID_HIDDEN(ID_AA64AFR1_EL1), | |
1567 | ID_UNALLOCATED(5,6), | |
1568 | ID_UNALLOCATED(5,7), | |
1569 | ||
1570 | /* CRm=6 */ | |
1571 | ID_SANITISED(ID_AA64ISAR0_EL1), | |
1572 | ID_SANITISED(ID_AA64ISAR1_EL1), | |
9e45365f | 1573 | ID_SANITISED(ID_AA64ISAR2_EL1), |
93390c0a DM |
1574 | ID_UNALLOCATED(6,3), |
1575 | ID_UNALLOCATED(6,4), | |
1576 | ID_UNALLOCATED(6,5), | |
1577 | ID_UNALLOCATED(6,6), | |
1578 | ID_UNALLOCATED(6,7), | |
1579 | ||
1580 | /* CRm=7 */ | |
1581 | ID_SANITISED(ID_AA64MMFR0_EL1), | |
1582 | ID_SANITISED(ID_AA64MMFR1_EL1), | |
1583 | ID_SANITISED(ID_AA64MMFR2_EL1), | |
1584 | ID_UNALLOCATED(7,3), | |
1585 | ID_UNALLOCATED(7,4), | |
1586 | ID_UNALLOCATED(7,5), | |
1587 | ID_UNALLOCATED(7,6), | |
1588 | ID_UNALLOCATED(7,7), | |
1589 | ||
851050a5 | 1590 | { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, |
af473829 | 1591 | { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, |
851050a5 | 1592 | { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, |
2ac638fc | 1593 | |
e1f358b5 SP |
1594 | MTE_REG(RGSR_EL1), |
1595 | MTE_REG(GCR_EL1), | |
2ac638fc | 1596 | |
73433762 | 1597 | { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, |
cc427cbb | 1598 | { SYS_DESC(SYS_TRFCR_EL1), undef_access }, |
851050a5 MR |
1599 | { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, |
1600 | { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, | |
1601 | { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, | |
1602 | ||
384b40ca MR |
1603 | PTRAUTH_KEY(APIA), |
1604 | PTRAUTH_KEY(APIB), | |
1605 | PTRAUTH_KEY(APDA), | |
1606 | PTRAUTH_KEY(APDB), | |
1607 | PTRAUTH_KEY(APGA), | |
1608 | ||
851050a5 MR |
1609 | { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, |
1610 | { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, | |
1611 | { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, | |
558daf69 DG |
1612 | |
1613 | { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, | |
1614 | { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, | |
1615 | { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, | |
1616 | { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, | |
1617 | { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, | |
1618 | { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, | |
1619 | { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, | |
1620 | { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, | |
1621 | ||
e1f358b5 SP |
1622 | MTE_REG(TFSR_EL1), |
1623 | MTE_REG(TFSRE0_EL1), | |
2ac638fc | 1624 | |
851050a5 MR |
1625 | { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, |
1626 | { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, | |
7c8c5e6a | 1627 | |
13611bc8 AE |
1628 | { SYS_DESC(SYS_PMSCR_EL1), undef_access }, |
1629 | { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, | |
1630 | { SYS_DESC(SYS_PMSICR_EL1), undef_access }, | |
1631 | { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, | |
1632 | { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, | |
1633 | { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, | |
1634 | { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, | |
1635 | { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, | |
1636 | { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, | |
1637 | { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, | |
1638 | { SYS_DESC(SYS_PMBSR_EL1), undef_access }, | |
1639 | /* PMBIDR_EL1 is not trapped */ | |
1640 | ||
11663111 MZ |
1641 | { PMU_SYS_REG(SYS_PMINTENSET_EL1), |
1642 | .access = access_pminten, .reg = PMINTENSET_EL1 }, | |
1643 | { PMU_SYS_REG(SYS_PMINTENCLR_EL1), | |
1644 | .access = access_pminten, .reg = PMINTENSET_EL1 }, | |
46081078 | 1645 | { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, |
7c8c5e6a | 1646 | |
851050a5 MR |
1647 | { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, |
1648 | { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, | |
7c8c5e6a | 1649 | |
22925521 MZ |
1650 | { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, |
1651 | { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, | |
1652 | { SYS_DESC(SYS_LORN_EL1), trap_loregion }, | |
1653 | { SYS_DESC(SYS_LORC_EL1), trap_loregion }, | |
1654 | { SYS_DESC(SYS_LORID_EL1), trap_loregion }, | |
cc33c4e2 | 1655 | |
851050a5 | 1656 | { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 }, |
c773ae2b | 1657 | { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, |
db7dedd0 | 1658 | |
7b1dba1f | 1659 | { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, |
e7f1d1ee | 1660 | { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, |
7b1dba1f | 1661 | { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, |
e7f1d1ee | 1662 | { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, |
7b1dba1f | 1663 | { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, |
e804d208 | 1664 | { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, |
03bd646d MZ |
1665 | { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, |
1666 | { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, | |
7b1dba1f | 1667 | { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, |
e7f1d1ee | 1668 | { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, |
7b1dba1f | 1669 | { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, |
e804d208 | 1670 | { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, |
db7dedd0 | 1671 | |
851050a5 MR |
1672 | { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, |
1673 | { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, | |
7c8c5e6a | 1674 | |
ed4ffaf4 MZ |
1675 | { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, |
1676 | ||
851050a5 | 1677 | { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, |
7c8c5e6a | 1678 | |
f7f2b15c AB |
1679 | { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, |
1680 | { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, | |
1681 | { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, | |
1682 | { SYS_DESC(SYS_CTR_EL0), access_ctr }, | |
7c8c5e6a | 1683 | |
11663111 MZ |
1684 | { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr, |
1685 | .reset = reset_pmcr, .reg = PMCR_EL0 }, | |
1686 | { PMU_SYS_REG(SYS_PMCNTENSET_EL0), | |
1687 | .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, | |
1688 | { PMU_SYS_REG(SYS_PMCNTENCLR_EL0), | |
1689 | .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, | |
1690 | { PMU_SYS_REG(SYS_PMOVSCLR_EL0), | |
1691 | .access = access_pmovs, .reg = PMOVSSET_EL0 }, | |
7a3ba309 MZ |
1692 | /* |
1693 | * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was | |
1694 | * previously (and pointlessly) advertised in the past... | |
1695 | */ | |
11663111 | 1696 | { PMU_SYS_REG(SYS_PMSWINC_EL0), |
5a430976 | 1697 | .get_user = get_raz_reg, .set_user = set_wi_reg, |
7a3ba309 | 1698 | .access = access_pmswinc, .reset = NULL }, |
11663111 | 1699 | { PMU_SYS_REG(SYS_PMSELR_EL0), |
0ab410a9 | 1700 | .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, |
11663111 MZ |
1701 | { PMU_SYS_REG(SYS_PMCEID0_EL0), |
1702 | .access = access_pmceid, .reset = NULL }, | |
1703 | { PMU_SYS_REG(SYS_PMCEID1_EL0), | |
1704 | .access = access_pmceid, .reset = NULL }, | |
1705 | { PMU_SYS_REG(SYS_PMCCNTR_EL0), | |
0ab410a9 | 1706 | .access = access_pmu_evcntr, .reset = reset_unknown, .reg = PMCCNTR_EL0 }, |
11663111 MZ |
1707 | { PMU_SYS_REG(SYS_PMXEVTYPER_EL0), |
1708 | .access = access_pmu_evtyper, .reset = NULL }, | |
1709 | { PMU_SYS_REG(SYS_PMXEVCNTR_EL0), | |
1710 | .access = access_pmu_evcntr, .reset = NULL }, | |
174ed3e4 MR |
1711 | /* |
1712 | * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero | |
d692b8ad SZ |
1713 | * in 32bit mode. Here we choose to reset it as zero for consistency. |
1714 | */ | |
11663111 MZ |
1715 | { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr, |
1716 | .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, | |
1717 | { PMU_SYS_REG(SYS_PMOVSSET_EL0), | |
1718 | .access = access_pmovs, .reg = PMOVSSET_EL0 }, | |
7c8c5e6a | 1719 | |
851050a5 MR |
1720 | { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, |
1721 | { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, | |
4fcdf106 | 1722 | |
ed4ffaf4 MZ |
1723 | { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, |
1724 | ||
338b1793 MZ |
1725 | { SYS_DESC(SYS_AMCR_EL0), undef_access }, |
1726 | { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, | |
1727 | { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, | |
1728 | { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, | |
1729 | { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, | |
1730 | { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, | |
1731 | { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, | |
1732 | { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, | |
4fcdf106 IV |
1733 | AMU_AMEVCNTR0_EL0(0), |
1734 | AMU_AMEVCNTR0_EL0(1), | |
1735 | AMU_AMEVCNTR0_EL0(2), | |
1736 | AMU_AMEVCNTR0_EL0(3), | |
1737 | AMU_AMEVCNTR0_EL0(4), | |
1738 | AMU_AMEVCNTR0_EL0(5), | |
1739 | AMU_AMEVCNTR0_EL0(6), | |
1740 | AMU_AMEVCNTR0_EL0(7), | |
1741 | AMU_AMEVCNTR0_EL0(8), | |
1742 | AMU_AMEVCNTR0_EL0(9), | |
1743 | AMU_AMEVCNTR0_EL0(10), | |
1744 | AMU_AMEVCNTR0_EL0(11), | |
1745 | AMU_AMEVCNTR0_EL0(12), | |
1746 | AMU_AMEVCNTR0_EL0(13), | |
1747 | AMU_AMEVCNTR0_EL0(14), | |
1748 | AMU_AMEVCNTR0_EL0(15), | |
493cf9b7 VM |
1749 | AMU_AMEVTYPER0_EL0(0), |
1750 | AMU_AMEVTYPER0_EL0(1), | |
1751 | AMU_AMEVTYPER0_EL0(2), | |
1752 | AMU_AMEVTYPER0_EL0(3), | |
1753 | AMU_AMEVTYPER0_EL0(4), | |
1754 | AMU_AMEVTYPER0_EL0(5), | |
1755 | AMU_AMEVTYPER0_EL0(6), | |
1756 | AMU_AMEVTYPER0_EL0(7), | |
1757 | AMU_AMEVTYPER0_EL0(8), | |
1758 | AMU_AMEVTYPER0_EL0(9), | |
1759 | AMU_AMEVTYPER0_EL0(10), | |
1760 | AMU_AMEVTYPER0_EL0(11), | |
1761 | AMU_AMEVTYPER0_EL0(12), | |
1762 | AMU_AMEVTYPER0_EL0(13), | |
1763 | AMU_AMEVTYPER0_EL0(14), | |
1764 | AMU_AMEVTYPER0_EL0(15), | |
4fcdf106 IV |
1765 | AMU_AMEVCNTR1_EL0(0), |
1766 | AMU_AMEVCNTR1_EL0(1), | |
1767 | AMU_AMEVCNTR1_EL0(2), | |
1768 | AMU_AMEVCNTR1_EL0(3), | |
1769 | AMU_AMEVCNTR1_EL0(4), | |
1770 | AMU_AMEVCNTR1_EL0(5), | |
1771 | AMU_AMEVCNTR1_EL0(6), | |
1772 | AMU_AMEVCNTR1_EL0(7), | |
1773 | AMU_AMEVCNTR1_EL0(8), | |
1774 | AMU_AMEVCNTR1_EL0(9), | |
1775 | AMU_AMEVCNTR1_EL0(10), | |
1776 | AMU_AMEVCNTR1_EL0(11), | |
1777 | AMU_AMEVCNTR1_EL0(12), | |
1778 | AMU_AMEVCNTR1_EL0(13), | |
1779 | AMU_AMEVCNTR1_EL0(14), | |
1780 | AMU_AMEVCNTR1_EL0(15), | |
493cf9b7 VM |
1781 | AMU_AMEVTYPER1_EL0(0), |
1782 | AMU_AMEVTYPER1_EL0(1), | |
1783 | AMU_AMEVTYPER1_EL0(2), | |
1784 | AMU_AMEVTYPER1_EL0(3), | |
1785 | AMU_AMEVTYPER1_EL0(4), | |
1786 | AMU_AMEVTYPER1_EL0(5), | |
1787 | AMU_AMEVTYPER1_EL0(6), | |
1788 | AMU_AMEVTYPER1_EL0(7), | |
1789 | AMU_AMEVTYPER1_EL0(8), | |
1790 | AMU_AMEVTYPER1_EL0(9), | |
1791 | AMU_AMEVTYPER1_EL0(10), | |
1792 | AMU_AMEVTYPER1_EL0(11), | |
1793 | AMU_AMEVTYPER1_EL0(12), | |
1794 | AMU_AMEVTYPER1_EL0(13), | |
1795 | AMU_AMEVTYPER1_EL0(14), | |
1796 | AMU_AMEVTYPER1_EL0(15), | |
62a89c44 | 1797 | |
84135d3d AP |
1798 | { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, |
1799 | { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, | |
1800 | { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, | |
c9a3c58f | 1801 | |
051ff581 SZ |
1802 | /* PMEVCNTRn_EL0 */ |
1803 | PMU_PMEVCNTR_EL0(0), | |
1804 | PMU_PMEVCNTR_EL0(1), | |
1805 | PMU_PMEVCNTR_EL0(2), | |
1806 | PMU_PMEVCNTR_EL0(3), | |
1807 | PMU_PMEVCNTR_EL0(4), | |
1808 | PMU_PMEVCNTR_EL0(5), | |
1809 | PMU_PMEVCNTR_EL0(6), | |
1810 | PMU_PMEVCNTR_EL0(7), | |
1811 | PMU_PMEVCNTR_EL0(8), | |
1812 | PMU_PMEVCNTR_EL0(9), | |
1813 | PMU_PMEVCNTR_EL0(10), | |
1814 | PMU_PMEVCNTR_EL0(11), | |
1815 | PMU_PMEVCNTR_EL0(12), | |
1816 | PMU_PMEVCNTR_EL0(13), | |
1817 | PMU_PMEVCNTR_EL0(14), | |
1818 | PMU_PMEVCNTR_EL0(15), | |
1819 | PMU_PMEVCNTR_EL0(16), | |
1820 | PMU_PMEVCNTR_EL0(17), | |
1821 | PMU_PMEVCNTR_EL0(18), | |
1822 | PMU_PMEVCNTR_EL0(19), | |
1823 | PMU_PMEVCNTR_EL0(20), | |
1824 | PMU_PMEVCNTR_EL0(21), | |
1825 | PMU_PMEVCNTR_EL0(22), | |
1826 | PMU_PMEVCNTR_EL0(23), | |
1827 | PMU_PMEVCNTR_EL0(24), | |
1828 | PMU_PMEVCNTR_EL0(25), | |
1829 | PMU_PMEVCNTR_EL0(26), | |
1830 | PMU_PMEVCNTR_EL0(27), | |
1831 | PMU_PMEVCNTR_EL0(28), | |
1832 | PMU_PMEVCNTR_EL0(29), | |
1833 | PMU_PMEVCNTR_EL0(30), | |
9feb21ac SZ |
1834 | /* PMEVTYPERn_EL0 */ |
1835 | PMU_PMEVTYPER_EL0(0), | |
1836 | PMU_PMEVTYPER_EL0(1), | |
1837 | PMU_PMEVTYPER_EL0(2), | |
1838 | PMU_PMEVTYPER_EL0(3), | |
1839 | PMU_PMEVTYPER_EL0(4), | |
1840 | PMU_PMEVTYPER_EL0(5), | |
1841 | PMU_PMEVTYPER_EL0(6), | |
1842 | PMU_PMEVTYPER_EL0(7), | |
1843 | PMU_PMEVTYPER_EL0(8), | |
1844 | PMU_PMEVTYPER_EL0(9), | |
1845 | PMU_PMEVTYPER_EL0(10), | |
1846 | PMU_PMEVTYPER_EL0(11), | |
1847 | PMU_PMEVTYPER_EL0(12), | |
1848 | PMU_PMEVTYPER_EL0(13), | |
1849 | PMU_PMEVTYPER_EL0(14), | |
1850 | PMU_PMEVTYPER_EL0(15), | |
1851 | PMU_PMEVTYPER_EL0(16), | |
1852 | PMU_PMEVTYPER_EL0(17), | |
1853 | PMU_PMEVTYPER_EL0(18), | |
1854 | PMU_PMEVTYPER_EL0(19), | |
1855 | PMU_PMEVTYPER_EL0(20), | |
1856 | PMU_PMEVTYPER_EL0(21), | |
1857 | PMU_PMEVTYPER_EL0(22), | |
1858 | PMU_PMEVTYPER_EL0(23), | |
1859 | PMU_PMEVTYPER_EL0(24), | |
1860 | PMU_PMEVTYPER_EL0(25), | |
1861 | PMU_PMEVTYPER_EL0(26), | |
1862 | PMU_PMEVTYPER_EL0(27), | |
1863 | PMU_PMEVTYPER_EL0(28), | |
1864 | PMU_PMEVTYPER_EL0(29), | |
1865 | PMU_PMEVTYPER_EL0(30), | |
174ed3e4 MR |
1866 | /* |
1867 | * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero | |
9feb21ac SZ |
1868 | * in 32bit mode. Here we choose to reset it as zero for consistency. |
1869 | */ | |
11663111 MZ |
1870 | { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper, |
1871 | .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, | |
051ff581 | 1872 | |
851050a5 MR |
1873 | { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, |
1874 | { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, | |
c88b0936 | 1875 | { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, |
62a89c44 MZ |
1876 | }; |
1877 | ||
8c358b29 | 1878 | static bool trap_dbgdidr(struct kvm_vcpu *vcpu, |
3fec037d | 1879 | struct sys_reg_params *p, |
bdfb4b38 MZ |
1880 | const struct sys_reg_desc *r) |
1881 | { | |
1882 | if (p->is_write) { | |
1883 | return ignore_write(vcpu, p); | |
1884 | } else { | |
46823dd1 DM |
1885 | u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); |
1886 | u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); | |
28c5dcb2 | 1887 | u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); |
bdfb4b38 | 1888 | |
2ec5be3d PF |
1889 | p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | |
1890 | (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | | |
1891 | (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) | |
bea7e97f | 1892 | | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); |
bdfb4b38 MZ |
1893 | return true; |
1894 | } | |
1895 | } | |
1896 | ||
1da42c34 MZ |
1897 | /* |
1898 | * AArch32 debug register mappings | |
84e690bf AB |
1899 | * |
1900 | * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] | |
1901 | * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] | |
1902 | * | |
1da42c34 MZ |
1903 | * None of the other registers share their location, so treat them as |
1904 | * if they were 64bit. | |
84e690bf | 1905 | */ |
1da42c34 MZ |
1906 | #define DBG_BCR_BVR_WCR_WVR(n) \ |
1907 | /* DBGBVRn */ \ | |
1908 | { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ | |
1909 | /* DBGBCRn */ \ | |
1910 | { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ | |
1911 | /* DBGWVRn */ \ | |
1912 | { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ | |
1913 | /* DBGWCRn */ \ | |
84e690bf AB |
1914 | { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } |
1915 | ||
1da42c34 MZ |
1916 | #define DBGBXVR(n) \ |
1917 | { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } | |
bdfb4b38 MZ |
1918 | |
1919 | /* | |
1920 | * Trapped cp14 registers. We generally ignore most of the external | |
1921 | * debug, on the principle that they don't really make sense to a | |
84e690bf | 1922 | * guest. Revisit this one day, would this principle change. |
bdfb4b38 | 1923 | */ |
72564016 | 1924 | static const struct sys_reg_desc cp14_regs[] = { |
8c358b29 AE |
1925 | /* DBGDIDR */ |
1926 | { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, | |
bdfb4b38 MZ |
1927 | /* DBGDTRRXext */ |
1928 | { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, | |
1929 | ||
1930 | DBG_BCR_BVR_WCR_WVR(0), | |
1931 | /* DBGDSCRint */ | |
1932 | { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, | |
1933 | DBG_BCR_BVR_WCR_WVR(1), | |
1934 | /* DBGDCCINT */ | |
1da42c34 | 1935 | { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, |
bdfb4b38 | 1936 | /* DBGDSCRext */ |
1da42c34 | 1937 | { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, |
bdfb4b38 MZ |
1938 | DBG_BCR_BVR_WCR_WVR(2), |
1939 | /* DBGDTR[RT]Xint */ | |
1940 | { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, | |
1941 | /* DBGDTR[RT]Xext */ | |
1942 | { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, | |
1943 | DBG_BCR_BVR_WCR_WVR(3), | |
1944 | DBG_BCR_BVR_WCR_WVR(4), | |
1945 | DBG_BCR_BVR_WCR_WVR(5), | |
1946 | /* DBGWFAR */ | |
1947 | { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, | |
1948 | /* DBGOSECCR */ | |
1949 | { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, | |
1950 | DBG_BCR_BVR_WCR_WVR(6), | |
1951 | /* DBGVCR */ | |
1da42c34 | 1952 | { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, |
bdfb4b38 MZ |
1953 | DBG_BCR_BVR_WCR_WVR(7), |
1954 | DBG_BCR_BVR_WCR_WVR(8), | |
1955 | DBG_BCR_BVR_WCR_WVR(9), | |
1956 | DBG_BCR_BVR_WCR_WVR(10), | |
1957 | DBG_BCR_BVR_WCR_WVR(11), | |
1958 | DBG_BCR_BVR_WCR_WVR(12), | |
1959 | DBG_BCR_BVR_WCR_WVR(13), | |
1960 | DBG_BCR_BVR_WCR_WVR(14), | |
1961 | DBG_BCR_BVR_WCR_WVR(15), | |
1962 | ||
1963 | /* DBGDRAR (32bit) */ | |
1964 | { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, | |
1965 | ||
1966 | DBGBXVR(0), | |
1967 | /* DBGOSLAR */ | |
f24adc65 | 1968 | { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, |
bdfb4b38 MZ |
1969 | DBGBXVR(1), |
1970 | /* DBGOSLSR */ | |
d42e2671 | 1971 | { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, |
bdfb4b38 MZ |
1972 | DBGBXVR(2), |
1973 | DBGBXVR(3), | |
1974 | /* DBGOSDLR */ | |
1975 | { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, | |
1976 | DBGBXVR(4), | |
1977 | /* DBGPRCR */ | |
1978 | { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, | |
1979 | DBGBXVR(5), | |
1980 | DBGBXVR(6), | |
1981 | DBGBXVR(7), | |
1982 | DBGBXVR(8), | |
1983 | DBGBXVR(9), | |
1984 | DBGBXVR(10), | |
1985 | DBGBXVR(11), | |
1986 | DBGBXVR(12), | |
1987 | DBGBXVR(13), | |
1988 | DBGBXVR(14), | |
1989 | DBGBXVR(15), | |
1990 | ||
1991 | /* DBGDSAR (32bit) */ | |
1992 | { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, | |
1993 | ||
1994 | /* DBGDEVID2 */ | |
1995 | { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, | |
1996 | /* DBGDEVID1 */ | |
1997 | { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, | |
1998 | /* DBGDEVID */ | |
1999 | { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, | |
2000 | /* DBGCLAIMSET */ | |
2001 | { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, | |
2002 | /* DBGCLAIMCLR */ | |
2003 | { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, | |
2004 | /* DBGAUTHSTATUS */ | |
2005 | { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, | |
72564016 MZ |
2006 | }; |
2007 | ||
a9866ba0 MZ |
2008 | /* Trapped cp14 64bit registers */ |
2009 | static const struct sys_reg_desc cp14_64_regs[] = { | |
bdfb4b38 MZ |
2010 | /* DBGDRAR (64bit) */ |
2011 | { Op1( 0), CRm( 1), .access = trap_raz_wi }, | |
2012 | ||
2013 | /* DBGDSAR (64bit) */ | |
2014 | { Op1( 0), CRm( 2), .access = trap_raz_wi }, | |
a9866ba0 MZ |
2015 | }; |
2016 | ||
051ff581 SZ |
2017 | /* Macro to expand the PMEVCNTRn register */ |
2018 | #define PMU_PMEVCNTR(n) \ | |
2019 | /* PMEVCNTRn */ \ | |
2020 | { Op1(0), CRn(0b1110), \ | |
2021 | CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ | |
2022 | access_pmu_evcntr } | |
2023 | ||
9feb21ac SZ |
2024 | /* Macro to expand the PMEVTYPERn register */ |
2025 | #define PMU_PMEVTYPER(n) \ | |
2026 | /* PMEVTYPERn */ \ | |
2027 | { Op1(0), CRn(0b1110), \ | |
2028 | CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ | |
2029 | access_pmu_evtyper } | |
2030 | ||
4d44923b MZ |
2031 | /* |
2032 | * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, | |
2033 | * depending on the way they are accessed (as a 32bit or a 64bit | |
2034 | * register). | |
2035 | */ | |
62a89c44 | 2036 | static const struct sys_reg_desc cp15_regs[] = { |
f7f2b15c | 2037 | { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, |
b1ea1d76 MZ |
2038 | { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, |
2039 | /* ACTLR */ | |
2040 | { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, | |
2041 | /* ACTLR2 */ | |
2042 | { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, | |
2043 | { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, | |
2044 | { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, | |
2045 | /* TTBCR */ | |
2046 | { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, | |
2047 | /* TTBCR2 */ | |
2048 | { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, | |
2049 | { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, | |
2050 | /* DFSR */ | |
2051 | { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, | |
2052 | { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, | |
2053 | /* ADFSR */ | |
2054 | { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, | |
2055 | /* AIFSR */ | |
2056 | { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, | |
2057 | /* DFAR */ | |
2058 | { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, | |
2059 | /* IFAR */ | |
2060 | { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, | |
4d44923b | 2061 | |
62a89c44 MZ |
2062 | /* |
2063 | * DC{C,I,CI}SW operations: | |
2064 | */ | |
2065 | { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, | |
2066 | { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, | |
2067 | { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, | |
4d44923b | 2068 | |
7609c125 | 2069 | /* PMU */ |
ab946834 | 2070 | { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, |
96b0eebc SZ |
2071 | { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, |
2072 | { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, | |
76d883c4 | 2073 | { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, |
7a0adc70 | 2074 | { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, |
3965c3ce | 2075 | { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, |
99b6a401 MZ |
2076 | { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, |
2077 | { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, | |
051ff581 | 2078 | { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, |
9feb21ac | 2079 | { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, |
051ff581 | 2080 | { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, |
d692b8ad | 2081 | { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, |
9db52c78 SZ |
2082 | { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, |
2083 | { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, | |
76d883c4 | 2084 | { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, |
99b6a401 MZ |
2085 | { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid }, |
2086 | { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid }, | |
46081078 MZ |
2087 | /* PMMIR */ |
2088 | { Op1( 0), CRn( 9), CRm(14), Op2( 6), trap_raz_wi }, | |
4d44923b | 2089 | |
b1ea1d76 MZ |
2090 | /* PRRR/MAIR0 */ |
2091 | { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, | |
2092 | /* NMRR/MAIR1 */ | |
2093 | { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, | |
2094 | /* AMAIR0 */ | |
2095 | { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, | |
2096 | /* AMAIR1 */ | |
2097 | { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, | |
db7dedd0 CD |
2098 | |
2099 | /* ICC_SRE */ | |
f7f6f2d9 | 2100 | { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, |
db7dedd0 | 2101 | |
b1ea1d76 | 2102 | { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, |
051ff581 | 2103 | |
84135d3d AP |
2104 | /* Arch Tmers */ |
2105 | { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, | |
2106 | { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, | |
eac137b4 | 2107 | |
051ff581 SZ |
2108 | /* PMEVCNTRn */ |
2109 | PMU_PMEVCNTR(0), | |
2110 | PMU_PMEVCNTR(1), | |
2111 | PMU_PMEVCNTR(2), | |
2112 | PMU_PMEVCNTR(3), | |
2113 | PMU_PMEVCNTR(4), | |
2114 | PMU_PMEVCNTR(5), | |
2115 | PMU_PMEVCNTR(6), | |
2116 | PMU_PMEVCNTR(7), | |
2117 | PMU_PMEVCNTR(8), | |
2118 | PMU_PMEVCNTR(9), | |
2119 | PMU_PMEVCNTR(10), | |
2120 | PMU_PMEVCNTR(11), | |
2121 | PMU_PMEVCNTR(12), | |
2122 | PMU_PMEVCNTR(13), | |
2123 | PMU_PMEVCNTR(14), | |
2124 | PMU_PMEVCNTR(15), | |
2125 | PMU_PMEVCNTR(16), | |
2126 | PMU_PMEVCNTR(17), | |
2127 | PMU_PMEVCNTR(18), | |
2128 | PMU_PMEVCNTR(19), | |
2129 | PMU_PMEVCNTR(20), | |
2130 | PMU_PMEVCNTR(21), | |
2131 | PMU_PMEVCNTR(22), | |
2132 | PMU_PMEVCNTR(23), | |
2133 | PMU_PMEVCNTR(24), | |
2134 | PMU_PMEVCNTR(25), | |
2135 | PMU_PMEVCNTR(26), | |
2136 | PMU_PMEVCNTR(27), | |
2137 | PMU_PMEVCNTR(28), | |
2138 | PMU_PMEVCNTR(29), | |
2139 | PMU_PMEVCNTR(30), | |
9feb21ac SZ |
2140 | /* PMEVTYPERn */ |
2141 | PMU_PMEVTYPER(0), | |
2142 | PMU_PMEVTYPER(1), | |
2143 | PMU_PMEVTYPER(2), | |
2144 | PMU_PMEVTYPER(3), | |
2145 | PMU_PMEVTYPER(4), | |
2146 | PMU_PMEVTYPER(5), | |
2147 | PMU_PMEVTYPER(6), | |
2148 | PMU_PMEVTYPER(7), | |
2149 | PMU_PMEVTYPER(8), | |
2150 | PMU_PMEVTYPER(9), | |
2151 | PMU_PMEVTYPER(10), | |
2152 | PMU_PMEVTYPER(11), | |
2153 | PMU_PMEVTYPER(12), | |
2154 | PMU_PMEVTYPER(13), | |
2155 | PMU_PMEVTYPER(14), | |
2156 | PMU_PMEVTYPER(15), | |
2157 | PMU_PMEVTYPER(16), | |
2158 | PMU_PMEVTYPER(17), | |
2159 | PMU_PMEVTYPER(18), | |
2160 | PMU_PMEVTYPER(19), | |
2161 | PMU_PMEVTYPER(20), | |
2162 | PMU_PMEVTYPER(21), | |
2163 | PMU_PMEVTYPER(22), | |
2164 | PMU_PMEVTYPER(23), | |
2165 | PMU_PMEVTYPER(24), | |
2166 | PMU_PMEVTYPER(25), | |
2167 | PMU_PMEVTYPER(26), | |
2168 | PMU_PMEVTYPER(27), | |
2169 | PMU_PMEVTYPER(28), | |
2170 | PMU_PMEVTYPER(29), | |
2171 | PMU_PMEVTYPER(30), | |
2172 | /* PMCCFILTR */ | |
2173 | { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, | |
f7f2b15c AB |
2174 | |
2175 | { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, | |
2176 | { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, | |
b1ea1d76 | 2177 | { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, |
a9866ba0 MZ |
2178 | }; |
2179 | ||
2180 | static const struct sys_reg_desc cp15_64_regs[] = { | |
b1ea1d76 | 2181 | { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, |
051ff581 | 2182 | { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, |
03bd646d | 2183 | { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ |
b1ea1d76 | 2184 | { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, |
03bd646d MZ |
2185 | { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ |
2186 | { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ | |
84135d3d | 2187 | { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, |
7c8c5e6a MZ |
2188 | }; |
2189 | ||
bb44a8db MZ |
2190 | static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, |
2191 | bool is_32) | |
2192 | { | |
2193 | unsigned int i; | |
2194 | ||
2195 | for (i = 0; i < n; i++) { | |
2196 | if (!is_32 && table[i].reg && !table[i].reset) { | |
2197 | kvm_err("sys_reg table %p entry %d has lacks reset\n", | |
2198 | table, i); | |
2199 | return 1; | |
2200 | } | |
2201 | ||
2202 | if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { | |
2203 | kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1); | |
2204 | return 1; | |
2205 | } | |
2206 | } | |
2207 | ||
2208 | return 0; | |
2209 | } | |
2210 | ||
74cc7e0c | 2211 | int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) |
62a89c44 MZ |
2212 | { |
2213 | kvm_inject_undefined(vcpu); | |
2214 | return 1; | |
2215 | } | |
2216 | ||
e70b9522 MZ |
2217 | static void perform_access(struct kvm_vcpu *vcpu, |
2218 | struct sys_reg_params *params, | |
2219 | const struct sys_reg_desc *r) | |
2220 | { | |
599d79dc MZ |
2221 | trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); |
2222 | ||
7f34e409 | 2223 | /* Check for regs disabled by runtime config */ |
01fe5ace | 2224 | if (sysreg_hidden(vcpu, r)) { |
7f34e409 DM |
2225 | kvm_inject_undefined(vcpu); |
2226 | return; | |
2227 | } | |
2228 | ||
e70b9522 MZ |
2229 | /* |
2230 | * Not having an accessor means that we have configured a trap | |
2231 | * that we don't know how to handle. This certainly qualifies | |
2232 | * as a gross bug that should be fixed right away. | |
2233 | */ | |
2234 | BUG_ON(!r->access); | |
2235 | ||
2236 | /* Skip instruction if instructed so */ | |
2237 | if (likely(r->access(vcpu, params, r))) | |
cdb5e02e | 2238 | kvm_incr_pc(vcpu); |
e70b9522 MZ |
2239 | } |
2240 | ||
72564016 MZ |
2241 | /* |
2242 | * emulate_cp -- tries to match a sys_reg access in a handling table, and | |
2243 | * call the corresponding trap handler. | |
2244 | * | |
2245 | * @params: pointer to the descriptor of the access | |
2246 | * @table: array of trap descriptors | |
2247 | * @num: size of the trap descriptor array | |
2248 | * | |
2249 | * Return 0 if the access has been handled, and -1 if not. | |
2250 | */ | |
2251 | static int emulate_cp(struct kvm_vcpu *vcpu, | |
3fec037d | 2252 | struct sys_reg_params *params, |
72564016 MZ |
2253 | const struct sys_reg_desc *table, |
2254 | size_t num) | |
62a89c44 | 2255 | { |
72564016 | 2256 | const struct sys_reg_desc *r; |
62a89c44 | 2257 | |
72564016 MZ |
2258 | if (!table) |
2259 | return -1; /* Not handled */ | |
62a89c44 | 2260 | |
62a89c44 | 2261 | r = find_reg(params, table, num); |
62a89c44 | 2262 | |
72564016 | 2263 | if (r) { |
e70b9522 MZ |
2264 | perform_access(vcpu, params, r); |
2265 | return 0; | |
72564016 MZ |
2266 | } |
2267 | ||
2268 | /* Not handled */ | |
2269 | return -1; | |
2270 | } | |
2271 | ||
2272 | static void unhandled_cp_access(struct kvm_vcpu *vcpu, | |
2273 | struct sys_reg_params *params) | |
2274 | { | |
3a949f4c | 2275 | u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); |
40c4f8d2 | 2276 | int cp = -1; |
72564016 | 2277 | |
3a949f4c | 2278 | switch (esr_ec) { |
c6d01a94 MR |
2279 | case ESR_ELx_EC_CP15_32: |
2280 | case ESR_ELx_EC_CP15_64: | |
72564016 MZ |
2281 | cp = 15; |
2282 | break; | |
c6d01a94 MR |
2283 | case ESR_ELx_EC_CP14_MR: |
2284 | case ESR_ELx_EC_CP14_64: | |
72564016 MZ |
2285 | cp = 14; |
2286 | break; | |
2287 | default: | |
40c4f8d2 | 2288 | WARN_ON(1); |
62a89c44 MZ |
2289 | } |
2290 | ||
bf4b96bb MR |
2291 | print_sys_reg_msg(params, |
2292 | "Unsupported guest CP%d access at: %08lx [%08lx]\n", | |
2293 | cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); | |
62a89c44 MZ |
2294 | kvm_inject_undefined(vcpu); |
2295 | } | |
2296 | ||
2297 | /** | |
7769db90 | 2298 | * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access |
62a89c44 MZ |
2299 | * @vcpu: The VCPU pointer |
2300 | * @run: The kvm_run struct | |
2301 | */ | |
72564016 MZ |
2302 | static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, |
2303 | const struct sys_reg_desc *global, | |
dcaffa7b | 2304 | size_t nr_global) |
62a89c44 MZ |
2305 | { |
2306 | struct sys_reg_params params; | |
3a949f4c | 2307 | u32 esr = kvm_vcpu_get_esr(vcpu); |
c667186f | 2308 | int Rt = kvm_vcpu_sys_get_rt(vcpu); |
3a949f4c | 2309 | int Rt2 = (esr >> 10) & 0x1f; |
62a89c44 | 2310 | |
3a949f4c GS |
2311 | params.CRm = (esr >> 1) & 0xf; |
2312 | params.is_write = ((esr & 1) == 0); | |
62a89c44 MZ |
2313 | |
2314 | params.Op0 = 0; | |
3a949f4c | 2315 | params.Op1 = (esr >> 16) & 0xf; |
62a89c44 MZ |
2316 | params.Op2 = 0; |
2317 | params.CRn = 0; | |
2318 | ||
2319 | /* | |
2ec5be3d | 2320 | * Make a 64-bit value out of Rt and Rt2. As we use the same trap |
62a89c44 MZ |
2321 | * backends between AArch32 and AArch64, we get away with it. |
2322 | */ | |
2323 | if (params.is_write) { | |
2ec5be3d PF |
2324 | params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; |
2325 | params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; | |
62a89c44 MZ |
2326 | } |
2327 | ||
b6b7a806 | 2328 | /* |
dcaffa7b | 2329 | * If the table contains a handler, handle the |
b6b7a806 MZ |
2330 | * potential register operation in the case of a read and return |
2331 | * with success. | |
2332 | */ | |
dcaffa7b | 2333 | if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { |
b6b7a806 MZ |
2334 | /* Split up the value between registers for the read side */ |
2335 | if (!params.is_write) { | |
2336 | vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); | |
2337 | vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); | |
2338 | } | |
62a89c44 | 2339 | |
b6b7a806 | 2340 | return 1; |
62a89c44 MZ |
2341 | } |
2342 | ||
b6b7a806 | 2343 | unhandled_cp_access(vcpu, ¶ms); |
62a89c44 MZ |
2344 | return 1; |
2345 | } | |
2346 | ||
2347 | /** | |
7769db90 | 2348 | * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access |
62a89c44 MZ |
2349 | * @vcpu: The VCPU pointer |
2350 | * @run: The kvm_run struct | |
2351 | */ | |
72564016 MZ |
2352 | static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, |
2353 | const struct sys_reg_desc *global, | |
dcaffa7b | 2354 | size_t nr_global) |
62a89c44 MZ |
2355 | { |
2356 | struct sys_reg_params params; | |
3a949f4c | 2357 | u32 esr = kvm_vcpu_get_esr(vcpu); |
c667186f | 2358 | int Rt = kvm_vcpu_sys_get_rt(vcpu); |
62a89c44 | 2359 | |
3a949f4c | 2360 | params.CRm = (esr >> 1) & 0xf; |
2ec5be3d | 2361 | params.regval = vcpu_get_reg(vcpu, Rt); |
3a949f4c GS |
2362 | params.is_write = ((esr & 1) == 0); |
2363 | params.CRn = (esr >> 10) & 0xf; | |
62a89c44 | 2364 | params.Op0 = 0; |
3a949f4c GS |
2365 | params.Op1 = (esr >> 14) & 0x7; |
2366 | params.Op2 = (esr >> 17) & 0x7; | |
62a89c44 | 2367 | |
dcaffa7b | 2368 | if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { |
2ec5be3d PF |
2369 | if (!params.is_write) |
2370 | vcpu_set_reg(vcpu, Rt, params.regval); | |
72564016 | 2371 | return 1; |
2ec5be3d | 2372 | } |
72564016 MZ |
2373 | |
2374 | unhandled_cp_access(vcpu, ¶ms); | |
62a89c44 MZ |
2375 | return 1; |
2376 | } | |
2377 | ||
74cc7e0c | 2378 | int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) |
72564016 | 2379 | { |
dcaffa7b | 2380 | return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); |
72564016 MZ |
2381 | } |
2382 | ||
74cc7e0c | 2383 | int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) |
72564016 | 2384 | { |
dcaffa7b | 2385 | return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs)); |
72564016 MZ |
2386 | } |
2387 | ||
74cc7e0c | 2388 | int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) |
72564016 | 2389 | { |
dcaffa7b | 2390 | return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); |
72564016 MZ |
2391 | } |
2392 | ||
74cc7e0c | 2393 | int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) |
72564016 | 2394 | { |
dcaffa7b | 2395 | return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs)); |
72564016 MZ |
2396 | } |
2397 | ||
54ad68b7 MR |
2398 | static bool is_imp_def_sys_reg(struct sys_reg_params *params) |
2399 | { | |
2400 | // See ARM DDI 0487E.a, section D12.3.2 | |
2401 | return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; | |
2402 | } | |
2403 | ||
7c8c5e6a | 2404 | static int emulate_sys_reg(struct kvm_vcpu *vcpu, |
3fec037d | 2405 | struct sys_reg_params *params) |
7c8c5e6a | 2406 | { |
dcaffa7b | 2407 | const struct sys_reg_desc *r; |
7c8c5e6a | 2408 | |
dcaffa7b | 2409 | r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); |
7c8c5e6a MZ |
2410 | |
2411 | if (likely(r)) { | |
e70b9522 | 2412 | perform_access(vcpu, params, r); |
54ad68b7 MR |
2413 | } else if (is_imp_def_sys_reg(params)) { |
2414 | kvm_inject_undefined(vcpu); | |
7c8c5e6a | 2415 | } else { |
bf4b96bb MR |
2416 | print_sys_reg_msg(params, |
2417 | "Unsupported guest sys_reg access at: %lx [%08lx]\n", | |
2418 | *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); | |
e70b9522 | 2419 | kvm_inject_undefined(vcpu); |
7c8c5e6a | 2420 | } |
7c8c5e6a MZ |
2421 | return 1; |
2422 | } | |
2423 | ||
750ed566 JM |
2424 | /** |
2425 | * kvm_reset_sys_regs - sets system registers to reset value | |
2426 | * @vcpu: The VCPU pointer | |
2427 | * | |
2428 | * This function finds the right table above and sets the registers on the | |
2429 | * virtual CPU struct to their architecturally defined reset values. | |
2430 | */ | |
2431 | void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) | |
7c8c5e6a MZ |
2432 | { |
2433 | unsigned long i; | |
2434 | ||
750ed566 JM |
2435 | for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) |
2436 | if (sys_reg_descs[i].reset) | |
2437 | sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); | |
7c8c5e6a MZ |
2438 | } |
2439 | ||
2440 | /** | |
2441 | * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access | |
2442 | * @vcpu: The VCPU pointer | |
7c8c5e6a | 2443 | */ |
74cc7e0c | 2444 | int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) |
7c8c5e6a MZ |
2445 | { |
2446 | struct sys_reg_params params; | |
3a949f4c | 2447 | unsigned long esr = kvm_vcpu_get_esr(vcpu); |
c667186f | 2448 | int Rt = kvm_vcpu_sys_get_rt(vcpu); |
2ec5be3d | 2449 | int ret; |
7c8c5e6a | 2450 | |
eef8c85a AB |
2451 | trace_kvm_handle_sys_reg(esr); |
2452 | ||
f76f89e2 | 2453 | params = esr_sys64_to_params(esr); |
2ec5be3d | 2454 | params.regval = vcpu_get_reg(vcpu, Rt); |
7c8c5e6a | 2455 | |
2ec5be3d PF |
2456 | ret = emulate_sys_reg(vcpu, ¶ms); |
2457 | ||
2458 | if (!params.is_write) | |
2459 | vcpu_set_reg(vcpu, Rt, params.regval); | |
2460 | return ret; | |
7c8c5e6a MZ |
2461 | } |
2462 | ||
2463 | /****************************************************************************** | |
2464 | * Userspace API | |
2465 | *****************************************************************************/ | |
2466 | ||
2467 | static bool index_to_params(u64 id, struct sys_reg_params *params) | |
2468 | { | |
2469 | switch (id & KVM_REG_SIZE_MASK) { | |
2470 | case KVM_REG_SIZE_U64: | |
2471 | /* Any unused index bits means it's not valid. */ | |
2472 | if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | |
2473 | | KVM_REG_ARM_COPROC_MASK | |
2474 | | KVM_REG_ARM64_SYSREG_OP0_MASK | |
2475 | | KVM_REG_ARM64_SYSREG_OP1_MASK | |
2476 | | KVM_REG_ARM64_SYSREG_CRN_MASK | |
2477 | | KVM_REG_ARM64_SYSREG_CRM_MASK | |
2478 | | KVM_REG_ARM64_SYSREG_OP2_MASK)) | |
2479 | return false; | |
2480 | params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) | |
2481 | >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); | |
2482 | params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) | |
2483 | >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); | |
2484 | params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) | |
2485 | >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); | |
2486 | params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) | |
2487 | >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); | |
2488 | params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) | |
2489 | >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); | |
2490 | return true; | |
2491 | default: | |
2492 | return false; | |
2493 | } | |
2494 | } | |
2495 | ||
4b927b94 VK |
2496 | const struct sys_reg_desc *find_reg_by_id(u64 id, |
2497 | struct sys_reg_params *params, | |
2498 | const struct sys_reg_desc table[], | |
2499 | unsigned int num) | |
2500 | { | |
2501 | if (!index_to_params(id, params)) | |
2502 | return NULL; | |
2503 | ||
2504 | return find_reg(params, table, num); | |
2505 | } | |
2506 | ||
7c8c5e6a MZ |
2507 | /* Decode an index value, and find the sys_reg_desc entry. */ |
2508 | static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, | |
2509 | u64 id) | |
2510 | { | |
dcaffa7b | 2511 | const struct sys_reg_desc *r; |
7c8c5e6a MZ |
2512 | struct sys_reg_params params; |
2513 | ||
2514 | /* We only do sys_reg for now. */ | |
2515 | if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) | |
2516 | return NULL; | |
2517 | ||
1ce74e96 WD |
2518 | if (!index_to_params(id, ¶ms)) |
2519 | return NULL; | |
2520 | ||
dcaffa7b | 2521 | r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); |
7c8c5e6a | 2522 | |
93390c0a DM |
2523 | /* Not saved in the sys_reg array and not otherwise accessible? */ |
2524 | if (r && !(r->reg || r->get_user)) | |
7c8c5e6a MZ |
2525 | r = NULL; |
2526 | ||
2527 | return r; | |
2528 | } | |
2529 | ||
2530 | /* | |
2531 | * These are the invariant sys_reg registers: we let the guest see the | |
2532 | * host versions of these, so they're part of the guest state. | |
2533 | * | |
2534 | * A future CPU may provide a mechanism to present different values to | |
2535 | * the guest, or a future kvm may trap them. | |
2536 | */ | |
2537 | ||
2538 | #define FUNCTION_INVARIANT(reg) \ | |
2539 | static void get_##reg(struct kvm_vcpu *v, \ | |
2540 | const struct sys_reg_desc *r) \ | |
2541 | { \ | |
1f3d8699 | 2542 | ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ |
7c8c5e6a MZ |
2543 | } |
2544 | ||
2545 | FUNCTION_INVARIANT(midr_el1) | |
7c8c5e6a | 2546 | FUNCTION_INVARIANT(revidr_el1) |
7c8c5e6a MZ |
2547 | FUNCTION_INVARIANT(clidr_el1) |
2548 | FUNCTION_INVARIANT(aidr_el1) | |
2549 | ||
f7f2b15c AB |
2550 | static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) |
2551 | { | |
2552 | ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); | |
2553 | } | |
2554 | ||
7c8c5e6a MZ |
2555 | /* ->val is filled in by kvm_sys_reg_table_init() */ |
2556 | static struct sys_reg_desc invariant_sys_regs[] = { | |
0d449541 MR |
2557 | { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, |
2558 | { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, | |
0d449541 MR |
2559 | { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, |
2560 | { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, | |
2561 | { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, | |
7c8c5e6a MZ |
2562 | }; |
2563 | ||
26c99af1 | 2564 | static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) |
7c8c5e6a | 2565 | { |
7c8c5e6a MZ |
2566 | if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) |
2567 | return -EFAULT; | |
2568 | return 0; | |
2569 | } | |
2570 | ||
26c99af1 | 2571 | static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) |
7c8c5e6a | 2572 | { |
7c8c5e6a MZ |
2573 | if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) |
2574 | return -EFAULT; | |
2575 | return 0; | |
2576 | } | |
2577 | ||
2578 | static int get_invariant_sys_reg(u64 id, void __user *uaddr) | |
2579 | { | |
2580 | struct sys_reg_params params; | |
2581 | const struct sys_reg_desc *r; | |
2582 | ||
4b927b94 VK |
2583 | r = find_reg_by_id(id, ¶ms, invariant_sys_regs, |
2584 | ARRAY_SIZE(invariant_sys_regs)); | |
7c8c5e6a MZ |
2585 | if (!r) |
2586 | return -ENOENT; | |
2587 | ||
2588 | return reg_to_user(uaddr, &r->val, id); | |
2589 | } | |
2590 | ||
2591 | static int set_invariant_sys_reg(u64 id, void __user *uaddr) | |
2592 | { | |
2593 | struct sys_reg_params params; | |
2594 | const struct sys_reg_desc *r; | |
2595 | int err; | |
2596 | u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ | |
2597 | ||
4b927b94 VK |
2598 | r = find_reg_by_id(id, ¶ms, invariant_sys_regs, |
2599 | ARRAY_SIZE(invariant_sys_regs)); | |
7c8c5e6a MZ |
2600 | if (!r) |
2601 | return -ENOENT; | |
2602 | ||
2603 | err = reg_from_user(&val, uaddr, id); | |
2604 | if (err) | |
2605 | return err; | |
2606 | ||
2607 | /* This is what we mean by invariant: you can't change it. */ | |
2608 | if (r->val != val) | |
2609 | return -EINVAL; | |
2610 | ||
2611 | return 0; | |
2612 | } | |
2613 | ||
2614 | static bool is_valid_cache(u32 val) | |
2615 | { | |
2616 | u32 level, ctype; | |
2617 | ||
2618 | if (val >= CSSELR_MAX) | |
18d45766 | 2619 | return false; |
7c8c5e6a MZ |
2620 | |
2621 | /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ | |
2622 | level = (val >> 1); | |
2623 | ctype = (cache_levels >> (level * 3)) & 7; | |
2624 | ||
2625 | switch (ctype) { | |
2626 | case 0: /* No cache */ | |
2627 | return false; | |
2628 | case 1: /* Instruction cache only */ | |
2629 | return (val & 1); | |
2630 | case 2: /* Data cache only */ | |
2631 | case 4: /* Unified cache */ | |
2632 | return !(val & 1); | |
2633 | case 3: /* Separate instruction and data caches */ | |
2634 | return true; | |
2635 | default: /* Reserved: we can't know instruction or data. */ | |
2636 | return false; | |
2637 | } | |
2638 | } | |
2639 | ||
2640 | static int demux_c15_get(u64 id, void __user *uaddr) | |
2641 | { | |
2642 | u32 val; | |
2643 | u32 __user *uval = uaddr; | |
2644 | ||
2645 | /* Fail if we have unknown bits set. */ | |
2646 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK | |
2647 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) | |
2648 | return -ENOENT; | |
2649 | ||
2650 | switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { | |
2651 | case KVM_REG_ARM_DEMUX_ID_CCSIDR: | |
2652 | if (KVM_REG_SIZE(id) != 4) | |
2653 | return -ENOENT; | |
2654 | val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) | |
2655 | >> KVM_REG_ARM_DEMUX_VAL_SHIFT; | |
2656 | if (!is_valid_cache(val)) | |
2657 | return -ENOENT; | |
2658 | ||
2659 | return put_user(get_ccsidr(val), uval); | |
2660 | default: | |
2661 | return -ENOENT; | |
2662 | } | |
2663 | } | |
2664 | ||
2665 | static int demux_c15_set(u64 id, void __user *uaddr) | |
2666 | { | |
2667 | u32 val, newval; | |
2668 | u32 __user *uval = uaddr; | |
2669 | ||
2670 | /* Fail if we have unknown bits set. */ | |
2671 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK | |
2672 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) | |
2673 | return -ENOENT; | |
2674 | ||
2675 | switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { | |
2676 | case KVM_REG_ARM_DEMUX_ID_CCSIDR: | |
2677 | if (KVM_REG_SIZE(id) != 4) | |
2678 | return -ENOENT; | |
2679 | val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) | |
2680 | >> KVM_REG_ARM_DEMUX_VAL_SHIFT; | |
2681 | if (!is_valid_cache(val)) | |
2682 | return -ENOENT; | |
2683 | ||
2684 | if (get_user(newval, uval)) | |
2685 | return -EFAULT; | |
2686 | ||
2687 | /* This is also invariant: you can't change it. */ | |
2688 | if (newval != get_ccsidr(val)) | |
2689 | return -EINVAL; | |
2690 | return 0; | |
2691 | default: | |
2692 | return -ENOENT; | |
2693 | } | |
2694 | } | |
2695 | ||
2696 | int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) | |
2697 | { | |
2698 | const struct sys_reg_desc *r; | |
2699 | void __user *uaddr = (void __user *)(unsigned long)reg->addr; | |
2700 | ||
2701 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) | |
2702 | return demux_c15_get(reg->id, uaddr); | |
2703 | ||
2704 | if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) | |
2705 | return -ENOENT; | |
2706 | ||
2707 | r = index_to_sys_reg_desc(vcpu, reg->id); | |
2708 | if (!r) | |
2709 | return get_invariant_sys_reg(reg->id, uaddr); | |
2710 | ||
7f34e409 | 2711 | /* Check for regs disabled by runtime config */ |
01fe5ace | 2712 | if (sysreg_hidden(vcpu, r)) |
7f34e409 DM |
2713 | return -ENOENT; |
2714 | ||
84e690bf AB |
2715 | if (r->get_user) |
2716 | return (r->get_user)(vcpu, r, reg, uaddr); | |
2717 | ||
8d404c4c | 2718 | return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id); |
7c8c5e6a MZ |
2719 | } |
2720 | ||
2721 | int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) | |
2722 | { | |
2723 | const struct sys_reg_desc *r; | |
2724 | void __user *uaddr = (void __user *)(unsigned long)reg->addr; | |
2725 | ||
2726 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) | |
2727 | return demux_c15_set(reg->id, uaddr); | |
2728 | ||
2729 | if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) | |
2730 | return -ENOENT; | |
2731 | ||
2732 | r = index_to_sys_reg_desc(vcpu, reg->id); | |
2733 | if (!r) | |
2734 | return set_invariant_sys_reg(reg->id, uaddr); | |
2735 | ||
7f34e409 | 2736 | /* Check for regs disabled by runtime config */ |
01fe5ace | 2737 | if (sysreg_hidden(vcpu, r)) |
7f34e409 DM |
2738 | return -ENOENT; |
2739 | ||
84e690bf AB |
2740 | if (r->set_user) |
2741 | return (r->set_user)(vcpu, r, reg, uaddr); | |
2742 | ||
8d404c4c | 2743 | return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); |
7c8c5e6a MZ |
2744 | } |
2745 | ||
2746 | static unsigned int num_demux_regs(void) | |
2747 | { | |
2748 | unsigned int i, count = 0; | |
2749 | ||
2750 | for (i = 0; i < CSSELR_MAX; i++) | |
2751 | if (is_valid_cache(i)) | |
2752 | count++; | |
2753 | ||
2754 | return count; | |
2755 | } | |
2756 | ||
2757 | static int write_demux_regids(u64 __user *uindices) | |
2758 | { | |
efd48cea | 2759 | u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; |
7c8c5e6a MZ |
2760 | unsigned int i; |
2761 | ||
2762 | val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; | |
2763 | for (i = 0; i < CSSELR_MAX; i++) { | |
2764 | if (!is_valid_cache(i)) | |
2765 | continue; | |
2766 | if (put_user(val | i, uindices)) | |
2767 | return -EFAULT; | |
2768 | uindices++; | |
2769 | } | |
2770 | return 0; | |
2771 | } | |
2772 | ||
2773 | static u64 sys_reg_to_index(const struct sys_reg_desc *reg) | |
2774 | { | |
2775 | return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | | |
2776 | KVM_REG_ARM64_SYSREG | | |
2777 | (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | | |
2778 | (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | | |
2779 | (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | | |
2780 | (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | | |
2781 | (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); | |
2782 | } | |
2783 | ||
2784 | static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) | |
2785 | { | |
2786 | if (!*uind) | |
2787 | return true; | |
2788 | ||
2789 | if (put_user(sys_reg_to_index(reg), *uind)) | |
2790 | return false; | |
2791 | ||
2792 | (*uind)++; | |
2793 | return true; | |
2794 | } | |
2795 | ||
7f34e409 DM |
2796 | static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, |
2797 | const struct sys_reg_desc *rd, | |
93390c0a DM |
2798 | u64 __user **uind, |
2799 | unsigned int *total) | |
2800 | { | |
2801 | /* | |
2802 | * Ignore registers we trap but don't save, | |
2803 | * and for which no custom user accessor is provided. | |
2804 | */ | |
2805 | if (!(rd->reg || rd->get_user)) | |
2806 | return 0; | |
2807 | ||
01fe5ace | 2808 | if (sysreg_hidden(vcpu, rd)) |
7f34e409 DM |
2809 | return 0; |
2810 | ||
93390c0a DM |
2811 | if (!copy_reg_to_user(rd, uind)) |
2812 | return -EFAULT; | |
2813 | ||
2814 | (*total)++; | |
2815 | return 0; | |
2816 | } | |
2817 | ||
7c8c5e6a MZ |
2818 | /* Assumed ordered tables, see kvm_sys_reg_table_init. */ |
2819 | static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) | |
2820 | { | |
dcaffa7b | 2821 | const struct sys_reg_desc *i2, *end2; |
7c8c5e6a | 2822 | unsigned int total = 0; |
93390c0a | 2823 | int err; |
7c8c5e6a | 2824 | |
7c8c5e6a MZ |
2825 | i2 = sys_reg_descs; |
2826 | end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); | |
2827 | ||
dcaffa7b JM |
2828 | while (i2 != end2) { |
2829 | err = walk_one_sys_reg(vcpu, i2++, &uind, &total); | |
93390c0a DM |
2830 | if (err) |
2831 | return err; | |
7c8c5e6a MZ |
2832 | } |
2833 | return total; | |
2834 | } | |
2835 | ||
2836 | unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) | |
2837 | { | |
2838 | return ARRAY_SIZE(invariant_sys_regs) | |
2839 | + num_demux_regs() | |
2840 | + walk_sys_regs(vcpu, (u64 __user *)NULL); | |
2841 | } | |
2842 | ||
2843 | int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) | |
2844 | { | |
2845 | unsigned int i; | |
2846 | int err; | |
2847 | ||
2848 | /* Then give them all the invariant registers' indices. */ | |
2849 | for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { | |
2850 | if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) | |
2851 | return -EFAULT; | |
2852 | uindices++; | |
2853 | } | |
2854 | ||
2855 | err = walk_sys_regs(vcpu, uindices); | |
2856 | if (err < 0) | |
2857 | return err; | |
2858 | uindices += err; | |
2859 | ||
2860 | return write_demux_regids(uindices); | |
2861 | } | |
2862 | ||
2863 | void kvm_sys_reg_table_init(void) | |
2864 | { | |
2865 | unsigned int i; | |
2866 | struct sys_reg_desc clidr; | |
2867 | ||
2868 | /* Make sure tables are unique and in order. */ | |
bb44a8db MZ |
2869 | BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false)); |
2870 | BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true)); | |
2871 | BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true)); | |
2872 | BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true)); | |
2873 | BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true)); | |
2874 | BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false)); | |
7c8c5e6a MZ |
2875 | |
2876 | /* We abuse the reset function to overwrite the table itself. */ | |
2877 | for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) | |
2878 | invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); | |
2879 | ||
2880 | /* | |
2881 | * CLIDR format is awkward, so clean it up. See ARM B4.1.20: | |
2882 | * | |
2883 | * If software reads the Cache Type fields from Ctype1 | |
2884 | * upwards, once it has seen a value of 0b000, no caches | |
2885 | * exist at further-out levels of the hierarchy. So, for | |
2886 | * example, if Ctype3 is the first Cache Type field with a | |
2887 | * value of 0b000, the values of Ctype4 to Ctype7 must be | |
2888 | * ignored. | |
2889 | */ | |
2890 | get_clidr_el1(NULL, &clidr); /* Ugly... */ | |
2891 | cache_levels = clidr.val; | |
2892 | for (i = 0; i < 7; i++) | |
2893 | if (((cache_levels >> (i*3)) & 7) == 0) | |
2894 | break; | |
2895 | /* Clear all higher bits. */ | |
2896 | cache_levels &= (1 << (i*3))-1; | |
2897 | } |