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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7c8c5e6a MZ |
2 | /* |
3 | * Copyright (C) 2012,2013 - ARM Ltd | |
4 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
5 | * | |
6 | * Derived from arch/arm/kvm/coproc.c: | |
7 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
8 | * Authors: Rusty Russell <rusty@rustcorp.com.au> | |
9 | * Christoffer Dall <c.dall@virtualopensystems.com> | |
7c8c5e6a MZ |
10 | */ |
11 | ||
c8857935 | 12 | #include <linux/bitfield.h> |
623eefa8 | 13 | #include <linux/bsearch.h> |
7af0c253 | 14 | #include <linux/cacheinfo.h> |
7c8c5e6a | 15 | #include <linux/kvm_host.h> |
c6d01a94 | 16 | #include <linux/mm.h> |
07d79fe7 | 17 | #include <linux/printk.h> |
7c8c5e6a | 18 | #include <linux/uaccess.h> |
c6d01a94 | 19 | |
7c8c5e6a MZ |
20 | #include <asm/cacheflush.h> |
21 | #include <asm/cputype.h> | |
0c557ed4 | 22 | #include <asm/debug-monitors.h> |
c6d01a94 MR |
23 | #include <asm/esr.h> |
24 | #include <asm/kvm_arm.h> | |
c6d01a94 | 25 | #include <asm/kvm_emulate.h> |
d47533da | 26 | #include <asm/kvm_hyp.h> |
c6d01a94 | 27 | #include <asm/kvm_mmu.h> |
6ff9dc23 | 28 | #include <asm/kvm_nested.h> |
ab946834 | 29 | #include <asm/perf_event.h> |
1f3d8699 | 30 | #include <asm/sysreg.h> |
c6d01a94 | 31 | |
7c8c5e6a MZ |
32 | #include <trace/events/kvm.h> |
33 | ||
34 | #include "sys_regs.h" | |
35 | ||
eef8c85a AB |
36 | #include "trace.h" |
37 | ||
7c8c5e6a | 38 | /* |
62a89c44 MZ |
39 | * For AArch32, we only take care of what is being trapped. Anything |
40 | * that has to do with init and userspace access has to go via the | |
41 | * 64bit interface. | |
7c8c5e6a MZ |
42 | */ |
43 | ||
f24adc65 | 44 | static u64 sys_reg_to_index(const struct sys_reg_desc *reg); |
c118cead JZ |
45 | static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
46 | u64 val); | |
f24adc65 | 47 | |
7b5b4df1 | 48 | static bool read_from_write_only(struct kvm_vcpu *vcpu, |
e7f1d1ee MZ |
49 | struct sys_reg_params *params, |
50 | const struct sys_reg_desc *r) | |
7b5b4df1 MZ |
51 | { |
52 | WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); | |
53 | print_sys_reg_instr(params); | |
54 | kvm_inject_undefined(vcpu); | |
55 | return false; | |
56 | } | |
57 | ||
7b1dba1f MZ |
58 | static bool write_to_read_only(struct kvm_vcpu *vcpu, |
59 | struct sys_reg_params *params, | |
60 | const struct sys_reg_desc *r) | |
61 | { | |
62 | WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); | |
63 | print_sys_reg_instr(params); | |
64 | kvm_inject_undefined(vcpu); | |
65 | return false; | |
66 | } | |
67 | ||
7ea90bdd MZ |
68 | u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) |
69 | { | |
70 | u64 val = 0x8badf00d8badf00d; | |
71 | ||
30b6ab45 | 72 | if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) && |
7ea90bdd MZ |
73 | __vcpu_read_sys_reg_from_cpu(reg, &val)) |
74 | return val; | |
75 | ||
76 | return __vcpu_sys_reg(vcpu, reg); | |
77 | } | |
78 | ||
79 | void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) | |
80 | { | |
30b6ab45 | 81 | if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) && |
7ea90bdd MZ |
82 | __vcpu_write_sys_reg_to_cpu(val, reg)) |
83 | return; | |
84 | ||
242b6f34 | 85 | __vcpu_sys_reg(vcpu, reg) = val; |
d47533da CD |
86 | } |
87 | ||
7c8c5e6a | 88 | /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ |
c73a4416 | 89 | #define CSSELR_MAX 14 |
7c8c5e6a | 90 | |
7af0c253 AO |
91 | /* |
92 | * Returns the minimum line size for the selected cache, expressed as | |
93 | * Log2(bytes). | |
94 | */ | |
95 | static u8 get_min_cache_line_size(bool icache) | |
96 | { | |
97 | u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); | |
98 | u8 field; | |
99 | ||
100 | if (icache) | |
101 | field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); | |
102 | else | |
103 | field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); | |
104 | ||
105 | /* | |
106 | * Cache line size is represented as Log2(words) in CTR_EL0. | |
107 | * Log2(bytes) can be derived with the following: | |
108 | * | |
109 | * Log2(words) + 2 = Log2(bytes / 4) + 2 | |
110 | * = Log2(bytes) - 2 + 2 | |
111 | * = Log2(bytes) | |
112 | */ | |
113 | return field + 2; | |
114 | } | |
115 | ||
7c8c5e6a | 116 | /* Which cache CCSIDR represents depends on CSSELR value. */ |
7af0c253 AO |
117 | static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) |
118 | { | |
119 | u8 line_size; | |
120 | ||
121 | if (vcpu->arch.ccsidr) | |
122 | return vcpu->arch.ccsidr[csselr]; | |
123 | ||
124 | line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); | |
125 | ||
126 | /* | |
127 | * Fabricate a CCSIDR value as the overriding value does not exist. | |
128 | * The real CCSIDR value will not be used as it can vary by the | |
129 | * physical CPU which the vcpu currently resides in. | |
130 | * | |
131 | * The line size is determined with get_min_cache_line_size(), which | |
132 | * should be valid for all CPUs even if they have different cache | |
133 | * configuration. | |
134 | * | |
135 | * The associativity bits are cleared, meaning the geometry of all data | |
136 | * and unified caches (which are guaranteed to be PIPT and thus | |
137 | * non-aliasing) are 1 set and 1 way. | |
138 | * Guests should not be doing cache operations by set/way at all, and | |
139 | * for this reason, we trap them and attempt to infer the intent, so | |
140 | * that we can flush the entire guest's address space at the appropriate | |
141 | * time. The exposed geometry minimizes the number of the traps. | |
142 | * [If guests should attempt to infer aliasing properties from the | |
143 | * geometry (which is not permitted by the architecture), they would | |
144 | * only do so for virtually indexed caches.] | |
145 | * | |
146 | * We don't check if the cache level exists as it is allowed to return | |
147 | * an UNKNOWN value if not. | |
148 | */ | |
149 | return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); | |
150 | } | |
151 | ||
152 | static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) | |
7c8c5e6a | 153 | { |
7af0c253 AO |
154 | u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; |
155 | u32 *ccsidr = vcpu->arch.ccsidr; | |
156 | u32 i; | |
157 | ||
158 | if ((val & CCSIDR_EL1_RES0) || | |
159 | line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) | |
160 | return -EINVAL; | |
161 | ||
162 | if (!ccsidr) { | |
163 | if (val == get_ccsidr(vcpu, csselr)) | |
164 | return 0; | |
7c8c5e6a | 165 | |
5f623a59 | 166 | ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); |
7af0c253 AO |
167 | if (!ccsidr) |
168 | return -ENOMEM; | |
7c8c5e6a | 169 | |
7af0c253 AO |
170 | for (i = 0; i < CSSELR_MAX; i++) |
171 | ccsidr[i] = get_ccsidr(vcpu, i); | |
172 | ||
173 | vcpu->arch.ccsidr = ccsidr; | |
174 | } | |
7c8c5e6a | 175 | |
7af0c253 | 176 | ccsidr[csselr] = val; |
7c8c5e6a | 177 | |
7af0c253 | 178 | return 0; |
7c8c5e6a MZ |
179 | } |
180 | ||
6ff9dc23 JL |
181 | static bool access_rw(struct kvm_vcpu *vcpu, |
182 | struct sys_reg_params *p, | |
183 | const struct sys_reg_desc *r) | |
184 | { | |
185 | if (p->is_write) | |
186 | vcpu_write_sys_reg(vcpu, p->regval, r->reg); | |
187 | else | |
188 | p->regval = vcpu_read_sys_reg(vcpu, r->reg); | |
189 | ||
190 | return true; | |
191 | } | |
192 | ||
3c1e7165 MZ |
193 | /* |
194 | * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). | |
195 | */ | |
7c8c5e6a | 196 | static bool access_dcsw(struct kvm_vcpu *vcpu, |
3fec037d | 197 | struct sys_reg_params *p, |
7c8c5e6a MZ |
198 | const struct sys_reg_desc *r) |
199 | { | |
7c8c5e6a | 200 | if (!p->is_write) |
e7f1d1ee | 201 | return read_from_write_only(vcpu, p, r); |
7c8c5e6a | 202 | |
09605e94 MZ |
203 | /* |
204 | * Only track S/W ops if we don't have FWB. It still indicates | |
205 | * that the guest is a bit broken (S/W operations should only | |
206 | * be done by firmware, knowing that there is only a single | |
207 | * CPU left in the system, and certainly not from non-secure | |
208 | * software). | |
209 | */ | |
210 | if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) | |
211 | kvm_set_way_flush(vcpu); | |
212 | ||
7c8c5e6a MZ |
213 | return true; |
214 | } | |
215 | ||
d282fa3c MZ |
216 | static bool access_dcgsw(struct kvm_vcpu *vcpu, |
217 | struct sys_reg_params *p, | |
218 | const struct sys_reg_desc *r) | |
219 | { | |
220 | if (!kvm_has_mte(vcpu->kvm)) { | |
221 | kvm_inject_undefined(vcpu); | |
222 | return false; | |
223 | } | |
224 | ||
225 | /* Treat MTE S/W ops as we treat the classic ones: with contempt */ | |
226 | return access_dcsw(vcpu, p, r); | |
227 | } | |
228 | ||
b1ea1d76 MZ |
229 | static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) |
230 | { | |
231 | switch (r->aarch32_map) { | |
232 | case AA32_LO: | |
233 | *mask = GENMASK_ULL(31, 0); | |
234 | *shift = 0; | |
235 | break; | |
236 | case AA32_HI: | |
237 | *mask = GENMASK_ULL(63, 32); | |
238 | *shift = 32; | |
239 | break; | |
240 | default: | |
241 | *mask = GENMASK_ULL(63, 0); | |
242 | *shift = 0; | |
243 | break; | |
244 | } | |
245 | } | |
246 | ||
4d44923b MZ |
247 | /* |
248 | * Generic accessor for VM registers. Only called as long as HCR_TVM | |
3c1e7165 MZ |
249 | * is set. If the guest enables the MMU, we stop trapping the VM |
250 | * sys_regs and leave it in complete control of the caches. | |
4d44923b MZ |
251 | */ |
252 | static bool access_vm_reg(struct kvm_vcpu *vcpu, | |
3fec037d | 253 | struct sys_reg_params *p, |
4d44923b MZ |
254 | const struct sys_reg_desc *r) |
255 | { | |
3c1e7165 | 256 | bool was_enabled = vcpu_has_cache_enabled(vcpu); |
b1ea1d76 | 257 | u64 val, mask, shift; |
4d44923b MZ |
258 | |
259 | BUG_ON(!p->is_write); | |
260 | ||
b1ea1d76 | 261 | get_access_mask(r, &mask, &shift); |
52f6c4f0 | 262 | |
b1ea1d76 MZ |
263 | if (~mask) { |
264 | val = vcpu_read_sys_reg(vcpu, r->reg); | |
265 | val &= ~mask; | |
dedf97e8 | 266 | } else { |
b1ea1d76 | 267 | val = 0; |
dedf97e8 | 268 | } |
b1ea1d76 MZ |
269 | |
270 | val |= (p->regval & (mask >> shift)) << shift; | |
271 | vcpu_write_sys_reg(vcpu, val, r->reg); | |
f0a3eaff | 272 | |
3c1e7165 | 273 | kvm_toggle_cache(vcpu, was_enabled); |
4d44923b MZ |
274 | return true; |
275 | } | |
276 | ||
af473829 JM |
277 | static bool access_actlr(struct kvm_vcpu *vcpu, |
278 | struct sys_reg_params *p, | |
279 | const struct sys_reg_desc *r) | |
280 | { | |
b1ea1d76 MZ |
281 | u64 mask, shift; |
282 | ||
af473829 JM |
283 | if (p->is_write) |
284 | return ignore_write(vcpu, p); | |
285 | ||
b1ea1d76 MZ |
286 | get_access_mask(r, &mask, &shift); |
287 | p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; | |
af473829 JM |
288 | |
289 | return true; | |
290 | } | |
291 | ||
6d52f35a AP |
292 | /* |
293 | * Trap handler for the GICv3 SGI generation system register. | |
294 | * Forward the request to the VGIC emulation. | |
295 | * The cp15_64 code makes sure this automatically works | |
296 | * for both AArch64 and AArch32 accesses. | |
297 | */ | |
298 | static bool access_gic_sgi(struct kvm_vcpu *vcpu, | |
3fec037d | 299 | struct sys_reg_params *p, |
6d52f35a AP |
300 | const struct sys_reg_desc *r) |
301 | { | |
03bd646d MZ |
302 | bool g1; |
303 | ||
6d52f35a | 304 | if (!p->is_write) |
e7f1d1ee | 305 | return read_from_write_only(vcpu, p, r); |
6d52f35a | 306 | |
03bd646d MZ |
307 | /* |
308 | * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates | |
309 | * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, | |
310 | * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively | |
311 | * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure | |
312 | * group. | |
313 | */ | |
50f30453 | 314 | if (p->Op0 == 0) { /* AArch32 */ |
03bd646d MZ |
315 | switch (p->Op1) { |
316 | default: /* Keep GCC quiet */ | |
317 | case 0: /* ICC_SGI1R */ | |
318 | g1 = true; | |
319 | break; | |
320 | case 1: /* ICC_ASGI1R */ | |
321 | case 2: /* ICC_SGI0R */ | |
322 | g1 = false; | |
323 | break; | |
324 | } | |
50f30453 | 325 | } else { /* AArch64 */ |
03bd646d MZ |
326 | switch (p->Op2) { |
327 | default: /* Keep GCC quiet */ | |
328 | case 5: /* ICC_SGI1R_EL1 */ | |
329 | g1 = true; | |
330 | break; | |
331 | case 6: /* ICC_ASGI1R_EL1 */ | |
332 | case 7: /* ICC_SGI0R_EL1 */ | |
333 | g1 = false; | |
334 | break; | |
335 | } | |
336 | } | |
337 | ||
338 | vgic_v3_dispatch_sgi(vcpu, p->regval, g1); | |
6d52f35a AP |
339 | |
340 | return true; | |
341 | } | |
342 | ||
b34f2bcb MZ |
343 | static bool access_gic_sre(struct kvm_vcpu *vcpu, |
344 | struct sys_reg_params *p, | |
345 | const struct sys_reg_desc *r) | |
346 | { | |
347 | if (p->is_write) | |
348 | return ignore_write(vcpu, p); | |
349 | ||
350 | p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; | |
351 | return true; | |
352 | } | |
353 | ||
7609c125 | 354 | static bool trap_raz_wi(struct kvm_vcpu *vcpu, |
3fec037d | 355 | struct sys_reg_params *p, |
7609c125 | 356 | const struct sys_reg_desc *r) |
7c8c5e6a MZ |
357 | { |
358 | if (p->is_write) | |
359 | return ignore_write(vcpu, p); | |
360 | else | |
361 | return read_zero(vcpu, p); | |
362 | } | |
363 | ||
6ff9dc23 JL |
364 | static bool trap_undef(struct kvm_vcpu *vcpu, |
365 | struct sys_reg_params *p, | |
366 | const struct sys_reg_desc *r) | |
367 | { | |
368 | kvm_inject_undefined(vcpu); | |
369 | return false; | |
370 | } | |
371 | ||
22925521 MZ |
372 | /* |
373 | * ARMv8.1 mandates at least a trivial LORegion implementation, where all the | |
374 | * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 | |
375 | * system, these registers should UNDEF. LORID_EL1 being a RO register, we | |
376 | * treat it separately. | |
377 | */ | |
378 | static bool trap_loregion(struct kvm_vcpu *vcpu, | |
379 | struct sys_reg_params *p, | |
380 | const struct sys_reg_desc *r) | |
cc33c4e2 | 381 | { |
22925521 | 382 | u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); |
7ba8b438 | 383 | u32 sr = reg_to_encoding(r); |
22925521 | 384 | |
6fcd0193 | 385 | if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) { |
22925521 MZ |
386 | kvm_inject_undefined(vcpu); |
387 | return false; | |
388 | } | |
389 | ||
390 | if (p->is_write && sr == SYS_LORID_EL1) | |
391 | return write_to_read_only(vcpu, p, r); | |
392 | ||
393 | return trap_raz_wi(vcpu, p, r); | |
cc33c4e2 MR |
394 | } |
395 | ||
f24adc65 OU |
396 | static bool trap_oslar_el1(struct kvm_vcpu *vcpu, |
397 | struct sys_reg_params *p, | |
398 | const struct sys_reg_desc *r) | |
399 | { | |
400 | u64 oslsr; | |
401 | ||
402 | if (!p->is_write) | |
403 | return read_from_write_only(vcpu, p, r); | |
404 | ||
405 | /* Forward the OSLK bit to OSLSR */ | |
187de7c2 MB |
406 | oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK; |
407 | if (p->regval & OSLAR_EL1_OSLK) | |
408 | oslsr |= OSLSR_EL1_OSLK; | |
f24adc65 OU |
409 | |
410 | __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr; | |
411 | return true; | |
412 | } | |
413 | ||
0c557ed4 | 414 | static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, |
3fec037d | 415 | struct sys_reg_params *p, |
0c557ed4 MZ |
416 | const struct sys_reg_desc *r) |
417 | { | |
d42e2671 | 418 | if (p->is_write) |
e2ffceaa | 419 | return write_to_read_only(vcpu, p, r); |
d42e2671 OU |
420 | |
421 | p->regval = __vcpu_sys_reg(vcpu, r->reg); | |
422 | return true; | |
423 | } | |
424 | ||
425 | static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
978ceeb3 | 426 | u64 val) |
d42e2671 | 427 | { |
f24adc65 OU |
428 | /* |
429 | * The only modifiable bit is the OSLK bit. Refuse the write if | |
430 | * userspace attempts to change any other bit in the register. | |
431 | */ | |
187de7c2 | 432 | if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) |
d42e2671 OU |
433 | return -EINVAL; |
434 | ||
f24adc65 | 435 | __vcpu_sys_reg(vcpu, rd->reg) = val; |
d42e2671 | 436 | return 0; |
0c557ed4 MZ |
437 | } |
438 | ||
439 | static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, | |
3fec037d | 440 | struct sys_reg_params *p, |
0c557ed4 MZ |
441 | const struct sys_reg_desc *r) |
442 | { | |
443 | if (p->is_write) { | |
444 | return ignore_write(vcpu, p); | |
445 | } else { | |
1f3d8699 | 446 | p->regval = read_sysreg(dbgauthstatus_el1); |
0c557ed4 MZ |
447 | return true; |
448 | } | |
449 | } | |
450 | ||
451 | /* | |
452 | * We want to avoid world-switching all the DBG registers all the | |
453 | * time: | |
e6bc555c | 454 | * |
0c557ed4 MZ |
455 | * - If we've touched any debug register, it is likely that we're |
456 | * going to touch more of them. It then makes sense to disable the | |
457 | * traps and start doing the save/restore dance | |
458 | * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is | |
459 | * then mandatory to save/restore the registers, as the guest | |
460 | * depends on them. | |
e6bc555c | 461 | * |
0c557ed4 MZ |
462 | * For this, we use a DIRTY bit, indicating the guest has modified the |
463 | * debug registers, used as follow: | |
464 | * | |
465 | * On guest entry: | |
466 | * - If the dirty bit is set (because we're coming back from trapping), | |
467 | * disable the traps, save host registers, restore guest registers. | |
468 | * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), | |
469 | * set the dirty bit, disable the traps, save host registers, | |
470 | * restore guest registers. | |
471 | * - Otherwise, enable the traps | |
472 | * | |
473 | * On guest exit: | |
474 | * - If the dirty bit is set, save guest registers, restore host | |
475 | * registers and clear the dirty bit. This ensure that the host can | |
476 | * now use the debug registers. | |
477 | */ | |
478 | static bool trap_debug_regs(struct kvm_vcpu *vcpu, | |
3fec037d | 479 | struct sys_reg_params *p, |
0c557ed4 MZ |
480 | const struct sys_reg_desc *r) |
481 | { | |
6ff9dc23 JL |
482 | access_rw(vcpu, p, r); |
483 | if (p->is_write) | |
b1da4908 | 484 | vcpu_set_flag(vcpu, DEBUG_DIRTY); |
0c557ed4 | 485 | |
2ec5be3d | 486 | trace_trap_reg(__func__, r->reg, p->is_write, p->regval); |
eef8c85a | 487 | |
0c557ed4 MZ |
488 | return true; |
489 | } | |
490 | ||
84e690bf AB |
491 | /* |
492 | * reg_to_dbg/dbg_to_reg | |
493 | * | |
494 | * A 32 bit write to a debug register leave top bits alone | |
495 | * A 32 bit read from a debug register only returns the bottom bits | |
496 | * | |
b1da4908 MZ |
497 | * All writes will set the DEBUG_DIRTY flag to ensure the hyp code |
498 | * switches between host and guest values in future. | |
84e690bf | 499 | */ |
281243cb MZ |
500 | static void reg_to_dbg(struct kvm_vcpu *vcpu, |
501 | struct sys_reg_params *p, | |
1da42c34 | 502 | const struct sys_reg_desc *rd, |
281243cb | 503 | u64 *dbg_reg) |
84e690bf | 504 | { |
1da42c34 | 505 | u64 mask, shift, val; |
84e690bf | 506 | |
1da42c34 | 507 | get_access_mask(rd, &mask, &shift); |
84e690bf | 508 | |
1da42c34 MZ |
509 | val = *dbg_reg; |
510 | val &= ~mask; | |
511 | val |= (p->regval & (mask >> shift)) << shift; | |
84e690bf | 512 | *dbg_reg = val; |
1da42c34 | 513 | |
b1da4908 | 514 | vcpu_set_flag(vcpu, DEBUG_DIRTY); |
84e690bf AB |
515 | } |
516 | ||
281243cb MZ |
517 | static void dbg_to_reg(struct kvm_vcpu *vcpu, |
518 | struct sys_reg_params *p, | |
1da42c34 | 519 | const struct sys_reg_desc *rd, |
281243cb | 520 | u64 *dbg_reg) |
84e690bf | 521 | { |
1da42c34 MZ |
522 | u64 mask, shift; |
523 | ||
524 | get_access_mask(rd, &mask, &shift); | |
525 | p->regval = (*dbg_reg & mask) >> shift; | |
84e690bf AB |
526 | } |
527 | ||
281243cb MZ |
528 | static bool trap_bvr(struct kvm_vcpu *vcpu, |
529 | struct sys_reg_params *p, | |
530 | const struct sys_reg_desc *rd) | |
84e690bf | 531 | { |
cb853ded | 532 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; |
84e690bf AB |
533 | |
534 | if (p->is_write) | |
1da42c34 | 535 | reg_to_dbg(vcpu, p, rd, dbg_reg); |
84e690bf | 536 | else |
1da42c34 | 537 | dbg_to_reg(vcpu, p, rd, dbg_reg); |
84e690bf | 538 | |
cb853ded | 539 | trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); |
eef8c85a | 540 | |
84e690bf AB |
541 | return true; |
542 | } | |
543 | ||
544 | static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
978ceeb3 | 545 | u64 val) |
84e690bf | 546 | { |
978ceeb3 | 547 | vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val; |
84e690bf AB |
548 | return 0; |
549 | } | |
550 | ||
551 | static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
978ceeb3 | 552 | u64 *val) |
84e690bf | 553 | { |
978ceeb3 | 554 | *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; |
84e690bf AB |
555 | return 0; |
556 | } | |
557 | ||
d86cde6e | 558 | static u64 reset_bvr(struct kvm_vcpu *vcpu, |
281243cb | 559 | const struct sys_reg_desc *rd) |
84e690bf | 560 | { |
cb853ded | 561 | vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; |
d86cde6e | 562 | return rd->val; |
84e690bf AB |
563 | } |
564 | ||
281243cb MZ |
565 | static bool trap_bcr(struct kvm_vcpu *vcpu, |
566 | struct sys_reg_params *p, | |
567 | const struct sys_reg_desc *rd) | |
84e690bf | 568 | { |
cb853ded | 569 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; |
84e690bf AB |
570 | |
571 | if (p->is_write) | |
1da42c34 | 572 | reg_to_dbg(vcpu, p, rd, dbg_reg); |
84e690bf | 573 | else |
1da42c34 | 574 | dbg_to_reg(vcpu, p, rd, dbg_reg); |
84e690bf | 575 | |
cb853ded | 576 | trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); |
eef8c85a | 577 | |
84e690bf AB |
578 | return true; |
579 | } | |
580 | ||
581 | static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
978ceeb3 | 582 | u64 val) |
84e690bf | 583 | { |
978ceeb3 | 584 | vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val; |
84e690bf AB |
585 | return 0; |
586 | } | |
587 | ||
588 | static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
978ceeb3 | 589 | u64 *val) |
84e690bf | 590 | { |
978ceeb3 | 591 | *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; |
84e690bf AB |
592 | return 0; |
593 | } | |
594 | ||
d86cde6e | 595 | static u64 reset_bcr(struct kvm_vcpu *vcpu, |
281243cb | 596 | const struct sys_reg_desc *rd) |
84e690bf | 597 | { |
cb853ded | 598 | vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val; |
d86cde6e | 599 | return rd->val; |
84e690bf AB |
600 | } |
601 | ||
281243cb MZ |
602 | static bool trap_wvr(struct kvm_vcpu *vcpu, |
603 | struct sys_reg_params *p, | |
604 | const struct sys_reg_desc *rd) | |
84e690bf | 605 | { |
cb853ded | 606 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; |
84e690bf AB |
607 | |
608 | if (p->is_write) | |
1da42c34 | 609 | reg_to_dbg(vcpu, p, rd, dbg_reg); |
84e690bf | 610 | else |
1da42c34 | 611 | dbg_to_reg(vcpu, p, rd, dbg_reg); |
84e690bf | 612 | |
cb853ded MZ |
613 | trace_trap_reg(__func__, rd->CRm, p->is_write, |
614 | vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]); | |
eef8c85a | 615 | |
84e690bf AB |
616 | return true; |
617 | } | |
618 | ||
619 | static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
978ceeb3 | 620 | u64 val) |
84e690bf | 621 | { |
978ceeb3 | 622 | vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val; |
84e690bf AB |
623 | return 0; |
624 | } | |
625 | ||
626 | static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
978ceeb3 | 627 | u64 *val) |
84e690bf | 628 | { |
978ceeb3 | 629 | *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]; |
84e690bf AB |
630 | return 0; |
631 | } | |
632 | ||
d86cde6e | 633 | static u64 reset_wvr(struct kvm_vcpu *vcpu, |
281243cb | 634 | const struct sys_reg_desc *rd) |
84e690bf | 635 | { |
cb853ded | 636 | vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val; |
d86cde6e | 637 | return rd->val; |
84e690bf AB |
638 | } |
639 | ||
281243cb MZ |
640 | static bool trap_wcr(struct kvm_vcpu *vcpu, |
641 | struct sys_reg_params *p, | |
642 | const struct sys_reg_desc *rd) | |
84e690bf | 643 | { |
cb853ded | 644 | u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; |
84e690bf AB |
645 | |
646 | if (p->is_write) | |
1da42c34 | 647 | reg_to_dbg(vcpu, p, rd, dbg_reg); |
84e690bf | 648 | else |
1da42c34 | 649 | dbg_to_reg(vcpu, p, rd, dbg_reg); |
84e690bf | 650 | |
cb853ded | 651 | trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); |
eef8c85a | 652 | |
84e690bf AB |
653 | return true; |
654 | } | |
655 | ||
656 | static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
978ceeb3 | 657 | u64 val) |
84e690bf | 658 | { |
978ceeb3 | 659 | vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val; |
84e690bf AB |
660 | return 0; |
661 | } | |
662 | ||
663 | static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
978ceeb3 | 664 | u64 *val) |
84e690bf | 665 | { |
978ceeb3 | 666 | *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; |
84e690bf AB |
667 | return 0; |
668 | } | |
669 | ||
d86cde6e | 670 | static u64 reset_wcr(struct kvm_vcpu *vcpu, |
281243cb | 671 | const struct sys_reg_desc *rd) |
84e690bf | 672 | { |
cb853ded | 673 | vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val; |
d86cde6e | 674 | return rd->val; |
84e690bf AB |
675 | } |
676 | ||
d86cde6e | 677 | static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
7c8c5e6a | 678 | { |
8d404c4c CD |
679 | u64 amair = read_sysreg(amair_el1); |
680 | vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); | |
d86cde6e | 681 | return amair; |
7c8c5e6a MZ |
682 | } |
683 | ||
d86cde6e | 684 | static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
af473829 JM |
685 | { |
686 | u64 actlr = read_sysreg(actlr_el1); | |
687 | vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); | |
d86cde6e | 688 | return actlr; |
af473829 JM |
689 | } |
690 | ||
d86cde6e | 691 | static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
7c8c5e6a | 692 | { |
4429fc64 AP |
693 | u64 mpidr; |
694 | ||
7c8c5e6a | 695 | /* |
4429fc64 AP |
696 | * Map the vcpu_id into the first three affinity level fields of |
697 | * the MPIDR. We limit the number of VCPUs in level 0 due to a | |
698 | * limitation to 16 CPUs in that level in the ICC_SGIxR registers | |
699 | * of the GICv3 to be able to address each CPU directly when | |
700 | * sending IPIs. | |
7c8c5e6a | 701 | */ |
4429fc64 AP |
702 | mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); |
703 | mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); | |
704 | mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); | |
d86cde6e JZ |
705 | mpidr |= (1ULL << 31); |
706 | vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); | |
707 | ||
708 | return mpidr; | |
7c8c5e6a MZ |
709 | } |
710 | ||
11663111 MZ |
711 | static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, |
712 | const struct sys_reg_desc *r) | |
713 | { | |
714 | if (kvm_vcpu_has_pmu(vcpu)) | |
715 | return 0; | |
716 | ||
717 | return REG_HIDDEN; | |
718 | } | |
719 | ||
d86cde6e | 720 | static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
0ab410a9 MZ |
721 | { |
722 | u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); | |
723 | ||
724 | /* No PMU available, any PMU reg may UNDEF... */ | |
725 | if (!kvm_arm_support_pmu_v3()) | |
d86cde6e | 726 | return 0; |
0ab410a9 MZ |
727 | |
728 | n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; | |
729 | n &= ARMV8_PMU_PMCR_N_MASK; | |
730 | if (n) | |
731 | mask |= GENMASK(n - 1, 0); | |
732 | ||
733 | reset_unknown(vcpu, r); | |
734 | __vcpu_sys_reg(vcpu, r->reg) &= mask; | |
d86cde6e JZ |
735 | |
736 | return __vcpu_sys_reg(vcpu, r->reg); | |
0ab410a9 MZ |
737 | } |
738 | ||
d86cde6e | 739 | static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
0ab410a9 MZ |
740 | { |
741 | reset_unknown(vcpu, r); | |
742 | __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); | |
d86cde6e JZ |
743 | |
744 | return __vcpu_sys_reg(vcpu, r->reg); | |
0ab410a9 MZ |
745 | } |
746 | ||
d86cde6e | 747 | static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
0ab410a9 MZ |
748 | { |
749 | reset_unknown(vcpu, r); | |
750 | __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK; | |
d86cde6e JZ |
751 | |
752 | return __vcpu_sys_reg(vcpu, r->reg); | |
0ab410a9 MZ |
753 | } |
754 | ||
d86cde6e | 755 | static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
0ab410a9 MZ |
756 | { |
757 | reset_unknown(vcpu, r); | |
758 | __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK; | |
d86cde6e JZ |
759 | |
760 | return __vcpu_sys_reg(vcpu, r->reg); | |
0ab410a9 MZ |
761 | } |
762 | ||
d86cde6e | 763 | static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
ab946834 | 764 | { |
292e8f14 | 765 | u64 pmcr; |
ab946834 | 766 | |
2a5f1b67 MZ |
767 | /* No PMU available, PMCR_EL0 may UNDEF... */ |
768 | if (!kvm_arm_support_pmu_v3()) | |
d86cde6e | 769 | return 0; |
2a5f1b67 | 770 | |
292e8f14 | 771 | /* Only preserve PMCR_EL0.N, and reset the rest to 0 */ |
aff23483 | 772 | pmcr = read_sysreg(pmcr_el0) & (ARMV8_PMU_PMCR_N_MASK << ARMV8_PMU_PMCR_N_SHIFT); |
f3c6efc7 | 773 | if (!kvm_supports_32bit_el0()) |
292e8f14 MZ |
774 | pmcr |= ARMV8_PMU_PMCR_LC; |
775 | ||
776 | __vcpu_sys_reg(vcpu, r->reg) = pmcr; | |
d86cde6e JZ |
777 | |
778 | return __vcpu_sys_reg(vcpu, r->reg); | |
ab946834 SZ |
779 | } |
780 | ||
6c007036 | 781 | static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) |
d692b8ad | 782 | { |
8d404c4c | 783 | u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); |
7ded92e2 | 784 | bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); |
d692b8ad | 785 | |
24d5950f MZ |
786 | if (!enabled) |
787 | kvm_inject_undefined(vcpu); | |
d692b8ad | 788 | |
6c007036 | 789 | return !enabled; |
d692b8ad SZ |
790 | } |
791 | ||
6c007036 | 792 | static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) |
d692b8ad | 793 | { |
6c007036 MZ |
794 | return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); |
795 | } | |
d692b8ad | 796 | |
6c007036 MZ |
797 | static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) |
798 | { | |
799 | return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); | |
d692b8ad SZ |
800 | } |
801 | ||
802 | static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) | |
803 | { | |
6c007036 | 804 | return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); |
d692b8ad SZ |
805 | } |
806 | ||
807 | static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) | |
808 | { | |
6c007036 | 809 | return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); |
d692b8ad SZ |
810 | } |
811 | ||
ab946834 SZ |
812 | static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
813 | const struct sys_reg_desc *r) | |
814 | { | |
815 | u64 val; | |
816 | ||
d692b8ad SZ |
817 | if (pmu_access_el0_disabled(vcpu)) |
818 | return false; | |
819 | ||
ab946834 | 820 | if (p->is_write) { |
64d6820d MZ |
821 | /* |
822 | * Only update writeable bits of PMCR (continuing into | |
823 | * kvm_pmu_handle_pmcr() as well) | |
824 | */ | |
8d404c4c | 825 | val = __vcpu_sys_reg(vcpu, PMCR_EL0); |
ab946834 SZ |
826 | val &= ~ARMV8_PMU_PMCR_MASK; |
827 | val |= p->regval & ARMV8_PMU_PMCR_MASK; | |
f3c6efc7 | 828 | if (!kvm_supports_32bit_el0()) |
6f163714 | 829 | val |= ARMV8_PMU_PMCR_LC; |
76993739 | 830 | kvm_pmu_handle_pmcr(vcpu, val); |
ab946834 SZ |
831 | } else { |
832 | /* PMCR.P & PMCR.C are RAZ */ | |
8d404c4c | 833 | val = __vcpu_sys_reg(vcpu, PMCR_EL0) |
ab946834 SZ |
834 | & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); |
835 | p->regval = val; | |
836 | } | |
837 | ||
838 | return true; | |
839 | } | |
840 | ||
3965c3ce SZ |
841 | static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
842 | const struct sys_reg_desc *r) | |
843 | { | |
d692b8ad SZ |
844 | if (pmu_access_event_counter_el0_disabled(vcpu)) |
845 | return false; | |
846 | ||
3965c3ce | 847 | if (p->is_write) |
8d404c4c | 848 | __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; |
3965c3ce SZ |
849 | else |
850 | /* return PMSELR.SEL field */ | |
8d404c4c | 851 | p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) |
3965c3ce SZ |
852 | & ARMV8_PMU_COUNTER_MASK; |
853 | ||
854 | return true; | |
855 | } | |
856 | ||
a86b5505 SZ |
857 | static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
858 | const struct sys_reg_desc *r) | |
859 | { | |
99b6a401 | 860 | u64 pmceid, mask, shift; |
a86b5505 | 861 | |
a86b5505 SZ |
862 | BUG_ON(p->is_write); |
863 | ||
d692b8ad SZ |
864 | if (pmu_access_el0_disabled(vcpu)) |
865 | return false; | |
866 | ||
99b6a401 MZ |
867 | get_access_mask(r, &mask, &shift); |
868 | ||
88865bec | 869 | pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); |
99b6a401 MZ |
870 | pmceid &= mask; |
871 | pmceid >>= shift; | |
a86b5505 SZ |
872 | |
873 | p->regval = pmceid; | |
874 | ||
875 | return true; | |
876 | } | |
877 | ||
051ff581 SZ |
878 | static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) |
879 | { | |
880 | u64 pmcr, val; | |
881 | ||
8d404c4c | 882 | pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); |
051ff581 | 883 | val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; |
24d5950f MZ |
884 | if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { |
885 | kvm_inject_undefined(vcpu); | |
051ff581 | 886 | return false; |
24d5950f | 887 | } |
051ff581 SZ |
888 | |
889 | return true; | |
890 | } | |
891 | ||
9228b261 RW |
892 | static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, |
893 | u64 *val) | |
894 | { | |
895 | u64 idx; | |
896 | ||
897 | if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) | |
898 | /* PMCCNTR_EL0 */ | |
899 | idx = ARMV8_PMU_CYCLE_IDX; | |
900 | else | |
901 | /* PMEVCNTRn_EL0 */ | |
902 | idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); | |
903 | ||
904 | *val = kvm_pmu_get_counter_value(vcpu, idx); | |
905 | return 0; | |
906 | } | |
907 | ||
051ff581 SZ |
908 | static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, |
909 | struct sys_reg_params *p, | |
910 | const struct sys_reg_desc *r) | |
911 | { | |
a3da9358 | 912 | u64 idx = ~0UL; |
051ff581 SZ |
913 | |
914 | if (r->CRn == 9 && r->CRm == 13) { | |
915 | if (r->Op2 == 2) { | |
916 | /* PMXEVCNTR_EL0 */ | |
d692b8ad SZ |
917 | if (pmu_access_event_counter_el0_disabled(vcpu)) |
918 | return false; | |
919 | ||
8d404c4c | 920 | idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) |
051ff581 SZ |
921 | & ARMV8_PMU_COUNTER_MASK; |
922 | } else if (r->Op2 == 0) { | |
923 | /* PMCCNTR_EL0 */ | |
d692b8ad SZ |
924 | if (pmu_access_cycle_counter_el0_disabled(vcpu)) |
925 | return false; | |
926 | ||
051ff581 | 927 | idx = ARMV8_PMU_CYCLE_IDX; |
051ff581 | 928 | } |
9e3f7a29 WH |
929 | } else if (r->CRn == 0 && r->CRm == 9) { |
930 | /* PMCCNTR */ | |
931 | if (pmu_access_event_counter_el0_disabled(vcpu)) | |
932 | return false; | |
933 | ||
934 | idx = ARMV8_PMU_CYCLE_IDX; | |
051ff581 SZ |
935 | } else if (r->CRn == 14 && (r->CRm & 12) == 8) { |
936 | /* PMEVCNTRn_EL0 */ | |
d692b8ad SZ |
937 | if (pmu_access_event_counter_el0_disabled(vcpu)) |
938 | return false; | |
939 | ||
051ff581 | 940 | idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); |
051ff581 SZ |
941 | } |
942 | ||
a3da9358 MZ |
943 | /* Catch any decoding mistake */ |
944 | WARN_ON(idx == ~0UL); | |
945 | ||
051ff581 SZ |
946 | if (!pmu_counter_idx_valid(vcpu, idx)) |
947 | return false; | |
948 | ||
d692b8ad SZ |
949 | if (p->is_write) { |
950 | if (pmu_access_el0_disabled(vcpu)) | |
951 | return false; | |
952 | ||
051ff581 | 953 | kvm_pmu_set_counter_value(vcpu, idx, p->regval); |
d692b8ad | 954 | } else { |
051ff581 | 955 | p->regval = kvm_pmu_get_counter_value(vcpu, idx); |
d692b8ad | 956 | } |
051ff581 SZ |
957 | |
958 | return true; | |
959 | } | |
960 | ||
9feb21ac SZ |
961 | static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
962 | const struct sys_reg_desc *r) | |
963 | { | |
964 | u64 idx, reg; | |
965 | ||
d692b8ad SZ |
966 | if (pmu_access_el0_disabled(vcpu)) |
967 | return false; | |
968 | ||
9feb21ac SZ |
969 | if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { |
970 | /* PMXEVTYPER_EL0 */ | |
8d404c4c | 971 | idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; |
9feb21ac SZ |
972 | reg = PMEVTYPER0_EL0 + idx; |
973 | } else if (r->CRn == 14 && (r->CRm & 12) == 12) { | |
974 | idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); | |
975 | if (idx == ARMV8_PMU_CYCLE_IDX) | |
976 | reg = PMCCFILTR_EL0; | |
977 | else | |
978 | /* PMEVTYPERn_EL0 */ | |
979 | reg = PMEVTYPER0_EL0 + idx; | |
980 | } else { | |
981 | BUG(); | |
982 | } | |
983 | ||
984 | if (!pmu_counter_idx_valid(vcpu, idx)) | |
985 | return false; | |
986 | ||
987 | if (p->is_write) { | |
988 | kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); | |
435e53fb | 989 | kvm_vcpu_pmu_restore_guest(vcpu); |
9feb21ac | 990 | } else { |
8d404c4c | 991 | p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; |
9feb21ac SZ |
992 | } |
993 | ||
994 | return true; | |
995 | } | |
996 | ||
96b0eebc SZ |
997 | static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
998 | const struct sys_reg_desc *r) | |
999 | { | |
1000 | u64 val, mask; | |
1001 | ||
d692b8ad SZ |
1002 | if (pmu_access_el0_disabled(vcpu)) |
1003 | return false; | |
1004 | ||
96b0eebc SZ |
1005 | mask = kvm_pmu_valid_counter_mask(vcpu); |
1006 | if (p->is_write) { | |
1007 | val = p->regval & mask; | |
1008 | if (r->Op2 & 0x1) { | |
1009 | /* accessing PMCNTENSET_EL0 */ | |
8d404c4c | 1010 | __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; |
418e5ca8 | 1011 | kvm_pmu_enable_counter_mask(vcpu, val); |
435e53fb | 1012 | kvm_vcpu_pmu_restore_guest(vcpu); |
96b0eebc SZ |
1013 | } else { |
1014 | /* accessing PMCNTENCLR_EL0 */ | |
8d404c4c | 1015 | __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; |
418e5ca8 | 1016 | kvm_pmu_disable_counter_mask(vcpu, val); |
96b0eebc SZ |
1017 | } |
1018 | } else { | |
f5eff400 | 1019 | p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); |
96b0eebc SZ |
1020 | } |
1021 | ||
1022 | return true; | |
1023 | } | |
1024 | ||
9db52c78 SZ |
1025 | static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
1026 | const struct sys_reg_desc *r) | |
1027 | { | |
1028 | u64 mask = kvm_pmu_valid_counter_mask(vcpu); | |
1029 | ||
b0737e99 | 1030 | if (check_pmu_access_disabled(vcpu, 0)) |
d692b8ad SZ |
1031 | return false; |
1032 | ||
9db52c78 SZ |
1033 | if (p->is_write) { |
1034 | u64 val = p->regval & mask; | |
1035 | ||
1036 | if (r->Op2 & 0x1) | |
1037 | /* accessing PMINTENSET_EL1 */ | |
8d404c4c | 1038 | __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; |
9db52c78 SZ |
1039 | else |
1040 | /* accessing PMINTENCLR_EL1 */ | |
8d404c4c | 1041 | __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; |
9db52c78 | 1042 | } else { |
f5eff400 | 1043 | p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); |
9db52c78 SZ |
1044 | } |
1045 | ||
1046 | return true; | |
1047 | } | |
1048 | ||
76d883c4 SZ |
1049 | static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
1050 | const struct sys_reg_desc *r) | |
1051 | { | |
1052 | u64 mask = kvm_pmu_valid_counter_mask(vcpu); | |
1053 | ||
d692b8ad SZ |
1054 | if (pmu_access_el0_disabled(vcpu)) |
1055 | return false; | |
1056 | ||
76d883c4 SZ |
1057 | if (p->is_write) { |
1058 | if (r->CRm & 0x2) | |
1059 | /* accessing PMOVSSET_EL0 */ | |
8d404c4c | 1060 | __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); |
76d883c4 SZ |
1061 | else |
1062 | /* accessing PMOVSCLR_EL0 */ | |
8d404c4c | 1063 | __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); |
76d883c4 | 1064 | } else { |
f5eff400 | 1065 | p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); |
76d883c4 SZ |
1066 | } |
1067 | ||
1068 | return true; | |
1069 | } | |
1070 | ||
7a0adc70 SZ |
1071 | static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
1072 | const struct sys_reg_desc *r) | |
1073 | { | |
1074 | u64 mask; | |
1075 | ||
e0443230 | 1076 | if (!p->is_write) |
e7f1d1ee | 1077 | return read_from_write_only(vcpu, p, r); |
e0443230 | 1078 | |
d692b8ad SZ |
1079 | if (pmu_write_swinc_el0_disabled(vcpu)) |
1080 | return false; | |
1081 | ||
e0443230 MZ |
1082 | mask = kvm_pmu_valid_counter_mask(vcpu); |
1083 | kvm_pmu_software_increment(vcpu, p->regval & mask); | |
1084 | return true; | |
7a0adc70 SZ |
1085 | } |
1086 | ||
d692b8ad SZ |
1087 | static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
1088 | const struct sys_reg_desc *r) | |
1089 | { | |
d692b8ad | 1090 | if (p->is_write) { |
9008c235 MZ |
1091 | if (!vcpu_mode_priv(vcpu)) { |
1092 | kvm_inject_undefined(vcpu); | |
d692b8ad | 1093 | return false; |
9008c235 | 1094 | } |
d692b8ad | 1095 | |
8d404c4c CD |
1096 | __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = |
1097 | p->regval & ARMV8_PMU_USERENR_MASK; | |
d692b8ad | 1098 | } else { |
8d404c4c | 1099 | p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) |
d692b8ad SZ |
1100 | & ARMV8_PMU_USERENR_MASK; |
1101 | } | |
1102 | ||
1103 | return true; | |
1104 | } | |
1105 | ||
0c557ed4 MZ |
1106 | /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ |
1107 | #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ | |
ee1b64e6 | 1108 | { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ |
03fdfb26 | 1109 | trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ |
ee1b64e6 | 1110 | { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ |
03fdfb26 | 1111 | trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ |
ee1b64e6 | 1112 | { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ |
03fdfb26 | 1113 | trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ |
ee1b64e6 | 1114 | { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ |
03fdfb26 | 1115 | trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } |
0c557ed4 | 1116 | |
9d2a55b4 XC |
1117 | #define PMU_SYS_REG(name) \ |
1118 | SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ | |
1119 | .visibility = pmu_visibility | |
11663111 | 1120 | |
051ff581 SZ |
1121 | /* Macro to expand the PMEVCNTRn_EL0 register */ |
1122 | #define PMU_PMEVCNTR_EL0(n) \ | |
9d2a55b4 | 1123 | { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ |
9228b261 | 1124 | .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ |
11663111 | 1125 | .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } |
051ff581 | 1126 | |
9feb21ac SZ |
1127 | /* Macro to expand the PMEVTYPERn_EL0 register */ |
1128 | #define PMU_PMEVTYPER_EL0(n) \ | |
9d2a55b4 | 1129 | { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ |
0ab410a9 | 1130 | .reset = reset_pmevtyper, \ |
11663111 | 1131 | .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } |
9feb21ac | 1132 | |
338b1793 MZ |
1133 | static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
1134 | const struct sys_reg_desc *r) | |
4fcdf106 IV |
1135 | { |
1136 | kvm_inject_undefined(vcpu); | |
1137 | ||
1138 | return false; | |
1139 | } | |
1140 | ||
1141 | /* Macro to expand the AMU counter and type registers*/ | |
338b1793 MZ |
1142 | #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } |
1143 | #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } | |
1144 | #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } | |
1145 | #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } | |
384b40ca MR |
1146 | |
1147 | static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, | |
1148 | const struct sys_reg_desc *rd) | |
1149 | { | |
01fe5ace | 1150 | return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; |
384b40ca MR |
1151 | } |
1152 | ||
338b1793 MZ |
1153 | /* |
1154 | * If we land here on a PtrAuth access, that is because we didn't | |
1155 | * fixup the access on exit by allowing the PtrAuth sysregs. The only | |
1156 | * way this happens is when the guest does not have PtrAuth support | |
1157 | * enabled. | |
1158 | */ | |
384b40ca | 1159 | #define __PTRAUTH_KEY(k) \ |
338b1793 | 1160 | { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ |
384b40ca MR |
1161 | .visibility = ptrauth_visibility} |
1162 | ||
1163 | #define PTRAUTH_KEY(k) \ | |
1164 | __PTRAUTH_KEY(k ## KEYLO_EL1), \ | |
1165 | __PTRAUTH_KEY(k ## KEYHI_EL1) | |
1166 | ||
84135d3d AP |
1167 | static bool access_arch_timer(struct kvm_vcpu *vcpu, |
1168 | struct sys_reg_params *p, | |
1169 | const struct sys_reg_desc *r) | |
c9a3c58f | 1170 | { |
84135d3d AP |
1171 | enum kvm_arch_timers tmr; |
1172 | enum kvm_arch_timer_regs treg; | |
1173 | u64 reg = reg_to_encoding(r); | |
7b6b4631 | 1174 | |
84135d3d AP |
1175 | switch (reg) { |
1176 | case SYS_CNTP_TVAL_EL0: | |
1177 | case SYS_AARCH32_CNTP_TVAL: | |
1178 | tmr = TIMER_PTIMER; | |
1179 | treg = TIMER_REG_TVAL; | |
1180 | break; | |
1181 | case SYS_CNTP_CTL_EL0: | |
1182 | case SYS_AARCH32_CNTP_CTL: | |
1183 | tmr = TIMER_PTIMER; | |
1184 | treg = TIMER_REG_CTL; | |
1185 | break; | |
1186 | case SYS_CNTP_CVAL_EL0: | |
1187 | case SYS_AARCH32_CNTP_CVAL: | |
1188 | tmr = TIMER_PTIMER; | |
1189 | treg = TIMER_REG_CVAL; | |
1190 | break; | |
c605ee24 MZ |
1191 | case SYS_CNTPCT_EL0: |
1192 | case SYS_CNTPCTSS_EL0: | |
1193 | case SYS_AARCH32_CNTPCT: | |
1194 | tmr = TIMER_PTIMER; | |
1195 | treg = TIMER_REG_CNT; | |
1196 | break; | |
84135d3d | 1197 | default: |
ba82e06c MZ |
1198 | print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); |
1199 | kvm_inject_undefined(vcpu); | |
1200 | return false; | |
c1b135af | 1201 | } |
7b6b4631 | 1202 | |
7b6b4631 | 1203 | if (p->is_write) |
84135d3d | 1204 | kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); |
7b6b4631 | 1205 | else |
84135d3d | 1206 | p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); |
7b6b4631 | 1207 | |
c9a3c58f JL |
1208 | return true; |
1209 | } | |
1210 | ||
2e8bf0cb JZ |
1211 | static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, |
1212 | s64 new, s64 cur) | |
3d0dba57 | 1213 | { |
2e8bf0cb JZ |
1214 | struct arm64_ftr_bits kvm_ftr = *ftrp; |
1215 | ||
1216 | /* Some features have different safe value type in KVM than host features */ | |
1217 | switch (id) { | |
1218 | case SYS_ID_AA64DFR0_EL1: | |
1219 | if (kvm_ftr.shift == ID_AA64DFR0_EL1_PMUVer_SHIFT) | |
1220 | kvm_ftr.type = FTR_LOWER_SAFE; | |
1221 | break; | |
1222 | case SYS_ID_DFR0_EL1: | |
1223 | if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) | |
1224 | kvm_ftr.type = FTR_LOWER_SAFE; | |
1225 | break; | |
1226 | } | |
3d0dba57 | 1227 | |
2e8bf0cb | 1228 | return arm64_ftr_safe_value(&kvm_ftr, new, cur); |
3d0dba57 MZ |
1229 | } |
1230 | ||
2e8bf0cb JZ |
1231 | /** |
1232 | * arm64_check_features() - Check if a feature register value constitutes | |
1233 | * a subset of features indicated by the idreg's KVM sanitised limit. | |
1234 | * | |
1235 | * This function will check if each feature field of @val is the "safe" value | |
1236 | * against idreg's KVM sanitised limit return from reset() callback. | |
1237 | * If a field value in @val is the same as the one in limit, it is always | |
1238 | * considered the safe value regardless For register fields that are not in | |
1239 | * writable, only the value in limit is considered the safe value. | |
1240 | * | |
1241 | * Return: 0 if all the fields are safe. Otherwise, return negative errno. | |
1242 | */ | |
1243 | static int arm64_check_features(struct kvm_vcpu *vcpu, | |
1244 | const struct sys_reg_desc *rd, | |
1245 | u64 val) | |
d82e0dfd | 1246 | { |
2e8bf0cb JZ |
1247 | const struct arm64_ftr_reg *ftr_reg; |
1248 | const struct arm64_ftr_bits *ftrp = NULL; | |
1249 | u32 id = reg_to_encoding(rd); | |
1250 | u64 writable_mask = rd->val; | |
1251 | u64 limit = rd->reset(vcpu, rd); | |
1252 | u64 mask = 0; | |
1253 | ||
1254 | /* | |
1255 | * Hidden and unallocated ID registers may not have a corresponding | |
1256 | * struct arm64_ftr_reg. Of course, if the register is RAZ we know the | |
1257 | * only safe value is 0. | |
1258 | */ | |
1259 | if (sysreg_visible_as_raz(vcpu, rd)) | |
1260 | return val ? -E2BIG : 0; | |
1261 | ||
1262 | ftr_reg = get_arm64_ftr_reg(id); | |
1263 | if (!ftr_reg) | |
1264 | return -EINVAL; | |
1265 | ||
1266 | ftrp = ftr_reg->ftr_bits; | |
1267 | ||
1268 | for (; ftrp && ftrp->width; ftrp++) { | |
1269 | s64 f_val, f_lim, safe_val; | |
1270 | u64 ftr_mask; | |
1271 | ||
1272 | ftr_mask = arm64_ftr_mask(ftrp); | |
1273 | if ((ftr_mask & writable_mask) != ftr_mask) | |
1274 | continue; | |
1275 | ||
1276 | f_val = arm64_ftr_value(ftrp, val); | |
1277 | f_lim = arm64_ftr_value(ftrp, limit); | |
1278 | mask |= ftr_mask; | |
1279 | ||
1280 | if (f_val == f_lim) | |
1281 | safe_val = f_val; | |
1282 | else | |
1283 | safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); | |
1284 | ||
1285 | if (safe_val != f_val) | |
1286 | return -E2BIG; | |
d82e0dfd | 1287 | } |
2e8bf0cb JZ |
1288 | |
1289 | /* For fields that are not writable, values in limit are the safe values. */ | |
1290 | if ((val & ~mask) != (limit & ~mask)) | |
1291 | return -E2BIG; | |
1292 | ||
1293 | return 0; | |
d82e0dfd MZ |
1294 | } |
1295 | ||
3d0dba57 MZ |
1296 | static u8 pmuver_to_perfmon(u8 pmuver) |
1297 | { | |
1298 | switch (pmuver) { | |
1299 | case ID_AA64DFR0_EL1_PMUVer_IMP: | |
753d734f | 1300 | return ID_DFR0_EL1_PerfMon_PMUv3; |
3d0dba57 | 1301 | case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: |
753d734f | 1302 | return ID_DFR0_EL1_PerfMon_IMPDEF; |
3d0dba57 MZ |
1303 | default: |
1304 | /* Anything ARMv8.1+ and NI have the same value. For now. */ | |
1305 | return pmuver; | |
1306 | } | |
1307 | } | |
1308 | ||
93390c0a | 1309 | /* Read a sanitised cpufeature ID register by sys_reg_desc */ |
d86cde6e JZ |
1310 | static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, |
1311 | const struct sys_reg_desc *r) | |
93390c0a | 1312 | { |
7ba8b438 | 1313 | u32 id = reg_to_encoding(r); |
00d5101b AE |
1314 | u64 val; |
1315 | ||
cdd5036d | 1316 | if (sysreg_visible_as_raz(vcpu, r)) |
00d5101b AE |
1317 | return 0; |
1318 | ||
1319 | val = read_sanitised_ftr_reg(id); | |
93390c0a | 1320 | |
c8857935 | 1321 | switch (id) { |
c8857935 | 1322 | case SYS_ID_AA64PFR1_EL1: |
16dd1fbb | 1323 | if (!kvm_has_mte(vcpu->kvm)) |
6ca2b9ca | 1324 | val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); |
90807748 | 1325 | |
6ca2b9ca | 1326 | val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); |
c8857935 MZ |
1327 | break; |
1328 | case SYS_ID_AA64ISAR1_EL1: | |
1329 | if (!vcpu_has_ptrauth(vcpu)) | |
aa50479b MB |
1330 | val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | |
1331 | ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | | |
1332 | ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | | |
1333 | ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); | |
c8857935 | 1334 | break; |
def8c222 VM |
1335 | case SYS_ID_AA64ISAR2_EL1: |
1336 | if (!vcpu_has_ptrauth(vcpu)) | |
b2d71f27 MB |
1337 | val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | |
1338 | ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); | |
06e0b802 | 1339 | if (!cpus_have_final_cap(ARM64_HAS_WFXT)) |
b2d71f27 | 1340 | val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); |
3172613f | 1341 | val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS); |
def8c222 | 1342 | break; |
bf48040c AO |
1343 | case SYS_ID_AA64MMFR2_EL1: |
1344 | val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; | |
1345 | break; | |
1346 | case SYS_ID_MMFR4_EL1: | |
1347 | val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); | |
1348 | break; | |
07d79fe7 DM |
1349 | } |
1350 | ||
1351 | return val; | |
93390c0a DM |
1352 | } |
1353 | ||
d86cde6e JZ |
1354 | static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, |
1355 | const struct sys_reg_desc *r) | |
1356 | { | |
1357 | return __kvm_read_sanitised_id_reg(vcpu, r); | |
1358 | } | |
1359 | ||
1360 | static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) | |
1361 | { | |
6db7af0d | 1362 | return IDREG(vcpu->kvm, reg_to_encoding(r)); |
d86cde6e JZ |
1363 | } |
1364 | ||
47334146 JZ |
1365 | /* |
1366 | * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is | |
1367 | * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. | |
1368 | */ | |
1369 | static inline bool is_id_reg(u32 id) | |
1370 | { | |
1371 | return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && | |
1372 | sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && | |
1373 | sys_reg_CRm(id) < 8); | |
1374 | } | |
1375 | ||
912dee57 AJ |
1376 | static unsigned int id_visibility(const struct kvm_vcpu *vcpu, |
1377 | const struct sys_reg_desc *r) | |
1378 | { | |
7ba8b438 | 1379 | u32 id = reg_to_encoding(r); |
c512298e AJ |
1380 | |
1381 | switch (id) { | |
1382 | case SYS_ID_AA64ZFR0_EL1: | |
1383 | if (!vcpu_has_sve(vcpu)) | |
1384 | return REG_RAZ; | |
1385 | break; | |
1386 | } | |
1387 | ||
912dee57 AJ |
1388 | return 0; |
1389 | } | |
1390 | ||
d5efec7e OU |
1391 | static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, |
1392 | const struct sys_reg_desc *r) | |
1393 | { | |
1394 | /* | |
1395 | * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any | |
1396 | * EL. Promote to RAZ/WI in order to guarantee consistency between | |
1397 | * systems. | |
1398 | */ | |
1399 | if (!kvm_supports_32bit_el0()) | |
1400 | return REG_RAZ | REG_USER_WI; | |
1401 | ||
1402 | return id_visibility(vcpu, r); | |
1403 | } | |
1404 | ||
34b4d203 OU |
1405 | static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, |
1406 | const struct sys_reg_desc *r) | |
1407 | { | |
1408 | return REG_RAZ; | |
1409 | } | |
1410 | ||
93390c0a DM |
1411 | /* cpufeature ID register access trap handlers */ |
1412 | ||
93390c0a DM |
1413 | static bool access_id_reg(struct kvm_vcpu *vcpu, |
1414 | struct sys_reg_params *p, | |
1415 | const struct sys_reg_desc *r) | |
1416 | { | |
4782ccc8 OU |
1417 | if (p->is_write) |
1418 | return write_to_read_only(vcpu, p, r); | |
1419 | ||
cdd5036d | 1420 | p->regval = read_id_reg(vcpu, r); |
9f75b6d4 MZ |
1421 | if (vcpu_has_nv(vcpu)) |
1422 | access_nested_id_reg(vcpu, p, r); | |
1423 | ||
4782ccc8 | 1424 | return true; |
93390c0a DM |
1425 | } |
1426 | ||
73433762 DM |
1427 | /* Visibility overrides for SVE-specific control registers */ |
1428 | static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, | |
1429 | const struct sys_reg_desc *rd) | |
1430 | { | |
1431 | if (vcpu_has_sve(vcpu)) | |
1432 | return 0; | |
1433 | ||
01fe5ace | 1434 | return REG_HIDDEN; |
73433762 DM |
1435 | } |
1436 | ||
c39f5974 JZ |
1437 | static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, |
1438 | const struct sys_reg_desc *rd) | |
23711a5e | 1439 | { |
c39f5974 JZ |
1440 | u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); |
1441 | ||
1442 | if (!vcpu_has_sve(vcpu)) | |
1443 | val &= ~ID_AA64PFR0_EL1_SVE_MASK; | |
23711a5e MZ |
1444 | |
1445 | /* | |
c39f5974 JZ |
1446 | * The default is to expose CSV2 == 1 if the HW isn't affected. |
1447 | * Although this is a per-CPU feature, we make it global because | |
1448 | * asymmetric systems are just a nuisance. | |
1449 | * | |
1450 | * Userspace can override this as long as it doesn't promise | |
1451 | * the impossible. | |
23711a5e | 1452 | */ |
c39f5974 JZ |
1453 | if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { |
1454 | val &= ~ID_AA64PFR0_EL1_CSV2_MASK; | |
1455 | val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); | |
1456 | } | |
1457 | if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { | |
1458 | val &= ~ID_AA64PFR0_EL1_CSV3_MASK; | |
1459 | val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); | |
1460 | } | |
23711a5e | 1461 | |
c39f5974 JZ |
1462 | if (kvm_vgic_global_state.type == VGIC_V3) { |
1463 | val &= ~ID_AA64PFR0_EL1_GIC_MASK; | |
1464 | val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); | |
1465 | } | |
4f1df628 | 1466 | |
c39f5974 | 1467 | val &= ~ID_AA64PFR0_EL1_AMU_MASK; |
23711a5e | 1468 | |
c39f5974 JZ |
1469 | return val; |
1470 | } | |
23711a5e | 1471 | |
c118cead JZ |
1472 | static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, |
1473 | const struct sys_reg_desc *rd) | |
1474 | { | |
1475 | u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); | |
1476 | ||
1477 | /* Limit debug to ARMv8.0 */ | |
1478 | val &= ~ID_AA64DFR0_EL1_DebugVer_MASK; | |
1479 | val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DebugVer, IMP); | |
1480 | ||
1481 | /* | |
1482 | * Only initialize the PMU version if the vCPU was configured with one. | |
1483 | */ | |
1484 | val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; | |
1485 | if (kvm_vcpu_has_pmu(vcpu)) | |
1486 | val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, | |
1487 | kvm_arm_pmu_get_pmuver_limit()); | |
1488 | ||
1489 | /* Hide SPE from guests */ | |
1490 | val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; | |
1491 | ||
1492 | return val; | |
23711a5e MZ |
1493 | } |
1494 | ||
60e651ff MZ |
1495 | static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, |
1496 | const struct sys_reg_desc *rd, | |
1497 | u64 val) | |
1498 | { | |
c118cead | 1499 | u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); |
60e651ff MZ |
1500 | |
1501 | /* | |
f90f9360 OU |
1502 | * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the |
1503 | * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously | |
1504 | * exposed an IMP_DEF PMU to userspace and the guest on systems w/ | |
1505 | * non-architectural PMUs. Of course, PMUv3 is the only game in town for | |
1506 | * PMU virtualization, so the IMP_DEF value was rather user-hostile. | |
1507 | * | |
1508 | * At minimum, we're on the hook to allow values that were given to | |
1509 | * userspace by KVM. Cover our tracks here and replace the IMP_DEF value | |
1510 | * with a more sensible NI. The value of an ID register changing under | |
1511 | * the nose of the guest is unfortunate, but is certainly no more | |
1512 | * surprising than an ill-guided PMU driver poking at impdef system | |
1513 | * registers that end in an UNDEF... | |
60e651ff | 1514 | */ |
68667240 | 1515 | if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) |
f90f9360 | 1516 | val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; |
60e651ff | 1517 | |
68667240 | 1518 | return set_id_reg(vcpu, rd, val); |
c118cead | 1519 | } |
60e651ff | 1520 | |
c118cead JZ |
1521 | static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, |
1522 | const struct sys_reg_desc *rd) | |
1523 | { | |
1524 | u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); | |
1525 | u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); | |
60e651ff | 1526 | |
c118cead JZ |
1527 | val &= ~ID_DFR0_EL1_PerfMon_MASK; |
1528 | if (kvm_vcpu_has_pmu(vcpu)) | |
1529 | val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); | |
60e651ff | 1530 | |
c118cead | 1531 | return val; |
60e651ff MZ |
1532 | } |
1533 | ||
d82e0dfd MZ |
1534 | static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, |
1535 | const struct sys_reg_desc *rd, | |
1536 | u64 val) | |
1537 | { | |
c118cead | 1538 | u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); |
d82e0dfd | 1539 | |
f90f9360 OU |
1540 | if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { |
1541 | val &= ~ID_DFR0_EL1_PerfMon_MASK; | |
1542 | perfmon = 0; | |
1543 | } | |
d82e0dfd MZ |
1544 | |
1545 | /* | |
1546 | * Allow DFR0_EL1.PerfMon to be set from userspace as long as | |
1547 | * it doesn't promise more than what the HW gives us on the | |
1548 | * AArch64 side (as everything is emulated with that), and | |
1549 | * that this is a PMUv3. | |
1550 | */ | |
c118cead | 1551 | if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) |
d82e0dfd MZ |
1552 | return -EINVAL; |
1553 | ||
68667240 | 1554 | return set_id_reg(vcpu, rd, val); |
d82e0dfd MZ |
1555 | } |
1556 | ||
93390c0a DM |
1557 | /* |
1558 | * cpufeature ID register user accessors | |
1559 | * | |
1560 | * For now, these registers are immutable for userspace, so no values | |
1561 | * are stored, and for set_id_reg() we don't allow the effective value | |
1562 | * to be changed. | |
1563 | */ | |
93390c0a | 1564 | static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
978ceeb3 | 1565 | u64 *val) |
93390c0a | 1566 | { |
6db7af0d OU |
1567 | /* |
1568 | * Avoid locking if the VM has already started, as the ID registers are | |
1569 | * guaranteed to be invariant at that point. | |
1570 | */ | |
1571 | if (kvm_vm_has_ran_once(vcpu->kvm)) { | |
1572 | *val = read_id_reg(vcpu, rd); | |
1573 | return 0; | |
1574 | } | |
1575 | ||
1576 | mutex_lock(&vcpu->kvm->arch.config_lock); | |
cdd5036d | 1577 | *val = read_id_reg(vcpu, rd); |
6db7af0d OU |
1578 | mutex_unlock(&vcpu->kvm->arch.config_lock); |
1579 | ||
4782ccc8 | 1580 | return 0; |
93390c0a DM |
1581 | } |
1582 | ||
1583 | static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
978ceeb3 | 1584 | u64 val) |
93390c0a | 1585 | { |
2e8bf0cb JZ |
1586 | u32 id = reg_to_encoding(rd); |
1587 | int ret; | |
4782ccc8 | 1588 | |
2e8bf0cb JZ |
1589 | mutex_lock(&vcpu->kvm->arch.config_lock); |
1590 | ||
1591 | /* | |
1592 | * Once the VM has started the ID registers are immutable. Reject any | |
1593 | * write that does not match the final register value. | |
1594 | */ | |
1595 | if (kvm_vm_has_ran_once(vcpu->kvm)) { | |
1596 | if (val != read_id_reg(vcpu, rd)) | |
1597 | ret = -EBUSY; | |
1598 | else | |
1599 | ret = 0; | |
1600 | ||
1601 | mutex_unlock(&vcpu->kvm->arch.config_lock); | |
1602 | return ret; | |
1603 | } | |
1604 | ||
1605 | ret = arm64_check_features(vcpu, rd, val); | |
1606 | if (!ret) | |
1607 | IDREG(vcpu->kvm, id) = val; | |
1608 | ||
1609 | mutex_unlock(&vcpu->kvm->arch.config_lock); | |
1610 | ||
1611 | /* | |
1612 | * arm64_check_features() returns -E2BIG to indicate the register's | |
1613 | * feature set is a superset of the maximally-allowed register value. | |
1614 | * While it would be nice to precisely describe this to userspace, the | |
1615 | * existing UAPI for KVM_SET_ONE_REG has it that invalid register | |
1616 | * writes return -EINVAL. | |
1617 | */ | |
1618 | if (ret == -E2BIG) | |
1619 | ret = -EINVAL; | |
1620 | return ret; | |
93390c0a DM |
1621 | } |
1622 | ||
5a430976 | 1623 | static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
978ceeb3 | 1624 | u64 *val) |
5a430976 | 1625 | { |
978ceeb3 MZ |
1626 | *val = 0; |
1627 | return 0; | |
5a430976 AE |
1628 | } |
1629 | ||
7a3ba309 | 1630 | static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, |
978ceeb3 | 1631 | u64 val) |
7a3ba309 | 1632 | { |
7a3ba309 MZ |
1633 | return 0; |
1634 | } | |
1635 | ||
f7f2b15c AB |
1636 | static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
1637 | const struct sys_reg_desc *r) | |
1638 | { | |
1639 | if (p->is_write) | |
1640 | return write_to_read_only(vcpu, p, r); | |
1641 | ||
1642 | p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); | |
1643 | return true; | |
1644 | } | |
1645 | ||
1646 | static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, | |
1647 | const struct sys_reg_desc *r) | |
1648 | { | |
1649 | if (p->is_write) | |
1650 | return write_to_read_only(vcpu, p, r); | |
1651 | ||
7af0c253 | 1652 | p->regval = __vcpu_sys_reg(vcpu, r->reg); |
f7f2b15c AB |
1653 | return true; |
1654 | } | |
1655 | ||
7af0c253 AO |
1656 | /* |
1657 | * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary | |
1658 | * by the physical CPU which the vcpu currently resides in. | |
1659 | */ | |
d86cde6e | 1660 | static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) |
7af0c253 AO |
1661 | { |
1662 | u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); | |
1663 | u64 clidr; | |
1664 | u8 loc; | |
1665 | ||
1666 | if ((ctr_el0 & CTR_EL0_IDC)) { | |
1667 | /* | |
1668 | * Data cache clean to the PoU is not required so LoUU and LoUIS | |
1669 | * will not be set and a unified cache, which will be marked as | |
1670 | * LoC, will be added. | |
1671 | * | |
1672 | * If not DIC, let the unified cache L2 so that an instruction | |
1673 | * cache can be added as L1 later. | |
1674 | */ | |
1675 | loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; | |
1676 | clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); | |
1677 | } else { | |
1678 | /* | |
1679 | * Data cache clean to the PoU is required so let L1 have a data | |
1680 | * cache and mark it as LoUU and LoUIS. As L1 has a data cache, | |
1681 | * it can be marked as LoC too. | |
1682 | */ | |
1683 | loc = 1; | |
1684 | clidr = 1 << CLIDR_LOUU_SHIFT; | |
1685 | clidr |= 1 << CLIDR_LOUIS_SHIFT; | |
1686 | clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); | |
1687 | } | |
1688 | ||
1689 | /* | |
1690 | * Instruction cache invalidation to the PoU is required so let L1 have | |
1691 | * an instruction cache. If L1 already has a data cache, it will be | |
1692 | * CACHE_TYPE_SEPARATE. | |
1693 | */ | |
1694 | if (!(ctr_el0 & CTR_EL0_DIC)) | |
1695 | clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); | |
1696 | ||
1697 | clidr |= loc << CLIDR_LOC_SHIFT; | |
1698 | ||
1699 | /* | |
1700 | * Add tag cache unified to data cache. Allocation tags and data are | |
1701 | * unified in a cache line so that it looks valid even if there is only | |
1702 | * one cache line. | |
1703 | */ | |
1704 | if (kvm_has_mte(vcpu->kvm)) | |
1705 | clidr |= 2 << CLIDR_TTYPE_SHIFT(loc); | |
1706 | ||
1707 | __vcpu_sys_reg(vcpu, r->reg) = clidr; | |
d86cde6e JZ |
1708 | |
1709 | return __vcpu_sys_reg(vcpu, r->reg); | |
7af0c253 AO |
1710 | } |
1711 | ||
1712 | static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, | |
1713 | u64 val) | |
1714 | { | |
1715 | u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); | |
1716 | u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); | |
1717 | ||
1718 | if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) | |
1719 | return -EINVAL; | |
1720 | ||
1721 | __vcpu_sys_reg(vcpu, rd->reg) = val; | |
1722 | ||
1723 | return 0; | |
1724 | } | |
1725 | ||
f7f2b15c AB |
1726 | static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, |
1727 | const struct sys_reg_desc *r) | |
1728 | { | |
7c582bf4 JM |
1729 | int reg = r->reg; |
1730 | ||
f7f2b15c | 1731 | if (p->is_write) |
7c582bf4 | 1732 | vcpu_write_sys_reg(vcpu, p->regval, reg); |
f7f2b15c | 1733 | else |
7c582bf4 | 1734 | p->regval = vcpu_read_sys_reg(vcpu, reg); |
f7f2b15c AB |
1735 | return true; |
1736 | } | |
1737 | ||
1738 | static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, | |
1739 | const struct sys_reg_desc *r) | |
1740 | { | |
1741 | u32 csselr; | |
1742 | ||
1743 | if (p->is_write) | |
1744 | return write_to_read_only(vcpu, p, r); | |
1745 | ||
1746 | csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); | |
7af0c253 AO |
1747 | csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; |
1748 | if (csselr < CSSELR_MAX) | |
1749 | p->regval = get_ccsidr(vcpu, csselr); | |
793acf87 | 1750 | |
f7f2b15c AB |
1751 | return true; |
1752 | } | |
1753 | ||
e1f358b5 SP |
1754 | static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, |
1755 | const struct sys_reg_desc *rd) | |
1756 | { | |
673638f4 SP |
1757 | if (kvm_has_mte(vcpu->kvm)) |
1758 | return 0; | |
1759 | ||
e1f358b5 SP |
1760 | return REG_HIDDEN; |
1761 | } | |
1762 | ||
1763 | #define MTE_REG(name) { \ | |
1764 | SYS_DESC(SYS_##name), \ | |
1765 | .access = undef_access, \ | |
1766 | .reset = reset_unknown, \ | |
1767 | .reg = name, \ | |
1768 | .visibility = mte_visibility, \ | |
1769 | } | |
1770 | ||
6ff9dc23 JL |
1771 | static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, |
1772 | const struct sys_reg_desc *rd) | |
1773 | { | |
1774 | if (vcpu_has_nv(vcpu)) | |
1775 | return 0; | |
1776 | ||
1777 | return REG_HIDDEN; | |
1778 | } | |
1779 | ||
1780 | #define EL2_REG(name, acc, rst, v) { \ | |
1781 | SYS_DESC(SYS_##name), \ | |
1782 | .access = acc, \ | |
1783 | .reset = rst, \ | |
1784 | .reg = name, \ | |
1785 | .visibility = el2_visibility, \ | |
1786 | .val = v, \ | |
1787 | } | |
1788 | ||
280b748e JL |
1789 | /* |
1790 | * EL{0,1}2 registers are the EL2 view on an EL0 or EL1 register when | |
1791 | * HCR_EL2.E2H==1, and only in the sysreg table for convenience of | |
1792 | * handling traps. Given that, they are always hidden from userspace. | |
1793 | */ | |
1794 | static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, | |
1795 | const struct sys_reg_desc *rd) | |
1796 | { | |
1797 | return REG_HIDDEN_USER; | |
1798 | } | |
1799 | ||
1800 | #define EL12_REG(name, acc, rst, v) { \ | |
1801 | SYS_DESC(SYS_##name##_EL12), \ | |
1802 | .access = acc, \ | |
1803 | .reset = rst, \ | |
1804 | .reg = name##_EL1, \ | |
1805 | .val = v, \ | |
1806 | .visibility = elx2_visibility, \ | |
1807 | } | |
1808 | ||
d86cde6e JZ |
1809 | /* |
1810 | * Since reset() callback and field val are not used for idregs, they will be | |
1811 | * used for specific purposes for idregs. | |
1812 | * The reset() would return KVM sanitised register value. The value would be the | |
1813 | * same as the host kernel sanitised value if there is no KVM sanitisation. | |
1814 | * The val would be used as a mask indicating writable fields for the idreg. | |
1815 | * Only bits with 1 are writable from userspace. This mask might not be | |
1816 | * necessary in the future whenever all ID registers are enabled as writable | |
1817 | * from userspace. | |
1818 | */ | |
1819 | ||
93390c0a DM |
1820 | /* sys_reg_desc initialiser for known cpufeature ID registers */ |
1821 | #define ID_SANITISED(name) { \ | |
1822 | SYS_DESC(SYS_##name), \ | |
1823 | .access = access_id_reg, \ | |
1824 | .get_user = get_id_reg, \ | |
1825 | .set_user = set_id_reg, \ | |
912dee57 | 1826 | .visibility = id_visibility, \ |
d86cde6e JZ |
1827 | .reset = kvm_read_sanitised_id_reg, \ |
1828 | .val = 0, \ | |
93390c0a DM |
1829 | } |
1830 | ||
d5efec7e OU |
1831 | /* sys_reg_desc initialiser for known cpufeature ID registers */ |
1832 | #define AA32_ID_SANITISED(name) { \ | |
1833 | SYS_DESC(SYS_##name), \ | |
1834 | .access = access_id_reg, \ | |
1835 | .get_user = get_id_reg, \ | |
1836 | .set_user = set_id_reg, \ | |
1837 | .visibility = aa32_id_visibility, \ | |
d86cde6e JZ |
1838 | .reset = kvm_read_sanitised_id_reg, \ |
1839 | .val = 0, \ | |
d5efec7e OU |
1840 | } |
1841 | ||
93390c0a DM |
1842 | /* |
1843 | * sys_reg_desc initialiser for architecturally unallocated cpufeature ID | |
1844 | * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 | |
1845 | * (1 <= crm < 8, 0 <= Op2 < 8). | |
1846 | */ | |
1847 | #define ID_UNALLOCATED(crm, op2) { \ | |
1848 | Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ | |
34b4d203 OU |
1849 | .access = access_id_reg, \ |
1850 | .get_user = get_id_reg, \ | |
1851 | .set_user = set_id_reg, \ | |
d86cde6e JZ |
1852 | .visibility = raz_visibility, \ |
1853 | .reset = kvm_read_sanitised_id_reg, \ | |
1854 | .val = 0, \ | |
93390c0a DM |
1855 | } |
1856 | ||
1857 | /* | |
1858 | * sys_reg_desc initialiser for known ID registers that we hide from guests. | |
1859 | * For now, these are exposed just like unallocated ID regs: they appear | |
1860 | * RAZ for the guest. | |
1861 | */ | |
1862 | #define ID_HIDDEN(name) { \ | |
1863 | SYS_DESC(SYS_##name), \ | |
34b4d203 OU |
1864 | .access = access_id_reg, \ |
1865 | .get_user = get_id_reg, \ | |
1866 | .set_user = set_id_reg, \ | |
1867 | .visibility = raz_visibility, \ | |
d86cde6e JZ |
1868 | .reset = kvm_read_sanitised_id_reg, \ |
1869 | .val = 0, \ | |
93390c0a DM |
1870 | } |
1871 | ||
6ff9dc23 JL |
1872 | static bool access_sp_el1(struct kvm_vcpu *vcpu, |
1873 | struct sys_reg_params *p, | |
1874 | const struct sys_reg_desc *r) | |
1875 | { | |
1876 | if (p->is_write) | |
1877 | __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; | |
1878 | else | |
1879 | p->regval = __vcpu_sys_reg(vcpu, SP_EL1); | |
1880 | ||
1881 | return true; | |
1882 | } | |
1883 | ||
9da117ee JL |
1884 | static bool access_elr(struct kvm_vcpu *vcpu, |
1885 | struct sys_reg_params *p, | |
1886 | const struct sys_reg_desc *r) | |
1887 | { | |
1888 | if (p->is_write) | |
1889 | vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); | |
1890 | else | |
1891 | p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); | |
1892 | ||
1893 | return true; | |
1894 | } | |
1895 | ||
1896 | static bool access_spsr(struct kvm_vcpu *vcpu, | |
1897 | struct sys_reg_params *p, | |
1898 | const struct sys_reg_desc *r) | |
1899 | { | |
1900 | if (p->is_write) | |
1901 | __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; | |
1902 | else | |
1903 | p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); | |
1904 | ||
1905 | return true; | |
1906 | } | |
1907 | ||
7c8c5e6a MZ |
1908 | /* |
1909 | * Architected system registers. | |
1910 | * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 | |
7609c125 | 1911 | * |
0c557ed4 MZ |
1912 | * Debug handling: We do trap most, if not all debug related system |
1913 | * registers. The implementation is good enough to ensure that a guest | |
1914 | * can use these with minimal performance degradation. The drawback is | |
7dabf02f OU |
1915 | * that we don't implement any of the external debug architecture. |
1916 | * This should be revisited if we ever encounter a more demanding | |
1917 | * guest... | |
7c8c5e6a MZ |
1918 | */ |
1919 | static const struct sys_reg_desc sys_reg_descs[] = { | |
7606e078 | 1920 | { SYS_DESC(SYS_DC_ISW), access_dcsw }, |
d282fa3c MZ |
1921 | { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, |
1922 | { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, | |
7606e078 | 1923 | { SYS_DESC(SYS_DC_CSW), access_dcsw }, |
d282fa3c MZ |
1924 | { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, |
1925 | { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, | |
7606e078 | 1926 | { SYS_DESC(SYS_DC_CISW), access_dcsw }, |
d282fa3c MZ |
1927 | { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, |
1928 | { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, | |
7c8c5e6a | 1929 | |
0c557ed4 MZ |
1930 | DBG_BCR_BVR_WCR_WVR_EL1(0), |
1931 | DBG_BCR_BVR_WCR_WVR_EL1(1), | |
ee1b64e6 MR |
1932 | { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, |
1933 | { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, | |
0c557ed4 MZ |
1934 | DBG_BCR_BVR_WCR_WVR_EL1(2), |
1935 | DBG_BCR_BVR_WCR_WVR_EL1(3), | |
1936 | DBG_BCR_BVR_WCR_WVR_EL1(4), | |
1937 | DBG_BCR_BVR_WCR_WVR_EL1(5), | |
1938 | DBG_BCR_BVR_WCR_WVR_EL1(6), | |
1939 | DBG_BCR_BVR_WCR_WVR_EL1(7), | |
1940 | DBG_BCR_BVR_WCR_WVR_EL1(8), | |
1941 | DBG_BCR_BVR_WCR_WVR_EL1(9), | |
1942 | DBG_BCR_BVR_WCR_WVR_EL1(10), | |
1943 | DBG_BCR_BVR_WCR_WVR_EL1(11), | |
1944 | DBG_BCR_BVR_WCR_WVR_EL1(12), | |
1945 | DBG_BCR_BVR_WCR_WVR_EL1(13), | |
1946 | DBG_BCR_BVR_WCR_WVR_EL1(14), | |
1947 | DBG_BCR_BVR_WCR_WVR_EL1(15), | |
1948 | ||
ee1b64e6 | 1949 | { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, |
f24adc65 | 1950 | { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, |
d42e2671 | 1951 | { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, |
187de7c2 | 1952 | OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, |
ee1b64e6 MR |
1953 | { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, |
1954 | { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, | |
1955 | { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, | |
1956 | { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, | |
1957 | { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, | |
1958 | ||
1959 | { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, | |
1960 | { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, | |
1961 | // DBGDTR[TR]X_EL0 share the same encoding | |
1962 | { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, | |
1963 | ||
1964 | { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, | |
62a89c44 | 1965 | |
851050a5 | 1966 | { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, |
93390c0a DM |
1967 | |
1968 | /* | |
1969 | * ID regs: all ID_SANITISED() entries here must have corresponding | |
1970 | * entries in arm64_ftr_regs[]. | |
1971 | */ | |
1972 | ||
1973 | /* AArch64 mappings of the AArch32 ID registers */ | |
1974 | /* CRm=1 */ | |
d5efec7e OU |
1975 | AA32_ID_SANITISED(ID_PFR0_EL1), |
1976 | AA32_ID_SANITISED(ID_PFR1_EL1), | |
c118cead JZ |
1977 | { SYS_DESC(SYS_ID_DFR0_EL1), |
1978 | .access = access_id_reg, | |
1979 | .get_user = get_id_reg, | |
1980 | .set_user = set_id_dfr0_el1, | |
1981 | .visibility = aa32_id_visibility, | |
1982 | .reset = read_sanitised_id_dfr0_el1, | |
1983 | .val = ID_DFR0_EL1_PerfMon_MASK, }, | |
93390c0a | 1984 | ID_HIDDEN(ID_AFR0_EL1), |
d5efec7e OU |
1985 | AA32_ID_SANITISED(ID_MMFR0_EL1), |
1986 | AA32_ID_SANITISED(ID_MMFR1_EL1), | |
1987 | AA32_ID_SANITISED(ID_MMFR2_EL1), | |
1988 | AA32_ID_SANITISED(ID_MMFR3_EL1), | |
93390c0a DM |
1989 | |
1990 | /* CRm=2 */ | |
d5efec7e OU |
1991 | AA32_ID_SANITISED(ID_ISAR0_EL1), |
1992 | AA32_ID_SANITISED(ID_ISAR1_EL1), | |
1993 | AA32_ID_SANITISED(ID_ISAR2_EL1), | |
1994 | AA32_ID_SANITISED(ID_ISAR3_EL1), | |
1995 | AA32_ID_SANITISED(ID_ISAR4_EL1), | |
1996 | AA32_ID_SANITISED(ID_ISAR5_EL1), | |
1997 | AA32_ID_SANITISED(ID_MMFR4_EL1), | |
1998 | AA32_ID_SANITISED(ID_ISAR6_EL1), | |
93390c0a DM |
1999 | |
2000 | /* CRm=3 */ | |
d5efec7e OU |
2001 | AA32_ID_SANITISED(MVFR0_EL1), |
2002 | AA32_ID_SANITISED(MVFR1_EL1), | |
2003 | AA32_ID_SANITISED(MVFR2_EL1), | |
93390c0a | 2004 | ID_UNALLOCATED(3,3), |
d5efec7e | 2005 | AA32_ID_SANITISED(ID_PFR2_EL1), |
dd35ec07 | 2006 | ID_HIDDEN(ID_DFR1_EL1), |
d5efec7e | 2007 | AA32_ID_SANITISED(ID_MMFR5_EL1), |
93390c0a DM |
2008 | ID_UNALLOCATED(3,7), |
2009 | ||
2010 | /* AArch64 ID registers */ | |
2011 | /* CRm=4 */ | |
c39f5974 JZ |
2012 | { SYS_DESC(SYS_ID_AA64PFR0_EL1), |
2013 | .access = access_id_reg, | |
2014 | .get_user = get_id_reg, | |
68667240 | 2015 | .set_user = set_id_reg, |
c39f5974 JZ |
2016 | .reset = read_sanitised_id_aa64pfr0_el1, |
2017 | .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, }, | |
93390c0a DM |
2018 | ID_SANITISED(ID_AA64PFR1_EL1), |
2019 | ID_UNALLOCATED(4,2), | |
2020 | ID_UNALLOCATED(4,3), | |
c512298e | 2021 | ID_SANITISED(ID_AA64ZFR0_EL1), |
90807748 | 2022 | ID_HIDDEN(ID_AA64SMFR0_EL1), |
93390c0a DM |
2023 | ID_UNALLOCATED(4,6), |
2024 | ID_UNALLOCATED(4,7), | |
2025 | ||
2026 | /* CRm=5 */ | |
c118cead JZ |
2027 | { SYS_DESC(SYS_ID_AA64DFR0_EL1), |
2028 | .access = access_id_reg, | |
2029 | .get_user = get_id_reg, | |
2030 | .set_user = set_id_aa64dfr0_el1, | |
2031 | .reset = read_sanitised_id_aa64dfr0_el1, | |
2032 | .val = ID_AA64DFR0_EL1_PMUVer_MASK, }, | |
93390c0a DM |
2033 | ID_SANITISED(ID_AA64DFR1_EL1), |
2034 | ID_UNALLOCATED(5,2), | |
2035 | ID_UNALLOCATED(5,3), | |
2036 | ID_HIDDEN(ID_AA64AFR0_EL1), | |
2037 | ID_HIDDEN(ID_AA64AFR1_EL1), | |
2038 | ID_UNALLOCATED(5,6), | |
2039 | ID_UNALLOCATED(5,7), | |
2040 | ||
2041 | /* CRm=6 */ | |
2042 | ID_SANITISED(ID_AA64ISAR0_EL1), | |
2043 | ID_SANITISED(ID_AA64ISAR1_EL1), | |
9e45365f | 2044 | ID_SANITISED(ID_AA64ISAR2_EL1), |
93390c0a DM |
2045 | ID_UNALLOCATED(6,3), |
2046 | ID_UNALLOCATED(6,4), | |
2047 | ID_UNALLOCATED(6,5), | |
2048 | ID_UNALLOCATED(6,6), | |
2049 | ID_UNALLOCATED(6,7), | |
2050 | ||
2051 | /* CRm=7 */ | |
2052 | ID_SANITISED(ID_AA64MMFR0_EL1), | |
2053 | ID_SANITISED(ID_AA64MMFR1_EL1), | |
2054 | ID_SANITISED(ID_AA64MMFR2_EL1), | |
8ef67c67 | 2055 | ID_SANITISED(ID_AA64MMFR3_EL1), |
93390c0a DM |
2056 | ID_UNALLOCATED(7,4), |
2057 | ID_UNALLOCATED(7,5), | |
2058 | ID_UNALLOCATED(7,6), | |
2059 | ID_UNALLOCATED(7,7), | |
2060 | ||
851050a5 | 2061 | { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, |
af473829 | 2062 | { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, |
851050a5 | 2063 | { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, |
2ac638fc | 2064 | |
e1f358b5 SP |
2065 | MTE_REG(RGSR_EL1), |
2066 | MTE_REG(GCR_EL1), | |
2ac638fc | 2067 | |
73433762 | 2068 | { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, |
cc427cbb | 2069 | { SYS_DESC(SYS_TRFCR_EL1), undef_access }, |
90807748 MB |
2070 | { SYS_DESC(SYS_SMPRI_EL1), undef_access }, |
2071 | { SYS_DESC(SYS_SMCR_EL1), undef_access }, | |
851050a5 MR |
2072 | { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, |
2073 | { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, | |
2074 | { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, | |
fbff5606 | 2075 | { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 }, |
851050a5 | 2076 | |
384b40ca MR |
2077 | PTRAUTH_KEY(APIA), |
2078 | PTRAUTH_KEY(APIB), | |
2079 | PTRAUTH_KEY(APDA), | |
2080 | PTRAUTH_KEY(APDB), | |
2081 | PTRAUTH_KEY(APGA), | |
2082 | ||
9da117ee JL |
2083 | { SYS_DESC(SYS_SPSR_EL1), access_spsr}, |
2084 | { SYS_DESC(SYS_ELR_EL1), access_elr}, | |
2085 | ||
851050a5 MR |
2086 | { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, |
2087 | { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, | |
2088 | { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, | |
558daf69 DG |
2089 | |
2090 | { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, | |
2091 | { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, | |
2092 | { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, | |
2093 | { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, | |
2094 | { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, | |
2095 | { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, | |
2096 | { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, | |
2097 | { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, | |
2098 | ||
e1f358b5 SP |
2099 | MTE_REG(TFSR_EL1), |
2100 | MTE_REG(TFSRE0_EL1), | |
2ac638fc | 2101 | |
851050a5 MR |
2102 | { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, |
2103 | { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, | |
7c8c5e6a | 2104 | |
13611bc8 AE |
2105 | { SYS_DESC(SYS_PMSCR_EL1), undef_access }, |
2106 | { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, | |
2107 | { SYS_DESC(SYS_PMSICR_EL1), undef_access }, | |
2108 | { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, | |
2109 | { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, | |
2110 | { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, | |
2111 | { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, | |
2112 | { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, | |
2113 | { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, | |
2114 | { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, | |
2115 | { SYS_DESC(SYS_PMBSR_EL1), undef_access }, | |
2116 | /* PMBIDR_EL1 is not trapped */ | |
2117 | ||
9d2a55b4 | 2118 | { PMU_SYS_REG(PMINTENSET_EL1), |
11663111 | 2119 | .access = access_pminten, .reg = PMINTENSET_EL1 }, |
9d2a55b4 | 2120 | { PMU_SYS_REG(PMINTENCLR_EL1), |
11663111 | 2121 | .access = access_pminten, .reg = PMINTENSET_EL1 }, |
46081078 | 2122 | { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, |
7c8c5e6a | 2123 | |
851050a5 | 2124 | { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, |
86f9de9d JG |
2125 | { SYS_DESC(SYS_PIRE0_EL1), access_vm_reg, reset_unknown, PIRE0_EL1 }, |
2126 | { SYS_DESC(SYS_PIR_EL1), access_vm_reg, reset_unknown, PIR_EL1 }, | |
851050a5 | 2127 | { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, |
7c8c5e6a | 2128 | |
22925521 MZ |
2129 | { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, |
2130 | { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, | |
2131 | { SYS_DESC(SYS_LORN_EL1), trap_loregion }, | |
2132 | { SYS_DESC(SYS_LORC_EL1), trap_loregion }, | |
2133 | { SYS_DESC(SYS_LORID_EL1), trap_loregion }, | |
cc33c4e2 | 2134 | |
9da117ee | 2135 | { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, |
c773ae2b | 2136 | { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, |
db7dedd0 | 2137 | |
7b1dba1f | 2138 | { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, |
e7f1d1ee | 2139 | { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, |
7b1dba1f | 2140 | { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, |
e7f1d1ee | 2141 | { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, |
7b1dba1f | 2142 | { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, |
e804d208 | 2143 | { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, |
03bd646d MZ |
2144 | { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, |
2145 | { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, | |
7b1dba1f | 2146 | { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, |
e7f1d1ee | 2147 | { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, |
7b1dba1f | 2148 | { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, |
e804d208 | 2149 | { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, |
db7dedd0 | 2150 | |
851050a5 MR |
2151 | { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, |
2152 | { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, | |
7c8c5e6a | 2153 | |
ed4ffaf4 MZ |
2154 | { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, |
2155 | ||
851050a5 | 2156 | { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, |
7c8c5e6a | 2157 | |
f7f2b15c | 2158 | { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, |
7af0c253 AO |
2159 | { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, |
2160 | .set_user = set_clidr }, | |
bf48040c | 2161 | { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, |
90807748 | 2162 | { SYS_DESC(SYS_SMIDR_EL1), undef_access }, |
f7f2b15c AB |
2163 | { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, |
2164 | { SYS_DESC(SYS_CTR_EL0), access_ctr }, | |
ec0067a6 | 2165 | { SYS_DESC(SYS_SVCR), undef_access }, |
7c8c5e6a | 2166 | |
9d2a55b4 | 2167 | { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, |
11663111 | 2168 | .reset = reset_pmcr, .reg = PMCR_EL0 }, |
9d2a55b4 | 2169 | { PMU_SYS_REG(PMCNTENSET_EL0), |
11663111 | 2170 | .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, |
9d2a55b4 | 2171 | { PMU_SYS_REG(PMCNTENCLR_EL0), |
11663111 | 2172 | .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, |
9d2a55b4 | 2173 | { PMU_SYS_REG(PMOVSCLR_EL0), |
11663111 | 2174 | .access = access_pmovs, .reg = PMOVSSET_EL0 }, |
7a3ba309 MZ |
2175 | /* |
2176 | * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was | |
2177 | * previously (and pointlessly) advertised in the past... | |
2178 | */ | |
9d2a55b4 | 2179 | { PMU_SYS_REG(PMSWINC_EL0), |
5a430976 | 2180 | .get_user = get_raz_reg, .set_user = set_wi_reg, |
7a3ba309 | 2181 | .access = access_pmswinc, .reset = NULL }, |
9d2a55b4 | 2182 | { PMU_SYS_REG(PMSELR_EL0), |
0ab410a9 | 2183 | .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, |
9d2a55b4 | 2184 | { PMU_SYS_REG(PMCEID0_EL0), |
11663111 | 2185 | .access = access_pmceid, .reset = NULL }, |
9d2a55b4 | 2186 | { PMU_SYS_REG(PMCEID1_EL0), |
11663111 | 2187 | .access = access_pmceid, .reset = NULL }, |
9d2a55b4 | 2188 | { PMU_SYS_REG(PMCCNTR_EL0), |
9228b261 RW |
2189 | .access = access_pmu_evcntr, .reset = reset_unknown, |
2190 | .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, | |
9d2a55b4 | 2191 | { PMU_SYS_REG(PMXEVTYPER_EL0), |
11663111 | 2192 | .access = access_pmu_evtyper, .reset = NULL }, |
9d2a55b4 | 2193 | { PMU_SYS_REG(PMXEVCNTR_EL0), |
11663111 | 2194 | .access = access_pmu_evcntr, .reset = NULL }, |
174ed3e4 MR |
2195 | /* |
2196 | * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero | |
d692b8ad SZ |
2197 | * in 32bit mode. Here we choose to reset it as zero for consistency. |
2198 | */ | |
9d2a55b4 | 2199 | { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, |
11663111 | 2200 | .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, |
9d2a55b4 | 2201 | { PMU_SYS_REG(PMOVSSET_EL0), |
11663111 | 2202 | .access = access_pmovs, .reg = PMOVSSET_EL0 }, |
7c8c5e6a | 2203 | |
851050a5 MR |
2204 | { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, |
2205 | { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, | |
90807748 | 2206 | { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, |
4fcdf106 | 2207 | |
ed4ffaf4 MZ |
2208 | { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, |
2209 | ||
338b1793 MZ |
2210 | { SYS_DESC(SYS_AMCR_EL0), undef_access }, |
2211 | { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, | |
2212 | { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, | |
2213 | { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, | |
2214 | { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, | |
2215 | { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, | |
2216 | { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, | |
2217 | { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, | |
4fcdf106 IV |
2218 | AMU_AMEVCNTR0_EL0(0), |
2219 | AMU_AMEVCNTR0_EL0(1), | |
2220 | AMU_AMEVCNTR0_EL0(2), | |
2221 | AMU_AMEVCNTR0_EL0(3), | |
2222 | AMU_AMEVCNTR0_EL0(4), | |
2223 | AMU_AMEVCNTR0_EL0(5), | |
2224 | AMU_AMEVCNTR0_EL0(6), | |
2225 | AMU_AMEVCNTR0_EL0(7), | |
2226 | AMU_AMEVCNTR0_EL0(8), | |
2227 | AMU_AMEVCNTR0_EL0(9), | |
2228 | AMU_AMEVCNTR0_EL0(10), | |
2229 | AMU_AMEVCNTR0_EL0(11), | |
2230 | AMU_AMEVCNTR0_EL0(12), | |
2231 | AMU_AMEVCNTR0_EL0(13), | |
2232 | AMU_AMEVCNTR0_EL0(14), | |
2233 | AMU_AMEVCNTR0_EL0(15), | |
493cf9b7 VM |
2234 | AMU_AMEVTYPER0_EL0(0), |
2235 | AMU_AMEVTYPER0_EL0(1), | |
2236 | AMU_AMEVTYPER0_EL0(2), | |
2237 | AMU_AMEVTYPER0_EL0(3), | |
2238 | AMU_AMEVTYPER0_EL0(4), | |
2239 | AMU_AMEVTYPER0_EL0(5), | |
2240 | AMU_AMEVTYPER0_EL0(6), | |
2241 | AMU_AMEVTYPER0_EL0(7), | |
2242 | AMU_AMEVTYPER0_EL0(8), | |
2243 | AMU_AMEVTYPER0_EL0(9), | |
2244 | AMU_AMEVTYPER0_EL0(10), | |
2245 | AMU_AMEVTYPER0_EL0(11), | |
2246 | AMU_AMEVTYPER0_EL0(12), | |
2247 | AMU_AMEVTYPER0_EL0(13), | |
2248 | AMU_AMEVTYPER0_EL0(14), | |
2249 | AMU_AMEVTYPER0_EL0(15), | |
4fcdf106 IV |
2250 | AMU_AMEVCNTR1_EL0(0), |
2251 | AMU_AMEVCNTR1_EL0(1), | |
2252 | AMU_AMEVCNTR1_EL0(2), | |
2253 | AMU_AMEVCNTR1_EL0(3), | |
2254 | AMU_AMEVCNTR1_EL0(4), | |
2255 | AMU_AMEVCNTR1_EL0(5), | |
2256 | AMU_AMEVCNTR1_EL0(6), | |
2257 | AMU_AMEVCNTR1_EL0(7), | |
2258 | AMU_AMEVCNTR1_EL0(8), | |
2259 | AMU_AMEVCNTR1_EL0(9), | |
2260 | AMU_AMEVCNTR1_EL0(10), | |
2261 | AMU_AMEVCNTR1_EL0(11), | |
2262 | AMU_AMEVCNTR1_EL0(12), | |
2263 | AMU_AMEVCNTR1_EL0(13), | |
2264 | AMU_AMEVCNTR1_EL0(14), | |
2265 | AMU_AMEVCNTR1_EL0(15), | |
493cf9b7 VM |
2266 | AMU_AMEVTYPER1_EL0(0), |
2267 | AMU_AMEVTYPER1_EL0(1), | |
2268 | AMU_AMEVTYPER1_EL0(2), | |
2269 | AMU_AMEVTYPER1_EL0(3), | |
2270 | AMU_AMEVTYPER1_EL0(4), | |
2271 | AMU_AMEVTYPER1_EL0(5), | |
2272 | AMU_AMEVTYPER1_EL0(6), | |
2273 | AMU_AMEVTYPER1_EL0(7), | |
2274 | AMU_AMEVTYPER1_EL0(8), | |
2275 | AMU_AMEVTYPER1_EL0(9), | |
2276 | AMU_AMEVTYPER1_EL0(10), | |
2277 | AMU_AMEVTYPER1_EL0(11), | |
2278 | AMU_AMEVTYPER1_EL0(12), | |
2279 | AMU_AMEVTYPER1_EL0(13), | |
2280 | AMU_AMEVTYPER1_EL0(14), | |
2281 | AMU_AMEVTYPER1_EL0(15), | |
62a89c44 | 2282 | |
c605ee24 MZ |
2283 | { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, |
2284 | { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, | |
84135d3d AP |
2285 | { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, |
2286 | { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, | |
2287 | { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, | |
c9a3c58f | 2288 | |
051ff581 SZ |
2289 | /* PMEVCNTRn_EL0 */ |
2290 | PMU_PMEVCNTR_EL0(0), | |
2291 | PMU_PMEVCNTR_EL0(1), | |
2292 | PMU_PMEVCNTR_EL0(2), | |
2293 | PMU_PMEVCNTR_EL0(3), | |
2294 | PMU_PMEVCNTR_EL0(4), | |
2295 | PMU_PMEVCNTR_EL0(5), | |
2296 | PMU_PMEVCNTR_EL0(6), | |
2297 | PMU_PMEVCNTR_EL0(7), | |
2298 | PMU_PMEVCNTR_EL0(8), | |
2299 | PMU_PMEVCNTR_EL0(9), | |
2300 | PMU_PMEVCNTR_EL0(10), | |
2301 | PMU_PMEVCNTR_EL0(11), | |
2302 | PMU_PMEVCNTR_EL0(12), | |
2303 | PMU_PMEVCNTR_EL0(13), | |
2304 | PMU_PMEVCNTR_EL0(14), | |
2305 | PMU_PMEVCNTR_EL0(15), | |
2306 | PMU_PMEVCNTR_EL0(16), | |
2307 | PMU_PMEVCNTR_EL0(17), | |
2308 | PMU_PMEVCNTR_EL0(18), | |
2309 | PMU_PMEVCNTR_EL0(19), | |
2310 | PMU_PMEVCNTR_EL0(20), | |
2311 | PMU_PMEVCNTR_EL0(21), | |
2312 | PMU_PMEVCNTR_EL0(22), | |
2313 | PMU_PMEVCNTR_EL0(23), | |
2314 | PMU_PMEVCNTR_EL0(24), | |
2315 | PMU_PMEVCNTR_EL0(25), | |
2316 | PMU_PMEVCNTR_EL0(26), | |
2317 | PMU_PMEVCNTR_EL0(27), | |
2318 | PMU_PMEVCNTR_EL0(28), | |
2319 | PMU_PMEVCNTR_EL0(29), | |
2320 | PMU_PMEVCNTR_EL0(30), | |
9feb21ac SZ |
2321 | /* PMEVTYPERn_EL0 */ |
2322 | PMU_PMEVTYPER_EL0(0), | |
2323 | PMU_PMEVTYPER_EL0(1), | |
2324 | PMU_PMEVTYPER_EL0(2), | |
2325 | PMU_PMEVTYPER_EL0(3), | |
2326 | PMU_PMEVTYPER_EL0(4), | |
2327 | PMU_PMEVTYPER_EL0(5), | |
2328 | PMU_PMEVTYPER_EL0(6), | |
2329 | PMU_PMEVTYPER_EL0(7), | |
2330 | PMU_PMEVTYPER_EL0(8), | |
2331 | PMU_PMEVTYPER_EL0(9), | |
2332 | PMU_PMEVTYPER_EL0(10), | |
2333 | PMU_PMEVTYPER_EL0(11), | |
2334 | PMU_PMEVTYPER_EL0(12), | |
2335 | PMU_PMEVTYPER_EL0(13), | |
2336 | PMU_PMEVTYPER_EL0(14), | |
2337 | PMU_PMEVTYPER_EL0(15), | |
2338 | PMU_PMEVTYPER_EL0(16), | |
2339 | PMU_PMEVTYPER_EL0(17), | |
2340 | PMU_PMEVTYPER_EL0(18), | |
2341 | PMU_PMEVTYPER_EL0(19), | |
2342 | PMU_PMEVTYPER_EL0(20), | |
2343 | PMU_PMEVTYPER_EL0(21), | |
2344 | PMU_PMEVTYPER_EL0(22), | |
2345 | PMU_PMEVTYPER_EL0(23), | |
2346 | PMU_PMEVTYPER_EL0(24), | |
2347 | PMU_PMEVTYPER_EL0(25), | |
2348 | PMU_PMEVTYPER_EL0(26), | |
2349 | PMU_PMEVTYPER_EL0(27), | |
2350 | PMU_PMEVTYPER_EL0(28), | |
2351 | PMU_PMEVTYPER_EL0(29), | |
2352 | PMU_PMEVTYPER_EL0(30), | |
174ed3e4 MR |
2353 | /* |
2354 | * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero | |
9feb21ac SZ |
2355 | * in 32bit mode. Here we choose to reset it as zero for consistency. |
2356 | */ | |
9d2a55b4 | 2357 | { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, |
11663111 | 2358 | .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, |
051ff581 | 2359 | |
6ff9dc23 JL |
2360 | EL2_REG(VPIDR_EL2, access_rw, reset_unknown, 0), |
2361 | EL2_REG(VMPIDR_EL2, access_rw, reset_unknown, 0), | |
2362 | EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), | |
2363 | EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), | |
2364 | EL2_REG(HCR_EL2, access_rw, reset_val, 0), | |
2365 | EL2_REG(MDCR_EL2, access_rw, reset_val, 0), | |
75c76ab5 | 2366 | EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), |
6ff9dc23 JL |
2367 | EL2_REG(HSTR_EL2, access_rw, reset_val, 0), |
2368 | EL2_REG(HACR_EL2, access_rw, reset_val, 0), | |
2369 | ||
2370 | EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), | |
2371 | EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), | |
2372 | EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), | |
2373 | EL2_REG(VTTBR_EL2, access_rw, reset_val, 0), | |
2374 | EL2_REG(VTCR_EL2, access_rw, reset_val, 0), | |
2375 | ||
851050a5 | 2376 | { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, |
6ff9dc23 JL |
2377 | EL2_REG(SPSR_EL2, access_rw, reset_val, 0), |
2378 | EL2_REG(ELR_EL2, access_rw, reset_val, 0), | |
2379 | { SYS_DESC(SYS_SP_EL1), access_sp_el1}, | |
2380 | ||
851050a5 | 2381 | { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, |
6ff9dc23 JL |
2382 | EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), |
2383 | EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), | |
2384 | EL2_REG(ESR_EL2, access_rw, reset_val, 0), | |
c88b0936 | 2385 | { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, |
6ff9dc23 JL |
2386 | |
2387 | EL2_REG(FAR_EL2, access_rw, reset_val, 0), | |
2388 | EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), | |
2389 | ||
2390 | EL2_REG(MAIR_EL2, access_rw, reset_val, 0), | |
2391 | EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), | |
2392 | ||
2393 | EL2_REG(VBAR_EL2, access_rw, reset_val, 0), | |
2394 | EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), | |
2395 | { SYS_DESC(SYS_RMR_EL2), trap_undef }, | |
2396 | ||
2397 | EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), | |
2398 | EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), | |
2399 | ||
2400 | EL2_REG(CNTVOFF_EL2, access_rw, reset_val, 0), | |
2401 | EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), | |
2402 | ||
280b748e JL |
2403 | EL12_REG(SCTLR, access_vm_reg, reset_val, 0x00C50078), |
2404 | EL12_REG(CPACR, access_rw, reset_val, 0), | |
2405 | EL12_REG(TTBR0, access_vm_reg, reset_unknown, 0), | |
2406 | EL12_REG(TTBR1, access_vm_reg, reset_unknown, 0), | |
2407 | EL12_REG(TCR, access_vm_reg, reset_val, 0), | |
2408 | { SYS_DESC(SYS_SPSR_EL12), access_spsr}, | |
2409 | { SYS_DESC(SYS_ELR_EL12), access_elr}, | |
2410 | EL12_REG(AFSR0, access_vm_reg, reset_unknown, 0), | |
2411 | EL12_REG(AFSR1, access_vm_reg, reset_unknown, 0), | |
2412 | EL12_REG(ESR, access_vm_reg, reset_unknown, 0), | |
2413 | EL12_REG(FAR, access_vm_reg, reset_unknown, 0), | |
2414 | EL12_REG(MAIR, access_vm_reg, reset_unknown, 0), | |
2415 | EL12_REG(AMAIR, access_vm_reg, reset_amair_el1, 0), | |
2416 | EL12_REG(VBAR, access_rw, reset_val, 0), | |
2417 | EL12_REG(CONTEXTIDR, access_vm_reg, reset_val, 0), | |
2418 | EL12_REG(CNTKCTL, access_rw, reset_val, 0), | |
2419 | ||
6ff9dc23 | 2420 | EL2_REG(SP_EL2, NULL, reset_unknown, 0), |
62a89c44 MZ |
2421 | }; |
2422 | ||
47334146 JZ |
2423 | static const struct sys_reg_desc *first_idreg; |
2424 | ||
8c358b29 | 2425 | static bool trap_dbgdidr(struct kvm_vcpu *vcpu, |
3fec037d | 2426 | struct sys_reg_params *p, |
bdfb4b38 MZ |
2427 | const struct sys_reg_desc *r) |
2428 | { | |
2429 | if (p->is_write) { | |
2430 | return ignore_write(vcpu, p); | |
2431 | } else { | |
46823dd1 DM |
2432 | u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); |
2433 | u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); | |
55adc08d | 2434 | u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT); |
bdfb4b38 | 2435 | |
fcf37b38 MB |
2436 | p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) | |
2437 | (((dfr >> ID_AA64DFR0_EL1_BRPs_SHIFT) & 0xf) << 24) | | |
2438 | (((dfr >> ID_AA64DFR0_EL1_CTX_CMPs_SHIFT) & 0xf) << 20) | |
bea7e97f | 2439 | | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); |
bdfb4b38 MZ |
2440 | return true; |
2441 | } | |
2442 | } | |
2443 | ||
1da42c34 MZ |
2444 | /* |
2445 | * AArch32 debug register mappings | |
84e690bf AB |
2446 | * |
2447 | * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] | |
2448 | * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] | |
2449 | * | |
1da42c34 MZ |
2450 | * None of the other registers share their location, so treat them as |
2451 | * if they were 64bit. | |
84e690bf | 2452 | */ |
1da42c34 MZ |
2453 | #define DBG_BCR_BVR_WCR_WVR(n) \ |
2454 | /* DBGBVRn */ \ | |
2455 | { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ | |
2456 | /* DBGBCRn */ \ | |
2457 | { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ | |
2458 | /* DBGWVRn */ \ | |
2459 | { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ | |
2460 | /* DBGWCRn */ \ | |
84e690bf AB |
2461 | { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } |
2462 | ||
1da42c34 MZ |
2463 | #define DBGBXVR(n) \ |
2464 | { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } | |
bdfb4b38 MZ |
2465 | |
2466 | /* | |
2467 | * Trapped cp14 registers. We generally ignore most of the external | |
2468 | * debug, on the principle that they don't really make sense to a | |
84e690bf | 2469 | * guest. Revisit this one day, would this principle change. |
bdfb4b38 | 2470 | */ |
72564016 | 2471 | static const struct sys_reg_desc cp14_regs[] = { |
8c358b29 AE |
2472 | /* DBGDIDR */ |
2473 | { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, | |
bdfb4b38 MZ |
2474 | /* DBGDTRRXext */ |
2475 | { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, | |
2476 | ||
2477 | DBG_BCR_BVR_WCR_WVR(0), | |
2478 | /* DBGDSCRint */ | |
2479 | { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, | |
2480 | DBG_BCR_BVR_WCR_WVR(1), | |
2481 | /* DBGDCCINT */ | |
1da42c34 | 2482 | { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, |
bdfb4b38 | 2483 | /* DBGDSCRext */ |
1da42c34 | 2484 | { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, |
bdfb4b38 MZ |
2485 | DBG_BCR_BVR_WCR_WVR(2), |
2486 | /* DBGDTR[RT]Xint */ | |
2487 | { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, | |
2488 | /* DBGDTR[RT]Xext */ | |
2489 | { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, | |
2490 | DBG_BCR_BVR_WCR_WVR(3), | |
2491 | DBG_BCR_BVR_WCR_WVR(4), | |
2492 | DBG_BCR_BVR_WCR_WVR(5), | |
2493 | /* DBGWFAR */ | |
2494 | { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, | |
2495 | /* DBGOSECCR */ | |
2496 | { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, | |
2497 | DBG_BCR_BVR_WCR_WVR(6), | |
2498 | /* DBGVCR */ | |
1da42c34 | 2499 | { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, |
bdfb4b38 MZ |
2500 | DBG_BCR_BVR_WCR_WVR(7), |
2501 | DBG_BCR_BVR_WCR_WVR(8), | |
2502 | DBG_BCR_BVR_WCR_WVR(9), | |
2503 | DBG_BCR_BVR_WCR_WVR(10), | |
2504 | DBG_BCR_BVR_WCR_WVR(11), | |
2505 | DBG_BCR_BVR_WCR_WVR(12), | |
2506 | DBG_BCR_BVR_WCR_WVR(13), | |
2507 | DBG_BCR_BVR_WCR_WVR(14), | |
2508 | DBG_BCR_BVR_WCR_WVR(15), | |
2509 | ||
2510 | /* DBGDRAR (32bit) */ | |
2511 | { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, | |
2512 | ||
2513 | DBGBXVR(0), | |
2514 | /* DBGOSLAR */ | |
f24adc65 | 2515 | { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, |
bdfb4b38 MZ |
2516 | DBGBXVR(1), |
2517 | /* DBGOSLSR */ | |
d42e2671 | 2518 | { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, |
bdfb4b38 MZ |
2519 | DBGBXVR(2), |
2520 | DBGBXVR(3), | |
2521 | /* DBGOSDLR */ | |
2522 | { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, | |
2523 | DBGBXVR(4), | |
2524 | /* DBGPRCR */ | |
2525 | { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, | |
2526 | DBGBXVR(5), | |
2527 | DBGBXVR(6), | |
2528 | DBGBXVR(7), | |
2529 | DBGBXVR(8), | |
2530 | DBGBXVR(9), | |
2531 | DBGBXVR(10), | |
2532 | DBGBXVR(11), | |
2533 | DBGBXVR(12), | |
2534 | DBGBXVR(13), | |
2535 | DBGBXVR(14), | |
2536 | DBGBXVR(15), | |
2537 | ||
2538 | /* DBGDSAR (32bit) */ | |
2539 | { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, | |
2540 | ||
2541 | /* DBGDEVID2 */ | |
2542 | { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, | |
2543 | /* DBGDEVID1 */ | |
2544 | { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, | |
2545 | /* DBGDEVID */ | |
2546 | { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, | |
2547 | /* DBGCLAIMSET */ | |
2548 | { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, | |
2549 | /* DBGCLAIMCLR */ | |
2550 | { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, | |
2551 | /* DBGAUTHSTATUS */ | |
2552 | { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, | |
72564016 MZ |
2553 | }; |
2554 | ||
a9866ba0 MZ |
2555 | /* Trapped cp14 64bit registers */ |
2556 | static const struct sys_reg_desc cp14_64_regs[] = { | |
bdfb4b38 MZ |
2557 | /* DBGDRAR (64bit) */ |
2558 | { Op1( 0), CRm( 1), .access = trap_raz_wi }, | |
2559 | ||
2560 | /* DBGDSAR (64bit) */ | |
2561 | { Op1( 0), CRm( 2), .access = trap_raz_wi }, | |
a9866ba0 MZ |
2562 | }; |
2563 | ||
a9e192cd AE |
2564 | #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ |
2565 | AA32(_map), \ | |
2566 | Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ | |
2567 | .visibility = pmu_visibility | |
2568 | ||
051ff581 SZ |
2569 | /* Macro to expand the PMEVCNTRn register */ |
2570 | #define PMU_PMEVCNTR(n) \ | |
a9e192cd AE |
2571 | { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ |
2572 | (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ | |
2573 | .access = access_pmu_evcntr } | |
051ff581 | 2574 | |
9feb21ac SZ |
2575 | /* Macro to expand the PMEVTYPERn register */ |
2576 | #define PMU_PMEVTYPER(n) \ | |
a9e192cd AE |
2577 | { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ |
2578 | (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ | |
2579 | .access = access_pmu_evtyper } | |
4d44923b MZ |
2580 | /* |
2581 | * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, | |
2582 | * depending on the way they are accessed (as a 32bit or a 64bit | |
2583 | * register). | |
2584 | */ | |
62a89c44 | 2585 | static const struct sys_reg_desc cp15_regs[] = { |
f7f2b15c | 2586 | { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, |
b1ea1d76 MZ |
2587 | { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, |
2588 | /* ACTLR */ | |
2589 | { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, | |
2590 | /* ACTLR2 */ | |
2591 | { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, | |
2592 | { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, | |
2593 | { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, | |
2594 | /* TTBCR */ | |
2595 | { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, | |
2596 | /* TTBCR2 */ | |
2597 | { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, | |
2598 | { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, | |
2599 | /* DFSR */ | |
2600 | { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, | |
2601 | { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, | |
2602 | /* ADFSR */ | |
2603 | { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, | |
2604 | /* AIFSR */ | |
2605 | { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, | |
2606 | /* DFAR */ | |
2607 | { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, | |
2608 | /* IFAR */ | |
2609 | { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, | |
4d44923b | 2610 | |
62a89c44 MZ |
2611 | /* |
2612 | * DC{C,I,CI}SW operations: | |
2613 | */ | |
2614 | { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, | |
2615 | { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, | |
2616 | { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, | |
4d44923b | 2617 | |
7609c125 | 2618 | /* PMU */ |
a9e192cd AE |
2619 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, |
2620 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, | |
2621 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, | |
2622 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, | |
2623 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, | |
2624 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, | |
2625 | { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, | |
2626 | { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, | |
2627 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, | |
2628 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, | |
2629 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, | |
2630 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, | |
2631 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, | |
2632 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, | |
2633 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, | |
2634 | { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, | |
2635 | { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, | |
46081078 | 2636 | /* PMMIR */ |
a9e192cd | 2637 | { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, |
4d44923b | 2638 | |
b1ea1d76 MZ |
2639 | /* PRRR/MAIR0 */ |
2640 | { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, | |
2641 | /* NMRR/MAIR1 */ | |
2642 | { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, | |
2643 | /* AMAIR0 */ | |
2644 | { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, | |
2645 | /* AMAIR1 */ | |
2646 | { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, | |
db7dedd0 CD |
2647 | |
2648 | /* ICC_SRE */ | |
f7f6f2d9 | 2649 | { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, |
db7dedd0 | 2650 | |
b1ea1d76 | 2651 | { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, |
051ff581 | 2652 | |
84135d3d AP |
2653 | /* Arch Tmers */ |
2654 | { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, | |
2655 | { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, | |
eac137b4 | 2656 | |
051ff581 SZ |
2657 | /* PMEVCNTRn */ |
2658 | PMU_PMEVCNTR(0), | |
2659 | PMU_PMEVCNTR(1), | |
2660 | PMU_PMEVCNTR(2), | |
2661 | PMU_PMEVCNTR(3), | |
2662 | PMU_PMEVCNTR(4), | |
2663 | PMU_PMEVCNTR(5), | |
2664 | PMU_PMEVCNTR(6), | |
2665 | PMU_PMEVCNTR(7), | |
2666 | PMU_PMEVCNTR(8), | |
2667 | PMU_PMEVCNTR(9), | |
2668 | PMU_PMEVCNTR(10), | |
2669 | PMU_PMEVCNTR(11), | |
2670 | PMU_PMEVCNTR(12), | |
2671 | PMU_PMEVCNTR(13), | |
2672 | PMU_PMEVCNTR(14), | |
2673 | PMU_PMEVCNTR(15), | |
2674 | PMU_PMEVCNTR(16), | |
2675 | PMU_PMEVCNTR(17), | |
2676 | PMU_PMEVCNTR(18), | |
2677 | PMU_PMEVCNTR(19), | |
2678 | PMU_PMEVCNTR(20), | |
2679 | PMU_PMEVCNTR(21), | |
2680 | PMU_PMEVCNTR(22), | |
2681 | PMU_PMEVCNTR(23), | |
2682 | PMU_PMEVCNTR(24), | |
2683 | PMU_PMEVCNTR(25), | |
2684 | PMU_PMEVCNTR(26), | |
2685 | PMU_PMEVCNTR(27), | |
2686 | PMU_PMEVCNTR(28), | |
2687 | PMU_PMEVCNTR(29), | |
2688 | PMU_PMEVCNTR(30), | |
9feb21ac SZ |
2689 | /* PMEVTYPERn */ |
2690 | PMU_PMEVTYPER(0), | |
2691 | PMU_PMEVTYPER(1), | |
2692 | PMU_PMEVTYPER(2), | |
2693 | PMU_PMEVTYPER(3), | |
2694 | PMU_PMEVTYPER(4), | |
2695 | PMU_PMEVTYPER(5), | |
2696 | PMU_PMEVTYPER(6), | |
2697 | PMU_PMEVTYPER(7), | |
2698 | PMU_PMEVTYPER(8), | |
2699 | PMU_PMEVTYPER(9), | |
2700 | PMU_PMEVTYPER(10), | |
2701 | PMU_PMEVTYPER(11), | |
2702 | PMU_PMEVTYPER(12), | |
2703 | PMU_PMEVTYPER(13), | |
2704 | PMU_PMEVTYPER(14), | |
2705 | PMU_PMEVTYPER(15), | |
2706 | PMU_PMEVTYPER(16), | |
2707 | PMU_PMEVTYPER(17), | |
2708 | PMU_PMEVTYPER(18), | |
2709 | PMU_PMEVTYPER(19), | |
2710 | PMU_PMEVTYPER(20), | |
2711 | PMU_PMEVTYPER(21), | |
2712 | PMU_PMEVTYPER(22), | |
2713 | PMU_PMEVTYPER(23), | |
2714 | PMU_PMEVTYPER(24), | |
2715 | PMU_PMEVTYPER(25), | |
2716 | PMU_PMEVTYPER(26), | |
2717 | PMU_PMEVTYPER(27), | |
2718 | PMU_PMEVTYPER(28), | |
2719 | PMU_PMEVTYPER(29), | |
2720 | PMU_PMEVTYPER(30), | |
2721 | /* PMCCFILTR */ | |
a9e192cd | 2722 | { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, |
f7f2b15c AB |
2723 | |
2724 | { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, | |
2725 | { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, | |
bf48040c AO |
2726 | |
2727 | /* CCSIDR2 */ | |
2728 | { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, | |
2729 | ||
b1ea1d76 | 2730 | { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, |
a9866ba0 MZ |
2731 | }; |
2732 | ||
2733 | static const struct sys_reg_desc cp15_64_regs[] = { | |
b1ea1d76 | 2734 | { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, |
a9e192cd | 2735 | { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, |
03bd646d | 2736 | { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ |
c605ee24 | 2737 | { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, |
b1ea1d76 | 2738 | { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, |
03bd646d MZ |
2739 | { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ |
2740 | { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ | |
84135d3d | 2741 | { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, |
a6610435 | 2742 | { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, |
7c8c5e6a MZ |
2743 | }; |
2744 | ||
f1f0c0cf AE |
2745 | static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, |
2746 | bool is_32) | |
bb44a8db MZ |
2747 | { |
2748 | unsigned int i; | |
2749 | ||
2750 | for (i = 0; i < n; i++) { | |
2751 | if (!is_32 && table[i].reg && !table[i].reset) { | |
325031d4 | 2752 | kvm_err("sys_reg table %pS entry %d lacks reset\n", &table[i], i); |
f1f0c0cf | 2753 | return false; |
bb44a8db MZ |
2754 | } |
2755 | ||
2756 | if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { | |
325031d4 | 2757 | kvm_err("sys_reg table %pS entry %d out of order\n", &table[i - 1], i - 1); |
f1f0c0cf | 2758 | return false; |
bb44a8db MZ |
2759 | } |
2760 | } | |
2761 | ||
f1f0c0cf | 2762 | return true; |
bb44a8db MZ |
2763 | } |
2764 | ||
74cc7e0c | 2765 | int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) |
62a89c44 MZ |
2766 | { |
2767 | kvm_inject_undefined(vcpu); | |
2768 | return 1; | |
2769 | } | |
2770 | ||
e70b9522 MZ |
2771 | static void perform_access(struct kvm_vcpu *vcpu, |
2772 | struct sys_reg_params *params, | |
2773 | const struct sys_reg_desc *r) | |
2774 | { | |
599d79dc MZ |
2775 | trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); |
2776 | ||
7f34e409 | 2777 | /* Check for regs disabled by runtime config */ |
01fe5ace | 2778 | if (sysreg_hidden(vcpu, r)) { |
7f34e409 DM |
2779 | kvm_inject_undefined(vcpu); |
2780 | return; | |
2781 | } | |
2782 | ||
e70b9522 MZ |
2783 | /* |
2784 | * Not having an accessor means that we have configured a trap | |
2785 | * that we don't know how to handle. This certainly qualifies | |
2786 | * as a gross bug that should be fixed right away. | |
2787 | */ | |
2788 | BUG_ON(!r->access); | |
2789 | ||
2790 | /* Skip instruction if instructed so */ | |
2791 | if (likely(r->access(vcpu, params, r))) | |
cdb5e02e | 2792 | kvm_incr_pc(vcpu); |
e70b9522 MZ |
2793 | } |
2794 | ||
72564016 MZ |
2795 | /* |
2796 | * emulate_cp -- tries to match a sys_reg access in a handling table, and | |
2797 | * call the corresponding trap handler. | |
2798 | * | |
2799 | * @params: pointer to the descriptor of the access | |
2800 | * @table: array of trap descriptors | |
2801 | * @num: size of the trap descriptor array | |
2802 | * | |
001bb819 | 2803 | * Return true if the access has been handled, false if not. |
72564016 | 2804 | */ |
001bb819 OU |
2805 | static bool emulate_cp(struct kvm_vcpu *vcpu, |
2806 | struct sys_reg_params *params, | |
2807 | const struct sys_reg_desc *table, | |
2808 | size_t num) | |
62a89c44 | 2809 | { |
72564016 | 2810 | const struct sys_reg_desc *r; |
62a89c44 | 2811 | |
72564016 | 2812 | if (!table) |
001bb819 | 2813 | return false; /* Not handled */ |
62a89c44 | 2814 | |
62a89c44 | 2815 | r = find_reg(params, table, num); |
62a89c44 | 2816 | |
72564016 | 2817 | if (r) { |
e70b9522 | 2818 | perform_access(vcpu, params, r); |
001bb819 | 2819 | return true; |
72564016 MZ |
2820 | } |
2821 | ||
2822 | /* Not handled */ | |
001bb819 | 2823 | return false; |
72564016 MZ |
2824 | } |
2825 | ||
2826 | static void unhandled_cp_access(struct kvm_vcpu *vcpu, | |
2827 | struct sys_reg_params *params) | |
2828 | { | |
3a949f4c | 2829 | u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); |
40c4f8d2 | 2830 | int cp = -1; |
72564016 | 2831 | |
3a949f4c | 2832 | switch (esr_ec) { |
c6d01a94 MR |
2833 | case ESR_ELx_EC_CP15_32: |
2834 | case ESR_ELx_EC_CP15_64: | |
72564016 MZ |
2835 | cp = 15; |
2836 | break; | |
c6d01a94 MR |
2837 | case ESR_ELx_EC_CP14_MR: |
2838 | case ESR_ELx_EC_CP14_64: | |
72564016 MZ |
2839 | cp = 14; |
2840 | break; | |
2841 | default: | |
40c4f8d2 | 2842 | WARN_ON(1); |
62a89c44 MZ |
2843 | } |
2844 | ||
bf4b96bb MR |
2845 | print_sys_reg_msg(params, |
2846 | "Unsupported guest CP%d access at: %08lx [%08lx]\n", | |
2847 | cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); | |
62a89c44 MZ |
2848 | kvm_inject_undefined(vcpu); |
2849 | } | |
2850 | ||
2851 | /** | |
7769db90 | 2852 | * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access |
62a89c44 MZ |
2853 | * @vcpu: The VCPU pointer |
2854 | * @run: The kvm_run struct | |
2855 | */ | |
72564016 MZ |
2856 | static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, |
2857 | const struct sys_reg_desc *global, | |
dcaffa7b | 2858 | size_t nr_global) |
62a89c44 MZ |
2859 | { |
2860 | struct sys_reg_params params; | |
0b12620f | 2861 | u64 esr = kvm_vcpu_get_esr(vcpu); |
c667186f | 2862 | int Rt = kvm_vcpu_sys_get_rt(vcpu); |
3a949f4c | 2863 | int Rt2 = (esr >> 10) & 0x1f; |
62a89c44 | 2864 | |
3a949f4c GS |
2865 | params.CRm = (esr >> 1) & 0xf; |
2866 | params.is_write = ((esr & 1) == 0); | |
62a89c44 MZ |
2867 | |
2868 | params.Op0 = 0; | |
3a949f4c | 2869 | params.Op1 = (esr >> 16) & 0xf; |
62a89c44 MZ |
2870 | params.Op2 = 0; |
2871 | params.CRn = 0; | |
2872 | ||
2873 | /* | |
2ec5be3d | 2874 | * Make a 64-bit value out of Rt and Rt2. As we use the same trap |
62a89c44 MZ |
2875 | * backends between AArch32 and AArch64, we get away with it. |
2876 | */ | |
2877 | if (params.is_write) { | |
2ec5be3d PF |
2878 | params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; |
2879 | params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; | |
62a89c44 MZ |
2880 | } |
2881 | ||
b6b7a806 | 2882 | /* |
dcaffa7b | 2883 | * If the table contains a handler, handle the |
b6b7a806 MZ |
2884 | * potential register operation in the case of a read and return |
2885 | * with success. | |
2886 | */ | |
001bb819 | 2887 | if (emulate_cp(vcpu, ¶ms, global, nr_global)) { |
b6b7a806 MZ |
2888 | /* Split up the value between registers for the read side */ |
2889 | if (!params.is_write) { | |
2890 | vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); | |
2891 | vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); | |
2892 | } | |
62a89c44 | 2893 | |
b6b7a806 | 2894 | return 1; |
62a89c44 MZ |
2895 | } |
2896 | ||
b6b7a806 | 2897 | unhandled_cp_access(vcpu, ¶ms); |
62a89c44 MZ |
2898 | return 1; |
2899 | } | |
2900 | ||
e6519766 OU |
2901 | static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); |
2902 | ||
9369bc5c OU |
2903 | /* |
2904 | * The CP10 ID registers are architecturally mapped to AArch64 feature | |
2905 | * registers. Abuse that fact so we can rely on the AArch64 handler for accesses | |
2906 | * from AArch32. | |
2907 | */ | |
ee87a9bd | 2908 | static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) |
9369bc5c OU |
2909 | { |
2910 | u8 reg_id = (esr >> 10) & 0xf; | |
2911 | bool valid; | |
2912 | ||
2913 | params->is_write = ((esr & 1) == 0); | |
2914 | params->Op0 = 3; | |
2915 | params->Op1 = 0; | |
2916 | params->CRn = 0; | |
2917 | params->CRm = 3; | |
2918 | ||
2919 | /* CP10 ID registers are read-only */ | |
2920 | valid = !params->is_write; | |
2921 | ||
2922 | switch (reg_id) { | |
2923 | /* MVFR0 */ | |
2924 | case 0b0111: | |
2925 | params->Op2 = 0; | |
2926 | break; | |
2927 | /* MVFR1 */ | |
2928 | case 0b0110: | |
2929 | params->Op2 = 1; | |
2930 | break; | |
2931 | /* MVFR2 */ | |
2932 | case 0b0101: | |
2933 | params->Op2 = 2; | |
2934 | break; | |
2935 | default: | |
2936 | valid = false; | |
2937 | } | |
2938 | ||
2939 | if (valid) | |
2940 | return true; | |
2941 | ||
2942 | kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", | |
2943 | params->is_write ? "write" : "read", reg_id); | |
2944 | return false; | |
2945 | } | |
2946 | ||
2947 | /** | |
2948 | * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and | |
2949 | * VFP Register' from AArch32. | |
2950 | * @vcpu: The vCPU pointer | |
2951 | * | |
2952 | * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. | |
2953 | * Work out the correct AArch64 system register encoding and reroute to the | |
2954 | * AArch64 system register emulation. | |
2955 | */ | |
2956 | int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) | |
2957 | { | |
2958 | int Rt = kvm_vcpu_sys_get_rt(vcpu); | |
ee87a9bd | 2959 | u64 esr = kvm_vcpu_get_esr(vcpu); |
9369bc5c OU |
2960 | struct sys_reg_params params; |
2961 | ||
2962 | /* UNDEF on any unhandled register access */ | |
2963 | if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { | |
2964 | kvm_inject_undefined(vcpu); | |
2965 | return 1; | |
2966 | } | |
2967 | ||
2968 | if (emulate_sys_reg(vcpu, ¶ms)) | |
2969 | vcpu_set_reg(vcpu, Rt, params.regval); | |
2970 | ||
2971 | return 1; | |
2972 | } | |
2973 | ||
e6519766 OU |
2974 | /** |
2975 | * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where | |
2976 | * CRn=0, which corresponds to the AArch32 feature | |
2977 | * registers. | |
2978 | * @vcpu: the vCPU pointer | |
2979 | * @params: the system register access parameters. | |
2980 | * | |
2981 | * Our cp15 system register tables do not enumerate the AArch32 feature | |
2982 | * registers. Conveniently, our AArch64 table does, and the AArch32 system | |
2983 | * register encoding can be trivially remapped into the AArch64 for the feature | |
2984 | * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. | |
2985 | * | |
2986 | * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit | |
2987 | * System registers with (coproc=0b1111, CRn==c0)", read accesses from this | |
2988 | * range are either UNKNOWN or RES0. Rerouting remains architectural as we | |
2989 | * treat undefined registers in this range as RAZ. | |
2990 | */ | |
2991 | static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, | |
2992 | struct sys_reg_params *params) | |
2993 | { | |
2994 | int Rt = kvm_vcpu_sys_get_rt(vcpu); | |
2995 | ||
2996 | /* Treat impossible writes to RO registers as UNDEFINED */ | |
2997 | if (params->is_write) { | |
2998 | unhandled_cp_access(vcpu, params); | |
2999 | return 1; | |
3000 | } | |
3001 | ||
3002 | params->Op0 = 3; | |
3003 | ||
3004 | /* | |
3005 | * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. | |
3006 | * Avoid conflicting with future expansion of AArch64 feature registers | |
3007 | * and simply treat them as RAZ here. | |
3008 | */ | |
3009 | if (params->CRm > 3) | |
3010 | params->regval = 0; | |
3011 | else if (!emulate_sys_reg(vcpu, params)) | |
3012 | return 1; | |
3013 | ||
3014 | vcpu_set_reg(vcpu, Rt, params->regval); | |
3015 | return 1; | |
3016 | } | |
3017 | ||
62a89c44 | 3018 | /** |
7769db90 | 3019 | * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access |
62a89c44 MZ |
3020 | * @vcpu: The VCPU pointer |
3021 | * @run: The kvm_run struct | |
3022 | */ | |
72564016 | 3023 | static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, |
e6519766 | 3024 | struct sys_reg_params *params, |
72564016 | 3025 | const struct sys_reg_desc *global, |
dcaffa7b | 3026 | size_t nr_global) |
62a89c44 | 3027 | { |
c667186f | 3028 | int Rt = kvm_vcpu_sys_get_rt(vcpu); |
62a89c44 | 3029 | |
e6519766 | 3030 | params->regval = vcpu_get_reg(vcpu, Rt); |
62a89c44 | 3031 | |
e6519766 OU |
3032 | if (emulate_cp(vcpu, params, global, nr_global)) { |
3033 | if (!params->is_write) | |
3034 | vcpu_set_reg(vcpu, Rt, params->regval); | |
72564016 | 3035 | return 1; |
2ec5be3d | 3036 | } |
72564016 | 3037 | |
e6519766 | 3038 | unhandled_cp_access(vcpu, params); |
62a89c44 MZ |
3039 | return 1; |
3040 | } | |
3041 | ||
74cc7e0c | 3042 | int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) |
72564016 | 3043 | { |
dcaffa7b | 3044 | return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); |
72564016 MZ |
3045 | } |
3046 | ||
74cc7e0c | 3047 | int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) |
72564016 | 3048 | { |
e6519766 OU |
3049 | struct sys_reg_params params; |
3050 | ||
3051 | params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); | |
3052 | ||
3053 | /* | |
3054 | * Certain AArch32 ID registers are handled by rerouting to the AArch64 | |
3055 | * system register table. Registers in the ID range where CRm=0 are | |
3056 | * excluded from this scheme as they do not trivially map into AArch64 | |
3057 | * system register encodings. | |
3058 | */ | |
3059 | if (params.Op1 == 0 && params.CRn == 0 && params.CRm) | |
3060 | return kvm_emulate_cp15_id_reg(vcpu, ¶ms); | |
3061 | ||
3062 | return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); | |
72564016 MZ |
3063 | } |
3064 | ||
74cc7e0c | 3065 | int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) |
72564016 | 3066 | { |
dcaffa7b | 3067 | return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); |
72564016 MZ |
3068 | } |
3069 | ||
74cc7e0c | 3070 | int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) |
72564016 | 3071 | { |
e6519766 OU |
3072 | struct sys_reg_params params; |
3073 | ||
3074 | params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); | |
3075 | ||
3076 | return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); | |
72564016 MZ |
3077 | } |
3078 | ||
54ad68b7 MR |
3079 | static bool is_imp_def_sys_reg(struct sys_reg_params *params) |
3080 | { | |
3081 | // See ARM DDI 0487E.a, section D12.3.2 | |
3082 | return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; | |
3083 | } | |
3084 | ||
28eda7b5 OU |
3085 | /** |
3086 | * emulate_sys_reg - Emulate a guest access to an AArch64 system register | |
3087 | * @vcpu: The VCPU pointer | |
3088 | * @params: Decoded system register parameters | |
3089 | * | |
3090 | * Return: true if the system register access was successful, false otherwise. | |
3091 | */ | |
3092 | static bool emulate_sys_reg(struct kvm_vcpu *vcpu, | |
3fec037d | 3093 | struct sys_reg_params *params) |
7c8c5e6a | 3094 | { |
dcaffa7b | 3095 | const struct sys_reg_desc *r; |
7c8c5e6a | 3096 | |
dcaffa7b | 3097 | r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); |
7c8c5e6a MZ |
3098 | |
3099 | if (likely(r)) { | |
e70b9522 | 3100 | perform_access(vcpu, params, r); |
28eda7b5 OU |
3101 | return true; |
3102 | } | |
3103 | ||
3104 | if (is_imp_def_sys_reg(params)) { | |
54ad68b7 | 3105 | kvm_inject_undefined(vcpu); |
7c8c5e6a | 3106 | } else { |
bf4b96bb MR |
3107 | print_sys_reg_msg(params, |
3108 | "Unsupported guest sys_reg access at: %lx [%08lx]\n", | |
3109 | *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); | |
e70b9522 | 3110 | kvm_inject_undefined(vcpu); |
7c8c5e6a | 3111 | } |
28eda7b5 | 3112 | return false; |
7c8c5e6a MZ |
3113 | } |
3114 | ||
47334146 JZ |
3115 | static void kvm_reset_id_regs(struct kvm_vcpu *vcpu) |
3116 | { | |
3117 | const struct sys_reg_desc *idreg = first_idreg; | |
3118 | u32 id = reg_to_encoding(idreg); | |
3119 | struct kvm *kvm = vcpu->kvm; | |
3120 | ||
3121 | if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) | |
3122 | return; | |
3123 | ||
3124 | lockdep_assert_held(&kvm->arch.config_lock); | |
3125 | ||
3126 | /* Initialize all idregs */ | |
3127 | while (is_id_reg(id)) { | |
3128 | IDREG(kvm, id) = idreg->reset(vcpu, idreg); | |
3129 | ||
3130 | idreg++; | |
3131 | id = reg_to_encoding(idreg); | |
3132 | } | |
3133 | ||
3134 | set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); | |
3135 | } | |
3136 | ||
750ed566 JM |
3137 | /** |
3138 | * kvm_reset_sys_regs - sets system registers to reset value | |
3139 | * @vcpu: The VCPU pointer | |
3140 | * | |
3141 | * This function finds the right table above and sets the registers on the | |
3142 | * virtual CPU struct to their architecturally defined reset values. | |
3143 | */ | |
3144 | void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) | |
7c8c5e6a MZ |
3145 | { |
3146 | unsigned long i; | |
3147 | ||
47334146 JZ |
3148 | kvm_reset_id_regs(vcpu); |
3149 | ||
3150 | for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { | |
3151 | const struct sys_reg_desc *r = &sys_reg_descs[i]; | |
3152 | ||
3153 | if (is_id_reg(reg_to_encoding(r))) | |
3154 | continue; | |
3155 | ||
3156 | if (r->reset) | |
3157 | r->reset(vcpu, r); | |
3158 | } | |
7c8c5e6a MZ |
3159 | } |
3160 | ||
3161 | /** | |
3162 | * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access | |
3163 | * @vcpu: The VCPU pointer | |
7c8c5e6a | 3164 | */ |
74cc7e0c | 3165 | int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) |
7c8c5e6a MZ |
3166 | { |
3167 | struct sys_reg_params params; | |
3a949f4c | 3168 | unsigned long esr = kvm_vcpu_get_esr(vcpu); |
c667186f | 3169 | int Rt = kvm_vcpu_sys_get_rt(vcpu); |
7c8c5e6a | 3170 | |
eef8c85a AB |
3171 | trace_kvm_handle_sys_reg(esr); |
3172 | ||
f76f89e2 | 3173 | params = esr_sys64_to_params(esr); |
2ec5be3d | 3174 | params.regval = vcpu_get_reg(vcpu, Rt); |
7c8c5e6a | 3175 | |
28eda7b5 OU |
3176 | if (!emulate_sys_reg(vcpu, ¶ms)) |
3177 | return 1; | |
2ec5be3d PF |
3178 | |
3179 | if (!params.is_write) | |
3180 | vcpu_set_reg(vcpu, Rt, params.regval); | |
28eda7b5 | 3181 | return 1; |
7c8c5e6a MZ |
3182 | } |
3183 | ||
3184 | /****************************************************************************** | |
3185 | * Userspace API | |
3186 | *****************************************************************************/ | |
3187 | ||
3188 | static bool index_to_params(u64 id, struct sys_reg_params *params) | |
3189 | { | |
3190 | switch (id & KVM_REG_SIZE_MASK) { | |
3191 | case KVM_REG_SIZE_U64: | |
3192 | /* Any unused index bits means it's not valid. */ | |
3193 | if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | |
3194 | | KVM_REG_ARM_COPROC_MASK | |
3195 | | KVM_REG_ARM64_SYSREG_OP0_MASK | |
3196 | | KVM_REG_ARM64_SYSREG_OP1_MASK | |
3197 | | KVM_REG_ARM64_SYSREG_CRN_MASK | |
3198 | | KVM_REG_ARM64_SYSREG_CRM_MASK | |
3199 | | KVM_REG_ARM64_SYSREG_OP2_MASK)) | |
3200 | return false; | |
3201 | params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) | |
3202 | >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); | |
3203 | params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) | |
3204 | >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); | |
3205 | params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) | |
3206 | >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); | |
3207 | params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) | |
3208 | >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); | |
3209 | params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) | |
3210 | >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); | |
3211 | return true; | |
3212 | default: | |
3213 | return false; | |
3214 | } | |
3215 | } | |
3216 | ||
da8d120f MZ |
3217 | const struct sys_reg_desc *get_reg_by_id(u64 id, |
3218 | const struct sys_reg_desc table[], | |
3219 | unsigned int num) | |
4b927b94 | 3220 | { |
da8d120f MZ |
3221 | struct sys_reg_params params; |
3222 | ||
3223 | if (!index_to_params(id, ¶ms)) | |
4b927b94 VK |
3224 | return NULL; |
3225 | ||
da8d120f | 3226 | return find_reg(¶ms, table, num); |
4b927b94 VK |
3227 | } |
3228 | ||
7c8c5e6a | 3229 | /* Decode an index value, and find the sys_reg_desc entry. */ |
ba23aec9 MZ |
3230 | static const struct sys_reg_desc * |
3231 | id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, | |
3232 | const struct sys_reg_desc table[], unsigned int num) | |
3233 | ||
7c8c5e6a | 3234 | { |
dcaffa7b | 3235 | const struct sys_reg_desc *r; |
7c8c5e6a MZ |
3236 | |
3237 | /* We only do sys_reg for now. */ | |
3238 | if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) | |
3239 | return NULL; | |
3240 | ||
ba23aec9 | 3241 | r = get_reg_by_id(id, table, num); |
7c8c5e6a | 3242 | |
93390c0a | 3243 | /* Not saved in the sys_reg array and not otherwise accessible? */ |
ba23aec9 | 3244 | if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) |
7c8c5e6a MZ |
3245 | r = NULL; |
3246 | ||
3247 | return r; | |
3248 | } | |
3249 | ||
3250 | /* | |
3251 | * These are the invariant sys_reg registers: we let the guest see the | |
3252 | * host versions of these, so they're part of the guest state. | |
3253 | * | |
3254 | * A future CPU may provide a mechanism to present different values to | |
3255 | * the guest, or a future kvm may trap them. | |
3256 | */ | |
3257 | ||
3258 | #define FUNCTION_INVARIANT(reg) \ | |
d86cde6e | 3259 | static u64 get_##reg(struct kvm_vcpu *v, \ |
7c8c5e6a MZ |
3260 | const struct sys_reg_desc *r) \ |
3261 | { \ | |
1f3d8699 | 3262 | ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ |
d86cde6e | 3263 | return ((struct sys_reg_desc *)r)->val; \ |
7c8c5e6a MZ |
3264 | } |
3265 | ||
3266 | FUNCTION_INVARIANT(midr_el1) | |
7c8c5e6a | 3267 | FUNCTION_INVARIANT(revidr_el1) |
7c8c5e6a MZ |
3268 | FUNCTION_INVARIANT(aidr_el1) |
3269 | ||
d86cde6e | 3270 | static u64 get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) |
f7f2b15c AB |
3271 | { |
3272 | ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); | |
d86cde6e | 3273 | return ((struct sys_reg_desc *)r)->val; |
f7f2b15c AB |
3274 | } |
3275 | ||
7c8c5e6a | 3276 | /* ->val is filled in by kvm_sys_reg_table_init() */ |
8d20bd63 | 3277 | static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { |
0d449541 MR |
3278 | { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, |
3279 | { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, | |
0d449541 MR |
3280 | { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, |
3281 | { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, | |
7c8c5e6a MZ |
3282 | }; |
3283 | ||
5a420ed9 | 3284 | static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) |
7c8c5e6a | 3285 | { |
7c8c5e6a MZ |
3286 | const struct sys_reg_desc *r; |
3287 | ||
da8d120f MZ |
3288 | r = get_reg_by_id(id, invariant_sys_regs, |
3289 | ARRAY_SIZE(invariant_sys_regs)); | |
7c8c5e6a MZ |
3290 | if (!r) |
3291 | return -ENOENT; | |
3292 | ||
5a420ed9 | 3293 | return put_user(r->val, uaddr); |
7c8c5e6a MZ |
3294 | } |
3295 | ||
5a420ed9 | 3296 | static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) |
7c8c5e6a | 3297 | { |
7c8c5e6a | 3298 | const struct sys_reg_desc *r; |
5a420ed9 | 3299 | u64 val; |
7c8c5e6a | 3300 | |
da8d120f MZ |
3301 | r = get_reg_by_id(id, invariant_sys_regs, |
3302 | ARRAY_SIZE(invariant_sys_regs)); | |
7c8c5e6a MZ |
3303 | if (!r) |
3304 | return -ENOENT; | |
3305 | ||
5a420ed9 MZ |
3306 | if (get_user(val, uaddr)) |
3307 | return -EFAULT; | |
7c8c5e6a MZ |
3308 | |
3309 | /* This is what we mean by invariant: you can't change it. */ | |
3310 | if (r->val != val) | |
3311 | return -EINVAL; | |
3312 | ||
3313 | return 0; | |
3314 | } | |
3315 | ||
7af0c253 | 3316 | static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) |
7c8c5e6a MZ |
3317 | { |
3318 | u32 val; | |
3319 | u32 __user *uval = uaddr; | |
3320 | ||
3321 | /* Fail if we have unknown bits set. */ | |
3322 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK | |
3323 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) | |
3324 | return -ENOENT; | |
3325 | ||
3326 | switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { | |
3327 | case KVM_REG_ARM_DEMUX_ID_CCSIDR: | |
3328 | if (KVM_REG_SIZE(id) != 4) | |
3329 | return -ENOENT; | |
3330 | val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) | |
3331 | >> KVM_REG_ARM_DEMUX_VAL_SHIFT; | |
7af0c253 | 3332 | if (val >= CSSELR_MAX) |
7c8c5e6a MZ |
3333 | return -ENOENT; |
3334 | ||
7af0c253 | 3335 | return put_user(get_ccsidr(vcpu, val), uval); |
7c8c5e6a MZ |
3336 | default: |
3337 | return -ENOENT; | |
3338 | } | |
3339 | } | |
3340 | ||
7af0c253 | 3341 | static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) |
7c8c5e6a MZ |
3342 | { |
3343 | u32 val, newval; | |
3344 | u32 __user *uval = uaddr; | |
3345 | ||
3346 | /* Fail if we have unknown bits set. */ | |
3347 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK | |
3348 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) | |
3349 | return -ENOENT; | |
3350 | ||
3351 | switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { | |
3352 | case KVM_REG_ARM_DEMUX_ID_CCSIDR: | |
3353 | if (KVM_REG_SIZE(id) != 4) | |
3354 | return -ENOENT; | |
3355 | val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) | |
3356 | >> KVM_REG_ARM_DEMUX_VAL_SHIFT; | |
7af0c253 | 3357 | if (val >= CSSELR_MAX) |
7c8c5e6a MZ |
3358 | return -ENOENT; |
3359 | ||
3360 | if (get_user(newval, uval)) | |
3361 | return -EFAULT; | |
3362 | ||
7af0c253 | 3363 | return set_ccsidr(vcpu, val, newval); |
7c8c5e6a MZ |
3364 | default: |
3365 | return -ENOENT; | |
3366 | } | |
3367 | } | |
3368 | ||
ba23aec9 MZ |
3369 | int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, |
3370 | const struct sys_reg_desc table[], unsigned int num) | |
7c8c5e6a | 3371 | { |
978ceeb3 | 3372 | u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; |
7c8c5e6a | 3373 | const struct sys_reg_desc *r; |
978ceeb3 MZ |
3374 | u64 val; |
3375 | int ret; | |
ba23aec9 MZ |
3376 | |
3377 | r = id_to_sys_reg_desc(vcpu, reg->id, table, num); | |
e6b367db | 3378 | if (!r || sysreg_hidden_user(vcpu, r)) |
ba23aec9 MZ |
3379 | return -ENOENT; |
3380 | ||
978ceeb3 MZ |
3381 | if (r->get_user) { |
3382 | ret = (r->get_user)(vcpu, r, &val); | |
3383 | } else { | |
3384 | val = __vcpu_sys_reg(vcpu, r->reg); | |
3385 | ret = 0; | |
3386 | } | |
3387 | ||
3388 | if (!ret) | |
3389 | ret = put_user(val, uaddr); | |
ba23aec9 | 3390 | |
978ceeb3 | 3391 | return ret; |
ba23aec9 MZ |
3392 | } |
3393 | ||
3394 | int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) | |
3395 | { | |
7c8c5e6a | 3396 | void __user *uaddr = (void __user *)(unsigned long)reg->addr; |
1deeffb5 | 3397 | int err; |
7c8c5e6a MZ |
3398 | |
3399 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) | |
7af0c253 | 3400 | return demux_c15_get(vcpu, reg->id, uaddr); |
7c8c5e6a | 3401 | |
1deeffb5 MZ |
3402 | err = get_invariant_sys_reg(reg->id, uaddr); |
3403 | if (err != -ENOENT) | |
3404 | return err; | |
7c8c5e6a | 3405 | |
ba23aec9 MZ |
3406 | return kvm_sys_reg_get_user(vcpu, reg, |
3407 | sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); | |
3408 | } | |
7c8c5e6a | 3409 | |
ba23aec9 MZ |
3410 | int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, |
3411 | const struct sys_reg_desc table[], unsigned int num) | |
3412 | { | |
978ceeb3 | 3413 | u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; |
ba23aec9 | 3414 | const struct sys_reg_desc *r; |
978ceeb3 MZ |
3415 | u64 val; |
3416 | int ret; | |
3417 | ||
3418 | if (get_user(val, uaddr)) | |
3419 | return -EFAULT; | |
ba23aec9 MZ |
3420 | |
3421 | r = id_to_sys_reg_desc(vcpu, reg->id, table, num); | |
e6b367db | 3422 | if (!r || sysreg_hidden_user(vcpu, r)) |
7f34e409 DM |
3423 | return -ENOENT; |
3424 | ||
4de06e4c OU |
3425 | if (sysreg_user_write_ignore(vcpu, r)) |
3426 | return 0; | |
3427 | ||
978ceeb3 MZ |
3428 | if (r->set_user) { |
3429 | ret = (r->set_user)(vcpu, r, val); | |
3430 | } else { | |
3431 | __vcpu_sys_reg(vcpu, r->reg) = val; | |
3432 | ret = 0; | |
3433 | } | |
84e690bf | 3434 | |
978ceeb3 | 3435 | return ret; |
7c8c5e6a MZ |
3436 | } |
3437 | ||
3438 | int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) | |
3439 | { | |
7c8c5e6a | 3440 | void __user *uaddr = (void __user *)(unsigned long)reg->addr; |
1deeffb5 | 3441 | int err; |
7c8c5e6a MZ |
3442 | |
3443 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) | |
7af0c253 | 3444 | return demux_c15_set(vcpu, reg->id, uaddr); |
7c8c5e6a | 3445 | |
1deeffb5 MZ |
3446 | err = set_invariant_sys_reg(reg->id, uaddr); |
3447 | if (err != -ENOENT) | |
3448 | return err; | |
84e690bf | 3449 | |
ba23aec9 MZ |
3450 | return kvm_sys_reg_set_user(vcpu, reg, |
3451 | sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); | |
7c8c5e6a MZ |
3452 | } |
3453 | ||
3454 | static unsigned int num_demux_regs(void) | |
3455 | { | |
7af0c253 | 3456 | return CSSELR_MAX; |
7c8c5e6a MZ |
3457 | } |
3458 | ||
3459 | static int write_demux_regids(u64 __user *uindices) | |
3460 | { | |
efd48cea | 3461 | u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; |
7c8c5e6a MZ |
3462 | unsigned int i; |
3463 | ||
3464 | val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; | |
3465 | for (i = 0; i < CSSELR_MAX; i++) { | |
7c8c5e6a MZ |
3466 | if (put_user(val | i, uindices)) |
3467 | return -EFAULT; | |
3468 | uindices++; | |
3469 | } | |
3470 | return 0; | |
3471 | } | |
3472 | ||
3473 | static u64 sys_reg_to_index(const struct sys_reg_desc *reg) | |
3474 | { | |
3475 | return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | | |
3476 | KVM_REG_ARM64_SYSREG | | |
3477 | (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | | |
3478 | (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | | |
3479 | (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | | |
3480 | (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | | |
3481 | (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); | |
3482 | } | |
3483 | ||
3484 | static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) | |
3485 | { | |
3486 | if (!*uind) | |
3487 | return true; | |
3488 | ||
3489 | if (put_user(sys_reg_to_index(reg), *uind)) | |
3490 | return false; | |
3491 | ||
3492 | (*uind)++; | |
3493 | return true; | |
3494 | } | |
3495 | ||
7f34e409 DM |
3496 | static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, |
3497 | const struct sys_reg_desc *rd, | |
93390c0a DM |
3498 | u64 __user **uind, |
3499 | unsigned int *total) | |
3500 | { | |
3501 | /* | |
3502 | * Ignore registers we trap but don't save, | |
3503 | * and for which no custom user accessor is provided. | |
3504 | */ | |
3505 | if (!(rd->reg || rd->get_user)) | |
3506 | return 0; | |
3507 | ||
e6b367db | 3508 | if (sysreg_hidden_user(vcpu, rd)) |
7f34e409 DM |
3509 | return 0; |
3510 | ||
93390c0a DM |
3511 | if (!copy_reg_to_user(rd, uind)) |
3512 | return -EFAULT; | |
3513 | ||
3514 | (*total)++; | |
3515 | return 0; | |
3516 | } | |
3517 | ||
7c8c5e6a MZ |
3518 | /* Assumed ordered tables, see kvm_sys_reg_table_init. */ |
3519 | static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) | |
3520 | { | |
dcaffa7b | 3521 | const struct sys_reg_desc *i2, *end2; |
7c8c5e6a | 3522 | unsigned int total = 0; |
93390c0a | 3523 | int err; |
7c8c5e6a | 3524 | |
7c8c5e6a MZ |
3525 | i2 = sys_reg_descs; |
3526 | end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); | |
3527 | ||
dcaffa7b JM |
3528 | while (i2 != end2) { |
3529 | err = walk_one_sys_reg(vcpu, i2++, &uind, &total); | |
93390c0a DM |
3530 | if (err) |
3531 | return err; | |
7c8c5e6a MZ |
3532 | } |
3533 | return total; | |
3534 | } | |
3535 | ||
3536 | unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) | |
3537 | { | |
3538 | return ARRAY_SIZE(invariant_sys_regs) | |
3539 | + num_demux_regs() | |
3540 | + walk_sys_regs(vcpu, (u64 __user *)NULL); | |
3541 | } | |
3542 | ||
3543 | int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) | |
3544 | { | |
3545 | unsigned int i; | |
3546 | int err; | |
3547 | ||
3548 | /* Then give them all the invariant registers' indices. */ | |
3549 | for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { | |
3550 | if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) | |
3551 | return -EFAULT; | |
3552 | uindices++; | |
3553 | } | |
3554 | ||
3555 | err = walk_sys_regs(vcpu, uindices); | |
3556 | if (err < 0) | |
3557 | return err; | |
3558 | uindices += err; | |
3559 | ||
3560 | return write_demux_regids(uindices); | |
3561 | } | |
3562 | ||
8d20bd63 | 3563 | int __init kvm_sys_reg_table_init(void) |
7c8c5e6a | 3564 | { |
47334146 | 3565 | struct sys_reg_params params; |
f1f0c0cf | 3566 | bool valid = true; |
7c8c5e6a | 3567 | unsigned int i; |
7c8c5e6a MZ |
3568 | |
3569 | /* Make sure tables are unique and in order. */ | |
f1f0c0cf AE |
3570 | valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); |
3571 | valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); | |
3572 | valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); | |
3573 | valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); | |
3574 | valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); | |
3575 | valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); | |
3576 | ||
3577 | if (!valid) | |
3578 | return -EINVAL; | |
7c8c5e6a MZ |
3579 | |
3580 | /* We abuse the reset function to overwrite the table itself. */ | |
3581 | for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) | |
3582 | invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); | |
3583 | ||
47334146 JZ |
3584 | /* Find the first idreg (SYS_ID_PFR0_EL1) in sys_reg_descs. */ |
3585 | params = encoding_to_params(SYS_ID_PFR0_EL1); | |
3586 | first_idreg = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); | |
3587 | if (!first_idreg) | |
3588 | return -EINVAL; | |
3589 | ||
f1f0c0cf | 3590 | return 0; |
7c8c5e6a | 3591 | } |