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KVM: arm64: Refactor vcpu_{read,write}_sys_reg
[linux-2.6-block.git] / arch / arm64 / kvm / sys_regs.c
CommitLineData
caab277b 1// SPDX-License-Identifier: GPL-2.0-only
7c8c5e6a
MZ		 2/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
7c8c5e6a
MZ		 10 */
11
623eefa8 12#include <linux/bsearch.h>
7c8c5e6a 13#include <linux/kvm_host.h>
c6d01a94 14#include <linux/mm.h>
07d79fe7 15#include <linux/printk.h>
7c8c5e6a 16#include <linux/uaccess.h>
c6d01a94 17
7c8c5e6a
MZ		 18#include <asm/cacheflush.h>
19#include <asm/cputype.h>
0c557ed4 20#include <asm/debug-monitors.h>
c6d01a94
MR		 21#include <asm/esr.h>
22#include <asm/kvm_arm.h>
23#include <asm/kvm_coproc.h>
24#include <asm/kvm_emulate.h>
d47533da 25#include <asm/kvm_hyp.h>
c6d01a94 26#include <asm/kvm_mmu.h>
ab946834 27#include <asm/perf_event.h>
1f3d8699 28#include <asm/sysreg.h>
c6d01a94 29
7c8c5e6a
MZ		 30#include <trace/events/kvm.h>
31
32#include "sys_regs.h"
33
eef8c85a
AB		 34#include "trace.h"
35
7c8c5e6a 36/*
656012c7 37 * All of this file is extremely similar to the ARM coproc.c, but the
7c8c5e6a
MZ		 38 * types are different. My gut feeling is that it should be pretty
39 * easy to merge, but that would be an ABI breakage -- again. VFP
40 * would also need to be abstracted.
62a89c44
MZ		 41 *
42 * For AArch32, we only take care of what is being trapped. Anything
43 * that has to do with init and userspace access has to go via the
44 * 64bit interface.
7c8c5e6a
MZ		 45 */
46
7b5b4df1 47static bool read_from_write_only(struct kvm_vcpu *vcpu,
e7f1d1ee
MZ		 48 struct sys_reg_params *params,
49 const struct sys_reg_desc *r)
7b5b4df1
MZ		 50{
51 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
52 print_sys_reg_instr(params);
53 kvm_inject_undefined(vcpu);
54 return false;
55}
56
7b1dba1f
MZ		 57static bool write_to_read_only(struct kvm_vcpu *vcpu,
58 struct sys_reg_params *params,
59 const struct sys_reg_desc *r)
60{
61 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
62 print_sys_reg_instr(params);
63 kvm_inject_undefined(vcpu);
64 return false;
65}
66
7ea90bdd 67static bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
d47533da 68{
d47533da
CD		 69 /*
70 * System registers listed in the switch are not saved on every
71 * exit from the guest but are only saved on vcpu_put.
fc7563b3
CD		 72 *
73 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
74 * should never be listed below, because the guest cannot modify its
75 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
76 * thread when emulating cross-VCPU communication.
d47533da
CD		 77 */
78 switch (reg) {
7ea90bdd
MZ		 79 case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break;
80 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
81 case ACTLR_EL1: *val = read_sysreg_s(SYS_ACTLR_EL1); break;
82 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
83 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
84 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
85 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
86 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
87 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
88 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
89 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
90 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
91 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
92 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
93 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
94 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
95 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
96 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
97 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
98 case PAR_EL1: *val = read_sysreg_s(SYS_PAR_EL1); break;
99 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
100 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
101 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
102 default: return false;
d47533da
CD		 103 }
104
7ea90bdd 105 return true;
d47533da
CD		 106}
107
7ea90bdd 108static bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
d47533da 109{
d47533da
CD		 110 /*
111 * System registers listed in the switch are not restored on every
112 * entry to the guest but are only restored on vcpu_load.
fc7563b3
CD		 113 *
114 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
656012c7
FT		 115 * should never be listed below, because the MPIDR should only be set
116 * once, before running the VCPU, and never changed later.
d47533da
CD		 117 */
118 switch (reg) {
7ea90bdd
MZ		 119 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break;
120 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
121 case ACTLR_EL1: write_sysreg_s(val, SYS_ACTLR_EL1); break;
122 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
123 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
124 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
125 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
126 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
127 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
128 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
129 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
130 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
131 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
132 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
133 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
134 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
135 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
136 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
137 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
138 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
139 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
140 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
141 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
142 default: return false;
d47533da
CD		 143 }
144
7ea90bdd
MZ		 145 return true;
146}
147
148u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
149{
150 u64 val = 0x8badf00d8badf00d;
151
152 if (vcpu->arch.sysregs_loaded_on_cpu &&
153 __vcpu_read_sys_reg_from_cpu(reg, &val))
154 return val;
155
156 return __vcpu_sys_reg(vcpu, reg);
157}
158
159void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
160{
161 if (vcpu->arch.sysregs_loaded_on_cpu &&
162 __vcpu_write_sys_reg_to_cpu(val, reg))
163 return;
164
d47533da
CD		 165 __vcpu_sys_reg(vcpu, reg) = val;
166}
167
7c8c5e6a
MZ		 168/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
169static u32 cache_levels;
170
171/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
172#define CSSELR_MAX 12
173
174/* Which cache CCSIDR represents depends on CSSELR value. */
175static u32 get_ccsidr(u32 csselr)
176{
177 u32 ccsidr;
178
179 /* Make sure noone else changes CSSELR during this! */
180 local_irq_disable();
1f3d8699 181 write_sysreg(csselr, csselr_el1);
7c8c5e6a 182 isb();
1f3d8699 183 ccsidr = read_sysreg(ccsidr_el1);
7c8c5e6a
MZ		 184 local_irq_enable();
185
186 return ccsidr;
187}
188
3c1e7165
MZ		 189/*
190 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
191 */
7c8c5e6a 192static bool access_dcsw(struct kvm_vcpu *vcpu,
3fec037d 193 struct sys_reg_params *p,
7c8c5e6a
MZ		 194 const struct sys_reg_desc *r)
195{
7c8c5e6a 196 if (!p->is_write)
e7f1d1ee 197 return read_from_write_only(vcpu, p, r);
7c8c5e6a 198
09605e94
MZ		 199 /*
200 * Only track S/W ops if we don't have FWB. It still indicates
201 * that the guest is a bit broken (S/W operations should only
202 * be done by firmware, knowing that there is only a single
203 * CPU left in the system, and certainly not from non-secure
204 * software).
205 */
206 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
207 kvm_set_way_flush(vcpu);
208
7c8c5e6a
MZ		 209 return true;
210}
211
4d44923b
MZ		 212/*
213 * Generic accessor for VM registers. Only called as long as HCR_TVM
3c1e7165
MZ		 214 * is set. If the guest enables the MMU, we stop trapping the VM
215 * sys_regs and leave it in complete control of the caches.
4d44923b
MZ		 216 */
217static bool access_vm_reg(struct kvm_vcpu *vcpu,
3fec037d 218 struct sys_reg_params *p,
4d44923b
MZ		 219 const struct sys_reg_desc *r)
220{
3c1e7165 221 bool was_enabled = vcpu_has_cache_enabled(vcpu);
52f6c4f0
CD		 222 u64 val;
223 int reg = r->reg;
4d44923b
MZ		 224
225 BUG_ON(!p->is_write);
226
52f6c4f0
CD		 227 /* See the 32bit mapping in kvm_host.h */
228 if (p->is_aarch32)
229 reg = r->reg / 2;
230
231 if (!p->is_aarch32 || !p->is_32bit) {
232 val = p->regval;
dedf97e8 233 } else {
8d404c4c 234 val = vcpu_read_sys_reg(vcpu, reg);
52f6c4f0
CD		 235 if (r->reg % 2)
236 val = (p->regval << 32) | (u64)lower_32_bits(val);
237 else
238 val = ((u64)upper_32_bits(val) << 32) |
239 lower_32_bits(p->regval);
dedf97e8 240 }
8d404c4c 241 vcpu_write_sys_reg(vcpu, val, reg);
f0a3eaff 242
3c1e7165 243 kvm_toggle_cache(vcpu, was_enabled);
4d44923b
MZ		 244 return true;
245}
246
6d52f35a
AP		 247/*
248 * Trap handler for the GICv3 SGI generation system register.
249 * Forward the request to the VGIC emulation.
250 * The cp15_64 code makes sure this automatically works
251 * for both AArch64 and AArch32 accesses.
252 */
253static bool access_gic_sgi(struct kvm_vcpu *vcpu,
3fec037d 254 struct sys_reg_params *p,
6d52f35a
AP		 255 const struct sys_reg_desc *r)
256{
03bd646d
MZ		 257 bool g1;
258
6d52f35a 259 if (!p->is_write)
e7f1d1ee 260 return read_from_write_only(vcpu, p, r);
6d52f35a 261
03bd646d
MZ		 262 /*
263 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
264 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
265 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
266 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
267 * group.
268 */
269 if (p->is_aarch32) {
270 switch (p->Op1) {
271 default: /* Keep GCC quiet */
272 case 0: /* ICC_SGI1R */
273 g1 = true;
274 break;
275 case 1: /* ICC_ASGI1R */
276 case 2: /* ICC_SGI0R */
277 g1 = false;
278 break;
279 }
280 } else {
281 switch (p->Op2) {
282 default: /* Keep GCC quiet */
283 case 5: /* ICC_SGI1R_EL1 */
284 g1 = true;
285 break;
286 case 6: /* ICC_ASGI1R_EL1 */
287 case 7: /* ICC_SGI0R_EL1 */
288 g1 = false;
289 break;
290 }
291 }
292
293 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
6d52f35a
AP		 294
295 return true;
296}
297
b34f2bcb
MZ		 298static bool access_gic_sre(struct kvm_vcpu *vcpu,
299 struct sys_reg_params *p,
300 const struct sys_reg_desc *r)
301{
302 if (p->is_write)
303 return ignore_write(vcpu, p);
304
305 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
306 return true;
307}
308
7609c125 309static bool trap_raz_wi(struct kvm_vcpu *vcpu,
3fec037d 310 struct sys_reg_params *p,
7609c125 311 const struct sys_reg_desc *r)
7c8c5e6a
MZ		 312{
313 if (p->is_write)
314 return ignore_write(vcpu, p);
315 else
316 return read_zero(vcpu, p);
317}
318
22925521
MZ		 319/*
320 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
321 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
322 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
323 * treat it separately.
324 */
325static bool trap_loregion(struct kvm_vcpu *vcpu,
326 struct sys_reg_params *p,
327 const struct sys_reg_desc *r)
cc33c4e2 328{
22925521
MZ		 329 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
330 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
331 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
332
333 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
334 kvm_inject_undefined(vcpu);
335 return false;
336 }
337
338 if (p->is_write && sr == SYS_LORID_EL1)
339 return write_to_read_only(vcpu, p, r);
340
341 return trap_raz_wi(vcpu, p, r);
cc33c4e2
MR		 342}
343
0c557ed4 344static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
3fec037d 345 struct sys_reg_params *p,
0c557ed4
MZ		 346 const struct sys_reg_desc *r)
347{
348 if (p->is_write) {
349 return ignore_write(vcpu, p);
350 } else {
2ec5be3d 351 p->regval = (1 << 3);
0c557ed4
MZ		 352 return true;
353 }
354}
355
356static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
3fec037d 357 struct sys_reg_params *p,
0c557ed4
MZ		 358 const struct sys_reg_desc *r)
359{
360 if (p->is_write) {
361 return ignore_write(vcpu, p);
362 } else {
1f3d8699 363 p->regval = read_sysreg(dbgauthstatus_el1);
0c557ed4
MZ		 364 return true;
365 }
366}
367
368/*
369 * We want to avoid world-switching all the DBG registers all the
370 * time:
371 *
372 * - If we've touched any debug register, it is likely that we're
373 * going to touch more of them. It then makes sense to disable the
374 * traps and start doing the save/restore dance
375 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
376 * then mandatory to save/restore the registers, as the guest
377 * depends on them.
378 *
379 * For this, we use a DIRTY bit, indicating the guest has modified the
380 * debug registers, used as follow:
381 *
382 * On guest entry:
383 * - If the dirty bit is set (because we're coming back from trapping),
384 * disable the traps, save host registers, restore guest registers.
385 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
386 * set the dirty bit, disable the traps, save host registers,
387 * restore guest registers.
388 * - Otherwise, enable the traps
389 *
390 * On guest exit:
391 * - If the dirty bit is set, save guest registers, restore host
392 * registers and clear the dirty bit. This ensure that the host can
393 * now use the debug registers.
394 */
395static bool trap_debug_regs(struct kvm_vcpu *vcpu,
3fec037d 396 struct sys_reg_params *p,
0c557ed4
MZ		 397 const struct sys_reg_desc *r)
398{
399 if (p->is_write) {
8d404c4c 400 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
fa89d31c 401 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
0c557ed4 402 } else {
8d404c4c 403 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
0c557ed4
MZ		 404 }
405
2ec5be3d 406 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
eef8c85a 407
0c557ed4
MZ		 408 return true;
409}
410
84e690bf
AB		 411/*
412 * reg_to_dbg/dbg_to_reg
413 *
414 * A 32 bit write to a debug register leave top bits alone
415 * A 32 bit read from a debug register only returns the bottom bits
416 *
417 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
418 * hyp.S code switches between host and guest values in future.
419 */
281243cb
MZ		 420static void reg_to_dbg(struct kvm_vcpu *vcpu,
421 struct sys_reg_params *p,
422 u64 *dbg_reg)
84e690bf 423{
2ec5be3d 424 u64 val = p->regval;
84e690bf
AB		 425
426 if (p->is_32bit) {
427 val &= 0xffffffffUL;
428 val |= ((*dbg_reg >> 32) << 32);
429 }
430
431 *dbg_reg = val;
fa89d31c 432 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
84e690bf
AB		 433}
434
281243cb
MZ		 435static void dbg_to_reg(struct kvm_vcpu *vcpu,
436 struct sys_reg_params *p,
437 u64 *dbg_reg)
84e690bf 438{
2ec5be3d 439 p->regval = *dbg_reg;
84e690bf 440 if (p->is_32bit)
2ec5be3d 441 p->regval &= 0xffffffffUL;
84e690bf
AB		 442}
443
281243cb
MZ		 444static bool trap_bvr(struct kvm_vcpu *vcpu,
445 struct sys_reg_params *p,
446 const struct sys_reg_desc *rd)
84e690bf
AB		 447{
448 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
449
450 if (p->is_write)
451 reg_to_dbg(vcpu, p, dbg_reg);
452 else
453 dbg_to_reg(vcpu, p, dbg_reg);
454
eef8c85a
AB		 455 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
456
84e690bf
AB		 457 return true;
458}
459
460static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
461 const struct kvm_one_reg *reg, void __user *uaddr)
462{
463 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
464
1713e5aa 465 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 466 return -EFAULT;
467 return 0;
468}
469
470static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
471 const struct kvm_one_reg *reg, void __user *uaddr)
472{
473 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
474
475 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
476 return -EFAULT;
477 return 0;
478}
479
281243cb
MZ		 480static void reset_bvr(struct kvm_vcpu *vcpu,
481 const struct sys_reg_desc *rd)
84e690bf
AB		 482{
483 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
484}
485
281243cb
MZ		 486static bool trap_bcr(struct kvm_vcpu *vcpu,
487 struct sys_reg_params *p,
488 const struct sys_reg_desc *rd)
84e690bf
AB		 489{
490 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
491
492 if (p->is_write)
493 reg_to_dbg(vcpu, p, dbg_reg);
494 else
495 dbg_to_reg(vcpu, p, dbg_reg);
496
eef8c85a
AB		 497 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
498
84e690bf
AB		 499 return true;
500}
501
502static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
503 const struct kvm_one_reg *reg, void __user *uaddr)
504{
505 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
506
1713e5aa 507 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 508 return -EFAULT;
509
510 return 0;
511}
512
513static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
514 const struct kvm_one_reg *reg, void __user *uaddr)
515{
516 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
517
518 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
519 return -EFAULT;
520 return 0;
521}
522
281243cb
MZ		 523static void reset_bcr(struct kvm_vcpu *vcpu,
524 const struct sys_reg_desc *rd)
84e690bf
AB		 525{
526 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
527}
528
281243cb
MZ		 529static bool trap_wvr(struct kvm_vcpu *vcpu,
530 struct sys_reg_params *p,
531 const struct sys_reg_desc *rd)
84e690bf
AB		 532{
533 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
534
535 if (p->is_write)
536 reg_to_dbg(vcpu, p, dbg_reg);
537 else
538 dbg_to_reg(vcpu, p, dbg_reg);
539
eef8c85a
AB		 540 trace_trap_reg(__func__, rd->reg, p->is_write,
541 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
542
84e690bf
AB		 543 return true;
544}
545
546static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
547 const struct kvm_one_reg *reg, void __user *uaddr)
548{
549 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
550
1713e5aa 551 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 552 return -EFAULT;
553 return 0;
554}
555
556static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
557 const struct kvm_one_reg *reg, void __user *uaddr)
558{
559 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
560
561 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
562 return -EFAULT;
563 return 0;
564}
565
281243cb
MZ		 566static void reset_wvr(struct kvm_vcpu *vcpu,
567 const struct sys_reg_desc *rd)
84e690bf
AB		 568{
569 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
570}
571
281243cb
MZ		 572static bool trap_wcr(struct kvm_vcpu *vcpu,
573 struct sys_reg_params *p,
574 const struct sys_reg_desc *rd)
84e690bf
AB		 575{
576 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
577
578 if (p->is_write)
579 reg_to_dbg(vcpu, p, dbg_reg);
580 else
581 dbg_to_reg(vcpu, p, dbg_reg);
582
eef8c85a
AB		 583 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
584
84e690bf
AB		 585 return true;
586}
587
588static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
589 const struct kvm_one_reg *reg, void __user *uaddr)
590{
591 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
592
1713e5aa 593 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 594 return -EFAULT;
595 return 0;
596}
597
598static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
599 const struct kvm_one_reg *reg, void __user *uaddr)
600{
601 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
602
603 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
604 return -EFAULT;
605 return 0;
606}
607
281243cb
MZ		 608static void reset_wcr(struct kvm_vcpu *vcpu,
609 const struct sys_reg_desc *rd)
84e690bf
AB		 610{
611 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
612}
613
7c8c5e6a
MZ		 614static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
615{
8d404c4c
CD		 616 u64 amair = read_sysreg(amair_el1);
617 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
7c8c5e6a
MZ		 618}
619
620static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
621{
4429fc64
AP		 622 u64 mpidr;
623
7c8c5e6a 624 /*
4429fc64
AP		 625 * Map the vcpu_id into the first three affinity level fields of
626 * the MPIDR. We limit the number of VCPUs in level 0 due to a
627 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
628 * of the GICv3 to be able to address each CPU directly when
629 * sending IPIs.
7c8c5e6a 630 */
4429fc64
AP		 631 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
632 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
633 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
8d404c4c 634 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
7c8c5e6a
MZ		 635}
636
ab946834
SZ		 637static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
638{
639 u64 pmcr, val;
640
1f3d8699
MR		 641 pmcr = read_sysreg(pmcr_el0);
642 /*
643 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
ab946834
SZ		 644 * except PMCR.E resetting to zero.
645 */
646 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
647 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
6f163714
MZ		 648 if (!system_supports_32bit_el0())
649 val |= ARMV8_PMU_PMCR_LC;
03fdfb26 650 __vcpu_sys_reg(vcpu, r->reg) = val;
ab946834
SZ		 651}
652
6c007036 653static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
d692b8ad 654{
8d404c4c 655 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
6c007036 656 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
d692b8ad 657
24d5950f
MZ		 658 if (!enabled)
659 kvm_inject_undefined(vcpu);
d692b8ad 660
6c007036 661 return !enabled;
d692b8ad
SZ		 662}
663
6c007036 664static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
d692b8ad 665{
6c007036
MZ		 666 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
667}
d692b8ad 668
6c007036
MZ		 669static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
670{
671 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 672}
673
674static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
675{
6c007036 676 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 677}
678
679static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
680{
6c007036 681 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 682}
683
ab946834
SZ		 684static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
685 const struct sys_reg_desc *r)
686{
687 u64 val;
688
689 if (!kvm_arm_pmu_v3_ready(vcpu))
690 return trap_raz_wi(vcpu, p, r);
691
d692b8ad
SZ		 692 if (pmu_access_el0_disabled(vcpu))
693 return false;
694
ab946834
SZ		 695 if (p->is_write) {
696 /* Only update writeable bits of PMCR */
8d404c4c 697 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
ab946834
SZ		 698 val &= ~ARMV8_PMU_PMCR_MASK;
699 val |= p->regval & ARMV8_PMU_PMCR_MASK;
6f163714
MZ		 700 if (!system_supports_32bit_el0())
701 val |= ARMV8_PMU_PMCR_LC;
8d404c4c 702 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
76993739 703 kvm_pmu_handle_pmcr(vcpu, val);
435e53fb 704 kvm_vcpu_pmu_restore_guest(vcpu);
ab946834
SZ		 705 } else {
706 /* PMCR.P & PMCR.C are RAZ */
8d404c4c 707 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
ab946834
SZ		 708 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
709 p->regval = val;
710 }
711
712 return true;
713}
714
3965c3ce
SZ		 715static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
716 const struct sys_reg_desc *r)
717{
718 if (!kvm_arm_pmu_v3_ready(vcpu))
719 return trap_raz_wi(vcpu, p, r);
720
d692b8ad
SZ		 721 if (pmu_access_event_counter_el0_disabled(vcpu))
722 return false;
723
3965c3ce 724 if (p->is_write)
8d404c4c 725 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
3965c3ce
SZ		 726 else
727 /* return PMSELR.SEL field */
8d404c4c 728 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
3965c3ce
SZ		 729 & ARMV8_PMU_COUNTER_MASK;
730
731 return true;
732}
733
a86b5505
SZ		 734static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
735 const struct sys_reg_desc *r)
736{
737 u64 pmceid;
738
739 if (!kvm_arm_pmu_v3_ready(vcpu))
740 return trap_raz_wi(vcpu, p, r);
741
742 BUG_ON(p->is_write);
743
d692b8ad
SZ		 744 if (pmu_access_el0_disabled(vcpu))
745 return false;
746
a86b5505 747 if (!(p->Op2 & 1))
1f3d8699 748 pmceid = read_sysreg(pmceid0_el0);
a86b5505 749 else
1f3d8699 750 pmceid = read_sysreg(pmceid1_el0);
a86b5505
SZ		 751
752 p->regval = pmceid;
753
754 return true;
755}
756
051ff581
SZ		 757static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
758{
759 u64 pmcr, val;
760
8d404c4c 761 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
051ff581 762 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
24d5950f
MZ		 763 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
764 kvm_inject_undefined(vcpu);
051ff581 765 return false;
24d5950f 766 }
051ff581
SZ		 767
768 return true;
769}
770
771static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
772 struct sys_reg_params *p,
773 const struct sys_reg_desc *r)
774{
775 u64 idx;
776
777 if (!kvm_arm_pmu_v3_ready(vcpu))
778 return trap_raz_wi(vcpu, p, r);
779
780 if (r->CRn == 9 && r->CRm == 13) {
781 if (r->Op2 == 2) {
782 /* PMXEVCNTR_EL0 */
d692b8ad
SZ		 783 if (pmu_access_event_counter_el0_disabled(vcpu))
784 return false;
785
8d404c4c 786 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
051ff581
SZ		 787 & ARMV8_PMU_COUNTER_MASK;
788 } else if (r->Op2 == 0) {
789 /* PMCCNTR_EL0 */
d692b8ad
SZ		 790 if (pmu_access_cycle_counter_el0_disabled(vcpu))
791 return false;
792
051ff581
SZ		 793 idx = ARMV8_PMU_CYCLE_IDX;
794 } else {
9e3f7a29 795 return false;
051ff581 796 }
9e3f7a29
WH		 797 } else if (r->CRn == 0 && r->CRm == 9) {
798 /* PMCCNTR */
799 if (pmu_access_event_counter_el0_disabled(vcpu))
800 return false;
801
802 idx = ARMV8_PMU_CYCLE_IDX;
051ff581
SZ		 803 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
804 /* PMEVCNTRn_EL0 */
d692b8ad
SZ		 805 if (pmu_access_event_counter_el0_disabled(vcpu))
806 return false;
807
051ff581
SZ		 808 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
809 } else {
9e3f7a29 810 return false;
051ff581
SZ		 811 }
812
813 if (!pmu_counter_idx_valid(vcpu, idx))
814 return false;
815
d692b8ad
SZ		 816 if (p->is_write) {
817 if (pmu_access_el0_disabled(vcpu))
818 return false;
819
051ff581 820 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
d692b8ad 821 } else {
051ff581 822 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
d692b8ad 823 }
051ff581
SZ		 824
825 return true;
826}
827
9feb21ac
SZ		 828static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
829 const struct sys_reg_desc *r)
830{
831 u64 idx, reg;
832
833 if (!kvm_arm_pmu_v3_ready(vcpu))
834 return trap_raz_wi(vcpu, p, r);
835
d692b8ad
SZ		 836 if (pmu_access_el0_disabled(vcpu))
837 return false;
838
9feb21ac
SZ		 839 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
840 /* PMXEVTYPER_EL0 */
8d404c4c 841 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
9feb21ac
SZ		 842 reg = PMEVTYPER0_EL0 + idx;
843 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
844 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
845 if (idx == ARMV8_PMU_CYCLE_IDX)
846 reg = PMCCFILTR_EL0;
847 else
848 /* PMEVTYPERn_EL0 */
849 reg = PMEVTYPER0_EL0 + idx;
850 } else {
851 BUG();
852 }
853
854 if (!pmu_counter_idx_valid(vcpu, idx))
855 return false;
856
857 if (p->is_write) {
858 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
8d404c4c 859 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
435e53fb 860 kvm_vcpu_pmu_restore_guest(vcpu);
9feb21ac 861 } else {
8d404c4c 862 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
9feb21ac
SZ		 863 }
864
865 return true;
866}
867
96b0eebc
SZ		 868static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
869 const struct sys_reg_desc *r)
870{
871 u64 val, mask;
872
873 if (!kvm_arm_pmu_v3_ready(vcpu))
874 return trap_raz_wi(vcpu, p, r);
875
d692b8ad
SZ		 876 if (pmu_access_el0_disabled(vcpu))
877 return false;
878
96b0eebc
SZ		 879 mask = kvm_pmu_valid_counter_mask(vcpu);
880 if (p->is_write) {
881 val = p->regval & mask;
882 if (r->Op2 & 0x1) {
883 /* accessing PMCNTENSET_EL0 */
8d404c4c 884 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
418e5ca8 885 kvm_pmu_enable_counter_mask(vcpu, val);
435e53fb 886 kvm_vcpu_pmu_restore_guest(vcpu);
96b0eebc
SZ		 887 } else {
888 /* accessing PMCNTENCLR_EL0 */
8d404c4c 889 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
418e5ca8 890 kvm_pmu_disable_counter_mask(vcpu, val);
96b0eebc
SZ		 891 }
892 } else {
8d404c4c 893 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
96b0eebc
SZ		 894 }
895
896 return true;
897}
898
9db52c78
SZ		 899static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
900 const struct sys_reg_desc *r)
901{
902 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
903
904 if (!kvm_arm_pmu_v3_ready(vcpu))
905 return trap_raz_wi(vcpu, p, r);
906
9008c235
MZ		 907 if (!vcpu_mode_priv(vcpu)) {
908 kvm_inject_undefined(vcpu);
d692b8ad 909 return false;
9008c235 910 }
d692b8ad 911
9db52c78
SZ		 912 if (p->is_write) {
913 u64 val = p->regval & mask;
914
915 if (r->Op2 & 0x1)
916 /* accessing PMINTENSET_EL1 */
8d404c4c 917 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
9db52c78
SZ		 918 else
919 /* accessing PMINTENCLR_EL1 */
8d404c4c 920 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
9db52c78 921 } else {
8d404c4c 922 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
9db52c78
SZ		 923 }
924
925 return true;
926}
927
76d883c4
SZ		 928static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
929 const struct sys_reg_desc *r)
930{
931 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
932
933 if (!kvm_arm_pmu_v3_ready(vcpu))
934 return trap_raz_wi(vcpu, p, r);
935
d692b8ad
SZ		 936 if (pmu_access_el0_disabled(vcpu))
937 return false;
938
76d883c4
SZ		 939 if (p->is_write) {
940 if (r->CRm & 0x2)
941 /* accessing PMOVSSET_EL0 */
8d404c4c 942 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
76d883c4
SZ		 943 else
944 /* accessing PMOVSCLR_EL0 */
8d404c4c 945 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
76d883c4 946 } else {
8d404c4c 947 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
76d883c4
SZ		 948 }
949
950 return true;
951}
952
7a0adc70
SZ		 953static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
954 const struct sys_reg_desc *r)
955{
956 u64 mask;
957
958 if (!kvm_arm_pmu_v3_ready(vcpu))
959 return trap_raz_wi(vcpu, p, r);
960
e0443230 961 if (!p->is_write)
e7f1d1ee 962 return read_from_write_only(vcpu, p, r);
e0443230 963
d692b8ad
SZ		 964 if (pmu_write_swinc_el0_disabled(vcpu))
965 return false;
966
e0443230
MZ		 967 mask = kvm_pmu_valid_counter_mask(vcpu);
968 kvm_pmu_software_increment(vcpu, p->regval & mask);
969 return true;
7a0adc70
SZ		 970}
971
d692b8ad
SZ		 972static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
973 const struct sys_reg_desc *r)
974{
975 if (!kvm_arm_pmu_v3_ready(vcpu))
976 return trap_raz_wi(vcpu, p, r);
977
978 if (p->is_write) {
9008c235
MZ		 979 if (!vcpu_mode_priv(vcpu)) {
980 kvm_inject_undefined(vcpu);
d692b8ad 981 return false;
9008c235 982 }
d692b8ad 983
8d404c4c
CD		 984 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
985 p->regval & ARMV8_PMU_USERENR_MASK;
d692b8ad 986 } else {
8d404c4c 987 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
d692b8ad
SZ		 988 & ARMV8_PMU_USERENR_MASK;
989 }
990
991 return true;
992}
993
09838de9
MZ		 994#define reg_to_encoding(x) \
995 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
996 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2);
997
0c557ed4
MZ		 998/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
999#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
ee1b64e6 1000 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
03fdfb26 1001 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
ee1b64e6 1002 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
03fdfb26 1003 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
ee1b64e6 1004 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
03fdfb26 1005 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
ee1b64e6 1006 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
03fdfb26 1007 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
0c557ed4 1008
051ff581
SZ		 1009/* Macro to expand the PMEVCNTRn_EL0 register */
1010#define PMU_PMEVCNTR_EL0(n) \
174ed3e4 1011 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \
051ff581
SZ		 1012 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
1013
9feb21ac
SZ		 1014/* Macro to expand the PMEVTYPERn_EL0 register */
1015#define PMU_PMEVTYPER_EL0(n) \
174ed3e4 1016 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \
9feb21ac
SZ		 1017 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
1018
4fcdf106
IV		 1019static bool access_amu(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1020 const struct sys_reg_desc *r)
1021{
1022 kvm_inject_undefined(vcpu);
1023
1024 return false;
1025}
1026
1027/* Macro to expand the AMU counter and type registers*/
1028#define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), access_amu }
1029#define AMU_AMEVTYPE0_EL0(n) { SYS_DESC(SYS_AMEVTYPE0_EL0(n)), access_amu }
1030#define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), access_amu }
1031#define AMU_AMEVTYPE1_EL0(n) { SYS_DESC(SYS_AMEVTYPE1_EL0(n)), access_amu }
1032
384b40ca
MR		 1033static bool trap_ptrauth(struct kvm_vcpu *vcpu,
1034 struct sys_reg_params *p,
1035 const struct sys_reg_desc *rd)
1036{
1037 kvm_arm_vcpu_ptrauth_trap(vcpu);
1038
1039 /*
1040 * Return false for both cases as we never skip the trapped
1041 * instruction:
1042 *
1043 * - Either we re-execute the same key register access instruction
1044 * after enabling ptrauth.
1045 * - Or an UNDEF is injected as ptrauth is not supported/enabled.
1046 */
1047 return false;
1048}
1049
1050static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1051 const struct sys_reg_desc *rd)
1052{
1053 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN_USER | REG_HIDDEN_GUEST;
1054}
1055
1056#define __PTRAUTH_KEY(k) \
1057 { SYS_DESC(SYS_## k), trap_ptrauth, reset_unknown, k, \
1058 .visibility = ptrauth_visibility}
1059
1060#define PTRAUTH_KEY(k) \
1061 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1062 __PTRAUTH_KEY(k ## KEYHI_EL1)
1063
84135d3d
AP		 1064static bool access_arch_timer(struct kvm_vcpu *vcpu,
1065 struct sys_reg_params *p,
1066 const struct sys_reg_desc *r)
c9a3c58f 1067{
84135d3d
AP		 1068 enum kvm_arch_timers tmr;
1069 enum kvm_arch_timer_regs treg;
1070 u64 reg = reg_to_encoding(r);
7b6b4631 1071
84135d3d
AP		 1072 switch (reg) {
1073 case SYS_CNTP_TVAL_EL0:
1074 case SYS_AARCH32_CNTP_TVAL:
1075 tmr = TIMER_PTIMER;
1076 treg = TIMER_REG_TVAL;
1077 break;
1078 case SYS_CNTP_CTL_EL0:
1079 case SYS_AARCH32_CNTP_CTL:
1080 tmr = TIMER_PTIMER;
1081 treg = TIMER_REG_CTL;
1082 break;
1083 case SYS_CNTP_CVAL_EL0:
1084 case SYS_AARCH32_CNTP_CVAL:
1085 tmr = TIMER_PTIMER;
1086 treg = TIMER_REG_CVAL;
1087 break;
1088 default:
1089 BUG();
c1b135af 1090 }
7b6b4631 1091
7b6b4631 1092 if (p->is_write)
84135d3d 1093 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
7b6b4631 1094 else
84135d3d 1095 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
7b6b4631 1096
c9a3c58f
JL		 1097 return true;
1098}
1099
93390c0a 1100/* Read a sanitised cpufeature ID register by sys_reg_desc */
1c199913
DM		 1101static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1102 struct sys_reg_desc const *r, bool raz)
93390c0a
DM		 1103{
1104 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1105 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
07d79fe7 1106 u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
93390c0a 1107
4fcdf106
IV		 1108 if (id == SYS_ID_AA64PFR0_EL1) {
1109 if (!vcpu_has_sve(vcpu))
1110 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
1111 val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
384b40ca 1112 } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
9eecfc22
KM		 1113 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
1114 (0xfUL << ID_AA64ISAR1_API_SHIFT) |
1115 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
1116 (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
c854188e
AM		 1117 } else if (id == SYS_ID_AA64DFR0_EL1) {
1118 /* Limit guests to PMUv3 for ARMv8.1 */
1119 val = cpuid_feature_cap_perfmon_field(val,
1120 ID_AA64DFR0_PMUVER_SHIFT,
1121 ID_AA64DFR0_PMUVER_8_1);
1122 } else if (id == SYS_ID_DFR0_EL1) {
1123 /* Limit guests to PMUv3 for ARMv8.1 */
1124 val = cpuid_feature_cap_perfmon_field(val,
1125 ID_DFR0_PERFMON_SHIFT,
1126 ID_DFR0_PERFMON_8_1);
07d79fe7
DM		 1127 }
1128
1129 return val;
93390c0a
DM		 1130}
1131
1132/* cpufeature ID register access trap handlers */
1133
1134static bool __access_id_reg(struct kvm_vcpu *vcpu,
1135 struct sys_reg_params *p,
1136 const struct sys_reg_desc *r,
1137 bool raz)
1138{
1139 if (p->is_write)
1140 return write_to_read_only(vcpu, p, r);
1141
1c199913 1142 p->regval = read_id_reg(vcpu, r, raz);
93390c0a
DM		 1143 return true;
1144}
1145
1146static bool access_id_reg(struct kvm_vcpu *vcpu,
1147 struct sys_reg_params *p,
1148 const struct sys_reg_desc *r)
1149{
1150 return __access_id_reg(vcpu, p, r, false);
1151}
1152
1153static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1154 struct sys_reg_params *p,
1155 const struct sys_reg_desc *r)
1156{
1157 return __access_id_reg(vcpu, p, r, true);
1158}
1159
1160static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1161static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1162static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1163
73433762
DM		 1164/* Visibility overrides for SVE-specific control registers */
1165static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1166 const struct sys_reg_desc *rd)
1167{
1168 if (vcpu_has_sve(vcpu))
1169 return 0;
1170
1171 return REG_HIDDEN_USER | REG_HIDDEN_GUEST;
1172}
1173
1174/* Visibility overrides for SVE-specific ID registers */
1175static unsigned int sve_id_visibility(const struct kvm_vcpu *vcpu,
1176 const struct sys_reg_desc *rd)
1177{
1178 if (vcpu_has_sve(vcpu))
1179 return 0;
1180
1181 return REG_HIDDEN_USER;
1182}
1183
1184/* Generate the emulated ID_AA64ZFR0_EL1 value exposed to the guest */
1185static u64 guest_id_aa64zfr0_el1(const struct kvm_vcpu *vcpu)
1186{
1187 if (!vcpu_has_sve(vcpu))
1188 return 0;
1189
1190 return read_sanitised_ftr_reg(SYS_ID_AA64ZFR0_EL1);
1191}
1192
1193static bool access_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1194 struct sys_reg_params *p,
1195 const struct sys_reg_desc *rd)
1196{
1197 if (p->is_write)
1198 return write_to_read_only(vcpu, p, rd);
1199
1200 p->regval = guest_id_aa64zfr0_el1(vcpu);
1201 return true;
1202}
1203
1204static int get_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1205 const struct sys_reg_desc *rd,
1206 const struct kvm_one_reg *reg, void __user *uaddr)
1207{
1208 u64 val;
1209
700698a8 1210 if (WARN_ON(!vcpu_has_sve(vcpu)))
73433762
DM		 1211 return -ENOENT;
1212
1213 val = guest_id_aa64zfr0_el1(vcpu);
1214 return reg_to_user(uaddr, &val, reg->id);
1215}
1216
1217static int set_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1218 const struct sys_reg_desc *rd,
1219 const struct kvm_one_reg *reg, void __user *uaddr)
1220{
1221 const u64 id = sys_reg_to_index(rd);
1222 int err;
1223 u64 val;
1224
700698a8 1225 if (WARN_ON(!vcpu_has_sve(vcpu)))
73433762
DM		 1226 return -ENOENT;
1227
1228 err = reg_from_user(&val, uaddr, id);
1229 if (err)
1230 return err;
1231
1232 /* This is what we mean by invariant: you can't change it. */
1233 if (val != guest_id_aa64zfr0_el1(vcpu))
1234 return -EINVAL;
1235
1236 return 0;
1237}
1238
93390c0a
DM		 1239/*
1240 * cpufeature ID register user accessors
1241 *
1242 * For now, these registers are immutable for userspace, so no values
1243 * are stored, and for set_id_reg() we don't allow the effective value
1244 * to be changed.
1245 */
1c199913
DM		 1246static int __get_id_reg(const struct kvm_vcpu *vcpu,
1247 const struct sys_reg_desc *rd, void __user *uaddr,
93390c0a
DM		 1248 bool raz)
1249{
1250 const u64 id = sys_reg_to_index(rd);
1c199913 1251 const u64 val = read_id_reg(vcpu, rd, raz);
93390c0a
DM		 1252
1253 return reg_to_user(uaddr, &val, id);
1254}
1255
1c199913
DM		 1256static int __set_id_reg(const struct kvm_vcpu *vcpu,
1257 const struct sys_reg_desc *rd, void __user *uaddr,
93390c0a
DM		 1258 bool raz)
1259{
1260 const u64 id = sys_reg_to_index(rd);
1261 int err;
1262 u64 val;
1263
1264 err = reg_from_user(&val, uaddr, id);
1265 if (err)
1266 return err;
1267
1268 /* This is what we mean by invariant: you can't change it. */
1c199913 1269 if (val != read_id_reg(vcpu, rd, raz))
93390c0a
DM		 1270 return -EINVAL;
1271
1272 return 0;
1273}
1274
1275static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1276 const struct kvm_one_reg *reg, void __user *uaddr)
1277{
1c199913 1278 return __get_id_reg(vcpu, rd, uaddr, false);
93390c0a
DM		 1279}
1280
1281static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1282 const struct kvm_one_reg *reg, void __user *uaddr)
1283{
1c199913 1284 return __set_id_reg(vcpu, rd, uaddr, false);
93390c0a
DM		 1285}
1286
1287static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1288 const struct kvm_one_reg *reg, void __user *uaddr)
1289{
1c199913 1290 return __get_id_reg(vcpu, rd, uaddr, true);
93390c0a
DM		 1291}
1292
1293static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1294 const struct kvm_one_reg *reg, void __user *uaddr)
1295{
1c199913 1296 return __set_id_reg(vcpu, rd, uaddr, true);
93390c0a
DM		 1297}
1298
f7f2b15c
AB		 1299static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1300 const struct sys_reg_desc *r)
1301{
1302 if (p->is_write)
1303 return write_to_read_only(vcpu, p, r);
1304
1305 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1306 return true;
1307}
1308
1309static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1310 const struct sys_reg_desc *r)
1311{
1312 if (p->is_write)
1313 return write_to_read_only(vcpu, p, r);
1314
1315 p->regval = read_sysreg(clidr_el1);
1316 return true;
1317}
1318
1319static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1320 const struct sys_reg_desc *r)
1321{
1322 if (p->is_write)
1323 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
1324 else
1325 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
1326 return true;
1327}
1328
1329static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1330 const struct sys_reg_desc *r)
1331{
1332 u32 csselr;
1333
1334 if (p->is_write)
1335 return write_to_read_only(vcpu, p, r);
1336
1337 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1338 p->regval = get_ccsidr(csselr);
793acf87
AB		 1339
1340 /*
1341 * Guests should not be doing cache operations by set/way at all, and
1342 * for this reason, we trap them and attempt to infer the intent, so
1343 * that we can flush the entire guest's address space at the appropriate
1344 * time.
1345 * To prevent this trapping from causing performance problems, let's
1346 * expose the geometry of all data and unified caches (which are
1347 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1348 * [If guests should attempt to infer aliasing properties from the
1349 * geometry (which is not permitted by the architecture), they would
1350 * only do so for virtually indexed caches.]
1351 */
1352 if (!(csselr & 1)) // data or unified cache
1353 p->regval &= ~GENMASK(27, 3);
f7f2b15c
AB		 1354 return true;
1355}
1356
93390c0a
DM		 1357/* sys_reg_desc initialiser for known cpufeature ID registers */
1358#define ID_SANITISED(name) { \
1359 SYS_DESC(SYS_##name), \
1360 .access = access_id_reg, \
1361 .get_user = get_id_reg, \
1362 .set_user = set_id_reg, \
1363}
1364
1365/*
1366 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1367 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1368 * (1 <= crm < 8, 0 <= Op2 < 8).
1369 */
1370#define ID_UNALLOCATED(crm, op2) { \
1371 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1372 .access = access_raz_id_reg, \
1373 .get_user = get_raz_id_reg, \
1374 .set_user = set_raz_id_reg, \
1375}
1376
1377/*
1378 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1379 * For now, these are exposed just like unallocated ID regs: they appear
1380 * RAZ for the guest.
1381 */
1382#define ID_HIDDEN(name) { \
1383 SYS_DESC(SYS_##name), \
1384 .access = access_raz_id_reg, \
1385 .get_user = get_raz_id_reg, \
1386 .set_user = set_raz_id_reg, \
1387}
1388
7c8c5e6a
MZ		 1389/*
1390 * Architected system registers.
1391 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
7609c125 1392 *
0c557ed4
MZ		 1393 * Debug handling: We do trap most, if not all debug related system
1394 * registers. The implementation is good enough to ensure that a guest
1395 * can use these with minimal performance degradation. The drawback is
1396 * that we don't implement any of the external debug, none of the
1397 * OSlock protocol. This should be revisited if we ever encounter a
1398 * more demanding guest...
7c8c5e6a
MZ		 1399 */
1400static const struct sys_reg_desc sys_reg_descs[] = {
7606e078
MR		 1401 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1402 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1403 { SYS_DESC(SYS_DC_CISW), access_dcsw },
7c8c5e6a 1404
0c557ed4
MZ		 1405 DBG_BCR_BVR_WCR_WVR_EL1(0),
1406 DBG_BCR_BVR_WCR_WVR_EL1(1),
ee1b64e6
MR		 1407 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1408 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
0c557ed4
MZ		 1409 DBG_BCR_BVR_WCR_WVR_EL1(2),
1410 DBG_BCR_BVR_WCR_WVR_EL1(3),
1411 DBG_BCR_BVR_WCR_WVR_EL1(4),
1412 DBG_BCR_BVR_WCR_WVR_EL1(5),
1413 DBG_BCR_BVR_WCR_WVR_EL1(6),
1414 DBG_BCR_BVR_WCR_WVR_EL1(7),
1415 DBG_BCR_BVR_WCR_WVR_EL1(8),
1416 DBG_BCR_BVR_WCR_WVR_EL1(9),
1417 DBG_BCR_BVR_WCR_WVR_EL1(10),
1418 DBG_BCR_BVR_WCR_WVR_EL1(11),
1419 DBG_BCR_BVR_WCR_WVR_EL1(12),
1420 DBG_BCR_BVR_WCR_WVR_EL1(13),
1421 DBG_BCR_BVR_WCR_WVR_EL1(14),
1422 DBG_BCR_BVR_WCR_WVR_EL1(15),
1423
ee1b64e6
MR		 1424 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1425 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1426 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1427 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1428 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1429 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1430 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1431 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1432
1433 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1434 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1435 // DBGDTR[TR]X_EL0 share the same encoding
1436 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1437
1438 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
62a89c44 1439
851050a5 1440 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
93390c0a
DM		 1441
1442 /*
1443 * ID regs: all ID_SANITISED() entries here must have corresponding
1444 * entries in arm64_ftr_regs[].
1445 */
1446
1447 /* AArch64 mappings of the AArch32 ID registers */
1448 /* CRm=1 */
1449 ID_SANITISED(ID_PFR0_EL1),
1450 ID_SANITISED(ID_PFR1_EL1),
1451 ID_SANITISED(ID_DFR0_EL1),
1452 ID_HIDDEN(ID_AFR0_EL1),
1453 ID_SANITISED(ID_MMFR0_EL1),
1454 ID_SANITISED(ID_MMFR1_EL1),
1455 ID_SANITISED(ID_MMFR2_EL1),
1456 ID_SANITISED(ID_MMFR3_EL1),
1457
1458 /* CRm=2 */
1459 ID_SANITISED(ID_ISAR0_EL1),
1460 ID_SANITISED(ID_ISAR1_EL1),
1461 ID_SANITISED(ID_ISAR2_EL1),
1462 ID_SANITISED(ID_ISAR3_EL1),
1463 ID_SANITISED(ID_ISAR4_EL1),
1464 ID_SANITISED(ID_ISAR5_EL1),
1465 ID_SANITISED(ID_MMFR4_EL1),
8e3747be 1466 ID_SANITISED(ID_ISAR6_EL1),
93390c0a
DM		 1467
1468 /* CRm=3 */
1469 ID_SANITISED(MVFR0_EL1),
1470 ID_SANITISED(MVFR1_EL1),
1471 ID_SANITISED(MVFR2_EL1),
1472 ID_UNALLOCATED(3,3),
1473 ID_UNALLOCATED(3,4),
1474 ID_UNALLOCATED(3,5),
1475 ID_UNALLOCATED(3,6),
1476 ID_UNALLOCATED(3,7),
1477
1478 /* AArch64 ID registers */
1479 /* CRm=4 */
1480 ID_SANITISED(ID_AA64PFR0_EL1),
1481 ID_SANITISED(ID_AA64PFR1_EL1),
1482 ID_UNALLOCATED(4,2),
1483 ID_UNALLOCATED(4,3),
73433762 1484 { SYS_DESC(SYS_ID_AA64ZFR0_EL1), access_id_aa64zfr0_el1, .get_user = get_id_aa64zfr0_el1, .set_user = set_id_aa64zfr0_el1, .visibility = sve_id_visibility },
93390c0a
DM		 1485 ID_UNALLOCATED(4,5),
1486 ID_UNALLOCATED(4,6),
1487 ID_UNALLOCATED(4,7),
1488
1489 /* CRm=5 */
1490 ID_SANITISED(ID_AA64DFR0_EL1),
1491 ID_SANITISED(ID_AA64DFR1_EL1),
1492 ID_UNALLOCATED(5,2),
1493 ID_UNALLOCATED(5,3),
1494 ID_HIDDEN(ID_AA64AFR0_EL1),
1495 ID_HIDDEN(ID_AA64AFR1_EL1),
1496 ID_UNALLOCATED(5,6),
1497 ID_UNALLOCATED(5,7),
1498
1499 /* CRm=6 */
1500 ID_SANITISED(ID_AA64ISAR0_EL1),
1501 ID_SANITISED(ID_AA64ISAR1_EL1),
1502 ID_UNALLOCATED(6,2),
1503 ID_UNALLOCATED(6,3),
1504 ID_UNALLOCATED(6,4),
1505 ID_UNALLOCATED(6,5),
1506 ID_UNALLOCATED(6,6),
1507 ID_UNALLOCATED(6,7),
1508
1509 /* CRm=7 */
1510 ID_SANITISED(ID_AA64MMFR0_EL1),
1511 ID_SANITISED(ID_AA64MMFR1_EL1),
1512 ID_SANITISED(ID_AA64MMFR2_EL1),
1513 ID_UNALLOCATED(7,3),
1514 ID_UNALLOCATED(7,4),
1515 ID_UNALLOCATED(7,5),
1516 ID_UNALLOCATED(7,6),
1517 ID_UNALLOCATED(7,7),
1518
851050a5
MR		 1519 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1520 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
73433762 1521 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
851050a5
MR		 1522 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1523 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1524 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1525
384b40ca
MR		 1526 PTRAUTH_KEY(APIA),
1527 PTRAUTH_KEY(APIB),
1528 PTRAUTH_KEY(APDA),
1529 PTRAUTH_KEY(APDB),
1530 PTRAUTH_KEY(APGA),
1531
851050a5
MR		 1532 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1533 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1534 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
558daf69
DG		 1535
1536 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1537 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1538 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1539 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1540 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1541 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1542 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1543 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1544
851050a5
MR		 1545 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1546 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
7c8c5e6a 1547
174ed3e4
MR		 1548 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
1549 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 },
7c8c5e6a 1550
851050a5
MR		 1551 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1552 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
7c8c5e6a 1553
22925521
MZ		 1554 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1555 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1556 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1557 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1558 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
cc33c4e2 1559
851050a5 1560 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
c773ae2b 1561 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
db7dedd0 1562
7b1dba1f 1563 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
e7f1d1ee 1564 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
7b1dba1f 1565 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
e7f1d1ee 1566 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
7b1dba1f 1567 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
e804d208 1568 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
03bd646d
MZ		 1569 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1570 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
7b1dba1f 1571 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
e7f1d1ee 1572 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
7b1dba1f 1573 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
e804d208 1574 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
db7dedd0 1575
851050a5
MR		 1576 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1577 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
7c8c5e6a 1578
851050a5 1579 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
7c8c5e6a 1580
f7f2b15c
AB		 1581 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1582 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1583 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1584 { SYS_DESC(SYS_CTR_EL0), access_ctr },
7c8c5e6a 1585
03fdfb26 1586 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 },
174ed3e4
MR		 1587 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1588 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, NULL, PMCNTENSET_EL0 },
1589 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, NULL, PMOVSSET_EL0 },
1590 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
1591 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
1592 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
1593 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
1594 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1595 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
1596 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
1597 /*
1598 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
d692b8ad
SZ		 1599 * in 32bit mode. Here we choose to reset it as zero for consistency.
1600 */
174ed3e4
MR		 1601 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1602 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
7c8c5e6a 1603
851050a5
MR		 1604 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1605 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
4fcdf106
IV		 1606
1607 { SYS_DESC(SYS_AMCR_EL0), access_amu },
1608 { SYS_DESC(SYS_AMCFGR_EL0), access_amu },
1609 { SYS_DESC(SYS_AMCGCR_EL0), access_amu },
1610 { SYS_DESC(SYS_AMUSERENR_EL0), access_amu },
1611 { SYS_DESC(SYS_AMCNTENCLR0_EL0), access_amu },
1612 { SYS_DESC(SYS_AMCNTENSET0_EL0), access_amu },
1613 { SYS_DESC(SYS_AMCNTENCLR1_EL0), access_amu },
1614 { SYS_DESC(SYS_AMCNTENSET1_EL0), access_amu },
1615 AMU_AMEVCNTR0_EL0(0),
1616 AMU_AMEVCNTR0_EL0(1),
1617 AMU_AMEVCNTR0_EL0(2),
1618 AMU_AMEVCNTR0_EL0(3),
1619 AMU_AMEVCNTR0_EL0(4),
1620 AMU_AMEVCNTR0_EL0(5),
1621 AMU_AMEVCNTR0_EL0(6),
1622 AMU_AMEVCNTR0_EL0(7),
1623 AMU_AMEVCNTR0_EL0(8),
1624 AMU_AMEVCNTR0_EL0(9),
1625 AMU_AMEVCNTR0_EL0(10),
1626 AMU_AMEVCNTR0_EL0(11),
1627 AMU_AMEVCNTR0_EL0(12),
1628 AMU_AMEVCNTR0_EL0(13),
1629 AMU_AMEVCNTR0_EL0(14),
1630 AMU_AMEVCNTR0_EL0(15),
1631 AMU_AMEVTYPE0_EL0(0),
1632 AMU_AMEVTYPE0_EL0(1),
1633 AMU_AMEVTYPE0_EL0(2),
1634 AMU_AMEVTYPE0_EL0(3),
1635 AMU_AMEVTYPE0_EL0(4),
1636 AMU_AMEVTYPE0_EL0(5),
1637 AMU_AMEVTYPE0_EL0(6),
1638 AMU_AMEVTYPE0_EL0(7),
1639 AMU_AMEVTYPE0_EL0(8),
1640 AMU_AMEVTYPE0_EL0(9),
1641 AMU_AMEVTYPE0_EL0(10),
1642 AMU_AMEVTYPE0_EL0(11),
1643 AMU_AMEVTYPE0_EL0(12),
1644 AMU_AMEVTYPE0_EL0(13),
1645 AMU_AMEVTYPE0_EL0(14),
1646 AMU_AMEVTYPE0_EL0(15),
1647 AMU_AMEVCNTR1_EL0(0),
1648 AMU_AMEVCNTR1_EL0(1),
1649 AMU_AMEVCNTR1_EL0(2),
1650 AMU_AMEVCNTR1_EL0(3),
1651 AMU_AMEVCNTR1_EL0(4),
1652 AMU_AMEVCNTR1_EL0(5),
1653 AMU_AMEVCNTR1_EL0(6),
1654 AMU_AMEVCNTR1_EL0(7),
1655 AMU_AMEVCNTR1_EL0(8),
1656 AMU_AMEVCNTR1_EL0(9),
1657 AMU_AMEVCNTR1_EL0(10),
1658 AMU_AMEVCNTR1_EL0(11),
1659 AMU_AMEVCNTR1_EL0(12),
1660 AMU_AMEVCNTR1_EL0(13),
1661 AMU_AMEVCNTR1_EL0(14),
1662 AMU_AMEVCNTR1_EL0(15),
1663 AMU_AMEVTYPE1_EL0(0),
1664 AMU_AMEVTYPE1_EL0(1),
1665 AMU_AMEVTYPE1_EL0(2),
1666 AMU_AMEVTYPE1_EL0(3),
1667 AMU_AMEVTYPE1_EL0(4),
1668 AMU_AMEVTYPE1_EL0(5),
1669 AMU_AMEVTYPE1_EL0(6),
1670 AMU_AMEVTYPE1_EL0(7),
1671 AMU_AMEVTYPE1_EL0(8),
1672 AMU_AMEVTYPE1_EL0(9),
1673 AMU_AMEVTYPE1_EL0(10),
1674 AMU_AMEVTYPE1_EL0(11),
1675 AMU_AMEVTYPE1_EL0(12),
1676 AMU_AMEVTYPE1_EL0(13),
1677 AMU_AMEVTYPE1_EL0(14),
1678 AMU_AMEVTYPE1_EL0(15),
62a89c44 1679
84135d3d
AP		 1680 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1681 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1682 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
c9a3c58f 1683
051ff581
SZ		 1684 /* PMEVCNTRn_EL0 */
1685 PMU_PMEVCNTR_EL0(0),
1686 PMU_PMEVCNTR_EL0(1),
1687 PMU_PMEVCNTR_EL0(2),
1688 PMU_PMEVCNTR_EL0(3),
1689 PMU_PMEVCNTR_EL0(4),
1690 PMU_PMEVCNTR_EL0(5),
1691 PMU_PMEVCNTR_EL0(6),
1692 PMU_PMEVCNTR_EL0(7),
1693 PMU_PMEVCNTR_EL0(8),
1694 PMU_PMEVCNTR_EL0(9),
1695 PMU_PMEVCNTR_EL0(10),
1696 PMU_PMEVCNTR_EL0(11),
1697 PMU_PMEVCNTR_EL0(12),
1698 PMU_PMEVCNTR_EL0(13),
1699 PMU_PMEVCNTR_EL0(14),
1700 PMU_PMEVCNTR_EL0(15),
1701 PMU_PMEVCNTR_EL0(16),
1702 PMU_PMEVCNTR_EL0(17),
1703 PMU_PMEVCNTR_EL0(18),
1704 PMU_PMEVCNTR_EL0(19),
1705 PMU_PMEVCNTR_EL0(20),
1706 PMU_PMEVCNTR_EL0(21),
1707 PMU_PMEVCNTR_EL0(22),
1708 PMU_PMEVCNTR_EL0(23),
1709 PMU_PMEVCNTR_EL0(24),
1710 PMU_PMEVCNTR_EL0(25),
1711 PMU_PMEVCNTR_EL0(26),
1712 PMU_PMEVCNTR_EL0(27),
1713 PMU_PMEVCNTR_EL0(28),
1714 PMU_PMEVCNTR_EL0(29),
1715 PMU_PMEVCNTR_EL0(30),
9feb21ac
SZ		 1716 /* PMEVTYPERn_EL0 */
1717 PMU_PMEVTYPER_EL0(0),
1718 PMU_PMEVTYPER_EL0(1),
1719 PMU_PMEVTYPER_EL0(2),
1720 PMU_PMEVTYPER_EL0(3),
1721 PMU_PMEVTYPER_EL0(4),
1722 PMU_PMEVTYPER_EL0(5),
1723 PMU_PMEVTYPER_EL0(6),
1724 PMU_PMEVTYPER_EL0(7),
1725 PMU_PMEVTYPER_EL0(8),
1726 PMU_PMEVTYPER_EL0(9),
1727 PMU_PMEVTYPER_EL0(10),
1728 PMU_PMEVTYPER_EL0(11),
1729 PMU_PMEVTYPER_EL0(12),
1730 PMU_PMEVTYPER_EL0(13),
1731 PMU_PMEVTYPER_EL0(14),
1732 PMU_PMEVTYPER_EL0(15),
1733 PMU_PMEVTYPER_EL0(16),
1734 PMU_PMEVTYPER_EL0(17),
1735 PMU_PMEVTYPER_EL0(18),
1736 PMU_PMEVTYPER_EL0(19),
1737 PMU_PMEVTYPER_EL0(20),
1738 PMU_PMEVTYPER_EL0(21),
1739 PMU_PMEVTYPER_EL0(22),
1740 PMU_PMEVTYPER_EL0(23),
1741 PMU_PMEVTYPER_EL0(24),
1742 PMU_PMEVTYPER_EL0(25),
1743 PMU_PMEVTYPER_EL0(26),
1744 PMU_PMEVTYPER_EL0(27),
1745 PMU_PMEVTYPER_EL0(28),
1746 PMU_PMEVTYPER_EL0(29),
1747 PMU_PMEVTYPER_EL0(30),
174ed3e4
MR		 1748 /*
1749 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
9feb21ac
SZ		 1750 * in 32bit mode. Here we choose to reset it as zero for consistency.
1751 */
174ed3e4 1752 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
051ff581 1753
851050a5
MR		 1754 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1755 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
c88b0936 1756 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
62a89c44
MZ		 1757};
1758
bdfb4b38 1759static bool trap_dbgidr(struct kvm_vcpu *vcpu,
3fec037d 1760 struct sys_reg_params *p,
bdfb4b38
MZ		 1761 const struct sys_reg_desc *r)
1762{
1763 if (p->is_write) {
1764 return ignore_write(vcpu, p);
1765 } else {
46823dd1
DM		 1766 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1767 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
28c5dcb2 1768 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
bdfb4b38 1769
2ec5be3d
PF		 1770 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1771 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1772 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1773 | (6 << 16) | (el3 << 14) | (el3 << 12));
bdfb4b38
MZ		 1774 return true;
1775 }
1776}
1777
1778static bool trap_debug32(struct kvm_vcpu *vcpu,
3fec037d 1779 struct sys_reg_params *p,
bdfb4b38
MZ		 1780 const struct sys_reg_desc *r)
1781{
1782 if (p->is_write) {
2ec5be3d 1783 vcpu_cp14(vcpu, r->reg) = p->regval;
fa89d31c 1784 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
bdfb4b38 1785 } else {
2ec5be3d 1786 p->regval = vcpu_cp14(vcpu, r->reg);
bdfb4b38
MZ		 1787 }
1788
1789 return true;
1790}
1791
84e690bf
AB		 1792/* AArch32 debug register mappings
1793 *
1794 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1795 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1796 *
1797 * All control registers and watchpoint value registers are mapped to
1798 * the lower 32 bits of their AArch64 equivalents. We share the trap
1799 * handlers with the above AArch64 code which checks what mode the
1800 * system is in.
1801 */
1802
281243cb
MZ		 1803static bool trap_xvr(struct kvm_vcpu *vcpu,
1804 struct sys_reg_params *p,
1805 const struct sys_reg_desc *rd)
84e690bf
AB		 1806{
1807 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1808
1809 if (p->is_write) {
1810 u64 val = *dbg_reg;
1811
1812 val &= 0xffffffffUL;
2ec5be3d 1813 val |= p->regval << 32;
84e690bf
AB		 1814 *dbg_reg = val;
1815
fa89d31c 1816 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
84e690bf 1817 } else {
2ec5be3d 1818 p->regval = *dbg_reg >> 32;
84e690bf
AB		 1819 }
1820
eef8c85a
AB		 1821 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1822
84e690bf
AB		 1823 return true;
1824}
1825
1826#define DBG_BCR_BVR_WCR_WVR(n) \
1827 /* DBGBVRn */ \
1828 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1829 /* DBGBCRn */ \
1830 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1831 /* DBGWVRn */ \
1832 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1833 /* DBGWCRn */ \
1834 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1835
1836#define DBGBXVR(n) \
1837 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
bdfb4b38
MZ		 1838
1839/*
1840 * Trapped cp14 registers. We generally ignore most of the external
1841 * debug, on the principle that they don't really make sense to a
84e690bf 1842 * guest. Revisit this one day, would this principle change.
bdfb4b38 1843 */
72564016 1844static const struct sys_reg_desc cp14_regs[] = {
bdfb4b38
MZ		 1845 /* DBGIDR */
1846 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1847 /* DBGDTRRXext */
1848 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1849
1850 DBG_BCR_BVR_WCR_WVR(0),
1851 /* DBGDSCRint */
1852 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1853 DBG_BCR_BVR_WCR_WVR(1),
1854 /* DBGDCCINT */
1855 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1856 /* DBGDSCRext */
1857 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1858 DBG_BCR_BVR_WCR_WVR(2),
1859 /* DBGDTR[RT]Xint */
1860 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1861 /* DBGDTR[RT]Xext */
1862 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1863 DBG_BCR_BVR_WCR_WVR(3),
1864 DBG_BCR_BVR_WCR_WVR(4),
1865 DBG_BCR_BVR_WCR_WVR(5),
1866 /* DBGWFAR */
1867 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1868 /* DBGOSECCR */
1869 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1870 DBG_BCR_BVR_WCR_WVR(6),
1871 /* DBGVCR */
1872 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1873 DBG_BCR_BVR_WCR_WVR(7),
1874 DBG_BCR_BVR_WCR_WVR(8),
1875 DBG_BCR_BVR_WCR_WVR(9),
1876 DBG_BCR_BVR_WCR_WVR(10),
1877 DBG_BCR_BVR_WCR_WVR(11),
1878 DBG_BCR_BVR_WCR_WVR(12),
1879 DBG_BCR_BVR_WCR_WVR(13),
1880 DBG_BCR_BVR_WCR_WVR(14),
1881 DBG_BCR_BVR_WCR_WVR(15),
1882
1883 /* DBGDRAR (32bit) */
1884 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1885
1886 DBGBXVR(0),
1887 /* DBGOSLAR */
1888 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1889 DBGBXVR(1),
1890 /* DBGOSLSR */
1891 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1892 DBGBXVR(2),
1893 DBGBXVR(3),
1894 /* DBGOSDLR */
1895 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1896 DBGBXVR(4),
1897 /* DBGPRCR */
1898 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1899 DBGBXVR(5),
1900 DBGBXVR(6),
1901 DBGBXVR(7),
1902 DBGBXVR(8),
1903 DBGBXVR(9),
1904 DBGBXVR(10),
1905 DBGBXVR(11),
1906 DBGBXVR(12),
1907 DBGBXVR(13),
1908 DBGBXVR(14),
1909 DBGBXVR(15),
1910
1911 /* DBGDSAR (32bit) */
1912 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1913
1914 /* DBGDEVID2 */
1915 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1916 /* DBGDEVID1 */
1917 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1918 /* DBGDEVID */
1919 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1920 /* DBGCLAIMSET */
1921 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1922 /* DBGCLAIMCLR */
1923 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1924 /* DBGAUTHSTATUS */
1925 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
72564016
MZ		 1926};
1927
a9866ba0
MZ		 1928/* Trapped cp14 64bit registers */
1929static const struct sys_reg_desc cp14_64_regs[] = {
bdfb4b38
MZ		 1930 /* DBGDRAR (64bit) */
1931 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1932
1933 /* DBGDSAR (64bit) */
1934 { Op1( 0), CRm( 2), .access = trap_raz_wi },
a9866ba0
MZ		 1935};
1936
051ff581
SZ		 1937/* Macro to expand the PMEVCNTRn register */
1938#define PMU_PMEVCNTR(n) \
1939 /* PMEVCNTRn */ \
1940 { Op1(0), CRn(0b1110), \
1941 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1942 access_pmu_evcntr }
1943
9feb21ac
SZ		 1944/* Macro to expand the PMEVTYPERn register */
1945#define PMU_PMEVTYPER(n) \
1946 /* PMEVTYPERn */ \
1947 { Op1(0), CRn(0b1110), \
1948 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1949 access_pmu_evtyper }
1950
4d44923b
MZ		 1951/*
1952 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1953 * depending on the way they are accessed (as a 32bit or a 64bit
1954 * register).
1955 */
62a89c44 1956static const struct sys_reg_desc cp15_regs[] = {
f7f2b15c 1957 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
3c1e7165 1958 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
4d44923b
MZ		 1959 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1960 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1961 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1962 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1963 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1964 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1965 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1966 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1967 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1968 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1969
62a89c44
MZ		 1970 /*
1971 * DC{C,I,CI}SW operations:
1972 */
1973 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1974 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1975 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
4d44923b 1976
7609c125 1977 /* PMU */
ab946834 1978 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
96b0eebc
SZ		 1979 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1980 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
76d883c4 1981 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
7a0adc70 1982 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
3965c3ce 1983 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
a86b5505
SZ		 1984 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1985 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
051ff581 1986 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
9feb21ac 1987 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
051ff581 1988 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
d692b8ad 1989 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
9db52c78
SZ		 1990 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1991 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
76d883c4 1992 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
4d44923b
MZ		 1993
1994 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1995 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1996 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1997 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
db7dedd0
CD		 1998
1999 /* ICC_SRE */
f7f6f2d9 2000 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
db7dedd0 2001
4d44923b 2002 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
051ff581 2003
84135d3d
AP		 2004 /* Arch Tmers */
2005 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
2006 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
eac137b4 2007
051ff581
SZ		 2008 /* PMEVCNTRn */
2009 PMU_PMEVCNTR(0),
2010 PMU_PMEVCNTR(1),
2011 PMU_PMEVCNTR(2),
2012 PMU_PMEVCNTR(3),
2013 PMU_PMEVCNTR(4),
2014 PMU_PMEVCNTR(5),
2015 PMU_PMEVCNTR(6),
2016 PMU_PMEVCNTR(7),
2017 PMU_PMEVCNTR(8),
2018 PMU_PMEVCNTR(9),
2019 PMU_PMEVCNTR(10),
2020 PMU_PMEVCNTR(11),
2021 PMU_PMEVCNTR(12),
2022 PMU_PMEVCNTR(13),
2023 PMU_PMEVCNTR(14),
2024 PMU_PMEVCNTR(15),
2025 PMU_PMEVCNTR(16),
2026 PMU_PMEVCNTR(17),
2027 PMU_PMEVCNTR(18),
2028 PMU_PMEVCNTR(19),
2029 PMU_PMEVCNTR(20),
2030 PMU_PMEVCNTR(21),
2031 PMU_PMEVCNTR(22),
2032 PMU_PMEVCNTR(23),
2033 PMU_PMEVCNTR(24),
2034 PMU_PMEVCNTR(25),
2035 PMU_PMEVCNTR(26),
2036 PMU_PMEVCNTR(27),
2037 PMU_PMEVCNTR(28),
2038 PMU_PMEVCNTR(29),
2039 PMU_PMEVCNTR(30),
9feb21ac
SZ		 2040 /* PMEVTYPERn */
2041 PMU_PMEVTYPER(0),
2042 PMU_PMEVTYPER(1),
2043 PMU_PMEVTYPER(2),
2044 PMU_PMEVTYPER(3),
2045 PMU_PMEVTYPER(4),
2046 PMU_PMEVTYPER(5),
2047 PMU_PMEVTYPER(6),
2048 PMU_PMEVTYPER(7),
2049 PMU_PMEVTYPER(8),
2050 PMU_PMEVTYPER(9),
2051 PMU_PMEVTYPER(10),
2052 PMU_PMEVTYPER(11),
2053 PMU_PMEVTYPER(12),
2054 PMU_PMEVTYPER(13),
2055 PMU_PMEVTYPER(14),
2056 PMU_PMEVTYPER(15),
2057 PMU_PMEVTYPER(16),
2058 PMU_PMEVTYPER(17),
2059 PMU_PMEVTYPER(18),
2060 PMU_PMEVTYPER(19),
2061 PMU_PMEVTYPER(20),
2062 PMU_PMEVTYPER(21),
2063 PMU_PMEVTYPER(22),
2064 PMU_PMEVTYPER(23),
2065 PMU_PMEVTYPER(24),
2066 PMU_PMEVTYPER(25),
2067 PMU_PMEVTYPER(26),
2068 PMU_PMEVTYPER(27),
2069 PMU_PMEVTYPER(28),
2070 PMU_PMEVTYPER(29),
2071 PMU_PMEVTYPER(30),
2072 /* PMCCFILTR */
2073 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
f7f2b15c
AB		 2074
2075 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2076 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2077 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR },
a9866ba0
MZ		 2078};
2079
2080static const struct sys_reg_desc cp15_64_regs[] = {
2081 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
051ff581 2082 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
03bd646d 2083 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
4d44923b 2084 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
03bd646d
MZ		 2085 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2086 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
84135d3d 2087 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
7c8c5e6a
MZ		 2088};
2089
2090/* Target specific emulation tables */
2091static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
2092
2093void kvm_register_target_sys_reg_table(unsigned int target,
2094 struct kvm_sys_reg_target_table *table)
2095{
2096 target_tables[target] = table;
2097}
2098
2099/* Get specific register table for this target. */
62a89c44
MZ		 2100static const struct sys_reg_desc *get_target_table(unsigned target,
2101 bool mode_is_64,
2102 size_t *num)
7c8c5e6a
MZ		 2103{
2104 struct kvm_sys_reg_target_table *table;
2105
2106 table = target_tables[target];
62a89c44
MZ		 2107 if (mode_is_64) {
2108 *num = table->table64.num;
2109 return table->table64.table;
2110 } else {
2111 *num = table->table32.num;
2112 return table->table32.table;
2113 }
7c8c5e6a
MZ		 2114}
2115
623eefa8
MZ		 2116static int match_sys_reg(const void *key, const void *elt)
2117{
2118 const unsigned long pval = (unsigned long)key;
2119 const struct sys_reg_desc *r = elt;
2120
09838de9 2121 return pval - reg_to_encoding(r);
623eefa8
MZ		 2122}
2123
7c8c5e6a
MZ		 2124static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
2125 const struct sys_reg_desc table[],
2126 unsigned int num)
2127{
09838de9 2128 unsigned long pval = reg_to_encoding(params);
623eefa8
MZ		 2129
2130 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
7c8c5e6a
MZ		 2131}
2132
62a89c44
MZ		 2133int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
2134{
2135 kvm_inject_undefined(vcpu);
2136 return 1;
2137}
2138
e70b9522
MZ		 2139static void perform_access(struct kvm_vcpu *vcpu,
2140 struct sys_reg_params *params,
2141 const struct sys_reg_desc *r)
2142{
599d79dc
MZ		 2143 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2144
7f34e409
DM		 2145 /* Check for regs disabled by runtime config */
2146 if (sysreg_hidden_from_guest(vcpu, r)) {
2147 kvm_inject_undefined(vcpu);
2148 return;
2149 }
2150
e70b9522
MZ		 2151 /*
2152 * Not having an accessor means that we have configured a trap
2153 * that we don't know how to handle. This certainly qualifies
2154 * as a gross bug that should be fixed right away.
2155 */
2156 BUG_ON(!r->access);
2157
2158 /* Skip instruction if instructed so */
2159 if (likely(r->access(vcpu, params, r)))
2160 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
2161}
2162
72564016
MZ		 2163/*
2164 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2165 * call the corresponding trap handler.
2166 *
2167 * @params: pointer to the descriptor of the access
2168 * @table: array of trap descriptors
2169 * @num: size of the trap descriptor array
2170 *
2171 * Return 0 if the access has been handled, and -1 if not.
2172 */
2173static int emulate_cp(struct kvm_vcpu *vcpu,
3fec037d 2174 struct sys_reg_params *params,
72564016
MZ		 2175 const struct sys_reg_desc *table,
2176 size_t num)
62a89c44 2177{
72564016 2178 const struct sys_reg_desc *r;
62a89c44 2179
72564016
MZ		 2180 if (!table)
2181 return -1; /* Not handled */
62a89c44 2182
62a89c44 2183 r = find_reg(params, table, num);
62a89c44 2184
72564016 2185 if (r) {
e70b9522
MZ		 2186 perform_access(vcpu, params, r);
2187 return 0;
72564016
MZ		 2188 }
2189
2190 /* Not handled */
2191 return -1;
2192}
2193
2194static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2195 struct sys_reg_params *params)
2196{
2197 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
40c4f8d2 2198 int cp = -1;
72564016
MZ		 2199
2200 switch(hsr_ec) {
c6d01a94
MR		 2201 case ESR_ELx_EC_CP15_32:
2202 case ESR_ELx_EC_CP15_64:
72564016
MZ		 2203 cp = 15;
2204 break;
c6d01a94
MR		 2205 case ESR_ELx_EC_CP14_MR:
2206 case ESR_ELx_EC_CP14_64:
72564016
MZ		 2207 cp = 14;
2208 break;
2209 default:
40c4f8d2 2210 WARN_ON(1);
62a89c44
MZ		 2211 }
2212
bf4b96bb
MR		 2213 print_sys_reg_msg(params,
2214 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2215 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
62a89c44
MZ		 2216 kvm_inject_undefined(vcpu);
2217}
2218
2219/**
7769db90 2220 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
62a89c44
MZ		 2221 * @vcpu: The VCPU pointer
2222 * @run: The kvm_run struct
2223 */
72564016
MZ		 2224static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2225 const struct sys_reg_desc *global,
2226 size_t nr_global,
2227 const struct sys_reg_desc *target_specific,
2228 size_t nr_specific)
62a89c44
MZ		 2229{
2230 struct sys_reg_params params;
2231 u32 hsr = kvm_vcpu_get_hsr(vcpu);
c667186f
MZ		 2232 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2233 int Rt2 = (hsr >> 10) & 0x1f;
62a89c44 2234
2072d29c
MZ		 2235 params.is_aarch32 = true;
2236 params.is_32bit = false;
62a89c44 2237 params.CRm = (hsr >> 1) & 0xf;
62a89c44
MZ		 2238 params.is_write = ((hsr & 1) == 0);
2239
2240 params.Op0 = 0;
2241 params.Op1 = (hsr >> 16) & 0xf;
2242 params.Op2 = 0;
2243 params.CRn = 0;
2244
2245 /*
2ec5be3d 2246 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
62a89c44
MZ		 2247 * backends between AArch32 and AArch64, we get away with it.
2248 */
2249 if (params.is_write) {
2ec5be3d
PF		 2250 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2251 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
62a89c44
MZ		 2252 }
2253
b6b7a806
MZ		 2254 /*
2255 * Try to emulate the coprocessor access using the target
2256 * specific table first, and using the global table afterwards.
2257 * If either of the tables contains a handler, handle the
2258 * potential register operation in the case of a read and return
2259 * with success.
2260 */
2261 if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
2262 !emulate_cp(vcpu, &params, global, nr_global)) {
2263 /* Split up the value between registers for the read side */
2264 if (!params.is_write) {
2265 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2266 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2267 }
62a89c44 2268
b6b7a806 2269 return 1;
62a89c44
MZ		 2270 }
2271
b6b7a806 2272 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 2273 return 1;
2274}
2275
2276/**
7769db90 2277 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
62a89c44
MZ		 2278 * @vcpu: The VCPU pointer
2279 * @run: The kvm_run struct
2280 */
72564016
MZ		 2281static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2282 const struct sys_reg_desc *global,
2283 size_t nr_global,
2284 const struct sys_reg_desc *target_specific,
2285 size_t nr_specific)
62a89c44
MZ		 2286{
2287 struct sys_reg_params params;
2288 u32 hsr = kvm_vcpu_get_hsr(vcpu);
c667186f 2289 int Rt = kvm_vcpu_sys_get_rt(vcpu);
62a89c44 2290
2072d29c
MZ		 2291 params.is_aarch32 = true;
2292 params.is_32bit = true;
62a89c44 2293 params.CRm = (hsr >> 1) & 0xf;
2ec5be3d 2294 params.regval = vcpu_get_reg(vcpu, Rt);
62a89c44
MZ		 2295 params.is_write = ((hsr & 1) == 0);
2296 params.CRn = (hsr >> 10) & 0xf;
2297 params.Op0 = 0;
2298 params.Op1 = (hsr >> 14) & 0x7;
2299 params.Op2 = (hsr >> 17) & 0x7;
2300
2ec5be3d
PF		 2301 if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
2302 !emulate_cp(vcpu, &params, global, nr_global)) {
2303 if (!params.is_write)
2304 vcpu_set_reg(vcpu, Rt, params.regval);
72564016 2305 return 1;
2ec5be3d 2306 }
72564016
MZ		 2307
2308 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 2309 return 1;
2310}
2311
72564016
MZ		 2312int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
2313{
2314 const struct sys_reg_desc *target_specific;
2315 size_t num;
2316
2317 target_specific = get_target_table(vcpu->arch.target, false, &num);
2318 return kvm_handle_cp_64(vcpu,
a9866ba0 2319 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
72564016
MZ		 2320 target_specific, num);
2321}
2322
2323int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
2324{
2325 const struct sys_reg_desc *target_specific;
2326 size_t num;
2327
2328 target_specific = get_target_table(vcpu->arch.target, false, &num);
2329 return kvm_handle_cp_32(vcpu,
2330 cp15_regs, ARRAY_SIZE(cp15_regs),
2331 target_specific, num);
2332}
2333
2334int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
2335{
2336 return kvm_handle_cp_64(vcpu,
a9866ba0 2337 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
72564016
MZ		 2338 NULL, 0);
2339}
2340
2341int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
2342{
2343 return kvm_handle_cp_32(vcpu,
2344 cp14_regs, ARRAY_SIZE(cp14_regs),
2345 NULL, 0);
2346}
2347
54ad68b7
MR		 2348static bool is_imp_def_sys_reg(struct sys_reg_params *params)
2349{
2350 // See ARM DDI 0487E.a, section D12.3.2
2351 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
2352}
2353
7c8c5e6a 2354static int emulate_sys_reg(struct kvm_vcpu *vcpu,
3fec037d 2355 struct sys_reg_params *params)
7c8c5e6a
MZ		 2356{
2357 size_t num;
2358 const struct sys_reg_desc *table, *r;
2359
62a89c44 2360 table = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 2361
2362 /* Search target-specific then generic table. */
2363 r = find_reg(params, table, num);
2364 if (!r)
2365 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2366
2367 if (likely(r)) {
e70b9522 2368 perform_access(vcpu, params, r);
54ad68b7
MR		 2369 } else if (is_imp_def_sys_reg(params)) {
2370 kvm_inject_undefined(vcpu);
7c8c5e6a 2371 } else {
bf4b96bb
MR		 2372 print_sys_reg_msg(params,
2373 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
2374 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
e70b9522 2375 kvm_inject_undefined(vcpu);
7c8c5e6a 2376 }
7c8c5e6a
MZ		 2377 return 1;
2378}
2379
2380static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
03fdfb26
MZ		 2381 const struct sys_reg_desc *table, size_t num,
2382 unsigned long *bmap)
7c8c5e6a
MZ		 2383{
2384 unsigned long i;
2385
2386 for (i = 0; i < num; i++)
03fdfb26
MZ		 2387 if (table[i].reset) {
2388 int reg = table[i].reg;
2389
7c8c5e6a 2390 table[i].reset(vcpu, &table[i]);
03fdfb26
MZ		 2391 if (reg > 0 && reg < NR_SYS_REGS)
2392 set_bit(reg, bmap);
2393 }
7c8c5e6a
MZ		 2394}
2395
2396/**
2397 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2398 * @vcpu: The VCPU pointer
2399 * @run: The kvm_run struct
2400 */
2401int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
2402{
2403 struct sys_reg_params params;
2404 unsigned long esr = kvm_vcpu_get_hsr(vcpu);
c667186f 2405 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2ec5be3d 2406 int ret;
7c8c5e6a 2407
eef8c85a
AB		 2408 trace_kvm_handle_sys_reg(esr);
2409
2072d29c
MZ		 2410 params.is_aarch32 = false;
2411 params.is_32bit = false;
7c8c5e6a
MZ		 2412 params.Op0 = (esr >> 20) & 3;
2413 params.Op1 = (esr >> 14) & 0x7;
2414 params.CRn = (esr >> 10) & 0xf;
2415 params.CRm = (esr >> 1) & 0xf;
2416 params.Op2 = (esr >> 17) & 0x7;
2ec5be3d 2417 params.regval = vcpu_get_reg(vcpu, Rt);
7c8c5e6a
MZ		 2418 params.is_write = !(esr & 1);
2419
2ec5be3d
PF		 2420 ret = emulate_sys_reg(vcpu, &params);
2421
2422 if (!params.is_write)
2423 vcpu_set_reg(vcpu, Rt, params.regval);
2424 return ret;
7c8c5e6a
MZ		 2425}
2426
2427/******************************************************************************
2428 * Userspace API
2429 *****************************************************************************/
2430
2431static bool index_to_params(u64 id, struct sys_reg_params *params)
2432{
2433 switch (id & KVM_REG_SIZE_MASK) {
2434 case KVM_REG_SIZE_U64:
2435 /* Any unused index bits means it's not valid. */
2436 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2437 | KVM_REG_ARM_COPROC_MASK
2438 | KVM_REG_ARM64_SYSREG_OP0_MASK
2439 | KVM_REG_ARM64_SYSREG_OP1_MASK
2440 | KVM_REG_ARM64_SYSREG_CRN_MASK
2441 | KVM_REG_ARM64_SYSREG_CRM_MASK
2442 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2443 return false;
2444 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2445 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2446 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2447 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2448 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2449 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2450 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2451 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2452 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2453 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2454 return true;
2455 default:
2456 return false;
2457 }
2458}
2459
4b927b94
VK		 2460const struct sys_reg_desc *find_reg_by_id(u64 id,
2461 struct sys_reg_params *params,
2462 const struct sys_reg_desc table[],
2463 unsigned int num)
2464{
2465 if (!index_to_params(id, params))
2466 return NULL;
2467
2468 return find_reg(params, table, num);
2469}
2470
7c8c5e6a
MZ		 2471/* Decode an index value, and find the sys_reg_desc entry. */
2472static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2473 u64 id)
2474{
2475 size_t num;
2476 const struct sys_reg_desc *table, *r;
2477 struct sys_reg_params params;
2478
2479 /* We only do sys_reg for now. */
2480 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2481 return NULL;
2482
1ce74e96
WD		 2483 if (!index_to_params(id, &params))
2484 return NULL;
2485
62a89c44 2486 table = get_target_table(vcpu->arch.target, true, &num);
1ce74e96 2487 r = find_reg(&params, table, num);
7c8c5e6a
MZ		 2488 if (!r)
2489 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2490
93390c0a
DM		 2491 /* Not saved in the sys_reg array and not otherwise accessible? */
2492 if (r && !(r->reg || r->get_user))
7c8c5e6a
MZ		 2493 r = NULL;
2494
2495 return r;
2496}
2497
2498/*
2499 * These are the invariant sys_reg registers: we let the guest see the
2500 * host versions of these, so they're part of the guest state.
2501 *
2502 * A future CPU may provide a mechanism to present different values to
2503 * the guest, or a future kvm may trap them.
2504 */
2505
2506#define FUNCTION_INVARIANT(reg) \
2507 static void get_##reg(struct kvm_vcpu *v, \
2508 const struct sys_reg_desc *r) \
2509 { \
1f3d8699 2510 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
7c8c5e6a
MZ		 2511 }
2512
2513FUNCTION_INVARIANT(midr_el1)
7c8c5e6a 2514FUNCTION_INVARIANT(revidr_el1)
7c8c5e6a
MZ		 2515FUNCTION_INVARIANT(clidr_el1)
2516FUNCTION_INVARIANT(aidr_el1)
2517
f7f2b15c
AB		 2518static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2519{
2520 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2521}
2522
7c8c5e6a
MZ		 2523/* ->val is filled in by kvm_sys_reg_table_init() */
2524static struct sys_reg_desc invariant_sys_regs[] = {
0d449541
MR		 2525 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2526 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
0d449541
MR		 2527 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2528 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2529 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
7c8c5e6a
MZ		 2530};
2531
26c99af1 2532static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
7c8c5e6a 2533{
7c8c5e6a
MZ		 2534 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2535 return -EFAULT;
2536 return 0;
2537}
2538
26c99af1 2539static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
7c8c5e6a 2540{
7c8c5e6a
MZ		 2541 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2542 return -EFAULT;
2543 return 0;
2544}
2545
2546static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2547{
2548 struct sys_reg_params params;
2549 const struct sys_reg_desc *r;
2550
4b927b94
VK		 2551 r = find_reg_by_id(id, &params, invariant_sys_regs,
2552 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 2553 if (!r)
2554 return -ENOENT;
2555
2556 return reg_to_user(uaddr, &r->val, id);
2557}
2558
2559static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2560{
2561 struct sys_reg_params params;
2562 const struct sys_reg_desc *r;
2563 int err;
2564 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2565
4b927b94
VK		 2566 r = find_reg_by_id(id, &params, invariant_sys_regs,
2567 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 2568 if (!r)
2569 return -ENOENT;
2570
2571 err = reg_from_user(&val, uaddr, id);
2572 if (err)
2573 return err;
2574
2575 /* This is what we mean by invariant: you can't change it. */
2576 if (r->val != val)
2577 return -EINVAL;
2578
2579 return 0;
2580}
2581
2582static bool is_valid_cache(u32 val)
2583{
2584 u32 level, ctype;
2585
2586 if (val >= CSSELR_MAX)
18d45766 2587 return false;
7c8c5e6a
MZ		 2588
2589 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2590 level = (val >> 1);
2591 ctype = (cache_levels >> (level * 3)) & 7;
2592
2593 switch (ctype) {
2594 case 0: /* No cache */
2595 return false;
2596 case 1: /* Instruction cache only */
2597 return (val & 1);
2598 case 2: /* Data cache only */
2599 case 4: /* Unified cache */
2600 return !(val & 1);
2601 case 3: /* Separate instruction and data caches */
2602 return true;
2603 default: /* Reserved: we can't know instruction or data. */
2604 return false;
2605 }
2606}
2607
2608static int demux_c15_get(u64 id, void __user *uaddr)
2609{
2610 u32 val;
2611 u32 __user *uval = uaddr;
2612
2613 /* Fail if we have unknown bits set. */
2614 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2615 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2616 return -ENOENT;
2617
2618 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2619 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2620 if (KVM_REG_SIZE(id) != 4)
2621 return -ENOENT;
2622 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2623 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2624 if (!is_valid_cache(val))
2625 return -ENOENT;
2626
2627 return put_user(get_ccsidr(val), uval);
2628 default:
2629 return -ENOENT;
2630 }
2631}
2632
2633static int demux_c15_set(u64 id, void __user *uaddr)
2634{
2635 u32 val, newval;
2636 u32 __user *uval = uaddr;
2637
2638 /* Fail if we have unknown bits set. */
2639 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2640 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2641 return -ENOENT;
2642
2643 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2644 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2645 if (KVM_REG_SIZE(id) != 4)
2646 return -ENOENT;
2647 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2648 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2649 if (!is_valid_cache(val))
2650 return -ENOENT;
2651
2652 if (get_user(newval, uval))
2653 return -EFAULT;
2654
2655 /* This is also invariant: you can't change it. */
2656 if (newval != get_ccsidr(val))
2657 return -EINVAL;
2658 return 0;
2659 default:
2660 return -ENOENT;
2661 }
2662}
2663
2664int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2665{
2666 const struct sys_reg_desc *r;
2667 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2668
2669 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2670 return demux_c15_get(reg->id, uaddr);
2671
2672 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2673 return -ENOENT;
2674
2675 r = index_to_sys_reg_desc(vcpu, reg->id);
2676 if (!r)
2677 return get_invariant_sys_reg(reg->id, uaddr);
2678
7f34e409
DM		 2679 /* Check for regs disabled by runtime config */
2680 if (sysreg_hidden_from_user(vcpu, r))
2681 return -ENOENT;
2682
84e690bf
AB		 2683 if (r->get_user)
2684 return (r->get_user)(vcpu, r, reg, uaddr);
2685
8d404c4c 2686 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
7c8c5e6a
MZ		 2687}
2688
2689int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2690{
2691 const struct sys_reg_desc *r;
2692 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2693
2694 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2695 return demux_c15_set(reg->id, uaddr);
2696
2697 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2698 return -ENOENT;
2699
2700 r = index_to_sys_reg_desc(vcpu, reg->id);
2701 if (!r)
2702 return set_invariant_sys_reg(reg->id, uaddr);
2703
7f34e409
DM		 2704 /* Check for regs disabled by runtime config */
2705 if (sysreg_hidden_from_user(vcpu, r))
2706 return -ENOENT;
2707
84e690bf
AB		 2708 if (r->set_user)
2709 return (r->set_user)(vcpu, r, reg, uaddr);
2710
8d404c4c 2711 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
7c8c5e6a
MZ		 2712}
2713
2714static unsigned int num_demux_regs(void)
2715{
2716 unsigned int i, count = 0;
2717
2718 for (i = 0; i < CSSELR_MAX; i++)
2719 if (is_valid_cache(i))
2720 count++;
2721
2722 return count;
2723}
2724
2725static int write_demux_regids(u64 __user *uindices)
2726{
efd48cea 2727 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
7c8c5e6a
MZ		 2728 unsigned int i;
2729
2730 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2731 for (i = 0; i < CSSELR_MAX; i++) {
2732 if (!is_valid_cache(i))
2733 continue;
2734 if (put_user(val | i, uindices))
2735 return -EFAULT;
2736 uindices++;
2737 }
2738 return 0;
2739}
2740
2741static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2742{
2743 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2744 KVM_REG_ARM64_SYSREG |
2745 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2746 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2747 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2748 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2749 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2750}
2751
2752static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2753{
2754 if (!*uind)
2755 return true;
2756
2757 if (put_user(sys_reg_to_index(reg), *uind))
2758 return false;
2759
2760 (*uind)++;
2761 return true;
2762}
2763
7f34e409
DM		 2764static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2765 const struct sys_reg_desc *rd,
93390c0a
DM		 2766 u64 __user **uind,
2767 unsigned int *total)
2768{
2769 /*
2770 * Ignore registers we trap but don't save,
2771 * and for which no custom user accessor is provided.
2772 */
2773 if (!(rd->reg || rd->get_user))
2774 return 0;
2775
7f34e409
DM		 2776 if (sysreg_hidden_from_user(vcpu, rd))
2777 return 0;
2778
93390c0a
DM		 2779 if (!copy_reg_to_user(rd, uind))
2780 return -EFAULT;
2781
2782 (*total)++;
2783 return 0;
2784}
2785
7c8c5e6a
MZ		 2786/* Assumed ordered tables, see kvm_sys_reg_table_init. */
2787static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2788{
2789 const struct sys_reg_desc *i1, *i2, *end1, *end2;
2790 unsigned int total = 0;
2791 size_t num;
93390c0a 2792 int err;
7c8c5e6a
MZ		 2793
2794 /* We check for duplicates here, to allow arch-specific overrides. */
62a89c44 2795 i1 = get_target_table(vcpu->arch.target, true, &num);
7c8c5e6a
MZ		 2796 end1 = i1 + num;
2797 i2 = sys_reg_descs;
2798 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2799
2800 BUG_ON(i1 == end1 || i2 == end2);
2801
2802 /* Walk carefully, as both tables may refer to the same register. */
2803 while (i1 || i2) {
2804 int cmp = cmp_sys_reg(i1, i2);
2805 /* target-specific overrides generic entry. */
93390c0a 2806 if (cmp <= 0)
7f34e409 2807 err = walk_one_sys_reg(vcpu, i1, &uind, &total);
93390c0a 2808 else
7f34e409 2809 err = walk_one_sys_reg(vcpu, i2, &uind, &total);
93390c0a
DM		 2810
2811 if (err)
2812 return err;
7c8c5e6a
MZ		 2813
2814 if (cmp <= 0 && ++i1 == end1)
2815 i1 = NULL;
2816 if (cmp >= 0 && ++i2 == end2)
2817 i2 = NULL;
2818 }
2819 return total;
2820}
2821
2822unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2823{
2824 return ARRAY_SIZE(invariant_sys_regs)
2825 + num_demux_regs()
2826 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2827}
2828
2829int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2830{
2831 unsigned int i;
2832 int err;
2833
2834 /* Then give them all the invariant registers' indices. */
2835 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2836 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2837 return -EFAULT;
2838 uindices++;
2839 }
2840
2841 err = walk_sys_regs(vcpu, uindices);
2842 if (err < 0)
2843 return err;
2844 uindices += err;
2845
2846 return write_demux_regids(uindices);
2847}
2848
e6a95517
MZ		 2849static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2850{
2851 unsigned int i;
2852
2853 for (i = 1; i < n; i++) {
2854 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2855 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2856 return 1;
2857 }
2858 }
2859
2860 return 0;
2861}
2862
7c8c5e6a
MZ		 2863void kvm_sys_reg_table_init(void)
2864{
2865 unsigned int i;
2866 struct sys_reg_desc clidr;
2867
2868 /* Make sure tables are unique and in order. */
e6a95517
MZ		 2869 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2870 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2871 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2872 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2873 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2874 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
7c8c5e6a
MZ		 2875
2876 /* We abuse the reset function to overwrite the table itself. */
2877 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2878 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2879
2880 /*
2881 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2882 *
2883 * If software reads the Cache Type fields from Ctype1
2884 * upwards, once it has seen a value of 0b000, no caches
2885 * exist at further-out levels of the hierarchy. So, for
2886 * example, if Ctype3 is the first Cache Type field with a
2887 * value of 0b000, the values of Ctype4 to Ctype7 must be
2888 * ignored.
2889 */
2890 get_clidr_el1(NULL, &clidr); /* Ugly... */
2891 cache_levels = clidr.val;
2892 for (i = 0; i < 7; i++)
2893 if (((cache_levels >> (i*3)) & 7) == 0)
2894 break;
2895 /* Clear all higher bits. */
2896 cache_levels &= (1 << (i*3))-1;
2897}
2898
2899/**
2900 * kvm_reset_sys_regs - sets system registers to reset value
2901 * @vcpu: The VCPU pointer
2902 *
2903 * This function finds the right table above and sets the registers on the
2904 * virtual CPU struct to their architecturally defined reset values.
2905 */
2906void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2907{
2908 size_t num;
2909 const struct sys_reg_desc *table;
03fdfb26 2910 DECLARE_BITMAP(bmap, NR_SYS_REGS) = { 0, };
7c8c5e6a
MZ		 2911
2912 /* Generic chip reset first (so target could override). */
03fdfb26 2913 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs), bmap);
7c8c5e6a 2914
62a89c44 2915 table = get_target_table(vcpu->arch.target, true, &num);
03fdfb26 2916 reset_sys_reg_descs(vcpu, table, num, bmap);
7c8c5e6a 2917
20589c8c 2918 for (num = 1; num < NR_SYS_REGS; num++) {
03fdfb26 2919 if (WARN(!test_bit(num, bmap),
20589c8c
MZ		 2920 "Didn't reset __vcpu_sys_reg(%zi)\n", num))
2921 break;
2922 }
7c8c5e6a 2923}
Linux 6.x block layer and io_uring tree(s)