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KVM: arm64: Add AArch32 mapping annotation
[linux-2.6-block.git] / arch / arm64 / kvm / sys_regs.c
CommitLineData
caab277b 1// SPDX-License-Identifier: GPL-2.0-only
7c8c5e6a
MZ		 2/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
7c8c5e6a
MZ		 10 */
11
623eefa8 12#include <linux/bsearch.h>
7c8c5e6a 13#include <linux/kvm_host.h>
c6d01a94 14#include <linux/mm.h>
07d79fe7 15#include <linux/printk.h>
7c8c5e6a 16#include <linux/uaccess.h>
c6d01a94 17
7c8c5e6a
MZ		 18#include <asm/cacheflush.h>
19#include <asm/cputype.h>
0c557ed4 20#include <asm/debug-monitors.h>
c6d01a94
MR		 21#include <asm/esr.h>
22#include <asm/kvm_arm.h>
23#include <asm/kvm_coproc.h>
24#include <asm/kvm_emulate.h>
d47533da 25#include <asm/kvm_hyp.h>
c6d01a94 26#include <asm/kvm_mmu.h>
ab946834 27#include <asm/perf_event.h>
1f3d8699 28#include <asm/sysreg.h>
c6d01a94 29
7c8c5e6a
MZ		 30#include <trace/events/kvm.h>
31
32#include "sys_regs.h"
33
eef8c85a
AB		 34#include "trace.h"
35
7c8c5e6a 36/*
656012c7 37 * All of this file is extremely similar to the ARM coproc.c, but the
7c8c5e6a
MZ		 38 * types are different. My gut feeling is that it should be pretty
39 * easy to merge, but that would be an ABI breakage -- again. VFP
40 * would also need to be abstracted.
62a89c44
MZ		 41 *
42 * For AArch32, we only take care of what is being trapped. Anything
43 * that has to do with init and userspace access has to go via the
44 * 64bit interface.
7c8c5e6a
MZ		 45 */
46
7b5b4df1 47static bool read_from_write_only(struct kvm_vcpu *vcpu,
e7f1d1ee
MZ		 48 struct sys_reg_params *params,
49 const struct sys_reg_desc *r)
7b5b4df1
MZ		 50{
51 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
52 print_sys_reg_instr(params);
53 kvm_inject_undefined(vcpu);
54 return false;
55}
56
7b1dba1f
MZ		 57static bool write_to_read_only(struct kvm_vcpu *vcpu,
58 struct sys_reg_params *params,
59 const struct sys_reg_desc *r)
60{
61 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
62 print_sys_reg_instr(params);
63 kvm_inject_undefined(vcpu);
64 return false;
65}
66
7ea90bdd
MZ		 67u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
68{
69 u64 val = 0x8badf00d8badf00d;
70
71 if (vcpu->arch.sysregs_loaded_on_cpu &&
72 __vcpu_read_sys_reg_from_cpu(reg, &val))
73 return val;
74
75 return __vcpu_sys_reg(vcpu, reg);
76}
77
78void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
79{
80 if (vcpu->arch.sysregs_loaded_on_cpu &&
81 __vcpu_write_sys_reg_to_cpu(val, reg))
82 return;
83
d47533da
CD		 84 __vcpu_sys_reg(vcpu, reg) = val;
85}
86
7c8c5e6a
MZ		 87/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
88static u32 cache_levels;
89
90/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
91#define CSSELR_MAX 12
92
93/* Which cache CCSIDR represents depends on CSSELR value. */
94static u32 get_ccsidr(u32 csselr)
95{
96 u32 ccsidr;
97
98 /* Make sure noone else changes CSSELR during this! */
99 local_irq_disable();
1f3d8699 100 write_sysreg(csselr, csselr_el1);
7c8c5e6a 101 isb();
1f3d8699 102 ccsidr = read_sysreg(ccsidr_el1);
7c8c5e6a
MZ		 103 local_irq_enable();
104
105 return ccsidr;
106}
107
3c1e7165
MZ		 108/*
109 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
110 */
7c8c5e6a 111static bool access_dcsw(struct kvm_vcpu *vcpu,
3fec037d 112 struct sys_reg_params *p,
7c8c5e6a
MZ		 113 const struct sys_reg_desc *r)
114{
7c8c5e6a 115 if (!p->is_write)
e7f1d1ee 116 return read_from_write_only(vcpu, p, r);
7c8c5e6a 117
09605e94
MZ		 118 /*
119 * Only track S/W ops if we don't have FWB. It still indicates
120 * that the guest is a bit broken (S/W operations should only
121 * be done by firmware, knowing that there is only a single
122 * CPU left in the system, and certainly not from non-secure
123 * software).
124 */
125 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
126 kvm_set_way_flush(vcpu);
127
7c8c5e6a
MZ		 128 return true;
129}
130
4d44923b
MZ		 131/*
132 * Generic accessor for VM registers. Only called as long as HCR_TVM
3c1e7165
MZ		 133 * is set. If the guest enables the MMU, we stop trapping the VM
134 * sys_regs and leave it in complete control of the caches.
4d44923b
MZ		 135 */
136static bool access_vm_reg(struct kvm_vcpu *vcpu,
3fec037d 137 struct sys_reg_params *p,
4d44923b
MZ		 138 const struct sys_reg_desc *r)
139{
3c1e7165 140 bool was_enabled = vcpu_has_cache_enabled(vcpu);
52f6c4f0
CD		 141 u64 val;
142 int reg = r->reg;
4d44923b
MZ		 143
144 BUG_ON(!p->is_write);
145
52f6c4f0
CD		 146 /* See the 32bit mapping in kvm_host.h */
147 if (p->is_aarch32)
148 reg = r->reg / 2;
149
150 if (!p->is_aarch32 || !p->is_32bit) {
151 val = p->regval;
dedf97e8 152 } else {
8d404c4c 153 val = vcpu_read_sys_reg(vcpu, reg);
52f6c4f0
CD		 154 if (r->reg % 2)
155 val = (p->regval << 32) | (u64)lower_32_bits(val);
156 else
157 val = ((u64)upper_32_bits(val) << 32) |
158 lower_32_bits(p->regval);
dedf97e8 159 }
8d404c4c 160 vcpu_write_sys_reg(vcpu, val, reg);
f0a3eaff 161
3c1e7165 162 kvm_toggle_cache(vcpu, was_enabled);
4d44923b
MZ		 163 return true;
164}
165
af473829
JM		 166static bool access_actlr(struct kvm_vcpu *vcpu,
167 struct sys_reg_params *p,
168 const struct sys_reg_desc *r)
169{
170 if (p->is_write)
171 return ignore_write(vcpu, p);
172
173 p->regval = vcpu_read_sys_reg(vcpu, ACTLR_EL1);
174
175 if (p->is_aarch32) {
176 if (r->Op2 & 2)
177 p->regval = upper_32_bits(p->regval);
178 else
179 p->regval = lower_32_bits(p->regval);
180 }
181
182 return true;
183}
184
6d52f35a
AP		 185/*
186 * Trap handler for the GICv3 SGI generation system register.
187 * Forward the request to the VGIC emulation.
188 * The cp15_64 code makes sure this automatically works
189 * for both AArch64 and AArch32 accesses.
190 */
191static bool access_gic_sgi(struct kvm_vcpu *vcpu,
3fec037d 192 struct sys_reg_params *p,
6d52f35a
AP		 193 const struct sys_reg_desc *r)
194{
03bd646d
MZ		 195 bool g1;
196
6d52f35a 197 if (!p->is_write)
e7f1d1ee 198 return read_from_write_only(vcpu, p, r);
6d52f35a 199
03bd646d
MZ		 200 /*
201 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
202 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
203 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
204 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
205 * group.
206 */
207 if (p->is_aarch32) {
208 switch (p->Op1) {
209 default: /* Keep GCC quiet */
210 case 0: /* ICC_SGI1R */
211 g1 = true;
212 break;
213 case 1: /* ICC_ASGI1R */
214 case 2: /* ICC_SGI0R */
215 g1 = false;
216 break;
217 }
218 } else {
219 switch (p->Op2) {
220 default: /* Keep GCC quiet */
221 case 5: /* ICC_SGI1R_EL1 */
222 g1 = true;
223 break;
224 case 6: /* ICC_ASGI1R_EL1 */
225 case 7: /* ICC_SGI0R_EL1 */
226 g1 = false;
227 break;
228 }
229 }
230
231 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
6d52f35a
AP		 232
233 return true;
234}
235
b34f2bcb
MZ		 236static bool access_gic_sre(struct kvm_vcpu *vcpu,
237 struct sys_reg_params *p,
238 const struct sys_reg_desc *r)
239{
240 if (p->is_write)
241 return ignore_write(vcpu, p);
242
243 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
244 return true;
245}
246
7609c125 247static bool trap_raz_wi(struct kvm_vcpu *vcpu,
3fec037d 248 struct sys_reg_params *p,
7609c125 249 const struct sys_reg_desc *r)
7c8c5e6a
MZ		 250{
251 if (p->is_write)
252 return ignore_write(vcpu, p);
253 else
254 return read_zero(vcpu, p);
255}
256
22925521
MZ		 257/*
258 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
259 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
260 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
261 * treat it separately.
262 */
263static bool trap_loregion(struct kvm_vcpu *vcpu,
264 struct sys_reg_params *p,
265 const struct sys_reg_desc *r)
cc33c4e2 266{
22925521
MZ		 267 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
268 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
269 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
270
271 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
272 kvm_inject_undefined(vcpu);
273 return false;
274 }
275
276 if (p->is_write && sr == SYS_LORID_EL1)
277 return write_to_read_only(vcpu, p, r);
278
279 return trap_raz_wi(vcpu, p, r);
cc33c4e2
MR		 280}
281
0c557ed4 282static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
3fec037d 283 struct sys_reg_params *p,
0c557ed4
MZ		 284 const struct sys_reg_desc *r)
285{
286 if (p->is_write) {
287 return ignore_write(vcpu, p);
288 } else {
2ec5be3d 289 p->regval = (1 << 3);
0c557ed4
MZ		 290 return true;
291 }
292}
293
294static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
3fec037d 295 struct sys_reg_params *p,
0c557ed4
MZ		 296 const struct sys_reg_desc *r)
297{
298 if (p->is_write) {
299 return ignore_write(vcpu, p);
300 } else {
1f3d8699 301 p->regval = read_sysreg(dbgauthstatus_el1);
0c557ed4
MZ		 302 return true;
303 }
304}
305
306/*
307 * We want to avoid world-switching all the DBG registers all the
308 * time:
309 *
310 * - If we've touched any debug register, it is likely that we're
311 * going to touch more of them. It then makes sense to disable the
312 * traps and start doing the save/restore dance
313 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
314 * then mandatory to save/restore the registers, as the guest
315 * depends on them.
316 *
317 * For this, we use a DIRTY bit, indicating the guest has modified the
318 * debug registers, used as follow:
319 *
320 * On guest entry:
321 * - If the dirty bit is set (because we're coming back from trapping),
322 * disable the traps, save host registers, restore guest registers.
323 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
324 * set the dirty bit, disable the traps, save host registers,
325 * restore guest registers.
326 * - Otherwise, enable the traps
327 *
328 * On guest exit:
329 * - If the dirty bit is set, save guest registers, restore host
330 * registers and clear the dirty bit. This ensure that the host can
331 * now use the debug registers.
332 */
333static bool trap_debug_regs(struct kvm_vcpu *vcpu,
3fec037d 334 struct sys_reg_params *p,
0c557ed4
MZ		 335 const struct sys_reg_desc *r)
336{
337 if (p->is_write) {
8d404c4c 338 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
fa89d31c 339 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
0c557ed4 340 } else {
8d404c4c 341 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
0c557ed4
MZ		 342 }
343
2ec5be3d 344 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
eef8c85a 345
0c557ed4
MZ		 346 return true;
347}
348
84e690bf
AB		 349/*
350 * reg_to_dbg/dbg_to_reg
351 *
352 * A 32 bit write to a debug register leave top bits alone
353 * A 32 bit read from a debug register only returns the bottom bits
354 *
355 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
356 * hyp.S code switches between host and guest values in future.
357 */
281243cb
MZ		 358static void reg_to_dbg(struct kvm_vcpu *vcpu,
359 struct sys_reg_params *p,
360 u64 *dbg_reg)
84e690bf 361{
2ec5be3d 362 u64 val = p->regval;
84e690bf
AB		 363
364 if (p->is_32bit) {
365 val &= 0xffffffffUL;
366 val |= ((*dbg_reg >> 32) << 32);
367 }
368
369 *dbg_reg = val;
fa89d31c 370 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
84e690bf
AB		 371}
372
281243cb
MZ		 373static void dbg_to_reg(struct kvm_vcpu *vcpu,
374 struct sys_reg_params *p,
375 u64 *dbg_reg)
84e690bf 376{
2ec5be3d 377 p->regval = *dbg_reg;
84e690bf 378 if (p->is_32bit)
2ec5be3d 379 p->regval &= 0xffffffffUL;
84e690bf
AB		 380}
381
281243cb
MZ		 382static bool trap_bvr(struct kvm_vcpu *vcpu,
383 struct sys_reg_params *p,
384 const struct sys_reg_desc *rd)
84e690bf
AB		 385{
386 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
387
388 if (p->is_write)
389 reg_to_dbg(vcpu, p, dbg_reg);
390 else
391 dbg_to_reg(vcpu, p, dbg_reg);
392
eef8c85a
AB		 393 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
394
84e690bf
AB		 395 return true;
396}
397
398static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
399 const struct kvm_one_reg *reg, void __user *uaddr)
400{
401 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
402
1713e5aa 403 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 404 return -EFAULT;
405 return 0;
406}
407
408static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
409 const struct kvm_one_reg *reg, void __user *uaddr)
410{
411 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
412
413 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
414 return -EFAULT;
415 return 0;
416}
417
281243cb
MZ		 418static void reset_bvr(struct kvm_vcpu *vcpu,
419 const struct sys_reg_desc *rd)
84e690bf
AB		 420{
421 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
422}
423
281243cb
MZ		 424static bool trap_bcr(struct kvm_vcpu *vcpu,
425 struct sys_reg_params *p,
426 const struct sys_reg_desc *rd)
84e690bf
AB		 427{
428 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
429
430 if (p->is_write)
431 reg_to_dbg(vcpu, p, dbg_reg);
432 else
433 dbg_to_reg(vcpu, p, dbg_reg);
434
eef8c85a
AB		 435 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
436
84e690bf
AB		 437 return true;
438}
439
440static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
441 const struct kvm_one_reg *reg, void __user *uaddr)
442{
443 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
444
1713e5aa 445 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 446 return -EFAULT;
447
448 return 0;
449}
450
451static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
452 const struct kvm_one_reg *reg, void __user *uaddr)
453{
454 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
455
456 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
457 return -EFAULT;
458 return 0;
459}
460
281243cb
MZ		 461static void reset_bcr(struct kvm_vcpu *vcpu,
462 const struct sys_reg_desc *rd)
84e690bf
AB		 463{
464 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
465}
466
281243cb
MZ		 467static bool trap_wvr(struct kvm_vcpu *vcpu,
468 struct sys_reg_params *p,
469 const struct sys_reg_desc *rd)
84e690bf
AB		 470{
471 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
472
473 if (p->is_write)
474 reg_to_dbg(vcpu, p, dbg_reg);
475 else
476 dbg_to_reg(vcpu, p, dbg_reg);
477
eef8c85a
AB		 478 trace_trap_reg(__func__, rd->reg, p->is_write,
479 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
480
84e690bf
AB		 481 return true;
482}
483
484static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
485 const struct kvm_one_reg *reg, void __user *uaddr)
486{
487 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
488
1713e5aa 489 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 490 return -EFAULT;
491 return 0;
492}
493
494static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
495 const struct kvm_one_reg *reg, void __user *uaddr)
496{
497 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
498
499 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
500 return -EFAULT;
501 return 0;
502}
503
281243cb
MZ		 504static void reset_wvr(struct kvm_vcpu *vcpu,
505 const struct sys_reg_desc *rd)
84e690bf
AB		 506{
507 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
508}
509
281243cb
MZ		 510static bool trap_wcr(struct kvm_vcpu *vcpu,
511 struct sys_reg_params *p,
512 const struct sys_reg_desc *rd)
84e690bf
AB		 513{
514 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
515
516 if (p->is_write)
517 reg_to_dbg(vcpu, p, dbg_reg);
518 else
519 dbg_to_reg(vcpu, p, dbg_reg);
520
eef8c85a
AB		 521 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
522
84e690bf
AB		 523 return true;
524}
525
526static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
527 const struct kvm_one_reg *reg, void __user *uaddr)
528{
529 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
530
1713e5aa 531 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
84e690bf
AB		 532 return -EFAULT;
533 return 0;
534}
535
536static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
537 const struct kvm_one_reg *reg, void __user *uaddr)
538{
539 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
540
541 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
542 return -EFAULT;
543 return 0;
544}
545
281243cb
MZ		 546static void reset_wcr(struct kvm_vcpu *vcpu,
547 const struct sys_reg_desc *rd)
84e690bf
AB		 548{
549 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
550}
551
7c8c5e6a
MZ		 552static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
553{
8d404c4c
CD		 554 u64 amair = read_sysreg(amair_el1);
555 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
7c8c5e6a
MZ		 556}
557
af473829
JM		 558static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
559{
560 u64 actlr = read_sysreg(actlr_el1);
561 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
562}
563
7c8c5e6a
MZ		 564static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
565{
4429fc64
AP		 566 u64 mpidr;
567
7c8c5e6a 568 /*
4429fc64
AP		 569 * Map the vcpu_id into the first three affinity level fields of
570 * the MPIDR. We limit the number of VCPUs in level 0 due to a
571 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
572 * of the GICv3 to be able to address each CPU directly when
573 * sending IPIs.
7c8c5e6a 574 */
4429fc64
AP		 575 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
576 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
577 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
8d404c4c 578 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
7c8c5e6a
MZ		 579}
580
ab946834
SZ		 581static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
582{
583 u64 pmcr, val;
584
1f3d8699
MR		 585 pmcr = read_sysreg(pmcr_el0);
586 /*
587 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
ab946834
SZ		 588 * except PMCR.E resetting to zero.
589 */
590 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
591 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
6f163714
MZ		 592 if (!system_supports_32bit_el0())
593 val |= ARMV8_PMU_PMCR_LC;
03fdfb26 594 __vcpu_sys_reg(vcpu, r->reg) = val;
ab946834
SZ		 595}
596
6c007036 597static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
d692b8ad 598{
8d404c4c 599 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
6c007036 600 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
d692b8ad 601
24d5950f
MZ		 602 if (!enabled)
603 kvm_inject_undefined(vcpu);
d692b8ad 604
6c007036 605 return !enabled;
d692b8ad
SZ		 606}
607
6c007036 608static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
d692b8ad 609{
6c007036
MZ		 610 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
611}
d692b8ad 612
6c007036
MZ		 613static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
614{
615 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 616}
617
618static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
619{
6c007036 620 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 621}
622
623static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
624{
6c007036 625 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 626}
627
ab946834
SZ		 628static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
629 const struct sys_reg_desc *r)
630{
631 u64 val;
632
633 if (!kvm_arm_pmu_v3_ready(vcpu))
634 return trap_raz_wi(vcpu, p, r);
635
d692b8ad
SZ		 636 if (pmu_access_el0_disabled(vcpu))
637 return false;
638
ab946834
SZ		 639 if (p->is_write) {
640 /* Only update writeable bits of PMCR */
8d404c4c 641 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
ab946834
SZ		 642 val &= ~ARMV8_PMU_PMCR_MASK;
643 val |= p->regval & ARMV8_PMU_PMCR_MASK;
6f163714
MZ		 644 if (!system_supports_32bit_el0())
645 val |= ARMV8_PMU_PMCR_LC;
8d404c4c 646 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
76993739 647 kvm_pmu_handle_pmcr(vcpu, val);
435e53fb 648 kvm_vcpu_pmu_restore_guest(vcpu);
ab946834
SZ		 649 } else {
650 /* PMCR.P & PMCR.C are RAZ */
8d404c4c 651 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
ab946834
SZ		 652 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
653 p->regval = val;
654 }
655
656 return true;
657}
658
3965c3ce
SZ		 659static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
660 const struct sys_reg_desc *r)
661{
662 if (!kvm_arm_pmu_v3_ready(vcpu))
663 return trap_raz_wi(vcpu, p, r);
664
d692b8ad
SZ		 665 if (pmu_access_event_counter_el0_disabled(vcpu))
666 return false;
667
3965c3ce 668 if (p->is_write)
8d404c4c 669 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
3965c3ce
SZ		 670 else
671 /* return PMSELR.SEL field */
8d404c4c 672 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
3965c3ce
SZ		 673 & ARMV8_PMU_COUNTER_MASK;
674
675 return true;
676}
677
a86b5505
SZ		 678static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
679 const struct sys_reg_desc *r)
680{
681 u64 pmceid;
682
683 if (!kvm_arm_pmu_v3_ready(vcpu))
684 return trap_raz_wi(vcpu, p, r);
685
686 BUG_ON(p->is_write);
687
d692b8ad
SZ		 688 if (pmu_access_el0_disabled(vcpu))
689 return false;
690
88865bec 691 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
a86b5505
SZ		 692
693 p->regval = pmceid;
694
695 return true;
696}
697
051ff581
SZ		 698static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
699{
700 u64 pmcr, val;
701
8d404c4c 702 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
051ff581 703 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
24d5950f
MZ		 704 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
705 kvm_inject_undefined(vcpu);
051ff581 706 return false;
24d5950f 707 }
051ff581
SZ		 708
709 return true;
710}
711
712static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
713 struct sys_reg_params *p,
714 const struct sys_reg_desc *r)
715{
716 u64 idx;
717
718 if (!kvm_arm_pmu_v3_ready(vcpu))
719 return trap_raz_wi(vcpu, p, r);
720
721 if (r->CRn == 9 && r->CRm == 13) {
722 if (r->Op2 == 2) {
723 /* PMXEVCNTR_EL0 */
d692b8ad
SZ		 724 if (pmu_access_event_counter_el0_disabled(vcpu))
725 return false;
726
8d404c4c 727 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
051ff581
SZ		 728 & ARMV8_PMU_COUNTER_MASK;
729 } else if (r->Op2 == 0) {
730 /* PMCCNTR_EL0 */
d692b8ad
SZ		 731 if (pmu_access_cycle_counter_el0_disabled(vcpu))
732 return false;
733
051ff581
SZ		 734 idx = ARMV8_PMU_CYCLE_IDX;
735 } else {
9e3f7a29 736 return false;
051ff581 737 }
9e3f7a29
WH		 738 } else if (r->CRn == 0 && r->CRm == 9) {
739 /* PMCCNTR */
740 if (pmu_access_event_counter_el0_disabled(vcpu))
741 return false;
742
743 idx = ARMV8_PMU_CYCLE_IDX;
051ff581
SZ		 744 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
745 /* PMEVCNTRn_EL0 */
d692b8ad
SZ		 746 if (pmu_access_event_counter_el0_disabled(vcpu))
747 return false;
748
051ff581
SZ		 749 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
750 } else {
9e3f7a29 751 return false;
051ff581
SZ		 752 }
753
754 if (!pmu_counter_idx_valid(vcpu, idx))
755 return false;
756
d692b8ad
SZ		 757 if (p->is_write) {
758 if (pmu_access_el0_disabled(vcpu))
759 return false;
760
051ff581 761 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
d692b8ad 762 } else {
051ff581 763 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
d692b8ad 764 }
051ff581
SZ		 765
766 return true;
767}
768
9feb21ac
SZ		 769static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
770 const struct sys_reg_desc *r)
771{
772 u64 idx, reg;
773
774 if (!kvm_arm_pmu_v3_ready(vcpu))
775 return trap_raz_wi(vcpu, p, r);
776
d692b8ad
SZ		 777 if (pmu_access_el0_disabled(vcpu))
778 return false;
779
9feb21ac
SZ		 780 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
781 /* PMXEVTYPER_EL0 */
8d404c4c 782 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
9feb21ac
SZ		 783 reg = PMEVTYPER0_EL0 + idx;
784 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
785 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
786 if (idx == ARMV8_PMU_CYCLE_IDX)
787 reg = PMCCFILTR_EL0;
788 else
789 /* PMEVTYPERn_EL0 */
790 reg = PMEVTYPER0_EL0 + idx;
791 } else {
792 BUG();
793 }
794
795 if (!pmu_counter_idx_valid(vcpu, idx))
796 return false;
797
798 if (p->is_write) {
799 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
8d404c4c 800 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
435e53fb 801 kvm_vcpu_pmu_restore_guest(vcpu);
9feb21ac 802 } else {
8d404c4c 803 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
9feb21ac
SZ		 804 }
805
806 return true;
807}
808
96b0eebc
SZ		 809static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
810 const struct sys_reg_desc *r)
811{
812 u64 val, mask;
813
814 if (!kvm_arm_pmu_v3_ready(vcpu))
815 return trap_raz_wi(vcpu, p, r);
816
d692b8ad
SZ		 817 if (pmu_access_el0_disabled(vcpu))
818 return false;
819
96b0eebc
SZ		 820 mask = kvm_pmu_valid_counter_mask(vcpu);
821 if (p->is_write) {
822 val = p->regval & mask;
823 if (r->Op2 & 0x1) {
824 /* accessing PMCNTENSET_EL0 */
8d404c4c 825 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
418e5ca8 826 kvm_pmu_enable_counter_mask(vcpu, val);
435e53fb 827 kvm_vcpu_pmu_restore_guest(vcpu);
96b0eebc
SZ		 828 } else {
829 /* accessing PMCNTENCLR_EL0 */
8d404c4c 830 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
418e5ca8 831 kvm_pmu_disable_counter_mask(vcpu, val);
96b0eebc
SZ		 832 }
833 } else {
8d404c4c 834 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
96b0eebc
SZ		 835 }
836
837 return true;
838}
839
9db52c78
SZ		 840static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
841 const struct sys_reg_desc *r)
842{
843 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
844
845 if (!kvm_arm_pmu_v3_ready(vcpu))
846 return trap_raz_wi(vcpu, p, r);
847
9008c235
MZ		 848 if (!vcpu_mode_priv(vcpu)) {
849 kvm_inject_undefined(vcpu);
d692b8ad 850 return false;
9008c235 851 }
d692b8ad 852
9db52c78
SZ		 853 if (p->is_write) {
854 u64 val = p->regval & mask;
855
856 if (r->Op2 & 0x1)
857 /* accessing PMINTENSET_EL1 */
8d404c4c 858 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
9db52c78
SZ		 859 else
860 /* accessing PMINTENCLR_EL1 */
8d404c4c 861 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
9db52c78 862 } else {
8d404c4c 863 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
9db52c78
SZ		 864 }
865
866 return true;
867}
868
76d883c4
SZ		 869static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
870 const struct sys_reg_desc *r)
871{
872 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
873
874 if (!kvm_arm_pmu_v3_ready(vcpu))
875 return trap_raz_wi(vcpu, p, r);
876
d692b8ad
SZ		 877 if (pmu_access_el0_disabled(vcpu))
878 return false;
879
76d883c4
SZ		 880 if (p->is_write) {
881 if (r->CRm & 0x2)
882 /* accessing PMOVSSET_EL0 */
8d404c4c 883 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
76d883c4
SZ		 884 else
885 /* accessing PMOVSCLR_EL0 */
8d404c4c 886 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
76d883c4 887 } else {
8d404c4c 888 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
76d883c4
SZ		 889 }
890
891 return true;
892}
893
7a0adc70
SZ		 894static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
895 const struct sys_reg_desc *r)
896{
897 u64 mask;
898
899 if (!kvm_arm_pmu_v3_ready(vcpu))
900 return trap_raz_wi(vcpu, p, r);
901
e0443230 902 if (!p->is_write)
e7f1d1ee 903 return read_from_write_only(vcpu, p, r);
e0443230 904
d692b8ad
SZ		 905 if (pmu_write_swinc_el0_disabled(vcpu))
906 return false;
907
e0443230
MZ		 908 mask = kvm_pmu_valid_counter_mask(vcpu);
909 kvm_pmu_software_increment(vcpu, p->regval & mask);
910 return true;
7a0adc70
SZ		 911}
912
d692b8ad
SZ		 913static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
914 const struct sys_reg_desc *r)
915{
916 if (!kvm_arm_pmu_v3_ready(vcpu))
917 return trap_raz_wi(vcpu, p, r);
918
919 if (p->is_write) {
9008c235
MZ		 920 if (!vcpu_mode_priv(vcpu)) {
921 kvm_inject_undefined(vcpu);
d692b8ad 922 return false;
9008c235 923 }
d692b8ad 924
8d404c4c
CD		 925 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
926 p->regval & ARMV8_PMU_USERENR_MASK;
d692b8ad 927 } else {
8d404c4c 928 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
d692b8ad
SZ		 929 & ARMV8_PMU_USERENR_MASK;
930 }
931
932 return true;
933}
934
09838de9
MZ		 935#define reg_to_encoding(x) \
936 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
937 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2);
938
0c557ed4
MZ		 939/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
940#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
ee1b64e6 941 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
03fdfb26 942 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
ee1b64e6 943 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
03fdfb26 944 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
ee1b64e6 945 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
03fdfb26 946 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
ee1b64e6 947 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
03fdfb26 948 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
0c557ed4 949
051ff581
SZ		 950/* Macro to expand the PMEVCNTRn_EL0 register */
951#define PMU_PMEVCNTR_EL0(n) \
174ed3e4 952 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \
051ff581
SZ		 953 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
954
9feb21ac
SZ		 955/* Macro to expand the PMEVTYPERn_EL0 register */
956#define PMU_PMEVTYPER_EL0(n) \
174ed3e4 957 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \
9feb21ac
SZ		 958 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
959
4fcdf106
IV		 960static bool access_amu(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
961 const struct sys_reg_desc *r)
962{
963 kvm_inject_undefined(vcpu);
964
965 return false;
966}
967
968/* Macro to expand the AMU counter and type registers*/
969#define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), access_amu }
493cf9b7 970#define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), access_amu }
4fcdf106 971#define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), access_amu }
493cf9b7 972#define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), access_amu }
4fcdf106 973
384b40ca
MR		 974static bool trap_ptrauth(struct kvm_vcpu *vcpu,
975 struct sys_reg_params *p,
976 const struct sys_reg_desc *rd)
977{
384b40ca 978 /*
29eb5a3c
MZ		 979 * If we land here, that is because we didn't fixup the access on exit
980 * by allowing the PtrAuth sysregs. The only way this happens is when
981 * the guest does not have PtrAuth support enabled.
384b40ca 982 */
29eb5a3c
MZ		 983 kvm_inject_undefined(vcpu);
984
384b40ca
MR		 985 return false;
986}
987
988static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
989 const struct sys_reg_desc *rd)
990{
991 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN_USER | REG_HIDDEN_GUEST;
992}
993
994#define __PTRAUTH_KEY(k) \
995 { SYS_DESC(SYS_## k), trap_ptrauth, reset_unknown, k, \
996 .visibility = ptrauth_visibility}
997
998#define PTRAUTH_KEY(k) \
999 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1000 __PTRAUTH_KEY(k ## KEYHI_EL1)
1001
84135d3d
AP		 1002static bool access_arch_timer(struct kvm_vcpu *vcpu,
1003 struct sys_reg_params *p,
1004 const struct sys_reg_desc *r)
c9a3c58f 1005{
84135d3d
AP		 1006 enum kvm_arch_timers tmr;
1007 enum kvm_arch_timer_regs treg;
1008 u64 reg = reg_to_encoding(r);
7b6b4631 1009
84135d3d
AP		 1010 switch (reg) {
1011 case SYS_CNTP_TVAL_EL0:
1012 case SYS_AARCH32_CNTP_TVAL:
1013 tmr = TIMER_PTIMER;
1014 treg = TIMER_REG_TVAL;
1015 break;
1016 case SYS_CNTP_CTL_EL0:
1017 case SYS_AARCH32_CNTP_CTL:
1018 tmr = TIMER_PTIMER;
1019 treg = TIMER_REG_CTL;
1020 break;
1021 case SYS_CNTP_CVAL_EL0:
1022 case SYS_AARCH32_CNTP_CVAL:
1023 tmr = TIMER_PTIMER;
1024 treg = TIMER_REG_CVAL;
1025 break;
1026 default:
1027 BUG();
c1b135af 1028 }
7b6b4631 1029
7b6b4631 1030 if (p->is_write)
84135d3d 1031 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
7b6b4631 1032 else
84135d3d 1033 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
7b6b4631 1034
c9a3c58f
JL		 1035 return true;
1036}
1037
93390c0a 1038/* Read a sanitised cpufeature ID register by sys_reg_desc */
1c199913
DM		 1039static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1040 struct sys_reg_desc const *r, bool raz)
93390c0a
DM		 1041{
1042 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1043 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
07d79fe7 1044 u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
93390c0a 1045
4fcdf106
IV		 1046 if (id == SYS_ID_AA64PFR0_EL1) {
1047 if (!vcpu_has_sve(vcpu))
1048 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
1049 val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
e1026237
MZ		 1050 if (!(val & (0xfUL << ID_AA64PFR0_CSV2_SHIFT)) &&
1051 arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED)
1052 val |= (1UL << ID_AA64PFR0_CSV2_SHIFT);
2ac638fc
CM		 1053 } else if (id == SYS_ID_AA64PFR1_EL1) {
1054 val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT);
384b40ca 1055 } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
9eecfc22
KM		 1056 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
1057 (0xfUL << ID_AA64ISAR1_API_SHIFT) |
1058 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
1059 (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
c854188e
AM		 1060 } else if (id == SYS_ID_AA64DFR0_EL1) {
1061 /* Limit guests to PMUv3 for ARMv8.1 */
1062 val = cpuid_feature_cap_perfmon_field(val,
1063 ID_AA64DFR0_PMUVER_SHIFT,
1064 ID_AA64DFR0_PMUVER_8_1);
1065 } else if (id == SYS_ID_DFR0_EL1) {
1066 /* Limit guests to PMUv3 for ARMv8.1 */
1067 val = cpuid_feature_cap_perfmon_field(val,
1068 ID_DFR0_PERFMON_SHIFT,
1069 ID_DFR0_PERFMON_8_1);
07d79fe7
DM		 1070 }
1071
1072 return val;
93390c0a
DM		 1073}
1074
1075/* cpufeature ID register access trap handlers */
1076
1077static bool __access_id_reg(struct kvm_vcpu *vcpu,
1078 struct sys_reg_params *p,
1079 const struct sys_reg_desc *r,
1080 bool raz)
1081{
1082 if (p->is_write)
1083 return write_to_read_only(vcpu, p, r);
1084
1c199913 1085 p->regval = read_id_reg(vcpu, r, raz);
93390c0a
DM		 1086 return true;
1087}
1088
1089static bool access_id_reg(struct kvm_vcpu *vcpu,
1090 struct sys_reg_params *p,
1091 const struct sys_reg_desc *r)
1092{
1093 return __access_id_reg(vcpu, p, r, false);
1094}
1095
1096static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1097 struct sys_reg_params *p,
1098 const struct sys_reg_desc *r)
1099{
1100 return __access_id_reg(vcpu, p, r, true);
1101}
1102
1103static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1104static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1105static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1106
73433762
DM		 1107/* Visibility overrides for SVE-specific control registers */
1108static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1109 const struct sys_reg_desc *rd)
1110{
1111 if (vcpu_has_sve(vcpu))
1112 return 0;
1113
1114 return REG_HIDDEN_USER | REG_HIDDEN_GUEST;
1115}
1116
1117/* Visibility overrides for SVE-specific ID registers */
1118static unsigned int sve_id_visibility(const struct kvm_vcpu *vcpu,
1119 const struct sys_reg_desc *rd)
1120{
1121 if (vcpu_has_sve(vcpu))
1122 return 0;
1123
1124 return REG_HIDDEN_USER;
1125}
1126
1127/* Generate the emulated ID_AA64ZFR0_EL1 value exposed to the guest */
1128static u64 guest_id_aa64zfr0_el1(const struct kvm_vcpu *vcpu)
1129{
1130 if (!vcpu_has_sve(vcpu))
1131 return 0;
1132
1133 return read_sanitised_ftr_reg(SYS_ID_AA64ZFR0_EL1);
1134}
1135
1136static bool access_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1137 struct sys_reg_params *p,
1138 const struct sys_reg_desc *rd)
1139{
1140 if (p->is_write)
1141 return write_to_read_only(vcpu, p, rd);
1142
1143 p->regval = guest_id_aa64zfr0_el1(vcpu);
1144 return true;
1145}
1146
1147static int get_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1148 const struct sys_reg_desc *rd,
1149 const struct kvm_one_reg *reg, void __user *uaddr)
1150{
1151 u64 val;
1152
700698a8 1153 if (WARN_ON(!vcpu_has_sve(vcpu)))
73433762
DM		 1154 return -ENOENT;
1155
1156 val = guest_id_aa64zfr0_el1(vcpu);
1157 return reg_to_user(uaddr, &val, reg->id);
1158}
1159
1160static int set_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1161 const struct sys_reg_desc *rd,
1162 const struct kvm_one_reg *reg, void __user *uaddr)
1163{
1164 const u64 id = sys_reg_to_index(rd);
1165 int err;
1166 u64 val;
1167
700698a8 1168 if (WARN_ON(!vcpu_has_sve(vcpu)))
73433762
DM		 1169 return -ENOENT;
1170
1171 err = reg_from_user(&val, uaddr, id);
1172 if (err)
1173 return err;
1174
1175 /* This is what we mean by invariant: you can't change it. */
1176 if (val != guest_id_aa64zfr0_el1(vcpu))
1177 return -EINVAL;
1178
1179 return 0;
1180}
1181
93390c0a
DM		 1182/*
1183 * cpufeature ID register user accessors
1184 *
1185 * For now, these registers are immutable for userspace, so no values
1186 * are stored, and for set_id_reg() we don't allow the effective value
1187 * to be changed.
1188 */
1c199913
DM		 1189static int __get_id_reg(const struct kvm_vcpu *vcpu,
1190 const struct sys_reg_desc *rd, void __user *uaddr,
93390c0a
DM		 1191 bool raz)
1192{
1193 const u64 id = sys_reg_to_index(rd);
1c199913 1194 const u64 val = read_id_reg(vcpu, rd, raz);
93390c0a
DM		 1195
1196 return reg_to_user(uaddr, &val, id);
1197}
1198
1c199913
DM		 1199static int __set_id_reg(const struct kvm_vcpu *vcpu,
1200 const struct sys_reg_desc *rd, void __user *uaddr,
93390c0a
DM		 1201 bool raz)
1202{
1203 const u64 id = sys_reg_to_index(rd);
1204 int err;
1205 u64 val;
1206
1207 err = reg_from_user(&val, uaddr, id);
1208 if (err)
1209 return err;
1210
1211 /* This is what we mean by invariant: you can't change it. */
1c199913 1212 if (val != read_id_reg(vcpu, rd, raz))
93390c0a
DM		 1213 return -EINVAL;
1214
1215 return 0;
1216}
1217
1218static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1219 const struct kvm_one_reg *reg, void __user *uaddr)
1220{
1c199913 1221 return __get_id_reg(vcpu, rd, uaddr, false);
93390c0a
DM		 1222}
1223
1224static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1225 const struct kvm_one_reg *reg, void __user *uaddr)
1226{
1c199913 1227 return __set_id_reg(vcpu, rd, uaddr, false);
93390c0a
DM		 1228}
1229
1230static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1231 const struct kvm_one_reg *reg, void __user *uaddr)
1232{
1c199913 1233 return __get_id_reg(vcpu, rd, uaddr, true);
93390c0a
DM		 1234}
1235
1236static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1237 const struct kvm_one_reg *reg, void __user *uaddr)
1238{
1c199913 1239 return __set_id_reg(vcpu, rd, uaddr, true);
93390c0a
DM		 1240}
1241
f7f2b15c
AB		 1242static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1243 const struct sys_reg_desc *r)
1244{
1245 if (p->is_write)
1246 return write_to_read_only(vcpu, p, r);
1247
1248 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1249 return true;
1250}
1251
1252static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1253 const struct sys_reg_desc *r)
1254{
1255 if (p->is_write)
1256 return write_to_read_only(vcpu, p, r);
1257
1258 p->regval = read_sysreg(clidr_el1);
1259 return true;
1260}
1261
1262static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1263 const struct sys_reg_desc *r)
1264{
7c582bf4
JM		 1265 int reg = r->reg;
1266
1267 /* See the 32bit mapping in kvm_host.h */
1268 if (p->is_aarch32)
1269 reg = r->reg / 2;
1270
f7f2b15c 1271 if (p->is_write)
7c582bf4 1272 vcpu_write_sys_reg(vcpu, p->regval, reg);
f7f2b15c 1273 else
7c582bf4 1274 p->regval = vcpu_read_sys_reg(vcpu, reg);
f7f2b15c
AB		 1275 return true;
1276}
1277
1278static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1279 const struct sys_reg_desc *r)
1280{
1281 u32 csselr;
1282
1283 if (p->is_write)
1284 return write_to_read_only(vcpu, p, r);
1285
1286 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1287 p->regval = get_ccsidr(csselr);
793acf87
AB		 1288
1289 /*
1290 * Guests should not be doing cache operations by set/way at all, and
1291 * for this reason, we trap them and attempt to infer the intent, so
1292 * that we can flush the entire guest's address space at the appropriate
1293 * time.
1294 * To prevent this trapping from causing performance problems, let's
1295 * expose the geometry of all data and unified caches (which are
1296 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1297 * [If guests should attempt to infer aliasing properties from the
1298 * geometry (which is not permitted by the architecture), they would
1299 * only do so for virtually indexed caches.]
1300 */
1301 if (!(csselr & 1)) // data or unified cache
1302 p->regval &= ~GENMASK(27, 3);
f7f2b15c
AB		 1303 return true;
1304}
1305
2ac638fc
CM		 1306static bool access_mte_regs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1307 const struct sys_reg_desc *r)
1308{
1309 kvm_inject_undefined(vcpu);
1310 return false;
1311}
1312
93390c0a
DM		 1313/* sys_reg_desc initialiser for known cpufeature ID registers */
1314#define ID_SANITISED(name) { \
1315 SYS_DESC(SYS_##name), \
1316 .access = access_id_reg, \
1317 .get_user = get_id_reg, \
1318 .set_user = set_id_reg, \
1319}
1320
1321/*
1322 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1323 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1324 * (1 <= crm < 8, 0 <= Op2 < 8).
1325 */
1326#define ID_UNALLOCATED(crm, op2) { \
1327 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1328 .access = access_raz_id_reg, \
1329 .get_user = get_raz_id_reg, \
1330 .set_user = set_raz_id_reg, \
1331}
1332
1333/*
1334 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1335 * For now, these are exposed just like unallocated ID regs: they appear
1336 * RAZ for the guest.
1337 */
1338#define ID_HIDDEN(name) { \
1339 SYS_DESC(SYS_##name), \
1340 .access = access_raz_id_reg, \
1341 .get_user = get_raz_id_reg, \
1342 .set_user = set_raz_id_reg, \
1343}
1344
7c8c5e6a
MZ		 1345/*
1346 * Architected system registers.
1347 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
7609c125 1348 *
0c557ed4
MZ		 1349 * Debug handling: We do trap most, if not all debug related system
1350 * registers. The implementation is good enough to ensure that a guest
1351 * can use these with minimal performance degradation. The drawback is
1352 * that we don't implement any of the external debug, none of the
1353 * OSlock protocol. This should be revisited if we ever encounter a
1354 * more demanding guest...
7c8c5e6a
MZ		 1355 */
1356static const struct sys_reg_desc sys_reg_descs[] = {
7606e078
MR		 1357 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1358 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1359 { SYS_DESC(SYS_DC_CISW), access_dcsw },
7c8c5e6a 1360
0c557ed4
MZ		 1361 DBG_BCR_BVR_WCR_WVR_EL1(0),
1362 DBG_BCR_BVR_WCR_WVR_EL1(1),
ee1b64e6
MR		 1363 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1364 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
0c557ed4
MZ		 1365 DBG_BCR_BVR_WCR_WVR_EL1(2),
1366 DBG_BCR_BVR_WCR_WVR_EL1(3),
1367 DBG_BCR_BVR_WCR_WVR_EL1(4),
1368 DBG_BCR_BVR_WCR_WVR_EL1(5),
1369 DBG_BCR_BVR_WCR_WVR_EL1(6),
1370 DBG_BCR_BVR_WCR_WVR_EL1(7),
1371 DBG_BCR_BVR_WCR_WVR_EL1(8),
1372 DBG_BCR_BVR_WCR_WVR_EL1(9),
1373 DBG_BCR_BVR_WCR_WVR_EL1(10),
1374 DBG_BCR_BVR_WCR_WVR_EL1(11),
1375 DBG_BCR_BVR_WCR_WVR_EL1(12),
1376 DBG_BCR_BVR_WCR_WVR_EL1(13),
1377 DBG_BCR_BVR_WCR_WVR_EL1(14),
1378 DBG_BCR_BVR_WCR_WVR_EL1(15),
1379
ee1b64e6
MR		 1380 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1381 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1382 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1383 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1384 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1385 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1386 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1387 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1388
1389 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1390 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1391 // DBGDTR[TR]X_EL0 share the same encoding
1392 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1393
1394 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
62a89c44 1395
851050a5 1396 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
93390c0a
DM		 1397
1398 /*
1399 * ID regs: all ID_SANITISED() entries here must have corresponding
1400 * entries in arm64_ftr_regs[].
1401 */
1402
1403 /* AArch64 mappings of the AArch32 ID registers */
1404 /* CRm=1 */
1405 ID_SANITISED(ID_PFR0_EL1),
1406 ID_SANITISED(ID_PFR1_EL1),
1407 ID_SANITISED(ID_DFR0_EL1),
1408 ID_HIDDEN(ID_AFR0_EL1),
1409 ID_SANITISED(ID_MMFR0_EL1),
1410 ID_SANITISED(ID_MMFR1_EL1),
1411 ID_SANITISED(ID_MMFR2_EL1),
1412 ID_SANITISED(ID_MMFR3_EL1),
1413
1414 /* CRm=2 */
1415 ID_SANITISED(ID_ISAR0_EL1),
1416 ID_SANITISED(ID_ISAR1_EL1),
1417 ID_SANITISED(ID_ISAR2_EL1),
1418 ID_SANITISED(ID_ISAR3_EL1),
1419 ID_SANITISED(ID_ISAR4_EL1),
1420 ID_SANITISED(ID_ISAR5_EL1),
1421 ID_SANITISED(ID_MMFR4_EL1),
8e3747be 1422 ID_SANITISED(ID_ISAR6_EL1),
93390c0a
DM		 1423
1424 /* CRm=3 */
1425 ID_SANITISED(MVFR0_EL1),
1426 ID_SANITISED(MVFR1_EL1),
1427 ID_SANITISED(MVFR2_EL1),
1428 ID_UNALLOCATED(3,3),
16824085 1429 ID_SANITISED(ID_PFR2_EL1),
dd35ec07 1430 ID_HIDDEN(ID_DFR1_EL1),
152accf8 1431 ID_SANITISED(ID_MMFR5_EL1),
93390c0a
DM		 1432 ID_UNALLOCATED(3,7),
1433
1434 /* AArch64 ID registers */
1435 /* CRm=4 */
1436 ID_SANITISED(ID_AA64PFR0_EL1),
1437 ID_SANITISED(ID_AA64PFR1_EL1),
1438 ID_UNALLOCATED(4,2),
1439 ID_UNALLOCATED(4,3),
73433762 1440 { SYS_DESC(SYS_ID_AA64ZFR0_EL1), access_id_aa64zfr0_el1, .get_user = get_id_aa64zfr0_el1, .set_user = set_id_aa64zfr0_el1, .visibility = sve_id_visibility },
93390c0a
DM		 1441 ID_UNALLOCATED(4,5),
1442 ID_UNALLOCATED(4,6),
1443 ID_UNALLOCATED(4,7),
1444
1445 /* CRm=5 */
1446 ID_SANITISED(ID_AA64DFR0_EL1),
1447 ID_SANITISED(ID_AA64DFR1_EL1),
1448 ID_UNALLOCATED(5,2),
1449 ID_UNALLOCATED(5,3),
1450 ID_HIDDEN(ID_AA64AFR0_EL1),
1451 ID_HIDDEN(ID_AA64AFR1_EL1),
1452 ID_UNALLOCATED(5,6),
1453 ID_UNALLOCATED(5,7),
1454
1455 /* CRm=6 */
1456 ID_SANITISED(ID_AA64ISAR0_EL1),
1457 ID_SANITISED(ID_AA64ISAR1_EL1),
1458 ID_UNALLOCATED(6,2),
1459 ID_UNALLOCATED(6,3),
1460 ID_UNALLOCATED(6,4),
1461 ID_UNALLOCATED(6,5),
1462 ID_UNALLOCATED(6,6),
1463 ID_UNALLOCATED(6,7),
1464
1465 /* CRm=7 */
1466 ID_SANITISED(ID_AA64MMFR0_EL1),
1467 ID_SANITISED(ID_AA64MMFR1_EL1),
1468 ID_SANITISED(ID_AA64MMFR2_EL1),
1469 ID_UNALLOCATED(7,3),
1470 ID_UNALLOCATED(7,4),
1471 ID_UNALLOCATED(7,5),
1472 ID_UNALLOCATED(7,6),
1473 ID_UNALLOCATED(7,7),
1474
851050a5 1475 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
af473829 1476 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
851050a5 1477 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
2ac638fc
CM		 1478
1479 { SYS_DESC(SYS_RGSR_EL1), access_mte_regs },
1480 { SYS_DESC(SYS_GCR_EL1), access_mte_regs },
1481
73433762 1482 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
851050a5
MR		 1483 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1484 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1485 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1486
384b40ca
MR		 1487 PTRAUTH_KEY(APIA),
1488 PTRAUTH_KEY(APIB),
1489 PTRAUTH_KEY(APDA),
1490 PTRAUTH_KEY(APDB),
1491 PTRAUTH_KEY(APGA),
1492
851050a5
MR		 1493 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1494 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1495 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
558daf69
DG		 1496
1497 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1498 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1499 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1500 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1501 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1502 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1503 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1504 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1505
2ac638fc
CM		 1506 { SYS_DESC(SYS_TFSR_EL1), access_mte_regs },
1507 { SYS_DESC(SYS_TFSRE0_EL1), access_mte_regs },
1508
851050a5
MR		 1509 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1510 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
7c8c5e6a 1511
174ed3e4 1512 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
7ccadf23 1513 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
7c8c5e6a 1514
851050a5
MR		 1515 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1516 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
7c8c5e6a 1517
22925521
MZ		 1518 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1519 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1520 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1521 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1522 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
cc33c4e2 1523
851050a5 1524 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
c773ae2b 1525 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
db7dedd0 1526
7b1dba1f 1527 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
e7f1d1ee 1528 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
7b1dba1f 1529 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
e7f1d1ee 1530 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
7b1dba1f 1531 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
e804d208 1532 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
03bd646d
MZ		 1533 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1534 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
7b1dba1f 1535 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
e7f1d1ee 1536 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
7b1dba1f 1537 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
e804d208 1538 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
db7dedd0 1539
851050a5
MR		 1540 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1541 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
7c8c5e6a 1542
851050a5 1543 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
7c8c5e6a 1544
f7f2b15c
AB		 1545 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1546 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1547 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1548 { SYS_DESC(SYS_CTR_EL0), access_ctr },
7c8c5e6a 1549
03fdfb26 1550 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 },
174ed3e4 1551 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
7ccadf23
MZ		 1552 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1553 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
174ed3e4
MR		 1554 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
1555 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
1556 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
1557 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
1558 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1559 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
1560 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
1561 /*
1562 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
d692b8ad
SZ		 1563 * in 32bit mode. Here we choose to reset it as zero for consistency.
1564 */
174ed3e4
MR		 1565 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1566 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
7c8c5e6a 1567
851050a5
MR		 1568 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1569 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
4fcdf106
IV		 1570
1571 { SYS_DESC(SYS_AMCR_EL0), access_amu },
1572 { SYS_DESC(SYS_AMCFGR_EL0), access_amu },
1573 { SYS_DESC(SYS_AMCGCR_EL0), access_amu },
1574 { SYS_DESC(SYS_AMUSERENR_EL0), access_amu },
1575 { SYS_DESC(SYS_AMCNTENCLR0_EL0), access_amu },
1576 { SYS_DESC(SYS_AMCNTENSET0_EL0), access_amu },
1577 { SYS_DESC(SYS_AMCNTENCLR1_EL0), access_amu },
1578 { SYS_DESC(SYS_AMCNTENSET1_EL0), access_amu },
1579 AMU_AMEVCNTR0_EL0(0),
1580 AMU_AMEVCNTR0_EL0(1),
1581 AMU_AMEVCNTR0_EL0(2),
1582 AMU_AMEVCNTR0_EL0(3),
1583 AMU_AMEVCNTR0_EL0(4),
1584 AMU_AMEVCNTR0_EL0(5),
1585 AMU_AMEVCNTR0_EL0(6),
1586 AMU_AMEVCNTR0_EL0(7),
1587 AMU_AMEVCNTR0_EL0(8),
1588 AMU_AMEVCNTR0_EL0(9),
1589 AMU_AMEVCNTR0_EL0(10),
1590 AMU_AMEVCNTR0_EL0(11),
1591 AMU_AMEVCNTR0_EL0(12),
1592 AMU_AMEVCNTR0_EL0(13),
1593 AMU_AMEVCNTR0_EL0(14),
1594 AMU_AMEVCNTR0_EL0(15),
493cf9b7
VM		 1595 AMU_AMEVTYPER0_EL0(0),
1596 AMU_AMEVTYPER0_EL0(1),
1597 AMU_AMEVTYPER0_EL0(2),
1598 AMU_AMEVTYPER0_EL0(3),
1599 AMU_AMEVTYPER0_EL0(4),
1600 AMU_AMEVTYPER0_EL0(5),
1601 AMU_AMEVTYPER0_EL0(6),
1602 AMU_AMEVTYPER0_EL0(7),
1603 AMU_AMEVTYPER0_EL0(8),
1604 AMU_AMEVTYPER0_EL0(9),
1605 AMU_AMEVTYPER0_EL0(10),
1606 AMU_AMEVTYPER0_EL0(11),
1607 AMU_AMEVTYPER0_EL0(12),
1608 AMU_AMEVTYPER0_EL0(13),
1609 AMU_AMEVTYPER0_EL0(14),
1610 AMU_AMEVTYPER0_EL0(15),
4fcdf106
IV		 1611 AMU_AMEVCNTR1_EL0(0),
1612 AMU_AMEVCNTR1_EL0(1),
1613 AMU_AMEVCNTR1_EL0(2),
1614 AMU_AMEVCNTR1_EL0(3),
1615 AMU_AMEVCNTR1_EL0(4),
1616 AMU_AMEVCNTR1_EL0(5),
1617 AMU_AMEVCNTR1_EL0(6),
1618 AMU_AMEVCNTR1_EL0(7),
1619 AMU_AMEVCNTR1_EL0(8),
1620 AMU_AMEVCNTR1_EL0(9),
1621 AMU_AMEVCNTR1_EL0(10),
1622 AMU_AMEVCNTR1_EL0(11),
1623 AMU_AMEVCNTR1_EL0(12),
1624 AMU_AMEVCNTR1_EL0(13),
1625 AMU_AMEVCNTR1_EL0(14),
1626 AMU_AMEVCNTR1_EL0(15),
493cf9b7
VM		 1627 AMU_AMEVTYPER1_EL0(0),
1628 AMU_AMEVTYPER1_EL0(1),
1629 AMU_AMEVTYPER1_EL0(2),
1630 AMU_AMEVTYPER1_EL0(3),
1631 AMU_AMEVTYPER1_EL0(4),
1632 AMU_AMEVTYPER1_EL0(5),
1633 AMU_AMEVTYPER1_EL0(6),
1634 AMU_AMEVTYPER1_EL0(7),
1635 AMU_AMEVTYPER1_EL0(8),
1636 AMU_AMEVTYPER1_EL0(9),
1637 AMU_AMEVTYPER1_EL0(10),
1638 AMU_AMEVTYPER1_EL0(11),
1639 AMU_AMEVTYPER1_EL0(12),
1640 AMU_AMEVTYPER1_EL0(13),
1641 AMU_AMEVTYPER1_EL0(14),
1642 AMU_AMEVTYPER1_EL0(15),
62a89c44 1643
84135d3d
AP		 1644 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1645 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1646 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
c9a3c58f 1647
051ff581
SZ		 1648 /* PMEVCNTRn_EL0 */
1649 PMU_PMEVCNTR_EL0(0),
1650 PMU_PMEVCNTR_EL0(1),
1651 PMU_PMEVCNTR_EL0(2),
1652 PMU_PMEVCNTR_EL0(3),
1653 PMU_PMEVCNTR_EL0(4),
1654 PMU_PMEVCNTR_EL0(5),
1655 PMU_PMEVCNTR_EL0(6),
1656 PMU_PMEVCNTR_EL0(7),
1657 PMU_PMEVCNTR_EL0(8),
1658 PMU_PMEVCNTR_EL0(9),
1659 PMU_PMEVCNTR_EL0(10),
1660 PMU_PMEVCNTR_EL0(11),
1661 PMU_PMEVCNTR_EL0(12),
1662 PMU_PMEVCNTR_EL0(13),
1663 PMU_PMEVCNTR_EL0(14),
1664 PMU_PMEVCNTR_EL0(15),
1665 PMU_PMEVCNTR_EL0(16),
1666 PMU_PMEVCNTR_EL0(17),
1667 PMU_PMEVCNTR_EL0(18),
1668 PMU_PMEVCNTR_EL0(19),
1669 PMU_PMEVCNTR_EL0(20),
1670 PMU_PMEVCNTR_EL0(21),
1671 PMU_PMEVCNTR_EL0(22),
1672 PMU_PMEVCNTR_EL0(23),
1673 PMU_PMEVCNTR_EL0(24),
1674 PMU_PMEVCNTR_EL0(25),
1675 PMU_PMEVCNTR_EL0(26),
1676 PMU_PMEVCNTR_EL0(27),
1677 PMU_PMEVCNTR_EL0(28),
1678 PMU_PMEVCNTR_EL0(29),
1679 PMU_PMEVCNTR_EL0(30),
9feb21ac
SZ		 1680 /* PMEVTYPERn_EL0 */
1681 PMU_PMEVTYPER_EL0(0),
1682 PMU_PMEVTYPER_EL0(1),
1683 PMU_PMEVTYPER_EL0(2),
1684 PMU_PMEVTYPER_EL0(3),
1685 PMU_PMEVTYPER_EL0(4),
1686 PMU_PMEVTYPER_EL0(5),
1687 PMU_PMEVTYPER_EL0(6),
1688 PMU_PMEVTYPER_EL0(7),
1689 PMU_PMEVTYPER_EL0(8),
1690 PMU_PMEVTYPER_EL0(9),
1691 PMU_PMEVTYPER_EL0(10),
1692 PMU_PMEVTYPER_EL0(11),
1693 PMU_PMEVTYPER_EL0(12),
1694 PMU_PMEVTYPER_EL0(13),
1695 PMU_PMEVTYPER_EL0(14),
1696 PMU_PMEVTYPER_EL0(15),
1697 PMU_PMEVTYPER_EL0(16),
1698 PMU_PMEVTYPER_EL0(17),
1699 PMU_PMEVTYPER_EL0(18),
1700 PMU_PMEVTYPER_EL0(19),
1701 PMU_PMEVTYPER_EL0(20),
1702 PMU_PMEVTYPER_EL0(21),
1703 PMU_PMEVTYPER_EL0(22),
1704 PMU_PMEVTYPER_EL0(23),
1705 PMU_PMEVTYPER_EL0(24),
1706 PMU_PMEVTYPER_EL0(25),
1707 PMU_PMEVTYPER_EL0(26),
1708 PMU_PMEVTYPER_EL0(27),
1709 PMU_PMEVTYPER_EL0(28),
1710 PMU_PMEVTYPER_EL0(29),
1711 PMU_PMEVTYPER_EL0(30),
174ed3e4
MR		 1712 /*
1713 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
9feb21ac
SZ		 1714 * in 32bit mode. Here we choose to reset it as zero for consistency.
1715 */
174ed3e4 1716 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
051ff581 1717
851050a5
MR		 1718 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1719 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
c88b0936 1720 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
62a89c44
MZ		 1721};
1722
bdfb4b38 1723static bool trap_dbgidr(struct kvm_vcpu *vcpu,
3fec037d 1724 struct sys_reg_params *p,
bdfb4b38
MZ		 1725 const struct sys_reg_desc *r)
1726{
1727 if (p->is_write) {
1728 return ignore_write(vcpu, p);
1729 } else {
46823dd1
DM		 1730 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1731 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
28c5dcb2 1732 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
bdfb4b38 1733
2ec5be3d
PF		 1734 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1735 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1736 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1737 | (6 << 16) | (el3 << 14) | (el3 << 12));
bdfb4b38
MZ		 1738 return true;
1739 }
1740}
1741
1742static bool trap_debug32(struct kvm_vcpu *vcpu,
3fec037d 1743 struct sys_reg_params *p,
bdfb4b38
MZ		 1744 const struct sys_reg_desc *r)
1745{
1746 if (p->is_write) {
2ec5be3d 1747 vcpu_cp14(vcpu, r->reg) = p->regval;
fa89d31c 1748 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
bdfb4b38 1749 } else {
2ec5be3d 1750 p->regval = vcpu_cp14(vcpu, r->reg);
bdfb4b38
MZ		 1751 }
1752
1753 return true;
1754}
1755
84e690bf
AB		 1756/* AArch32 debug register mappings
1757 *
1758 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1759 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1760 *
1761 * All control registers and watchpoint value registers are mapped to
1762 * the lower 32 bits of their AArch64 equivalents. We share the trap
1763 * handlers with the above AArch64 code which checks what mode the
1764 * system is in.
1765 */
1766
281243cb
MZ		 1767static bool trap_xvr(struct kvm_vcpu *vcpu,
1768 struct sys_reg_params *p,
1769 const struct sys_reg_desc *rd)
84e690bf
AB		 1770{
1771 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1772
1773 if (p->is_write) {
1774 u64 val = *dbg_reg;
1775
1776 val &= 0xffffffffUL;
2ec5be3d 1777 val |= p->regval << 32;
84e690bf
AB		 1778 *dbg_reg = val;
1779
fa89d31c 1780 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
84e690bf 1781 } else {
2ec5be3d 1782 p->regval = *dbg_reg >> 32;
84e690bf
AB		 1783 }
1784
eef8c85a
AB		 1785 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1786
84e690bf
AB		 1787 return true;
1788}
1789
1790#define DBG_BCR_BVR_WCR_WVR(n) \
1791 /* DBGBVRn */ \
1792 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1793 /* DBGBCRn */ \
1794 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1795 /* DBGWVRn */ \
1796 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1797 /* DBGWCRn */ \
1798 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1799
1800#define DBGBXVR(n) \
1801 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
bdfb4b38
MZ		 1802
1803/*
1804 * Trapped cp14 registers. We generally ignore most of the external
1805 * debug, on the principle that they don't really make sense to a
84e690bf 1806 * guest. Revisit this one day, would this principle change.
bdfb4b38 1807 */
72564016 1808static const struct sys_reg_desc cp14_regs[] = {
bdfb4b38
MZ		 1809 /* DBGIDR */
1810 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1811 /* DBGDTRRXext */
1812 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1813
1814 DBG_BCR_BVR_WCR_WVR(0),
1815 /* DBGDSCRint */
1816 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1817 DBG_BCR_BVR_WCR_WVR(1),
1818 /* DBGDCCINT */
4a1c2c7f 1819 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32, NULL, cp14_DBGDCCINT },
bdfb4b38 1820 /* DBGDSCRext */
4a1c2c7f 1821 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32, NULL, cp14_DBGDSCRext },
bdfb4b38
MZ		 1822 DBG_BCR_BVR_WCR_WVR(2),
1823 /* DBGDTR[RT]Xint */
1824 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1825 /* DBGDTR[RT]Xext */
1826 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1827 DBG_BCR_BVR_WCR_WVR(3),
1828 DBG_BCR_BVR_WCR_WVR(4),
1829 DBG_BCR_BVR_WCR_WVR(5),
1830 /* DBGWFAR */
1831 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1832 /* DBGOSECCR */
1833 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1834 DBG_BCR_BVR_WCR_WVR(6),
1835 /* DBGVCR */
4a1c2c7f 1836 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32, NULL, cp14_DBGVCR },
bdfb4b38
MZ		 1837 DBG_BCR_BVR_WCR_WVR(7),
1838 DBG_BCR_BVR_WCR_WVR(8),
1839 DBG_BCR_BVR_WCR_WVR(9),
1840 DBG_BCR_BVR_WCR_WVR(10),
1841 DBG_BCR_BVR_WCR_WVR(11),
1842 DBG_BCR_BVR_WCR_WVR(12),
1843 DBG_BCR_BVR_WCR_WVR(13),
1844 DBG_BCR_BVR_WCR_WVR(14),
1845 DBG_BCR_BVR_WCR_WVR(15),
1846
1847 /* DBGDRAR (32bit) */
1848 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1849
1850 DBGBXVR(0),
1851 /* DBGOSLAR */
1852 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1853 DBGBXVR(1),
1854 /* DBGOSLSR */
1855 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1856 DBGBXVR(2),
1857 DBGBXVR(3),
1858 /* DBGOSDLR */
1859 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1860 DBGBXVR(4),
1861 /* DBGPRCR */
1862 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1863 DBGBXVR(5),
1864 DBGBXVR(6),
1865 DBGBXVR(7),
1866 DBGBXVR(8),
1867 DBGBXVR(9),
1868 DBGBXVR(10),
1869 DBGBXVR(11),
1870 DBGBXVR(12),
1871 DBGBXVR(13),
1872 DBGBXVR(14),
1873 DBGBXVR(15),
1874
1875 /* DBGDSAR (32bit) */
1876 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1877
1878 /* DBGDEVID2 */
1879 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1880 /* DBGDEVID1 */
1881 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1882 /* DBGDEVID */
1883 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1884 /* DBGCLAIMSET */
1885 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1886 /* DBGCLAIMCLR */
1887 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1888 /* DBGAUTHSTATUS */
1889 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
72564016
MZ		 1890};
1891
a9866ba0
MZ		 1892/* Trapped cp14 64bit registers */
1893static const struct sys_reg_desc cp14_64_regs[] = {
bdfb4b38
MZ		 1894 /* DBGDRAR (64bit) */
1895 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1896
1897 /* DBGDSAR (64bit) */
1898 { Op1( 0), CRm( 2), .access = trap_raz_wi },
a9866ba0
MZ		 1899};
1900
051ff581
SZ		 1901/* Macro to expand the PMEVCNTRn register */
1902#define PMU_PMEVCNTR(n) \
1903 /* PMEVCNTRn */ \
1904 { Op1(0), CRn(0b1110), \
1905 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1906 access_pmu_evcntr }
1907
9feb21ac
SZ		 1908/* Macro to expand the PMEVTYPERn register */
1909#define PMU_PMEVTYPER(n) \
1910 /* PMEVTYPERn */ \
1911 { Op1(0), CRn(0b1110), \
1912 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1913 access_pmu_evtyper }
1914
4d44923b
MZ		 1915/*
1916 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1917 * depending on the way they are accessed (as a 32bit or a 64bit
1918 * register).
1919 */
62a89c44 1920static const struct sys_reg_desc cp15_regs[] = {
f7f2b15c 1921 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
3c1e7165 1922 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
af473829
JM		 1923 { Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr },
1924 { Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr },
4d44923b
MZ		 1925 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1926 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1927 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
ca4e5147 1928 { Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, c2_TTBCR2 },
4d44923b
MZ		 1929 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1930 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1931 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1932 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1933 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1934 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1935 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1936
62a89c44
MZ		 1937 /*
1938 * DC{C,I,CI}SW operations:
1939 */
1940 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1941 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1942 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
4d44923b 1943
7609c125 1944 /* PMU */
ab946834 1945 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
96b0eebc
SZ		 1946 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1947 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
76d883c4 1948 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
7a0adc70 1949 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
3965c3ce 1950 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
a86b5505
SZ		 1951 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1952 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
051ff581 1953 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
9feb21ac 1954 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
051ff581 1955 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
d692b8ad 1956 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
9db52c78
SZ		 1957 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1958 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
76d883c4 1959 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
4d44923b
MZ		 1960
1961 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1962 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1963 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1964 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
db7dedd0
CD		 1965
1966 /* ICC_SRE */
f7f6f2d9 1967 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
db7dedd0 1968
4d44923b 1969 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
051ff581 1970
84135d3d
AP		 1971 /* Arch Tmers */
1972 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
1973 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
eac137b4 1974
051ff581
SZ		 1975 /* PMEVCNTRn */
1976 PMU_PMEVCNTR(0),
1977 PMU_PMEVCNTR(1),
1978 PMU_PMEVCNTR(2),
1979 PMU_PMEVCNTR(3),
1980 PMU_PMEVCNTR(4),
1981 PMU_PMEVCNTR(5),
1982 PMU_PMEVCNTR(6),
1983 PMU_PMEVCNTR(7),
1984 PMU_PMEVCNTR(8),
1985 PMU_PMEVCNTR(9),
1986 PMU_PMEVCNTR(10),
1987 PMU_PMEVCNTR(11),
1988 PMU_PMEVCNTR(12),
1989 PMU_PMEVCNTR(13),
1990 PMU_PMEVCNTR(14),
1991 PMU_PMEVCNTR(15),
1992 PMU_PMEVCNTR(16),
1993 PMU_PMEVCNTR(17),
1994 PMU_PMEVCNTR(18),
1995 PMU_PMEVCNTR(19),
1996 PMU_PMEVCNTR(20),
1997 PMU_PMEVCNTR(21),
1998 PMU_PMEVCNTR(22),
1999 PMU_PMEVCNTR(23),
2000 PMU_PMEVCNTR(24),
2001 PMU_PMEVCNTR(25),
2002 PMU_PMEVCNTR(26),
2003 PMU_PMEVCNTR(27),
2004 PMU_PMEVCNTR(28),
2005 PMU_PMEVCNTR(29),
2006 PMU_PMEVCNTR(30),
9feb21ac
SZ		 2007 /* PMEVTYPERn */
2008 PMU_PMEVTYPER(0),
2009 PMU_PMEVTYPER(1),
2010 PMU_PMEVTYPER(2),
2011 PMU_PMEVTYPER(3),
2012 PMU_PMEVTYPER(4),
2013 PMU_PMEVTYPER(5),
2014 PMU_PMEVTYPER(6),
2015 PMU_PMEVTYPER(7),
2016 PMU_PMEVTYPER(8),
2017 PMU_PMEVTYPER(9),
2018 PMU_PMEVTYPER(10),
2019 PMU_PMEVTYPER(11),
2020 PMU_PMEVTYPER(12),
2021 PMU_PMEVTYPER(13),
2022 PMU_PMEVTYPER(14),
2023 PMU_PMEVTYPER(15),
2024 PMU_PMEVTYPER(16),
2025 PMU_PMEVTYPER(17),
2026 PMU_PMEVTYPER(18),
2027 PMU_PMEVTYPER(19),
2028 PMU_PMEVTYPER(20),
2029 PMU_PMEVTYPER(21),
2030 PMU_PMEVTYPER(22),
2031 PMU_PMEVTYPER(23),
2032 PMU_PMEVTYPER(24),
2033 PMU_PMEVTYPER(25),
2034 PMU_PMEVTYPER(26),
2035 PMU_PMEVTYPER(27),
2036 PMU_PMEVTYPER(28),
2037 PMU_PMEVTYPER(29),
2038 PMU_PMEVTYPER(30),
2039 /* PMCCFILTR */
2040 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
f7f2b15c
AB		 2041
2042 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2043 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2044 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR },
a9866ba0
MZ		 2045};
2046
2047static const struct sys_reg_desc cp15_64_regs[] = {
2048 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
051ff581 2049 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
03bd646d 2050 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
4d44923b 2051 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
03bd646d
MZ		 2052 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2053 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
84135d3d 2054 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
7c8c5e6a
MZ		 2055};
2056
bb44a8db
MZ		 2057static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2058 bool is_32)
2059{
2060 unsigned int i;
2061
2062 for (i = 0; i < n; i++) {
2063 if (!is_32 && table[i].reg && !table[i].reset) {
2064 kvm_err("sys_reg table %p entry %d has lacks reset\n",
2065 table, i);
2066 return 1;
2067 }
2068
2069 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2070 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2071 return 1;
2072 }
2073 }
2074
2075 return 0;
2076}
2077
623eefa8
MZ		 2078static int match_sys_reg(const void *key, const void *elt)
2079{
2080 const unsigned long pval = (unsigned long)key;
2081 const struct sys_reg_desc *r = elt;
2082
09838de9 2083 return pval - reg_to_encoding(r);
623eefa8
MZ		 2084}
2085
7c8c5e6a
MZ		 2086static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
2087 const struct sys_reg_desc table[],
2088 unsigned int num)
2089{
09838de9 2090 unsigned long pval = reg_to_encoding(params);
623eefa8
MZ		 2091
2092 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
7c8c5e6a
MZ		 2093}
2094
74cc7e0c 2095int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
62a89c44
MZ		 2096{
2097 kvm_inject_undefined(vcpu);
2098 return 1;
2099}
2100
e70b9522
MZ		 2101static void perform_access(struct kvm_vcpu *vcpu,
2102 struct sys_reg_params *params,
2103 const struct sys_reg_desc *r)
2104{
599d79dc
MZ		 2105 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2106
7f34e409
DM		 2107 /* Check for regs disabled by runtime config */
2108 if (sysreg_hidden_from_guest(vcpu, r)) {
2109 kvm_inject_undefined(vcpu);
2110 return;
2111 }
2112
e70b9522
MZ		 2113 /*
2114 * Not having an accessor means that we have configured a trap
2115 * that we don't know how to handle. This certainly qualifies
2116 * as a gross bug that should be fixed right away.
2117 */
2118 BUG_ON(!r->access);
2119
2120 /* Skip instruction if instructed so */
2121 if (likely(r->access(vcpu, params, r)))
cdb5e02e 2122 kvm_incr_pc(vcpu);
e70b9522
MZ		 2123}
2124
72564016
MZ		 2125/*
2126 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2127 * call the corresponding trap handler.
2128 *
2129 * @params: pointer to the descriptor of the access
2130 * @table: array of trap descriptors
2131 * @num: size of the trap descriptor array
2132 *
2133 * Return 0 if the access has been handled, and -1 if not.
2134 */
2135static int emulate_cp(struct kvm_vcpu *vcpu,
3fec037d 2136 struct sys_reg_params *params,
72564016
MZ		 2137 const struct sys_reg_desc *table,
2138 size_t num)
62a89c44 2139{
72564016 2140 const struct sys_reg_desc *r;
62a89c44 2141
72564016
MZ		 2142 if (!table)
2143 return -1; /* Not handled */
62a89c44 2144
62a89c44 2145 r = find_reg(params, table, num);
62a89c44 2146
72564016 2147 if (r) {
e70b9522
MZ		 2148 perform_access(vcpu, params, r);
2149 return 0;
72564016
MZ		 2150 }
2151
2152 /* Not handled */
2153 return -1;
2154}
2155
2156static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2157 struct sys_reg_params *params)
2158{
3a949f4c 2159 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
40c4f8d2 2160 int cp = -1;
72564016 2161
3a949f4c 2162 switch (esr_ec) {
c6d01a94
MR		 2163 case ESR_ELx_EC_CP15_32:
2164 case ESR_ELx_EC_CP15_64:
72564016
MZ		 2165 cp = 15;
2166 break;
c6d01a94
MR		 2167 case ESR_ELx_EC_CP14_MR:
2168 case ESR_ELx_EC_CP14_64:
72564016
MZ		 2169 cp = 14;
2170 break;
2171 default:
40c4f8d2 2172 WARN_ON(1);
62a89c44
MZ		 2173 }
2174
bf4b96bb
MR		 2175 print_sys_reg_msg(params,
2176 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2177 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
62a89c44
MZ		 2178 kvm_inject_undefined(vcpu);
2179}
2180
2181/**
7769db90 2182 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
62a89c44
MZ		 2183 * @vcpu: The VCPU pointer
2184 * @run: The kvm_run struct
2185 */
72564016
MZ		 2186static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2187 const struct sys_reg_desc *global,
dcaffa7b 2188 size_t nr_global)
62a89c44
MZ		 2189{
2190 struct sys_reg_params params;
3a949f4c 2191 u32 esr = kvm_vcpu_get_esr(vcpu);
c667186f 2192 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3a949f4c 2193 int Rt2 = (esr >> 10) & 0x1f;
62a89c44 2194
2072d29c
MZ		 2195 params.is_aarch32 = true;
2196 params.is_32bit = false;
3a949f4c
GS		 2197 params.CRm = (esr >> 1) & 0xf;
2198 params.is_write = ((esr & 1) == 0);
62a89c44
MZ		 2199
2200 params.Op0 = 0;
3a949f4c 2201 params.Op1 = (esr >> 16) & 0xf;
62a89c44
MZ		 2202 params.Op2 = 0;
2203 params.CRn = 0;
2204
2205 /*
2ec5be3d 2206 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
62a89c44
MZ		 2207 * backends between AArch32 and AArch64, we get away with it.
2208 */
2209 if (params.is_write) {
2ec5be3d
PF		 2210 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2211 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
62a89c44
MZ		 2212 }
2213
b6b7a806 2214 /*
dcaffa7b 2215 * If the table contains a handler, handle the
b6b7a806
MZ		 2216 * potential register operation in the case of a read and return
2217 * with success.
2218 */
dcaffa7b 2219 if (!emulate_cp(vcpu, &params, global, nr_global)) {
b6b7a806
MZ		 2220 /* Split up the value between registers for the read side */
2221 if (!params.is_write) {
2222 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2223 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2224 }
62a89c44 2225
b6b7a806 2226 return 1;
62a89c44
MZ		 2227 }
2228
b6b7a806 2229 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 2230 return 1;
2231}
2232
2233/**
7769db90 2234 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
62a89c44
MZ		 2235 * @vcpu: The VCPU pointer
2236 * @run: The kvm_run struct
2237 */
72564016
MZ		 2238static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2239 const struct sys_reg_desc *global,
dcaffa7b 2240 size_t nr_global)
62a89c44
MZ		 2241{
2242 struct sys_reg_params params;
3a949f4c 2243 u32 esr = kvm_vcpu_get_esr(vcpu);
c667186f 2244 int Rt = kvm_vcpu_sys_get_rt(vcpu);
62a89c44 2245
2072d29c
MZ		 2246 params.is_aarch32 = true;
2247 params.is_32bit = true;
3a949f4c 2248 params.CRm = (esr >> 1) & 0xf;
2ec5be3d 2249 params.regval = vcpu_get_reg(vcpu, Rt);
3a949f4c
GS		 2250 params.is_write = ((esr & 1) == 0);
2251 params.CRn = (esr >> 10) & 0xf;
62a89c44 2252 params.Op0 = 0;
3a949f4c
GS		 2253 params.Op1 = (esr >> 14) & 0x7;
2254 params.Op2 = (esr >> 17) & 0x7;
62a89c44 2255
dcaffa7b 2256 if (!emulate_cp(vcpu, &params, global, nr_global)) {
2ec5be3d
PF		 2257 if (!params.is_write)
2258 vcpu_set_reg(vcpu, Rt, params.regval);
72564016 2259 return 1;
2ec5be3d 2260 }
72564016
MZ		 2261
2262 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 2263 return 1;
2264}
2265
74cc7e0c 2266int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
72564016 2267{
dcaffa7b 2268 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
72564016
MZ		 2269}
2270
74cc7e0c 2271int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
72564016 2272{
dcaffa7b 2273 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
72564016
MZ		 2274}
2275
74cc7e0c 2276int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
72564016 2277{
dcaffa7b 2278 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
72564016
MZ		 2279}
2280
74cc7e0c 2281int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
72564016 2282{
dcaffa7b 2283 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs));
72564016
MZ		 2284}
2285
54ad68b7
MR		 2286static bool is_imp_def_sys_reg(struct sys_reg_params *params)
2287{
2288 // See ARM DDI 0487E.a, section D12.3.2
2289 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
2290}
2291
7c8c5e6a 2292static int emulate_sys_reg(struct kvm_vcpu *vcpu,
3fec037d 2293 struct sys_reg_params *params)
7c8c5e6a 2294{
dcaffa7b 2295 const struct sys_reg_desc *r;
7c8c5e6a 2296
dcaffa7b 2297 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
7c8c5e6a
MZ		 2298
2299 if (likely(r)) {
e70b9522 2300 perform_access(vcpu, params, r);
54ad68b7
MR		 2301 } else if (is_imp_def_sys_reg(params)) {
2302 kvm_inject_undefined(vcpu);
7c8c5e6a 2303 } else {
bf4b96bb
MR		 2304 print_sys_reg_msg(params,
2305 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
2306 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
e70b9522 2307 kvm_inject_undefined(vcpu);
7c8c5e6a 2308 }
7c8c5e6a
MZ		 2309 return 1;
2310}
2311
750ed566
JM		 2312/**
2313 * kvm_reset_sys_regs - sets system registers to reset value
2314 * @vcpu: The VCPU pointer
2315 *
2316 * This function finds the right table above and sets the registers on the
2317 * virtual CPU struct to their architecturally defined reset values.
2318 */
2319void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
7c8c5e6a
MZ		 2320{
2321 unsigned long i;
2322
750ed566
JM		 2323 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++)
2324 if (sys_reg_descs[i].reset)
2325 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]);
7c8c5e6a
MZ		 2326}
2327
2328/**
2329 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2330 * @vcpu: The VCPU pointer
7c8c5e6a 2331 */
74cc7e0c 2332int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
7c8c5e6a
MZ		 2333{
2334 struct sys_reg_params params;
3a949f4c 2335 unsigned long esr = kvm_vcpu_get_esr(vcpu);
c667186f 2336 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2ec5be3d 2337 int ret;
7c8c5e6a 2338
eef8c85a
AB		 2339 trace_kvm_handle_sys_reg(esr);
2340
2072d29c
MZ		 2341 params.is_aarch32 = false;
2342 params.is_32bit = false;
7c8c5e6a
MZ		 2343 params.Op0 = (esr >> 20) & 3;
2344 params.Op1 = (esr >> 14) & 0x7;
2345 params.CRn = (esr >> 10) & 0xf;
2346 params.CRm = (esr >> 1) & 0xf;
2347 params.Op2 = (esr >> 17) & 0x7;
2ec5be3d 2348 params.regval = vcpu_get_reg(vcpu, Rt);
7c8c5e6a
MZ		 2349 params.is_write = !(esr & 1);
2350
2ec5be3d
PF		 2351 ret = emulate_sys_reg(vcpu, &params);
2352
2353 if (!params.is_write)
2354 vcpu_set_reg(vcpu, Rt, params.regval);
2355 return ret;
7c8c5e6a
MZ		 2356}
2357
2358/******************************************************************************
2359 * Userspace API
2360 *****************************************************************************/
2361
2362static bool index_to_params(u64 id, struct sys_reg_params *params)
2363{
2364 switch (id & KVM_REG_SIZE_MASK) {
2365 case KVM_REG_SIZE_U64:
2366 /* Any unused index bits means it's not valid. */
2367 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2368 | KVM_REG_ARM_COPROC_MASK
2369 | KVM_REG_ARM64_SYSREG_OP0_MASK
2370 | KVM_REG_ARM64_SYSREG_OP1_MASK
2371 | KVM_REG_ARM64_SYSREG_CRN_MASK
2372 | KVM_REG_ARM64_SYSREG_CRM_MASK
2373 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2374 return false;
2375 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2376 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2377 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2378 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2379 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2380 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2381 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2382 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2383 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2384 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2385 return true;
2386 default:
2387 return false;
2388 }
2389}
2390
4b927b94
VK		 2391const struct sys_reg_desc *find_reg_by_id(u64 id,
2392 struct sys_reg_params *params,
2393 const struct sys_reg_desc table[],
2394 unsigned int num)
2395{
2396 if (!index_to_params(id, params))
2397 return NULL;
2398
2399 return find_reg(params, table, num);
2400}
2401
7c8c5e6a
MZ		 2402/* Decode an index value, and find the sys_reg_desc entry. */
2403static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2404 u64 id)
2405{
dcaffa7b 2406 const struct sys_reg_desc *r;
7c8c5e6a
MZ		 2407 struct sys_reg_params params;
2408
2409 /* We only do sys_reg for now. */
2410 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2411 return NULL;
2412
1ce74e96
WD		 2413 if (!index_to_params(id, &params))
2414 return NULL;
2415
dcaffa7b 2416 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
7c8c5e6a 2417
93390c0a
DM		 2418 /* Not saved in the sys_reg array and not otherwise accessible? */
2419 if (r && !(r->reg || r->get_user))
7c8c5e6a
MZ		 2420 r = NULL;
2421
2422 return r;
2423}
2424
2425/*
2426 * These are the invariant sys_reg registers: we let the guest see the
2427 * host versions of these, so they're part of the guest state.
2428 *
2429 * A future CPU may provide a mechanism to present different values to
2430 * the guest, or a future kvm may trap them.
2431 */
2432
2433#define FUNCTION_INVARIANT(reg) \
2434 static void get_##reg(struct kvm_vcpu *v, \
2435 const struct sys_reg_desc *r) \
2436 { \
1f3d8699 2437 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
7c8c5e6a
MZ		 2438 }
2439
2440FUNCTION_INVARIANT(midr_el1)
7c8c5e6a 2441FUNCTION_INVARIANT(revidr_el1)
7c8c5e6a
MZ		 2442FUNCTION_INVARIANT(clidr_el1)
2443FUNCTION_INVARIANT(aidr_el1)
2444
f7f2b15c
AB		 2445static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2446{
2447 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2448}
2449
7c8c5e6a
MZ		 2450/* ->val is filled in by kvm_sys_reg_table_init() */
2451static struct sys_reg_desc invariant_sys_regs[] = {
0d449541
MR		 2452 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2453 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
0d449541
MR		 2454 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2455 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2456 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
7c8c5e6a
MZ		 2457};
2458
26c99af1 2459static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
7c8c5e6a 2460{
7c8c5e6a
MZ		 2461 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2462 return -EFAULT;
2463 return 0;
2464}
2465
26c99af1 2466static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
7c8c5e6a 2467{
7c8c5e6a
MZ		 2468 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2469 return -EFAULT;
2470 return 0;
2471}
2472
2473static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2474{
2475 struct sys_reg_params params;
2476 const struct sys_reg_desc *r;
2477
4b927b94
VK		 2478 r = find_reg_by_id(id, &params, invariant_sys_regs,
2479 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 2480 if (!r)
2481 return -ENOENT;
2482
2483 return reg_to_user(uaddr, &r->val, id);
2484}
2485
2486static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2487{
2488 struct sys_reg_params params;
2489 const struct sys_reg_desc *r;
2490 int err;
2491 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2492
4b927b94
VK		 2493 r = find_reg_by_id(id, &params, invariant_sys_regs,
2494 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 2495 if (!r)
2496 return -ENOENT;
2497
2498 err = reg_from_user(&val, uaddr, id);
2499 if (err)
2500 return err;
2501
2502 /* This is what we mean by invariant: you can't change it. */
2503 if (r->val != val)
2504 return -EINVAL;
2505
2506 return 0;
2507}
2508
2509static bool is_valid_cache(u32 val)
2510{
2511 u32 level, ctype;
2512
2513 if (val >= CSSELR_MAX)
18d45766 2514 return false;
7c8c5e6a
MZ		 2515
2516 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2517 level = (val >> 1);
2518 ctype = (cache_levels >> (level * 3)) & 7;
2519
2520 switch (ctype) {
2521 case 0: /* No cache */
2522 return false;
2523 case 1: /* Instruction cache only */
2524 return (val & 1);
2525 case 2: /* Data cache only */
2526 case 4: /* Unified cache */
2527 return !(val & 1);
2528 case 3: /* Separate instruction and data caches */
2529 return true;
2530 default: /* Reserved: we can't know instruction or data. */
2531 return false;
2532 }
2533}
2534
2535static int demux_c15_get(u64 id, void __user *uaddr)
2536{
2537 u32 val;
2538 u32 __user *uval = uaddr;
2539
2540 /* Fail if we have unknown bits set. */
2541 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2542 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2543 return -ENOENT;
2544
2545 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2546 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2547 if (KVM_REG_SIZE(id) != 4)
2548 return -ENOENT;
2549 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2550 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2551 if (!is_valid_cache(val))
2552 return -ENOENT;
2553
2554 return put_user(get_ccsidr(val), uval);
2555 default:
2556 return -ENOENT;
2557 }
2558}
2559
2560static int demux_c15_set(u64 id, void __user *uaddr)
2561{
2562 u32 val, newval;
2563 u32 __user *uval = uaddr;
2564
2565 /* Fail if we have unknown bits set. */
2566 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2567 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2568 return -ENOENT;
2569
2570 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2571 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2572 if (KVM_REG_SIZE(id) != 4)
2573 return -ENOENT;
2574 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2575 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2576 if (!is_valid_cache(val))
2577 return -ENOENT;
2578
2579 if (get_user(newval, uval))
2580 return -EFAULT;
2581
2582 /* This is also invariant: you can't change it. */
2583 if (newval != get_ccsidr(val))
2584 return -EINVAL;
2585 return 0;
2586 default:
2587 return -ENOENT;
2588 }
2589}
2590
2591int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2592{
2593 const struct sys_reg_desc *r;
2594 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2595
2596 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2597 return demux_c15_get(reg->id, uaddr);
2598
2599 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2600 return -ENOENT;
2601
2602 r = index_to_sys_reg_desc(vcpu, reg->id);
2603 if (!r)
2604 return get_invariant_sys_reg(reg->id, uaddr);
2605
7f34e409
DM		 2606 /* Check for regs disabled by runtime config */
2607 if (sysreg_hidden_from_user(vcpu, r))
2608 return -ENOENT;
2609
84e690bf
AB		 2610 if (r->get_user)
2611 return (r->get_user)(vcpu, r, reg, uaddr);
2612
8d404c4c 2613 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
7c8c5e6a
MZ		 2614}
2615
2616int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2617{
2618 const struct sys_reg_desc *r;
2619 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2620
2621 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2622 return demux_c15_set(reg->id, uaddr);
2623
2624 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2625 return -ENOENT;
2626
2627 r = index_to_sys_reg_desc(vcpu, reg->id);
2628 if (!r)
2629 return set_invariant_sys_reg(reg->id, uaddr);
2630
7f34e409
DM		 2631 /* Check for regs disabled by runtime config */
2632 if (sysreg_hidden_from_user(vcpu, r))
2633 return -ENOENT;
2634
84e690bf
AB		 2635 if (r->set_user)
2636 return (r->set_user)(vcpu, r, reg, uaddr);
2637
8d404c4c 2638 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
7c8c5e6a
MZ		 2639}
2640
2641static unsigned int num_demux_regs(void)
2642{
2643 unsigned int i, count = 0;
2644
2645 for (i = 0; i < CSSELR_MAX; i++)
2646 if (is_valid_cache(i))
2647 count++;
2648
2649 return count;
2650}
2651
2652static int write_demux_regids(u64 __user *uindices)
2653{
efd48cea 2654 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
7c8c5e6a
MZ		 2655 unsigned int i;
2656
2657 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2658 for (i = 0; i < CSSELR_MAX; i++) {
2659 if (!is_valid_cache(i))
2660 continue;
2661 if (put_user(val | i, uindices))
2662 return -EFAULT;
2663 uindices++;
2664 }
2665 return 0;
2666}
2667
2668static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2669{
2670 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2671 KVM_REG_ARM64_SYSREG |
2672 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2673 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2674 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2675 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2676 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2677}
2678
2679static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2680{
2681 if (!*uind)
2682 return true;
2683
2684 if (put_user(sys_reg_to_index(reg), *uind))
2685 return false;
2686
2687 (*uind)++;
2688 return true;
2689}
2690
7f34e409
DM		 2691static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2692 const struct sys_reg_desc *rd,
93390c0a
DM		 2693 u64 __user **uind,
2694 unsigned int *total)
2695{
2696 /*
2697 * Ignore registers we trap but don't save,
2698 * and for which no custom user accessor is provided.
2699 */
2700 if (!(rd->reg || rd->get_user))
2701 return 0;
2702
7f34e409
DM		 2703 if (sysreg_hidden_from_user(vcpu, rd))
2704 return 0;
2705
93390c0a
DM		 2706 if (!copy_reg_to_user(rd, uind))
2707 return -EFAULT;
2708
2709 (*total)++;
2710 return 0;
2711}
2712
7c8c5e6a
MZ		 2713/* Assumed ordered tables, see kvm_sys_reg_table_init. */
2714static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2715{
dcaffa7b 2716 const struct sys_reg_desc *i2, *end2;
7c8c5e6a 2717 unsigned int total = 0;
93390c0a 2718 int err;
7c8c5e6a 2719
7c8c5e6a
MZ		 2720 i2 = sys_reg_descs;
2721 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2722
dcaffa7b
JM		 2723 while (i2 != end2) {
2724 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
93390c0a
DM		 2725 if (err)
2726 return err;
7c8c5e6a
MZ		 2727 }
2728 return total;
2729}
2730
2731unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2732{
2733 return ARRAY_SIZE(invariant_sys_regs)
2734 + num_demux_regs()
2735 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2736}
2737
2738int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2739{
2740 unsigned int i;
2741 int err;
2742
2743 /* Then give them all the invariant registers' indices. */
2744 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2745 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2746 return -EFAULT;
2747 uindices++;
2748 }
2749
2750 err = walk_sys_regs(vcpu, uindices);
2751 if (err < 0)
2752 return err;
2753 uindices += err;
2754
2755 return write_demux_regids(uindices);
2756}
2757
2758void kvm_sys_reg_table_init(void)
2759{
2760 unsigned int i;
2761 struct sys_reg_desc clidr;
2762
2763 /* Make sure tables are unique and in order. */
bb44a8db
MZ		 2764 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false));
2765 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true));
2766 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true));
2767 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true));
2768 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true));
2769 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false));
7c8c5e6a
MZ		 2770
2771 /* We abuse the reset function to overwrite the table itself. */
2772 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2773 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2774
2775 /*
2776 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2777 *
2778 * If software reads the Cache Type fields from Ctype1
2779 * upwards, once it has seen a value of 0b000, no caches
2780 * exist at further-out levels of the hierarchy. So, for
2781 * example, if Ctype3 is the first Cache Type field with a
2782 * value of 0b000, the values of Ctype4 to Ctype7 must be
2783 * ignored.
2784 */
2785 get_clidr_el1(NULL, &clidr); /* Ugly... */
2786 cache_levels = clidr.val;
2787 for (i = 0; i < 7; i++)
2788 if (((cache_levels >> (i*3)) & 7) == 0)
2789 break;
2790 /* Clear all higher bits. */
2791 cache_levels &= (1 << (i*3))-1;
2792}
Linux 6.x block layer and io_uring tree(s)