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KVM: arm64: Introduce a bad_trap() primitive for unexpected trap handling
[linux-2.6-block.git] / arch / arm64 / kvm / sys_regs.c
CommitLineData
caab277b 1// SPDX-License-Identifier: GPL-2.0-only
7c8c5e6a
MZ		 2/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
7c8c5e6a
MZ		 10 */
11
c8857935 12#include <linux/bitfield.h>
623eefa8 13#include <linux/bsearch.h>
7af0c253 14#include <linux/cacheinfo.h>
7c8c5e6a 15#include <linux/kvm_host.h>
c6d01a94 16#include <linux/mm.h>
07d79fe7 17#include <linux/printk.h>
7c8c5e6a 18#include <linux/uaccess.h>
c6d01a94 19
7c8c5e6a
MZ		 20#include <asm/cacheflush.h>
21#include <asm/cputype.h>
0c557ed4 22#include <asm/debug-monitors.h>
c6d01a94
MR		 23#include <asm/esr.h>
24#include <asm/kvm_arm.h>
c6d01a94 25#include <asm/kvm_emulate.h>
d47533da 26#include <asm/kvm_hyp.h>
c6d01a94 27#include <asm/kvm_mmu.h>
6ff9dc23 28#include <asm/kvm_nested.h>
ab946834 29#include <asm/perf_event.h>
1f3d8699 30#include <asm/sysreg.h>
c6d01a94 31
7c8c5e6a
MZ		 32#include <trace/events/kvm.h>
33
34#include "sys_regs.h"
35
eef8c85a
AB		 36#include "trace.h"
37
7c8c5e6a 38/*
62a89c44
MZ		 39 * For AArch32, we only take care of what is being trapped. Anything
40 * that has to do with init and userspace access has to go via the
41 * 64bit interface.
7c8c5e6a
MZ		 42 */
43
f24adc65 44static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
c118cead
JZ		 45static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
46 u64 val);
f24adc65 47
2733dd10
MZ		 48static bool bad_trap(struct kvm_vcpu *vcpu,
49 struct sys_reg_params *params,
50 const struct sys_reg_desc *r,
51 const char *msg)
7b5b4df1 52{
2733dd10 53 WARN_ONCE(1, "Unexpected %s\n", msg);
7b5b4df1
MZ		 54 print_sys_reg_instr(params);
55 kvm_inject_undefined(vcpu);
56 return false;
57}
58
2733dd10
MZ		 59static bool read_from_write_only(struct kvm_vcpu *vcpu,
60 struct sys_reg_params *params,
61 const struct sys_reg_desc *r)
62{
63 return bad_trap(vcpu, params, r,
64 "sys_reg read to write-only register");
65}
66
7b1dba1f
MZ		 67static bool write_to_read_only(struct kvm_vcpu *vcpu,
68 struct sys_reg_params *params,
69 const struct sys_reg_desc *r)
70{
2733dd10
MZ		 71 return bad_trap(vcpu, params, r,
72 "sys_reg write to read-only register");
7b1dba1f
MZ		 73}
74
7ea90bdd
MZ		 75u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
76{
77 u64 val = 0x8badf00d8badf00d;
78
30b6ab45 79 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) &&
7ea90bdd
MZ		 80 __vcpu_read_sys_reg_from_cpu(reg, &val))
81 return val;
82
83 return __vcpu_sys_reg(vcpu, reg);
84}
85
86void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
87{
30b6ab45 88 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) &&
7ea90bdd
MZ		 89 __vcpu_write_sys_reg_to_cpu(val, reg))
90 return;
91
242b6f34 92 __vcpu_sys_reg(vcpu, reg) = val;
d47533da
CD		 93}
94
7c8c5e6a 95/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
c73a4416 96#define CSSELR_MAX 14
7c8c5e6a 97
7af0c253
AO		 98/*
99 * Returns the minimum line size for the selected cache, expressed as
100 * Log2(bytes).
101 */
102static u8 get_min_cache_line_size(bool icache)
103{
104 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0);
105 u8 field;
106
107 if (icache)
108 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr);
109 else
110 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr);
111
112 /*
113 * Cache line size is represented as Log2(words) in CTR_EL0.
114 * Log2(bytes) can be derived with the following:
115 *
116 * Log2(words) + 2 = Log2(bytes / 4) + 2
117 * = Log2(bytes) - 2 + 2
118 * = Log2(bytes)
119 */
120 return field + 2;
121}
122
7c8c5e6a 123/* Which cache CCSIDR represents depends on CSSELR value. */
7af0c253
AO		 124static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr)
125{
126 u8 line_size;
127
128 if (vcpu->arch.ccsidr)
129 return vcpu->arch.ccsidr[csselr];
130
131 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD);
132
133 /*
134 * Fabricate a CCSIDR value as the overriding value does not exist.
135 * The real CCSIDR value will not be used as it can vary by the
136 * physical CPU which the vcpu currently resides in.
137 *
138 * The line size is determined with get_min_cache_line_size(), which
139 * should be valid for all CPUs even if they have different cache
140 * configuration.
141 *
142 * The associativity bits are cleared, meaning the geometry of all data
143 * and unified caches (which are guaranteed to be PIPT and thus
144 * non-aliasing) are 1 set and 1 way.
145 * Guests should not be doing cache operations by set/way at all, and
146 * for this reason, we trap them and attempt to infer the intent, so
147 * that we can flush the entire guest's address space at the appropriate
148 * time. The exposed geometry minimizes the number of the traps.
149 * [If guests should attempt to infer aliasing properties from the
150 * geometry (which is not permitted by the architecture), they would
151 * only do so for virtually indexed caches.]
152 *
153 * We don't check if the cache level exists as it is allowed to return
154 * an UNKNOWN value if not.
155 */
156 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4);
157}
158
159static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val)
7c8c5e6a 160{
7af0c253
AO		 161 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4;
162 u32 *ccsidr = vcpu->arch.ccsidr;
163 u32 i;
164
165 if ((val & CCSIDR_EL1_RES0) ||
166 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD))
167 return -EINVAL;
168
169 if (!ccsidr) {
170 if (val == get_ccsidr(vcpu, csselr))
171 return 0;
7c8c5e6a 172
5f623a59 173 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT);
7af0c253
AO		 174 if (!ccsidr)
175 return -ENOMEM;
7c8c5e6a 176
7af0c253
AO		 177 for (i = 0; i < CSSELR_MAX; i++)
178 ccsidr[i] = get_ccsidr(vcpu, i);
179
180 vcpu->arch.ccsidr = ccsidr;
181 }
7c8c5e6a 182
7af0c253 183 ccsidr[csselr] = val;
7c8c5e6a 184
7af0c253 185 return 0;
7c8c5e6a
MZ		 186}
187
6ff9dc23
JL		 188static bool access_rw(struct kvm_vcpu *vcpu,
189 struct sys_reg_params *p,
190 const struct sys_reg_desc *r)
191{
192 if (p->is_write)
193 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
194 else
195 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
196
197 return true;
198}
199
3c1e7165
MZ		 200/*
201 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
202 */
7c8c5e6a 203static bool access_dcsw(struct kvm_vcpu *vcpu,
3fec037d 204 struct sys_reg_params *p,
7c8c5e6a
MZ		 205 const struct sys_reg_desc *r)
206{
7c8c5e6a 207 if (!p->is_write)
e7f1d1ee 208 return read_from_write_only(vcpu, p, r);
7c8c5e6a 209
09605e94
MZ		 210 /*
211 * Only track S/W ops if we don't have FWB. It still indicates
212 * that the guest is a bit broken (S/W operations should only
213 * be done by firmware, knowing that there is only a single
214 * CPU left in the system, and certainly not from non-secure
215 * software).
216 */
d8569fba 217 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
09605e94
MZ		 218 kvm_set_way_flush(vcpu);
219
7c8c5e6a
MZ		 220 return true;
221}
222
d282fa3c
MZ		 223static bool access_dcgsw(struct kvm_vcpu *vcpu,
224 struct sys_reg_params *p,
225 const struct sys_reg_desc *r)
226{
227 if (!kvm_has_mte(vcpu->kvm)) {
228 kvm_inject_undefined(vcpu);
229 return false;
230 }
231
232 /* Treat MTE S/W ops as we treat the classic ones: with contempt */
233 return access_dcsw(vcpu, p, r);
234}
235
b1ea1d76
MZ		 236static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
237{
238 switch (r->aarch32_map) {
239 case AA32_LO:
240 *mask = GENMASK_ULL(31, 0);
241 *shift = 0;
242 break;
243 case AA32_HI:
244 *mask = GENMASK_ULL(63, 32);
245 *shift = 32;
246 break;
247 default:
248 *mask = GENMASK_ULL(63, 0);
249 *shift = 0;
250 break;
251 }
252}
253
4d44923b
MZ		 254/*
255 * Generic accessor for VM registers. Only called as long as HCR_TVM
3c1e7165
MZ		 256 * is set. If the guest enables the MMU, we stop trapping the VM
257 * sys_regs and leave it in complete control of the caches.
4d44923b
MZ		 258 */
259static bool access_vm_reg(struct kvm_vcpu *vcpu,
3fec037d 260 struct sys_reg_params *p,
4d44923b
MZ		 261 const struct sys_reg_desc *r)
262{
3c1e7165 263 bool was_enabled = vcpu_has_cache_enabled(vcpu);
b1ea1d76 264 u64 val, mask, shift;
4d44923b
MZ		 265
266 BUG_ON(!p->is_write);
267
b1ea1d76 268 get_access_mask(r, &mask, &shift);
52f6c4f0 269
b1ea1d76
MZ		 270 if (~mask) {
271 val = vcpu_read_sys_reg(vcpu, r->reg);
272 val &= ~mask;
dedf97e8 273 } else {
b1ea1d76 274 val = 0;
dedf97e8 275 }
b1ea1d76
MZ		 276
277 val |= (p->regval & (mask >> shift)) << shift;
278 vcpu_write_sys_reg(vcpu, val, r->reg);
f0a3eaff 279
3c1e7165 280 kvm_toggle_cache(vcpu, was_enabled);
4d44923b
MZ		 281 return true;
282}
283
af473829
JM		 284static bool access_actlr(struct kvm_vcpu *vcpu,
285 struct sys_reg_params *p,
286 const struct sys_reg_desc *r)
287{
b1ea1d76
MZ		 288 u64 mask, shift;
289
af473829
JM		 290 if (p->is_write)
291 return ignore_write(vcpu, p);
292
b1ea1d76
MZ		 293 get_access_mask(r, &mask, &shift);
294 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
af473829
JM		 295
296 return true;
297}
298
6d52f35a
AP		 299/*
300 * Trap handler for the GICv3 SGI generation system register.
301 * Forward the request to the VGIC emulation.
302 * The cp15_64 code makes sure this automatically works
303 * for both AArch64 and AArch32 accesses.
304 */
305static bool access_gic_sgi(struct kvm_vcpu *vcpu,
3fec037d 306 struct sys_reg_params *p,
6d52f35a
AP		 307 const struct sys_reg_desc *r)
308{
03bd646d
MZ		 309 bool g1;
310
6d52f35a 311 if (!p->is_write)
e7f1d1ee 312 return read_from_write_only(vcpu, p, r);
6d52f35a 313
03bd646d
MZ		 314 /*
315 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
316 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
317 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
318 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
319 * group.
320 */
50f30453 321 if (p->Op0 == 0) { /* AArch32 */
03bd646d
MZ		 322 switch (p->Op1) {
323 default: /* Keep GCC quiet */
324 case 0: /* ICC_SGI1R */
325 g1 = true;
326 break;
327 case 1: /* ICC_ASGI1R */
328 case 2: /* ICC_SGI0R */
329 g1 = false;
330 break;
331 }
50f30453 332 } else { /* AArch64 */
03bd646d
MZ		 333 switch (p->Op2) {
334 default: /* Keep GCC quiet */
335 case 5: /* ICC_SGI1R_EL1 */
336 g1 = true;
337 break;
338 case 6: /* ICC_ASGI1R_EL1 */
339 case 7: /* ICC_SGI0R_EL1 */
340 g1 = false;
341 break;
342 }
343 }
344
345 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
6d52f35a
AP		 346
347 return true;
348}
349
b34f2bcb
MZ		 350static bool access_gic_sre(struct kvm_vcpu *vcpu,
351 struct sys_reg_params *p,
352 const struct sys_reg_desc *r)
353{
354 if (p->is_write)
355 return ignore_write(vcpu, p);
356
357 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
358 return true;
359}
360
7609c125 361static bool trap_raz_wi(struct kvm_vcpu *vcpu,
3fec037d 362 struct sys_reg_params *p,
7609c125 363 const struct sys_reg_desc *r)
7c8c5e6a
MZ		 364{
365 if (p->is_write)
366 return ignore_write(vcpu, p);
367 else
368 return read_zero(vcpu, p);
369}
370
6ff9dc23
JL		 371static bool trap_undef(struct kvm_vcpu *vcpu,
372 struct sys_reg_params *p,
373 const struct sys_reg_desc *r)
374{
375 kvm_inject_undefined(vcpu);
376 return false;
377}
378
22925521
MZ		 379/*
380 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
381 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
382 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
383 * treat it separately.
384 */
385static bool trap_loregion(struct kvm_vcpu *vcpu,
386 struct sys_reg_params *p,
387 const struct sys_reg_desc *r)
cc33c4e2 388{
8b6958d6 389 u64 val = IDREG(vcpu->kvm, SYS_ID_AA64MMFR1_EL1);
7ba8b438 390 u32 sr = reg_to_encoding(r);
22925521 391
6fcd0193 392 if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) {
22925521
MZ		 393 kvm_inject_undefined(vcpu);
394 return false;
395 }
396
397 if (p->is_write && sr == SYS_LORID_EL1)
398 return write_to_read_only(vcpu, p, r);
399
400 return trap_raz_wi(vcpu, p, r);
cc33c4e2
MR		 401}
402
f24adc65
OU		 403static bool trap_oslar_el1(struct kvm_vcpu *vcpu,
404 struct sys_reg_params *p,
405 const struct sys_reg_desc *r)
406{
407 u64 oslsr;
408
409 if (!p->is_write)
410 return read_from_write_only(vcpu, p, r);
411
412 /* Forward the OSLK bit to OSLSR */
187de7c2
MB		 413 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK;
414 if (p->regval & OSLAR_EL1_OSLK)
415 oslsr |= OSLSR_EL1_OSLK;
f24adc65
OU		 416
417 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr;
418 return true;
419}
420
0c557ed4 421static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
3fec037d 422 struct sys_reg_params *p,
0c557ed4
MZ		 423 const struct sys_reg_desc *r)
424{
d42e2671 425 if (p->is_write)
e2ffceaa 426 return write_to_read_only(vcpu, p, r);
d42e2671
OU		 427
428 p->regval = __vcpu_sys_reg(vcpu, r->reg);
429 return true;
430}
431
432static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
978ceeb3 433 u64 val)
d42e2671 434{
f24adc65
OU		 435 /*
436 * The only modifiable bit is the OSLK bit. Refuse the write if
437 * userspace attempts to change any other bit in the register.
438 */
187de7c2 439 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK)
d42e2671
OU		 440 return -EINVAL;
441
f24adc65 442 __vcpu_sys_reg(vcpu, rd->reg) = val;
d42e2671 443 return 0;
0c557ed4
MZ		 444}
445
446static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
3fec037d 447 struct sys_reg_params *p,
0c557ed4
MZ		 448 const struct sys_reg_desc *r)
449{
450 if (p->is_write) {
451 return ignore_write(vcpu, p);
452 } else {
1f3d8699 453 p->regval = read_sysreg(dbgauthstatus_el1);
0c557ed4
MZ		 454 return true;
455 }
456}
457
458/*
459 * We want to avoid world-switching all the DBG registers all the
460 * time:
e6bc555c 461 *
0c557ed4
MZ		 462 * - If we've touched any debug register, it is likely that we're
463 * going to touch more of them. It then makes sense to disable the
464 * traps and start doing the save/restore dance
465 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
466 * then mandatory to save/restore the registers, as the guest
467 * depends on them.
e6bc555c 468 *
0c557ed4
MZ		 469 * For this, we use a DIRTY bit, indicating the guest has modified the
470 * debug registers, used as follow:
471 *
472 * On guest entry:
473 * - If the dirty bit is set (because we're coming back from trapping),
474 * disable the traps, save host registers, restore guest registers.
475 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
476 * set the dirty bit, disable the traps, save host registers,
477 * restore guest registers.
478 * - Otherwise, enable the traps
479 *
480 * On guest exit:
481 * - If the dirty bit is set, save guest registers, restore host
482 * registers and clear the dirty bit. This ensure that the host can
483 * now use the debug registers.
484 */
485static bool trap_debug_regs(struct kvm_vcpu *vcpu,
3fec037d 486 struct sys_reg_params *p,
0c557ed4
MZ		 487 const struct sys_reg_desc *r)
488{
6ff9dc23
JL		 489 access_rw(vcpu, p, r);
490 if (p->is_write)
b1da4908 491 vcpu_set_flag(vcpu, DEBUG_DIRTY);
0c557ed4 492
2ec5be3d 493 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
eef8c85a 494
0c557ed4
MZ		 495 return true;
496}
497
84e690bf
AB		 498/*
499 * reg_to_dbg/dbg_to_reg
500 *
501 * A 32 bit write to a debug register leave top bits alone
502 * A 32 bit read from a debug register only returns the bottom bits
503 *
b1da4908
MZ		 504 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code
505 * switches between host and guest values in future.
84e690bf 506 */
281243cb
MZ		 507static void reg_to_dbg(struct kvm_vcpu *vcpu,
508 struct sys_reg_params *p,
1da42c34 509 const struct sys_reg_desc *rd,
281243cb 510 u64 *dbg_reg)
84e690bf 511{
1da42c34 512 u64 mask, shift, val;
84e690bf 513
1da42c34 514 get_access_mask(rd, &mask, &shift);
84e690bf 515
1da42c34
MZ		 516 val = *dbg_reg;
517 val &= ~mask;
518 val |= (p->regval & (mask >> shift)) << shift;
84e690bf 519 *dbg_reg = val;
1da42c34 520
b1da4908 521 vcpu_set_flag(vcpu, DEBUG_DIRTY);
84e690bf
AB		 522}
523
281243cb
MZ		 524static void dbg_to_reg(struct kvm_vcpu *vcpu,
525 struct sys_reg_params *p,
1da42c34 526 const struct sys_reg_desc *rd,
281243cb 527 u64 *dbg_reg)
84e690bf 528{
1da42c34
MZ		 529 u64 mask, shift;
530
531 get_access_mask(rd, &mask, &shift);
532 p->regval = (*dbg_reg & mask) >> shift;
84e690bf
AB		 533}
534
281243cb
MZ		 535static bool trap_bvr(struct kvm_vcpu *vcpu,
536 struct sys_reg_params *p,
537 const struct sys_reg_desc *rd)
84e690bf 538{
cb853ded 539 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
84e690bf
AB		 540
541 if (p->is_write)
1da42c34 542 reg_to_dbg(vcpu, p, rd, dbg_reg);
84e690bf 543 else
1da42c34 544 dbg_to_reg(vcpu, p, rd, dbg_reg);
84e690bf 545
cb853ded 546 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
eef8c85a 547
84e690bf
AB		 548 return true;
549}
550
551static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
978ceeb3 552 u64 val)
84e690bf 553{
978ceeb3 554 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val;
84e690bf
AB		 555 return 0;
556}
557
558static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
978ceeb3 559 u64 *val)
84e690bf 560{
978ceeb3 561 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
84e690bf
AB		 562 return 0;
563}
564
d86cde6e 565static u64 reset_bvr(struct kvm_vcpu *vcpu,
281243cb 566 const struct sys_reg_desc *rd)
84e690bf 567{
cb853ded 568 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
d86cde6e 569 return rd->val;
84e690bf
AB		 570}
571
281243cb
MZ		 572static bool trap_bcr(struct kvm_vcpu *vcpu,
573 struct sys_reg_params *p,
574 const struct sys_reg_desc *rd)
84e690bf 575{
cb853ded 576 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
84e690bf
AB		 577
578 if (p->is_write)
1da42c34 579 reg_to_dbg(vcpu, p, rd, dbg_reg);
84e690bf 580 else
1da42c34 581 dbg_to_reg(vcpu, p, rd, dbg_reg);
84e690bf 582
cb853ded 583 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
eef8c85a 584
84e690bf
AB		 585 return true;
586}
587
588static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
978ceeb3 589 u64 val)
84e690bf 590{
978ceeb3 591 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val;
84e690bf
AB		 592 return 0;
593}
594
595static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
978ceeb3 596 u64 *val)
84e690bf 597{
978ceeb3 598 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
84e690bf
AB		 599 return 0;
600}
601
d86cde6e 602static u64 reset_bcr(struct kvm_vcpu *vcpu,
281243cb 603 const struct sys_reg_desc *rd)
84e690bf 604{
cb853ded 605 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
d86cde6e 606 return rd->val;
84e690bf
AB		 607}
608
281243cb
MZ		 609static bool trap_wvr(struct kvm_vcpu *vcpu,
610 struct sys_reg_params *p,
611 const struct sys_reg_desc *rd)
84e690bf 612{
cb853ded 613 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
84e690bf
AB		 614
615 if (p->is_write)
1da42c34 616 reg_to_dbg(vcpu, p, rd, dbg_reg);
84e690bf 617 else
1da42c34 618 dbg_to_reg(vcpu, p, rd, dbg_reg);
84e690bf 619
cb853ded
MZ		 620 trace_trap_reg(__func__, rd->CRm, p->is_write,
621 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
eef8c85a 622
84e690bf
AB		 623 return true;
624}
625
626static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
978ceeb3 627 u64 val)
84e690bf 628{
978ceeb3 629 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val;
84e690bf
AB		 630 return 0;
631}
632
633static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
978ceeb3 634 u64 *val)
84e690bf 635{
978ceeb3 636 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
84e690bf
AB		 637 return 0;
638}
639
d86cde6e 640static u64 reset_wvr(struct kvm_vcpu *vcpu,
281243cb 641 const struct sys_reg_desc *rd)
84e690bf 642{
cb853ded 643 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
d86cde6e 644 return rd->val;
84e690bf
AB		 645}
646
281243cb
MZ		 647static bool trap_wcr(struct kvm_vcpu *vcpu,
648 struct sys_reg_params *p,
649 const struct sys_reg_desc *rd)
84e690bf 650{
cb853ded 651 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
84e690bf
AB		 652
653 if (p->is_write)
1da42c34 654 reg_to_dbg(vcpu, p, rd, dbg_reg);
84e690bf 655 else
1da42c34 656 dbg_to_reg(vcpu, p, rd, dbg_reg);
84e690bf 657
cb853ded 658 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
eef8c85a 659
84e690bf
AB		 660 return true;
661}
662
663static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
978ceeb3 664 u64 val)
84e690bf 665{
978ceeb3 666 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val;
84e690bf
AB		 667 return 0;
668}
669
670static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
978ceeb3 671 u64 *val)
84e690bf 672{
978ceeb3 673 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
84e690bf
AB		 674 return 0;
675}
676
d86cde6e 677static u64 reset_wcr(struct kvm_vcpu *vcpu,
281243cb 678 const struct sys_reg_desc *rd)
84e690bf 679{
cb853ded 680 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
d86cde6e 681 return rd->val;
84e690bf
AB		 682}
683
d86cde6e 684static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
7c8c5e6a 685{
8d404c4c
CD		 686 u64 amair = read_sysreg(amair_el1);
687 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
d86cde6e 688 return amair;
7c8c5e6a
MZ		 689}
690
d86cde6e 691static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
af473829
JM		 692{
693 u64 actlr = read_sysreg(actlr_el1);
694 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
d86cde6e 695 return actlr;
af473829
JM		 696}
697
d86cde6e 698static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
7c8c5e6a 699{
4429fc64
AP		 700 u64 mpidr;
701
7c8c5e6a 702 /*
4429fc64
AP		 703 * Map the vcpu_id into the first three affinity level fields of
704 * the MPIDR. We limit the number of VCPUs in level 0 due to a
705 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
706 * of the GICv3 to be able to address each CPU directly when
707 * sending IPIs.
7c8c5e6a 708 */
4429fc64
AP		 709 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
710 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
711 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
d86cde6e
JZ		 712 mpidr |= (1ULL << 31);
713 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
714
715 return mpidr;
7c8c5e6a
MZ		 716}
717
11663111
MZ		 718static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
719 const struct sys_reg_desc *r)
720{
721 if (kvm_vcpu_has_pmu(vcpu))
722 return 0;
723
724 return REG_HIDDEN;
725}
726
d86cde6e 727static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
0ab410a9 728{
ea9ca904
RW		 729 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX);
730 u8 n = vcpu->kvm->arch.pmcr_n;
0ab410a9 731
0ab410a9
MZ		 732 if (n)
733 mask |= GENMASK(n - 1, 0);
734
735 reset_unknown(vcpu, r);
736 __vcpu_sys_reg(vcpu, r->reg) &= mask;
d86cde6e
JZ		 737
738 return __vcpu_sys_reg(vcpu, r->reg);
0ab410a9
MZ		 739}
740
d86cde6e 741static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
0ab410a9
MZ		 742{
743 reset_unknown(vcpu, r);
744 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
d86cde6e
JZ		 745
746 return __vcpu_sys_reg(vcpu, r->reg);
0ab410a9
MZ		 747}
748
d86cde6e 749static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
0ab410a9 750{
bc512d6a
OU		 751 /* This thing will UNDEF, who cares about the reset value? */
752 if (!kvm_vcpu_has_pmu(vcpu))
753 return 0;
754
0ab410a9 755 reset_unknown(vcpu, r);
bc512d6a 756 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm);
d86cde6e
JZ		 757
758 return __vcpu_sys_reg(vcpu, r->reg);
0ab410a9
MZ		 759}
760
d86cde6e 761static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
0ab410a9
MZ		 762{
763 reset_unknown(vcpu, r);
764 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
d86cde6e
JZ		 765
766 return __vcpu_sys_reg(vcpu, r->reg);
0ab410a9
MZ		 767}
768
d86cde6e 769static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
ab946834 770{
4d20debf 771 u64 pmcr = 0;
ab946834 772
f3c6efc7 773 if (!kvm_supports_32bit_el0())
292e8f14
MZ		 774 pmcr |= ARMV8_PMU_PMCR_LC;
775
4d20debf
RRA		 776 /*
777 * The value of PMCR.N field is included when the
778 * vCPU register is read via kvm_vcpu_read_pmcr().
779 */
292e8f14 780 __vcpu_sys_reg(vcpu, r->reg) = pmcr;
d86cde6e
JZ		 781
782 return __vcpu_sys_reg(vcpu, r->reg);
ab946834
SZ		 783}
784
6c007036 785static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
d692b8ad 786{
8d404c4c 787 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
7ded92e2 788 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
d692b8ad 789
24d5950f
MZ		 790 if (!enabled)
791 kvm_inject_undefined(vcpu);
d692b8ad 792
6c007036 793 return !enabled;
d692b8ad
SZ		 794}
795
6c007036 796static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
d692b8ad 797{
6c007036
MZ		 798 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
799}
d692b8ad 800
6c007036
MZ		 801static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
802{
803 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 804}
805
806static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
807{
6c007036 808 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 809}
810
811static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
812{
6c007036 813 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
d692b8ad
SZ		 814}
815
ab946834
SZ		 816static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
817 const struct sys_reg_desc *r)
818{
819 u64 val;
820
d692b8ad
SZ		 821 if (pmu_access_el0_disabled(vcpu))
822 return false;
823
ab946834 824 if (p->is_write) {
64d6820d
MZ		 825 /*
826 * Only update writeable bits of PMCR (continuing into
827 * kvm_pmu_handle_pmcr() as well)
828 */
57fc267f 829 val = kvm_vcpu_read_pmcr(vcpu);
ab946834
SZ		 830 val &= ~ARMV8_PMU_PMCR_MASK;
831 val |= p->regval & ARMV8_PMU_PMCR_MASK;
f3c6efc7 832 if (!kvm_supports_32bit_el0())
6f163714 833 val |= ARMV8_PMU_PMCR_LC;
76993739 834 kvm_pmu_handle_pmcr(vcpu, val);
ab946834
SZ		 835 } else {
836 /* PMCR.P & PMCR.C are RAZ */
57fc267f 837 val = kvm_vcpu_read_pmcr(vcpu)
ab946834
SZ		 838 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
839 p->regval = val;
840 }
841
842 return true;
843}
844
3965c3ce
SZ		 845static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
846 const struct sys_reg_desc *r)
847{
d692b8ad
SZ		 848 if (pmu_access_event_counter_el0_disabled(vcpu))
849 return false;
850
3965c3ce 851 if (p->is_write)
8d404c4c 852 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
3965c3ce
SZ		 853 else
854 /* return PMSELR.SEL field */
8d404c4c 855 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
3965c3ce
SZ		 856 & ARMV8_PMU_COUNTER_MASK;
857
858 return true;
859}
860
a86b5505
SZ		 861static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
862 const struct sys_reg_desc *r)
863{
99b6a401 864 u64 pmceid, mask, shift;
a86b5505 865
a86b5505
SZ		 866 BUG_ON(p->is_write);
867
d692b8ad
SZ		 868 if (pmu_access_el0_disabled(vcpu))
869 return false;
870
99b6a401
MZ		 871 get_access_mask(r, &mask, &shift);
872
88865bec 873 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
99b6a401
MZ		 874 pmceid &= mask;
875 pmceid >>= shift;
a86b5505
SZ		 876
877 p->regval = pmceid;
878
879 return true;
880}
881
051ff581
SZ		 882static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
883{
884 u64 pmcr, val;
885
57fc267f 886 pmcr = kvm_vcpu_read_pmcr(vcpu);
051ff581 887 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
24d5950f
MZ		 888 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
889 kvm_inject_undefined(vcpu);
051ff581 890 return false;
24d5950f 891 }
051ff581
SZ		 892
893 return true;
894}
895
9228b261
RW		 896static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
897 u64 *val)
898{
899 u64 idx;
900
901 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0)
902 /* PMCCNTR_EL0 */
903 idx = ARMV8_PMU_CYCLE_IDX;
904 else
905 /* PMEVCNTRn_EL0 */
906 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
907
908 *val = kvm_pmu_get_counter_value(vcpu, idx);
909 return 0;
910}
911
051ff581
SZ		 912static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
913 struct sys_reg_params *p,
914 const struct sys_reg_desc *r)
915{
a3da9358 916 u64 idx = ~0UL;
051ff581
SZ		 917
918 if (r->CRn == 9 && r->CRm == 13) {
919 if (r->Op2 == 2) {
920 /* PMXEVCNTR_EL0 */
d692b8ad
SZ		 921 if (pmu_access_event_counter_el0_disabled(vcpu))
922 return false;
923
8d404c4c 924 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
051ff581
SZ		 925 & ARMV8_PMU_COUNTER_MASK;
926 } else if (r->Op2 == 0) {
927 /* PMCCNTR_EL0 */
d692b8ad
SZ		 928 if (pmu_access_cycle_counter_el0_disabled(vcpu))
929 return false;
930
051ff581 931 idx = ARMV8_PMU_CYCLE_IDX;
051ff581 932 }
9e3f7a29
WH		 933 } else if (r->CRn == 0 && r->CRm == 9) {
934 /* PMCCNTR */
935 if (pmu_access_event_counter_el0_disabled(vcpu))
936 return false;
937
938 idx = ARMV8_PMU_CYCLE_IDX;
051ff581
SZ		 939 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
940 /* PMEVCNTRn_EL0 */
d692b8ad
SZ		 941 if (pmu_access_event_counter_el0_disabled(vcpu))
942 return false;
943
051ff581 944 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
051ff581
SZ		 945 }
946
a3da9358
MZ		 947 /* Catch any decoding mistake */
948 WARN_ON(idx == ~0UL);
949
051ff581
SZ		 950 if (!pmu_counter_idx_valid(vcpu, idx))
951 return false;
952
d692b8ad
SZ		 953 if (p->is_write) {
954 if (pmu_access_el0_disabled(vcpu))
955 return false;
956
051ff581 957 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
d692b8ad 958 } else {
051ff581 959 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
d692b8ad 960 }
051ff581
SZ		 961
962 return true;
963}
964
9feb21ac
SZ		 965static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
966 const struct sys_reg_desc *r)
967{
968 u64 idx, reg;
969
d692b8ad
SZ		 970 if (pmu_access_el0_disabled(vcpu))
971 return false;
972
9feb21ac
SZ		 973 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
974 /* PMXEVTYPER_EL0 */
8d404c4c 975 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
9feb21ac
SZ		 976 reg = PMEVTYPER0_EL0 + idx;
977 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
978 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
979 if (idx == ARMV8_PMU_CYCLE_IDX)
980 reg = PMCCFILTR_EL0;
981 else
982 /* PMEVTYPERn_EL0 */
983 reg = PMEVTYPER0_EL0 + idx;
984 } else {
985 BUG();
986 }
987
988 if (!pmu_counter_idx_valid(vcpu, idx))
989 return false;
990
991 if (p->is_write) {
992 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
435e53fb 993 kvm_vcpu_pmu_restore_guest(vcpu);
9feb21ac 994 } else {
bc512d6a 995 p->regval = __vcpu_sys_reg(vcpu, reg);
9feb21ac
SZ		 996 }
997
998 return true;
999}
1000
a45f41d7
RRA		 1001static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val)
1002{
1003 bool set;
1004
1005 val &= kvm_pmu_valid_counter_mask(vcpu);
1006
1007 switch (r->reg) {
1008 case PMOVSSET_EL0:
1009 /* CRm[1] being set indicates a SET register, and CLR otherwise */
1010 set = r->CRm & 2;
1011 break;
1012 default:
1013 /* Op2[0] being set indicates a SET register, and CLR otherwise */
1014 set = r->Op2 & 1;
1015 break;
1016 }
1017
1018 if (set)
1019 __vcpu_sys_reg(vcpu, r->reg) |= val;
1020 else
1021 __vcpu_sys_reg(vcpu, r->reg) &= ~val;
1022
1023 return 0;
1024}
1025
1026static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val)
1027{
1028 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
1029
1030 *val = __vcpu_sys_reg(vcpu, r->reg) & mask;
1031 return 0;
1032}
1033
96b0eebc
SZ		 1034static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1035 const struct sys_reg_desc *r)
1036{
1037 u64 val, mask;
1038
d692b8ad
SZ		 1039 if (pmu_access_el0_disabled(vcpu))
1040 return false;
1041
96b0eebc
SZ		 1042 mask = kvm_pmu_valid_counter_mask(vcpu);
1043 if (p->is_write) {
1044 val = p->regval & mask;
1045 if (r->Op2 & 0x1) {
1046 /* accessing PMCNTENSET_EL0 */
8d404c4c 1047 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
418e5ca8 1048 kvm_pmu_enable_counter_mask(vcpu, val);
435e53fb 1049 kvm_vcpu_pmu_restore_guest(vcpu);
96b0eebc
SZ		 1050 } else {
1051 /* accessing PMCNTENCLR_EL0 */
8d404c4c 1052 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
418e5ca8 1053 kvm_pmu_disable_counter_mask(vcpu, val);
96b0eebc
SZ		 1054 }
1055 } else {
f5eff400 1056 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
96b0eebc
SZ		 1057 }
1058
1059 return true;
1060}
1061
9db52c78
SZ		 1062static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1063 const struct sys_reg_desc *r)
1064{
1065 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
1066
b0737e99 1067 if (check_pmu_access_disabled(vcpu, 0))
d692b8ad
SZ		 1068 return false;
1069
9db52c78
SZ		 1070 if (p->is_write) {
1071 u64 val = p->regval & mask;
1072
1073 if (r->Op2 & 0x1)
1074 /* accessing PMINTENSET_EL1 */
8d404c4c 1075 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
9db52c78
SZ		 1076 else
1077 /* accessing PMINTENCLR_EL1 */
8d404c4c 1078 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
9db52c78 1079 } else {
f5eff400 1080 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
9db52c78
SZ		 1081 }
1082
1083 return true;
1084}
1085
76d883c4
SZ		 1086static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1087 const struct sys_reg_desc *r)
1088{
1089 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
1090
d692b8ad
SZ		 1091 if (pmu_access_el0_disabled(vcpu))
1092 return false;
1093
76d883c4
SZ		 1094 if (p->is_write) {
1095 if (r->CRm & 0x2)
1096 /* accessing PMOVSSET_EL0 */
8d404c4c 1097 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
76d883c4
SZ		 1098 else
1099 /* accessing PMOVSCLR_EL0 */
8d404c4c 1100 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
76d883c4 1101 } else {
f5eff400 1102 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
76d883c4
SZ		 1103 }
1104
1105 return true;
1106}
1107
7a0adc70
SZ		 1108static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1109 const struct sys_reg_desc *r)
1110{
1111 u64 mask;
1112
e0443230 1113 if (!p->is_write)
e7f1d1ee 1114 return read_from_write_only(vcpu, p, r);
e0443230 1115
d692b8ad
SZ		 1116 if (pmu_write_swinc_el0_disabled(vcpu))
1117 return false;
1118
e0443230
MZ		 1119 mask = kvm_pmu_valid_counter_mask(vcpu);
1120 kvm_pmu_software_increment(vcpu, p->regval & mask);
1121 return true;
7a0adc70
SZ		 1122}
1123
d692b8ad
SZ		 1124static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1125 const struct sys_reg_desc *r)
1126{
d692b8ad 1127 if (p->is_write) {
9008c235
MZ		 1128 if (!vcpu_mode_priv(vcpu)) {
1129 kvm_inject_undefined(vcpu);
d692b8ad 1130 return false;
9008c235 1131 }
d692b8ad 1132
8d404c4c
CD		 1133 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
1134 p->regval & ARMV8_PMU_USERENR_MASK;
d692b8ad 1135 } else {
8d404c4c 1136 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
d692b8ad
SZ		 1137 & ARMV8_PMU_USERENR_MASK;
1138 }
1139
1140 return true;
1141}
1142
4d20debf
RRA		 1143static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1144 u64 *val)
1145{
1146 *val = kvm_vcpu_read_pmcr(vcpu);
1147 return 0;
1148}
1149
ea9ca904
RW		 1150static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1151 u64 val)
1152{
1153 u8 new_n = (val >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
1154 struct kvm *kvm = vcpu->kvm;
1155
1156 mutex_lock(&kvm->arch.config_lock);
1157
1158 /*
1159 * The vCPU can't have more counters than the PMU hardware
1160 * implements. Ignore this error to maintain compatibility
1161 * with the existing KVM behavior.
1162 */
1163 if (!kvm_vm_has_ran_once(kvm) &&
1164 new_n <= kvm_arm_pmu_get_max_counters(kvm))
1165 kvm->arch.pmcr_n = new_n;
1166
1167 mutex_unlock(&kvm->arch.config_lock);
1168
1169 /*
1170 * Ignore writes to RES0 bits, read only bits that are cleared on
1171 * vCPU reset, and writable bits that KVM doesn't support yet.
1172 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace)
1173 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU.
1174 * But, we leave the bit as it is here, as the vCPU's PMUver might
1175 * be changed later (NOTE: the bit will be cleared on first vCPU run
1176 * if necessary).
1177 */
1178 val &= ARMV8_PMU_PMCR_MASK;
1179
1180 /* The LC bit is RES1 when AArch32 is not supported */
1181 if (!kvm_supports_32bit_el0())
1182 val |= ARMV8_PMU_PMCR_LC;
1183
1184 __vcpu_sys_reg(vcpu, r->reg) = val;
1185 return 0;
1186}
1187
0c557ed4
MZ		 1188/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
1189#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
ee1b64e6 1190 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
03fdfb26 1191 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
ee1b64e6 1192 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
03fdfb26 1193 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
ee1b64e6 1194 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
03fdfb26 1195 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
ee1b64e6 1196 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
03fdfb26 1197 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
0c557ed4 1198
9d2a55b4
XC		 1199#define PMU_SYS_REG(name) \
1200 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \
1201 .visibility = pmu_visibility
11663111 1202
051ff581
SZ		 1203/* Macro to expand the PMEVCNTRn_EL0 register */
1204#define PMU_PMEVCNTR_EL0(n) \
9d2a55b4 1205 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \
9228b261 1206 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \
11663111 1207 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
051ff581 1208
9feb21ac
SZ		 1209/* Macro to expand the PMEVTYPERn_EL0 register */
1210#define PMU_PMEVTYPER_EL0(n) \
9d2a55b4 1211 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \
0ab410a9 1212 .reset = reset_pmevtyper, \
11663111 1213 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
9feb21ac 1214
338b1793
MZ		 1215static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1216 const struct sys_reg_desc *r)
4fcdf106
IV		 1217{
1218 kvm_inject_undefined(vcpu);
1219
1220 return false;
1221}
1222
1223/* Macro to expand the AMU counter and type registers*/
338b1793
MZ		 1224#define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1225#define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1226#define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1227#define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
384b40ca
MR		 1228
1229static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1230 const struct sys_reg_desc *rd)
1231{
01fe5ace 1232 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
384b40ca
MR		 1233}
1234
338b1793
MZ		 1235/*
1236 * If we land here on a PtrAuth access, that is because we didn't
1237 * fixup the access on exit by allowing the PtrAuth sysregs. The only
1238 * way this happens is when the guest does not have PtrAuth support
1239 * enabled.
1240 */
384b40ca 1241#define __PTRAUTH_KEY(k) \
338b1793 1242 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
384b40ca
MR		 1243 .visibility = ptrauth_visibility}
1244
1245#define PTRAUTH_KEY(k) \
1246 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1247 __PTRAUTH_KEY(k ## KEYHI_EL1)
1248
84135d3d
AP		 1249static bool access_arch_timer(struct kvm_vcpu *vcpu,
1250 struct sys_reg_params *p,
1251 const struct sys_reg_desc *r)
c9a3c58f 1252{
84135d3d
AP		 1253 enum kvm_arch_timers tmr;
1254 enum kvm_arch_timer_regs treg;
1255 u64 reg = reg_to_encoding(r);
7b6b4631 1256
84135d3d
AP		 1257 switch (reg) {
1258 case SYS_CNTP_TVAL_EL0:
1259 case SYS_AARCH32_CNTP_TVAL:
1260 tmr = TIMER_PTIMER;
1261 treg = TIMER_REG_TVAL;
1262 break;
1263 case SYS_CNTP_CTL_EL0:
1264 case SYS_AARCH32_CNTP_CTL:
1265 tmr = TIMER_PTIMER;
1266 treg = TIMER_REG_CTL;
1267 break;
1268 case SYS_CNTP_CVAL_EL0:
1269 case SYS_AARCH32_CNTP_CVAL:
1270 tmr = TIMER_PTIMER;
1271 treg = TIMER_REG_CVAL;
1272 break;
c605ee24
MZ		 1273 case SYS_CNTPCT_EL0:
1274 case SYS_CNTPCTSS_EL0:
1275 case SYS_AARCH32_CNTPCT:
1276 tmr = TIMER_PTIMER;
1277 treg = TIMER_REG_CNT;
1278 break;
84135d3d 1279 default:
ba82e06c
MZ		 1280 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register");
1281 kvm_inject_undefined(vcpu);
1282 return false;
c1b135af 1283 }
7b6b4631 1284
7b6b4631 1285 if (p->is_write)
84135d3d 1286 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
7b6b4631 1287 else
84135d3d 1288 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
7b6b4631 1289
c9a3c58f
JL		 1290 return true;
1291}
1292
2e8bf0cb
JZ		 1293static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp,
1294 s64 new, s64 cur)
3d0dba57 1295{
2e8bf0cb
JZ		 1296 struct arm64_ftr_bits kvm_ftr = *ftrp;
1297
1298 /* Some features have different safe value type in KVM than host features */
1299 switch (id) {
1300 case SYS_ID_AA64DFR0_EL1:
a9bc4a1c
OU		 1301 switch (kvm_ftr.shift) {
1302 case ID_AA64DFR0_EL1_PMUVer_SHIFT:
2e8bf0cb 1303 kvm_ftr.type = FTR_LOWER_SAFE;
a9bc4a1c
OU		 1304 break;
1305 case ID_AA64DFR0_EL1_DebugVer_SHIFT:
2e8bf0cb 1306 kvm_ftr.type = FTR_LOWER_SAFE;
a9bc4a1c
OU		 1307 break;
1308 }
2e8bf0cb
JZ		 1309 break;
1310 case SYS_ID_DFR0_EL1:
1311 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT)
1312 kvm_ftr.type = FTR_LOWER_SAFE;
1313 break;
1314 }
3d0dba57 1315
2e8bf0cb 1316 return arm64_ftr_safe_value(&kvm_ftr, new, cur);
3d0dba57
MZ		 1317}
1318
7b424ffc 1319/*
2e8bf0cb
JZ		 1320 * arm64_check_features() - Check if a feature register value constitutes
1321 * a subset of features indicated by the idreg's KVM sanitised limit.
1322 *
1323 * This function will check if each feature field of @val is the "safe" value
1324 * against idreg's KVM sanitised limit return from reset() callback.
1325 * If a field value in @val is the same as the one in limit, it is always
1326 * considered the safe value regardless For register fields that are not in
1327 * writable, only the value in limit is considered the safe value.
1328 *
1329 * Return: 0 if all the fields are safe. Otherwise, return negative errno.
1330 */
1331static int arm64_check_features(struct kvm_vcpu *vcpu,
1332 const struct sys_reg_desc *rd,
1333 u64 val)
d82e0dfd 1334{
2e8bf0cb
JZ		 1335 const struct arm64_ftr_reg *ftr_reg;
1336 const struct arm64_ftr_bits *ftrp = NULL;
1337 u32 id = reg_to_encoding(rd);
1338 u64 writable_mask = rd->val;
1339 u64 limit = rd->reset(vcpu, rd);
1340 u64 mask = 0;
1341
1342 /*
1343 * Hidden and unallocated ID registers may not have a corresponding
1344 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the
1345 * only safe value is 0.
1346 */
1347 if (sysreg_visible_as_raz(vcpu, rd))
1348 return val ? -E2BIG : 0;
1349
1350 ftr_reg = get_arm64_ftr_reg(id);
1351 if (!ftr_reg)
1352 return -EINVAL;
1353
1354 ftrp = ftr_reg->ftr_bits;
1355
1356 for (; ftrp && ftrp->width; ftrp++) {
1357 s64 f_val, f_lim, safe_val;
1358 u64 ftr_mask;
1359
1360 ftr_mask = arm64_ftr_mask(ftrp);
1361 if ((ftr_mask & writable_mask) != ftr_mask)
1362 continue;
1363
1364 f_val = arm64_ftr_value(ftrp, val);
1365 f_lim = arm64_ftr_value(ftrp, limit);
1366 mask |= ftr_mask;
1367
1368 if (f_val == f_lim)
1369 safe_val = f_val;
1370 else
1371 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim);
1372
1373 if (safe_val != f_val)
1374 return -E2BIG;
d82e0dfd 1375 }
2e8bf0cb
JZ		 1376
1377 /* For fields that are not writable, values in limit are the safe values. */
1378 if ((val & ~mask) != (limit & ~mask))
1379 return -E2BIG;
1380
1381 return 0;
d82e0dfd
MZ		 1382}
1383
3d0dba57
MZ		 1384static u8 pmuver_to_perfmon(u8 pmuver)
1385{
1386 switch (pmuver) {
1387 case ID_AA64DFR0_EL1_PMUVer_IMP:
753d734f 1388 return ID_DFR0_EL1_PerfMon_PMUv3;
3d0dba57 1389 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF:
753d734f 1390 return ID_DFR0_EL1_PerfMon_IMPDEF;
3d0dba57
MZ		 1391 default:
1392 /* Anything ARMv8.1+ and NI have the same value. For now. */
1393 return pmuver;
1394 }
1395}
1396
93390c0a 1397/* Read a sanitised cpufeature ID register by sys_reg_desc */
d86cde6e
JZ		 1398static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu,
1399 const struct sys_reg_desc *r)
93390c0a 1400{
7ba8b438 1401 u32 id = reg_to_encoding(r);
00d5101b
AE		 1402 u64 val;
1403
cdd5036d 1404 if (sysreg_visible_as_raz(vcpu, r))
00d5101b
AE		 1405 return 0;
1406
1407 val = read_sanitised_ftr_reg(id);
93390c0a 1408
c8857935 1409 switch (id) {
c8857935 1410 case SYS_ID_AA64PFR1_EL1:
16dd1fbb 1411 if (!kvm_has_mte(vcpu->kvm))
6ca2b9ca 1412 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
90807748 1413
6ca2b9ca 1414 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);
c8857935
MZ		 1415 break;
1416 case SYS_ID_AA64ISAR1_EL1:
1417 if (!vcpu_has_ptrauth(vcpu))
aa50479b
MB		 1418 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
1419 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
1420 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
1421 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
c8857935 1422 break;
def8c222
VM		 1423 case SYS_ID_AA64ISAR2_EL1:
1424 if (!vcpu_has_ptrauth(vcpu))
b2d71f27
MB		 1425 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
1426 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
06e0b802 1427 if (!cpus_have_final_cap(ARM64_HAS_WFXT))
b2d71f27 1428 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
def8c222 1429 break;
bf48040c
AO		 1430 case SYS_ID_AA64MMFR2_EL1:
1431 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK;
1432 break;
1433 case SYS_ID_MMFR4_EL1:
1434 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX);
1435 break;
07d79fe7
DM		 1436 }
1437
1438 return val;
93390c0a
DM		 1439}
1440
d86cde6e
JZ		 1441static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu,
1442 const struct sys_reg_desc *r)
1443{
1444 return __kvm_read_sanitised_id_reg(vcpu, r);
1445}
1446
1447static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1448{
6db7af0d 1449 return IDREG(vcpu->kvm, reg_to_encoding(r));
d86cde6e
JZ		 1450}
1451
47334146
JZ		 1452/*
1453 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is
1454 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8.
1455 */
1456static inline bool is_id_reg(u32 id)
1457{
1458 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
1459 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
1460 sys_reg_CRm(id) < 8);
1461}
1462
3f9cd0ca
JZ		 1463static inline bool is_aa32_id_reg(u32 id)
1464{
1465 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
1466 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
1467 sys_reg_CRm(id) <= 3);
1468}
1469
912dee57
AJ		 1470static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1471 const struct sys_reg_desc *r)
1472{
7ba8b438 1473 u32 id = reg_to_encoding(r);
c512298e
AJ		 1474
1475 switch (id) {
1476 case SYS_ID_AA64ZFR0_EL1:
1477 if (!vcpu_has_sve(vcpu))
1478 return REG_RAZ;
1479 break;
1480 }
1481
912dee57
AJ		 1482 return 0;
1483}
1484
d5efec7e
OU		 1485static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
1486 const struct sys_reg_desc *r)
1487{
1488 /*
1489 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any
1490 * EL. Promote to RAZ/WI in order to guarantee consistency between
1491 * systems.
1492 */
1493 if (!kvm_supports_32bit_el0())
1494 return REG_RAZ | REG_USER_WI;
1495
1496 return id_visibility(vcpu, r);
1497}
1498
34b4d203
OU		 1499static unsigned int raz_visibility(const struct kvm_vcpu *vcpu,
1500 const struct sys_reg_desc *r)
1501{
1502 return REG_RAZ;
1503}
1504
93390c0a
DM		 1505/* cpufeature ID register access trap handlers */
1506
93390c0a
DM		 1507static bool access_id_reg(struct kvm_vcpu *vcpu,
1508 struct sys_reg_params *p,
1509 const struct sys_reg_desc *r)
1510{
4782ccc8
OU		 1511 if (p->is_write)
1512 return write_to_read_only(vcpu, p, r);
1513
cdd5036d 1514 p->regval = read_id_reg(vcpu, r);
9f75b6d4 1515
4782ccc8 1516 return true;
93390c0a
DM		 1517}
1518
73433762
DM		 1519/* Visibility overrides for SVE-specific control registers */
1520static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1521 const struct sys_reg_desc *rd)
1522{
1523 if (vcpu_has_sve(vcpu))
1524 return 0;
1525
01fe5ace 1526 return REG_HIDDEN;
73433762
DM		 1527}
1528
c39f5974
JZ		 1529static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1530 const struct sys_reg_desc *rd)
23711a5e 1531{
c39f5974
JZ		 1532 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1533
1534 if (!vcpu_has_sve(vcpu))
1535 val &= ~ID_AA64PFR0_EL1_SVE_MASK;
23711a5e
MZ		 1536
1537 /*
c39f5974
JZ		 1538 * The default is to expose CSV2 == 1 if the HW isn't affected.
1539 * Although this is a per-CPU feature, we make it global because
1540 * asymmetric systems are just a nuisance.
1541 *
1542 * Userspace can override this as long as it doesn't promise
1543 * the impossible.
23711a5e 1544 */
c39f5974
JZ		 1545 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
1546 val &= ~ID_AA64PFR0_EL1_CSV2_MASK;
1547 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP);
1548 }
1549 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
1550 val &= ~ID_AA64PFR0_EL1_CSV3_MASK;
1551 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP);
1552 }
23711a5e 1553
c39f5974
JZ		 1554 if (kvm_vgic_global_state.type == VGIC_V3) {
1555 val &= ~ID_AA64PFR0_EL1_GIC_MASK;
1556 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP);
1557 }
4f1df628 1558
c39f5974 1559 val &= ~ID_AA64PFR0_EL1_AMU_MASK;
23711a5e 1560
c39f5974
JZ		 1561 return val;
1562}
23711a5e 1563
a9bc4a1c
OU		 1564#define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \
1565({ \
1566 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \
1567 (val) &= ~reg##_##field##_MASK; \
1568 (val) |= FIELD_PREP(reg##_##field##_MASK, \
1569 min(__f_val, (u64)reg##_##field##_##limit)); \
1570 (val); \
1571})
1572
c118cead
JZ		 1573static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
1574 const struct sys_reg_desc *rd)
1575{
1576 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1577
9f9917bc 1578 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8);
c118cead
JZ		 1579
1580 /*
1581 * Only initialize the PMU version if the vCPU was configured with one.
1582 */
1583 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
1584 if (kvm_vcpu_has_pmu(vcpu))
1585 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer,
1586 kvm_arm_pmu_get_pmuver_limit());
1587
1588 /* Hide SPE from guests */
1589 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK;
1590
1591 return val;
23711a5e
MZ		 1592}
1593
60e651ff
MZ		 1594static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
1595 const struct sys_reg_desc *rd,
1596 u64 val)
1597{
a9bc4a1c 1598 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val);
c118cead 1599 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val);
60e651ff
MZ		 1600
1601 /*
f90f9360
OU		 1602 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the
1603 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously
1604 * exposed an IMP_DEF PMU to userspace and the guest on systems w/
1605 * non-architectural PMUs. Of course, PMUv3 is the only game in town for
1606 * PMU virtualization, so the IMP_DEF value was rather user-hostile.
1607 *
1608 * At minimum, we're on the hook to allow values that were given to
1609 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value
1610 * with a more sensible NI. The value of an ID register changing under
1611 * the nose of the guest is unfortunate, but is certainly no more
1612 * surprising than an ill-guided PMU driver poking at impdef system
1613 * registers that end in an UNDEF...
60e651ff 1614 */
68667240 1615 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
f90f9360 1616 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
60e651ff 1617
a9bc4a1c
OU		 1618 /*
1619 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a
1620 * nonzero minimum safe value.
1621 */
1622 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP)
1623 return -EINVAL;
1624
68667240 1625 return set_id_reg(vcpu, rd, val);
c118cead 1626}
60e651ff 1627
c118cead
JZ		 1628static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
1629 const struct sys_reg_desc *rd)
1630{
1631 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
1632 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1);
60e651ff 1633
c118cead
JZ		 1634 val &= ~ID_DFR0_EL1_PerfMon_MASK;
1635 if (kvm_vcpu_has_pmu(vcpu))
1636 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon);
60e651ff 1637
9f9917bc
OU		 1638 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8);
1639
c118cead 1640 return val;
60e651ff
MZ		 1641}
1642
d82e0dfd
MZ		 1643static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
1644 const struct sys_reg_desc *rd,
1645 u64 val)
1646{
c118cead 1647 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val);
a9bc4a1c 1648 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val);
d82e0dfd 1649
f90f9360
OU		 1650 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) {
1651 val &= ~ID_DFR0_EL1_PerfMon_MASK;
1652 perfmon = 0;
1653 }
d82e0dfd
MZ		 1654
1655 /*
1656 * Allow DFR0_EL1.PerfMon to be set from userspace as long as
1657 * it doesn't promise more than what the HW gives us on the
1658 * AArch64 side (as everything is emulated with that), and
1659 * that this is a PMUv3.
1660 */
c118cead 1661 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)
d82e0dfd
MZ		 1662 return -EINVAL;
1663
a9bc4a1c
OU		 1664 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8)
1665 return -EINVAL;
1666
68667240 1667 return set_id_reg(vcpu, rd, val);
d82e0dfd
MZ		 1668}
1669
93390c0a
DM		 1670/*
1671 * cpufeature ID register user accessors
1672 *
1673 * For now, these registers are immutable for userspace, so no values
1674 * are stored, and for set_id_reg() we don't allow the effective value
1675 * to be changed.
1676 */
93390c0a 1677static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
978ceeb3 1678 u64 *val)
93390c0a 1679{
6db7af0d
OU		 1680 /*
1681 * Avoid locking if the VM has already started, as the ID registers are
1682 * guaranteed to be invariant at that point.
1683 */
1684 if (kvm_vm_has_ran_once(vcpu->kvm)) {
1685 *val = read_id_reg(vcpu, rd);
1686 return 0;
1687 }
1688
1689 mutex_lock(&vcpu->kvm->arch.config_lock);
cdd5036d 1690 *val = read_id_reg(vcpu, rd);
6db7af0d
OU		 1691 mutex_unlock(&vcpu->kvm->arch.config_lock);
1692
4782ccc8 1693 return 0;
93390c0a
DM		 1694}
1695
1696static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
978ceeb3 1697 u64 val)
93390c0a 1698{
2e8bf0cb
JZ		 1699 u32 id = reg_to_encoding(rd);
1700 int ret;
4782ccc8 1701
2e8bf0cb
JZ		 1702 mutex_lock(&vcpu->kvm->arch.config_lock);
1703
1704 /*
1705 * Once the VM has started the ID registers are immutable. Reject any
1706 * write that does not match the final register value.
1707 */
1708 if (kvm_vm_has_ran_once(vcpu->kvm)) {
1709 if (val != read_id_reg(vcpu, rd))
1710 ret = -EBUSY;
1711 else
1712 ret = 0;
1713
1714 mutex_unlock(&vcpu->kvm->arch.config_lock);
1715 return ret;
1716 }
1717
1718 ret = arm64_check_features(vcpu, rd, val);
1719 if (!ret)
1720 IDREG(vcpu->kvm, id) = val;
1721
1722 mutex_unlock(&vcpu->kvm->arch.config_lock);
1723
1724 /*
1725 * arm64_check_features() returns -E2BIG to indicate the register's
1726 * feature set is a superset of the maximally-allowed register value.
1727 * While it would be nice to precisely describe this to userspace, the
1728 * existing UAPI for KVM_SET_ONE_REG has it that invalid register
1729 * writes return -EINVAL.
1730 */
1731 if (ret == -E2BIG)
1732 ret = -EINVAL;
1733 return ret;
93390c0a
DM		 1734}
1735
5a430976 1736static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
978ceeb3 1737 u64 *val)
5a430976 1738{
978ceeb3
MZ		 1739 *val = 0;
1740 return 0;
5a430976
AE		 1741}
1742
7a3ba309 1743static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
978ceeb3 1744 u64 val)
7a3ba309 1745{
7a3ba309
MZ		 1746 return 0;
1747}
1748
f7f2b15c
AB		 1749static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1750 const struct sys_reg_desc *r)
1751{
1752 if (p->is_write)
1753 return write_to_read_only(vcpu, p, r);
1754
1755 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1756 return true;
1757}
1758
1759static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1760 const struct sys_reg_desc *r)
1761{
1762 if (p->is_write)
1763 return write_to_read_only(vcpu, p, r);
1764
7af0c253 1765 p->regval = __vcpu_sys_reg(vcpu, r->reg);
f7f2b15c
AB		 1766 return true;
1767}
1768
7af0c253
AO		 1769/*
1770 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary
1771 * by the physical CPU which the vcpu currently resides in.
1772 */
d86cde6e 1773static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
7af0c253
AO		 1774{
1775 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
1776 u64 clidr;
1777 u8 loc;
1778
1779 if ((ctr_el0 & CTR_EL0_IDC)) {
1780 /*
1781 * Data cache clean to the PoU is not required so LoUU and LoUIS
1782 * will not be set and a unified cache, which will be marked as
1783 * LoC, will be added.
1784 *
1785 * If not DIC, let the unified cache L2 so that an instruction
1786 * cache can be added as L1 later.
1787 */
1788 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2;
1789 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc);
1790 } else {
1791 /*
1792 * Data cache clean to the PoU is required so let L1 have a data
1793 * cache and mark it as LoUU and LoUIS. As L1 has a data cache,
1794 * it can be marked as LoC too.
1795 */
1796 loc = 1;
1797 clidr = 1 << CLIDR_LOUU_SHIFT;
1798 clidr |= 1 << CLIDR_LOUIS_SHIFT;
1799 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1);
1800 }
1801
1802 /*
1803 * Instruction cache invalidation to the PoU is required so let L1 have
1804 * an instruction cache. If L1 already has a data cache, it will be
1805 * CACHE_TYPE_SEPARATE.
1806 */
1807 if (!(ctr_el0 & CTR_EL0_DIC))
1808 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1);
1809
1810 clidr |= loc << CLIDR_LOC_SHIFT;
1811
1812 /*
1813 * Add tag cache unified to data cache. Allocation tags and data are
1814 * unified in a cache line so that it looks valid even if there is only
1815 * one cache line.
1816 */
1817 if (kvm_has_mte(vcpu->kvm))
1818 clidr |= 2 << CLIDR_TTYPE_SHIFT(loc);
1819
1820 __vcpu_sys_reg(vcpu, r->reg) = clidr;
d86cde6e
JZ		 1821
1822 return __vcpu_sys_reg(vcpu, r->reg);
7af0c253
AO		 1823}
1824
1825static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1826 u64 val)
1827{
1828 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
1829 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val));
1830
1831 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc))
1832 return -EINVAL;
1833
1834 __vcpu_sys_reg(vcpu, rd->reg) = val;
1835
1836 return 0;
1837}
1838
f7f2b15c
AB		 1839static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1840 const struct sys_reg_desc *r)
1841{
7c582bf4
JM		 1842 int reg = r->reg;
1843
f7f2b15c 1844 if (p->is_write)
7c582bf4 1845 vcpu_write_sys_reg(vcpu, p->regval, reg);
f7f2b15c 1846 else
7c582bf4 1847 p->regval = vcpu_read_sys_reg(vcpu, reg);
f7f2b15c
AB		 1848 return true;
1849}
1850
1851static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1852 const struct sys_reg_desc *r)
1853{
1854 u32 csselr;
1855
1856 if (p->is_write)
1857 return write_to_read_only(vcpu, p, r);
1858
1859 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
7af0c253
AO		 1860 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD;
1861 if (csselr < CSSELR_MAX)
1862 p->regval = get_ccsidr(vcpu, csselr);
793acf87 1863
f7f2b15c
AB		 1864 return true;
1865}
1866
e1f358b5
SP		 1867static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
1868 const struct sys_reg_desc *rd)
1869{
673638f4
SP		 1870 if (kvm_has_mte(vcpu->kvm))
1871 return 0;
1872
e1f358b5
SP		 1873 return REG_HIDDEN;
1874}
1875
1876#define MTE_REG(name) { \
1877 SYS_DESC(SYS_##name), \
1878 .access = undef_access, \
1879 .reset = reset_unknown, \
1880 .reg = name, \
1881 .visibility = mte_visibility, \
1882}
1883
6ff9dc23
JL		 1884static unsigned int el2_visibility(const struct kvm_vcpu *vcpu,
1885 const struct sys_reg_desc *rd)
1886{
1887 if (vcpu_has_nv(vcpu))
1888 return 0;
1889
1890 return REG_HIDDEN;
1891}
1892
1893#define EL2_REG(name, acc, rst, v) { \
1894 SYS_DESC(SYS_##name), \
1895 .access = acc, \
1896 .reset = rst, \
1897 .reg = name, \
1898 .visibility = el2_visibility, \
1899 .val = v, \
1900}
1901
280b748e
JL		 1902/*
1903 * EL{0,1}2 registers are the EL2 view on an EL0 or EL1 register when
1904 * HCR_EL2.E2H==1, and only in the sysreg table for convenience of
1905 * handling traps. Given that, they are always hidden from userspace.
1906 */
3f7915cc
MZ		 1907static unsigned int hidden_user_visibility(const struct kvm_vcpu *vcpu,
1908 const struct sys_reg_desc *rd)
280b748e
JL		 1909{
1910 return REG_HIDDEN_USER;
1911}
1912
1913#define EL12_REG(name, acc, rst, v) { \
1914 SYS_DESC(SYS_##name##_EL12), \
1915 .access = acc, \
1916 .reset = rst, \
1917 .reg = name##_EL1, \
1918 .val = v, \
3f7915cc 1919 .visibility = hidden_user_visibility, \
280b748e
JL		 1920}
1921
d86cde6e
JZ		 1922/*
1923 * Since reset() callback and field val are not used for idregs, they will be
1924 * used for specific purposes for idregs.
1925 * The reset() would return KVM sanitised register value. The value would be the
1926 * same as the host kernel sanitised value if there is no KVM sanitisation.
1927 * The val would be used as a mask indicating writable fields for the idreg.
1928 * Only bits with 1 are writable from userspace. This mask might not be
1929 * necessary in the future whenever all ID registers are enabled as writable
1930 * from userspace.
1931 */
1932
56d77aa8 1933#define ID_DESC(name) \
93390c0a
DM		 1934 SYS_DESC(SYS_##name), \
1935 .access = access_id_reg, \
56d77aa8
OU		 1936 .get_user = get_id_reg \
1937
1938/* sys_reg_desc initialiser for known cpufeature ID registers */
1939#define ID_SANITISED(name) { \
1940 ID_DESC(name), \
93390c0a 1941 .set_user = set_id_reg, \
912dee57 1942 .visibility = id_visibility, \
d86cde6e
JZ		 1943 .reset = kvm_read_sanitised_id_reg, \
1944 .val = 0, \
93390c0a
DM		 1945}
1946
d5efec7e
OU		 1947/* sys_reg_desc initialiser for known cpufeature ID registers */
1948#define AA32_ID_SANITISED(name) { \
56d77aa8 1949 ID_DESC(name), \
d5efec7e
OU		 1950 .set_user = set_id_reg, \
1951 .visibility = aa32_id_visibility, \
d86cde6e
JZ		 1952 .reset = kvm_read_sanitised_id_reg, \
1953 .val = 0, \
d5efec7e
OU		 1954}
1955
56d77aa8
OU		 1956/* sys_reg_desc initialiser for writable ID registers */
1957#define ID_WRITABLE(name, mask) { \
1958 ID_DESC(name), \
1959 .set_user = set_id_reg, \
1960 .visibility = id_visibility, \
1961 .reset = kvm_read_sanitised_id_reg, \
1962 .val = mask, \
1963}
1964
93390c0a
DM		 1965/*
1966 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1967 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1968 * (1 <= crm < 8, 0 <= Op2 < 8).
1969 */
1970#define ID_UNALLOCATED(crm, op2) { \
1971 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
34b4d203
OU		 1972 .access = access_id_reg, \
1973 .get_user = get_id_reg, \
1974 .set_user = set_id_reg, \
d86cde6e
JZ		 1975 .visibility = raz_visibility, \
1976 .reset = kvm_read_sanitised_id_reg, \
1977 .val = 0, \
93390c0a
DM		 1978}
1979
1980/*
1981 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1982 * For now, these are exposed just like unallocated ID regs: they appear
1983 * RAZ for the guest.
1984 */
1985#define ID_HIDDEN(name) { \
56d77aa8 1986 ID_DESC(name), \
34b4d203
OU		 1987 .set_user = set_id_reg, \
1988 .visibility = raz_visibility, \
d86cde6e
JZ		 1989 .reset = kvm_read_sanitised_id_reg, \
1990 .val = 0, \
93390c0a
DM		 1991}
1992
6ff9dc23
JL		 1993static bool access_sp_el1(struct kvm_vcpu *vcpu,
1994 struct sys_reg_params *p,
1995 const struct sys_reg_desc *r)
1996{
1997 if (p->is_write)
1998 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval;
1999 else
2000 p->regval = __vcpu_sys_reg(vcpu, SP_EL1);
2001
2002 return true;
2003}
2004
9da117ee
JL		 2005static bool access_elr(struct kvm_vcpu *vcpu,
2006 struct sys_reg_params *p,
2007 const struct sys_reg_desc *r)
2008{
2009 if (p->is_write)
2010 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1);
2011 else
2012 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1);
2013
2014 return true;
2015}
2016
2017static bool access_spsr(struct kvm_vcpu *vcpu,
2018 struct sys_reg_params *p,
2019 const struct sys_reg_desc *r)
2020{
2021 if (p->is_write)
2022 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval;
2023 else
2024 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1);
2025
2026 return true;
2027}
2028
7c8c5e6a
MZ		 2029/*
2030 * Architected system registers.
2031 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
7609c125 2032 *
0c557ed4
MZ		 2033 * Debug handling: We do trap most, if not all debug related system
2034 * registers. The implementation is good enough to ensure that a guest
2035 * can use these with minimal performance degradation. The drawback is
7dabf02f
OU		 2036 * that we don't implement any of the external debug architecture.
2037 * This should be revisited if we ever encounter a more demanding
2038 * guest...
7c8c5e6a
MZ		 2039 */
2040static const struct sys_reg_desc sys_reg_descs[] = {
7606e078 2041 { SYS_DESC(SYS_DC_ISW), access_dcsw },
d282fa3c
MZ		 2042 { SYS_DESC(SYS_DC_IGSW), access_dcgsw },
2043 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw },
7606e078 2044 { SYS_DESC(SYS_DC_CSW), access_dcsw },
d282fa3c
MZ		 2045 { SYS_DESC(SYS_DC_CGSW), access_dcgsw },
2046 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw },
7606e078 2047 { SYS_DESC(SYS_DC_CISW), access_dcsw },
d282fa3c
MZ		 2048 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw },
2049 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw },
7c8c5e6a 2050
0c557ed4
MZ		 2051 DBG_BCR_BVR_WCR_WVR_EL1(0),
2052 DBG_BCR_BVR_WCR_WVR_EL1(1),
ee1b64e6
MR		 2053 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
2054 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
0c557ed4
MZ		 2055 DBG_BCR_BVR_WCR_WVR_EL1(2),
2056 DBG_BCR_BVR_WCR_WVR_EL1(3),
2057 DBG_BCR_BVR_WCR_WVR_EL1(4),
2058 DBG_BCR_BVR_WCR_WVR_EL1(5),
2059 DBG_BCR_BVR_WCR_WVR_EL1(6),
2060 DBG_BCR_BVR_WCR_WVR_EL1(7),
2061 DBG_BCR_BVR_WCR_WVR_EL1(8),
2062 DBG_BCR_BVR_WCR_WVR_EL1(9),
2063 DBG_BCR_BVR_WCR_WVR_EL1(10),
2064 DBG_BCR_BVR_WCR_WVR_EL1(11),
2065 DBG_BCR_BVR_WCR_WVR_EL1(12),
2066 DBG_BCR_BVR_WCR_WVR_EL1(13),
2067 DBG_BCR_BVR_WCR_WVR_EL1(14),
2068 DBG_BCR_BVR_WCR_WVR_EL1(15),
2069
ee1b64e6 2070 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
f24adc65 2071 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 },
d42e2671 2072 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
187de7c2 2073 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, },
ee1b64e6
MR		 2074 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
2075 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
2076 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
2077 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
2078 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
2079
2080 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
2081 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
2082 // DBGDTR[TR]X_EL0 share the same encoding
2083 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
2084
c7d11a61 2085 { SYS_DESC(SYS_DBGVCR32_EL2), trap_undef, reset_val, DBGVCR32_EL2, 0 },
62a89c44 2086
851050a5 2087 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
93390c0a
DM		 2088
2089 /*
2090 * ID regs: all ID_SANITISED() entries here must have corresponding
2091 * entries in arm64_ftr_regs[].
2092 */
2093
2094 /* AArch64 mappings of the AArch32 ID registers */
2095 /* CRm=1 */
d5efec7e
OU		 2096 AA32_ID_SANITISED(ID_PFR0_EL1),
2097 AA32_ID_SANITISED(ID_PFR1_EL1),
c118cead
JZ		 2098 { SYS_DESC(SYS_ID_DFR0_EL1),
2099 .access = access_id_reg,
2100 .get_user = get_id_reg,
2101 .set_user = set_id_dfr0_el1,
2102 .visibility = aa32_id_visibility,
2103 .reset = read_sanitised_id_dfr0_el1,
9f9917bc
OU		 2104 .val = ID_DFR0_EL1_PerfMon_MASK |
2105 ID_DFR0_EL1_CopDbg_MASK, },
93390c0a 2106 ID_HIDDEN(ID_AFR0_EL1),
d5efec7e
OU		 2107 AA32_ID_SANITISED(ID_MMFR0_EL1),
2108 AA32_ID_SANITISED(ID_MMFR1_EL1),
2109 AA32_ID_SANITISED(ID_MMFR2_EL1),
2110 AA32_ID_SANITISED(ID_MMFR3_EL1),
93390c0a
DM		 2111
2112 /* CRm=2 */
d5efec7e
OU		 2113 AA32_ID_SANITISED(ID_ISAR0_EL1),
2114 AA32_ID_SANITISED(ID_ISAR1_EL1),
2115 AA32_ID_SANITISED(ID_ISAR2_EL1),
2116 AA32_ID_SANITISED(ID_ISAR3_EL1),
2117 AA32_ID_SANITISED(ID_ISAR4_EL1),
2118 AA32_ID_SANITISED(ID_ISAR5_EL1),
2119 AA32_ID_SANITISED(ID_MMFR4_EL1),
2120 AA32_ID_SANITISED(ID_ISAR6_EL1),
93390c0a
DM		 2121
2122 /* CRm=3 */
d5efec7e
OU		 2123 AA32_ID_SANITISED(MVFR0_EL1),
2124 AA32_ID_SANITISED(MVFR1_EL1),
2125 AA32_ID_SANITISED(MVFR2_EL1),
93390c0a 2126 ID_UNALLOCATED(3,3),
d5efec7e 2127 AA32_ID_SANITISED(ID_PFR2_EL1),
dd35ec07 2128 ID_HIDDEN(ID_DFR1_EL1),
d5efec7e 2129 AA32_ID_SANITISED(ID_MMFR5_EL1),
93390c0a
DM		 2130 ID_UNALLOCATED(3,7),
2131
2132 /* AArch64 ID registers */
2133 /* CRm=4 */
c39f5974
JZ		 2134 { SYS_DESC(SYS_ID_AA64PFR0_EL1),
2135 .access = access_id_reg,
2136 .get_user = get_id_reg,
68667240 2137 .set_user = set_id_reg,
c39f5974 2138 .reset = read_sanitised_id_aa64pfr0_el1,
8cfd5be8
JZ		 2139 .val = ~(ID_AA64PFR0_EL1_AMU |
2140 ID_AA64PFR0_EL1_MPAM |
2141 ID_AA64PFR0_EL1_SVE |
2142 ID_AA64PFR0_EL1_RAS |
2143 ID_AA64PFR0_EL1_GIC |
2144 ID_AA64PFR0_EL1_AdvSIMD |
2145 ID_AA64PFR0_EL1_FP), },
93390c0a
DM		 2146 ID_SANITISED(ID_AA64PFR1_EL1),
2147 ID_UNALLOCATED(4,2),
2148 ID_UNALLOCATED(4,3),
f89fbb35 2149 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0),
90807748 2150 ID_HIDDEN(ID_AA64SMFR0_EL1),
93390c0a
DM		 2151 ID_UNALLOCATED(4,6),
2152 ID_UNALLOCATED(4,7),
2153
2154 /* CRm=5 */
c118cead
JZ		 2155 { SYS_DESC(SYS_ID_AA64DFR0_EL1),
2156 .access = access_id_reg,
2157 .get_user = get_id_reg,
2158 .set_user = set_id_aa64dfr0_el1,
2159 .reset = read_sanitised_id_aa64dfr0_el1,
9f9917bc
OU		 2160 .val = ID_AA64DFR0_EL1_PMUVer_MASK |
2161 ID_AA64DFR0_EL1_DebugVer_MASK, },
93390c0a
DM		 2162 ID_SANITISED(ID_AA64DFR1_EL1),
2163 ID_UNALLOCATED(5,2),
2164 ID_UNALLOCATED(5,3),
2165 ID_HIDDEN(ID_AA64AFR0_EL1),
2166 ID_HIDDEN(ID_AA64AFR1_EL1),
2167 ID_UNALLOCATED(5,6),
2168 ID_UNALLOCATED(5,7),
2169
2170 /* CRm=6 */
56d77aa8
OU		 2171 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0),
2172 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI |
2173 ID_AA64ISAR1_EL1_GPA |
2174 ID_AA64ISAR1_EL1_API |
2175 ID_AA64ISAR1_EL1_APA)),
2176 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 |
56d77aa8
OU		 2177 ID_AA64ISAR2_EL1_APA3 |
2178 ID_AA64ISAR2_EL1_GPA3)),
93390c0a
DM		 2179 ID_UNALLOCATED(6,3),
2180 ID_UNALLOCATED(6,4),
2181 ID_UNALLOCATED(6,5),
2182 ID_UNALLOCATED(6,6),
2183 ID_UNALLOCATED(6,7),
2184
2185 /* CRm=7 */
d5a32b60
JZ		 2186 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 |
2187 ID_AA64MMFR0_EL1_TGRAN4_2 |
2188 ID_AA64MMFR0_EL1_TGRAN64_2 |
2189 ID_AA64MMFR0_EL1_TGRAN16_2)),
2190 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 |
2191 ID_AA64MMFR1_EL1_HCX |
2192 ID_AA64MMFR1_EL1_XNX |
2193 ID_AA64MMFR1_EL1_TWED |
2194 ID_AA64MMFR1_EL1_XNX |
2195 ID_AA64MMFR1_EL1_VH |
2196 ID_AA64MMFR1_EL1_VMIDBits)),
2197 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 |
2198 ID_AA64MMFR2_EL1_EVT |
2199 ID_AA64MMFR2_EL1_FWB |
2200 ID_AA64MMFR2_EL1_IDS |
2201 ID_AA64MMFR2_EL1_NV |
2202 ID_AA64MMFR2_EL1_CCIDX)),
8ef67c67 2203 ID_SANITISED(ID_AA64MMFR3_EL1),
93390c0a
DM		 2204 ID_UNALLOCATED(7,4),
2205 ID_UNALLOCATED(7,5),
2206 ID_UNALLOCATED(7,6),
2207 ID_UNALLOCATED(7,7),
2208
851050a5 2209 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
af473829 2210 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
851050a5 2211 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
2ac638fc 2212
e1f358b5
SP		 2213 MTE_REG(RGSR_EL1),
2214 MTE_REG(GCR_EL1),
2ac638fc 2215
73433762 2216 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
cc427cbb 2217 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
90807748
MB		 2218 { SYS_DESC(SYS_SMPRI_EL1), undef_access },
2219 { SYS_DESC(SYS_SMCR_EL1), undef_access },
851050a5
MR		 2220 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
2221 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
2222 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
fbff5606 2223 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 },
851050a5 2224
384b40ca
MR		 2225 PTRAUTH_KEY(APIA),
2226 PTRAUTH_KEY(APIB),
2227 PTRAUTH_KEY(APDA),
2228 PTRAUTH_KEY(APDB),
2229 PTRAUTH_KEY(APGA),
2230
9da117ee
JL		 2231 { SYS_DESC(SYS_SPSR_EL1), access_spsr},
2232 { SYS_DESC(SYS_ELR_EL1), access_elr},
2233
851050a5
MR		 2234 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
2235 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
2236 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
558daf69
DG		 2237
2238 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
2239 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
2240 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
2241 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
2242 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
2243 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
2244 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
2245 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
2246
e1f358b5
SP		 2247 MTE_REG(TFSR_EL1),
2248 MTE_REG(TFSRE0_EL1),
2ac638fc 2249
851050a5
MR		 2250 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
2251 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
7c8c5e6a 2252
13611bc8
AE		 2253 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
2254 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
2255 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
2256 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
2257 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
2258 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
2259 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
2260 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
2261 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
2262 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
2263 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
2264 /* PMBIDR_EL1 is not trapped */
2265
9d2a55b4 2266 { PMU_SYS_REG(PMINTENSET_EL1),
a45f41d7
RRA		 2267 .access = access_pminten, .reg = PMINTENSET_EL1,
2268 .get_user = get_pmreg, .set_user = set_pmreg },
9d2a55b4 2269 { PMU_SYS_REG(PMINTENCLR_EL1),
a45f41d7
RRA		 2270 .access = access_pminten, .reg = PMINTENSET_EL1,
2271 .get_user = get_pmreg, .set_user = set_pmreg },
46081078 2272 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
7c8c5e6a 2273
851050a5 2274 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
839d9035
JG		 2275 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1 },
2276 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1 },
851050a5 2277 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
7c8c5e6a 2278
22925521
MZ		 2279 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
2280 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
2281 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
2282 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
2283 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
cc33c4e2 2284
9da117ee 2285 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },
c773ae2b 2286 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
db7dedd0 2287
7b1dba1f 2288 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
e7f1d1ee 2289 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
7b1dba1f 2290 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
e7f1d1ee 2291 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
7b1dba1f 2292 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
e804d208 2293 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
03bd646d
MZ		 2294 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
2295 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
7b1dba1f 2296 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
e7f1d1ee 2297 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
7b1dba1f 2298 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
e804d208 2299 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
db7dedd0 2300
851050a5
MR		 2301 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
2302 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
7c8c5e6a 2303
484f8682
MZ		 2304 { SYS_DESC(SYS_ACCDATA_EL1), undef_access },
2305
ed4ffaf4
MZ		 2306 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
2307
851050a5 2308 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
7c8c5e6a 2309
f7f2b15c 2310 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
7af0c253
AO		 2311 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1,
2312 .set_user = set_clidr },
bf48040c 2313 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access },
90807748 2314 { SYS_DESC(SYS_SMIDR_EL1), undef_access },
f7f2b15c
AB		 2315 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
2316 { SYS_DESC(SYS_CTR_EL0), access_ctr },
ec0067a6 2317 { SYS_DESC(SYS_SVCR), undef_access },
7c8c5e6a 2318
ea9ca904
RW		 2319 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr,
2320 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr },
9d2a55b4 2321 { PMU_SYS_REG(PMCNTENSET_EL0),
a45f41d7
RRA		 2322 .access = access_pmcnten, .reg = PMCNTENSET_EL0,
2323 .get_user = get_pmreg, .set_user = set_pmreg },
9d2a55b4 2324 { PMU_SYS_REG(PMCNTENCLR_EL0),
a45f41d7
RRA		 2325 .access = access_pmcnten, .reg = PMCNTENSET_EL0,
2326 .get_user = get_pmreg, .set_user = set_pmreg },
9d2a55b4 2327 { PMU_SYS_REG(PMOVSCLR_EL0),
a45f41d7
RRA		 2328 .access = access_pmovs, .reg = PMOVSSET_EL0,
2329 .get_user = get_pmreg, .set_user = set_pmreg },
7a3ba309
MZ		 2330 /*
2331 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
2332 * previously (and pointlessly) advertised in the past...
2333 */
9d2a55b4 2334 { PMU_SYS_REG(PMSWINC_EL0),
5a430976 2335 .get_user = get_raz_reg, .set_user = set_wi_reg,
7a3ba309 2336 .access = access_pmswinc, .reset = NULL },
9d2a55b4 2337 { PMU_SYS_REG(PMSELR_EL0),
0ab410a9 2338 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
9d2a55b4 2339 { PMU_SYS_REG(PMCEID0_EL0),
11663111 2340 .access = access_pmceid, .reset = NULL },
9d2a55b4 2341 { PMU_SYS_REG(PMCEID1_EL0),
11663111 2342 .access = access_pmceid, .reset = NULL },
9d2a55b4 2343 { PMU_SYS_REG(PMCCNTR_EL0),
9228b261
RW		 2344 .access = access_pmu_evcntr, .reset = reset_unknown,
2345 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr},
9d2a55b4 2346 { PMU_SYS_REG(PMXEVTYPER_EL0),
11663111 2347 .access = access_pmu_evtyper, .reset = NULL },
9d2a55b4 2348 { PMU_SYS_REG(PMXEVCNTR_EL0),
11663111 2349 .access = access_pmu_evcntr, .reset = NULL },
174ed3e4
MR		 2350 /*
2351 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
d692b8ad
SZ		 2352 * in 32bit mode. Here we choose to reset it as zero for consistency.
2353 */
9d2a55b4 2354 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr,
11663111 2355 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
9d2a55b4 2356 { PMU_SYS_REG(PMOVSSET_EL0),
a45f41d7
RRA		 2357 .access = access_pmovs, .reg = PMOVSSET_EL0,
2358 .get_user = get_pmreg, .set_user = set_pmreg },
7c8c5e6a 2359
851050a5
MR		 2360 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
2361 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
90807748 2362 { SYS_DESC(SYS_TPIDR2_EL0), undef_access },
4fcdf106 2363
ed4ffaf4
MZ		 2364 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
2365
338b1793
MZ		 2366 { SYS_DESC(SYS_AMCR_EL0), undef_access },
2367 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
2368 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
2369 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
2370 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
2371 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
2372 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
2373 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
4fcdf106
IV		 2374 AMU_AMEVCNTR0_EL0(0),
2375 AMU_AMEVCNTR0_EL0(1),
2376 AMU_AMEVCNTR0_EL0(2),
2377 AMU_AMEVCNTR0_EL0(3),
2378 AMU_AMEVCNTR0_EL0(4),
2379 AMU_AMEVCNTR0_EL0(5),
2380 AMU_AMEVCNTR0_EL0(6),
2381 AMU_AMEVCNTR0_EL0(7),
2382 AMU_AMEVCNTR0_EL0(8),
2383 AMU_AMEVCNTR0_EL0(9),
2384 AMU_AMEVCNTR0_EL0(10),
2385 AMU_AMEVCNTR0_EL0(11),
2386 AMU_AMEVCNTR0_EL0(12),
2387 AMU_AMEVCNTR0_EL0(13),
2388 AMU_AMEVCNTR0_EL0(14),
2389 AMU_AMEVCNTR0_EL0(15),
493cf9b7
VM		 2390 AMU_AMEVTYPER0_EL0(0),
2391 AMU_AMEVTYPER0_EL0(1),
2392 AMU_AMEVTYPER0_EL0(2),
2393 AMU_AMEVTYPER0_EL0(3),
2394 AMU_AMEVTYPER0_EL0(4),
2395 AMU_AMEVTYPER0_EL0(5),
2396 AMU_AMEVTYPER0_EL0(6),
2397 AMU_AMEVTYPER0_EL0(7),
2398 AMU_AMEVTYPER0_EL0(8),
2399 AMU_AMEVTYPER0_EL0(9),
2400 AMU_AMEVTYPER0_EL0(10),
2401 AMU_AMEVTYPER0_EL0(11),
2402 AMU_AMEVTYPER0_EL0(12),
2403 AMU_AMEVTYPER0_EL0(13),
2404 AMU_AMEVTYPER0_EL0(14),
2405 AMU_AMEVTYPER0_EL0(15),
4fcdf106
IV		 2406 AMU_AMEVCNTR1_EL0(0),
2407 AMU_AMEVCNTR1_EL0(1),
2408 AMU_AMEVCNTR1_EL0(2),
2409 AMU_AMEVCNTR1_EL0(3),
2410 AMU_AMEVCNTR1_EL0(4),
2411 AMU_AMEVCNTR1_EL0(5),
2412 AMU_AMEVCNTR1_EL0(6),
2413 AMU_AMEVCNTR1_EL0(7),
2414 AMU_AMEVCNTR1_EL0(8),
2415 AMU_AMEVCNTR1_EL0(9),
2416 AMU_AMEVCNTR1_EL0(10),
2417 AMU_AMEVCNTR1_EL0(11),
2418 AMU_AMEVCNTR1_EL0(12),
2419 AMU_AMEVCNTR1_EL0(13),
2420 AMU_AMEVCNTR1_EL0(14),
2421 AMU_AMEVCNTR1_EL0(15),
493cf9b7
VM		 2422 AMU_AMEVTYPER1_EL0(0),
2423 AMU_AMEVTYPER1_EL0(1),
2424 AMU_AMEVTYPER1_EL0(2),
2425 AMU_AMEVTYPER1_EL0(3),
2426 AMU_AMEVTYPER1_EL0(4),
2427 AMU_AMEVTYPER1_EL0(5),
2428 AMU_AMEVTYPER1_EL0(6),
2429 AMU_AMEVTYPER1_EL0(7),
2430 AMU_AMEVTYPER1_EL0(8),
2431 AMU_AMEVTYPER1_EL0(9),
2432 AMU_AMEVTYPER1_EL0(10),
2433 AMU_AMEVTYPER1_EL0(11),
2434 AMU_AMEVTYPER1_EL0(12),
2435 AMU_AMEVTYPER1_EL0(13),
2436 AMU_AMEVTYPER1_EL0(14),
2437 AMU_AMEVTYPER1_EL0(15),
62a89c44 2438
c605ee24
MZ		 2439 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer },
2440 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer },
84135d3d
AP		 2441 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
2442 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
2443 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
c9a3c58f 2444
051ff581
SZ		 2445 /* PMEVCNTRn_EL0 */
2446 PMU_PMEVCNTR_EL0(0),
2447 PMU_PMEVCNTR_EL0(1),
2448 PMU_PMEVCNTR_EL0(2),
2449 PMU_PMEVCNTR_EL0(3),
2450 PMU_PMEVCNTR_EL0(4),
2451 PMU_PMEVCNTR_EL0(5),
2452 PMU_PMEVCNTR_EL0(6),
2453 PMU_PMEVCNTR_EL0(7),
2454 PMU_PMEVCNTR_EL0(8),
2455 PMU_PMEVCNTR_EL0(9),
2456 PMU_PMEVCNTR_EL0(10),
2457 PMU_PMEVCNTR_EL0(11),
2458 PMU_PMEVCNTR_EL0(12),
2459 PMU_PMEVCNTR_EL0(13),
2460 PMU_PMEVCNTR_EL0(14),
2461 PMU_PMEVCNTR_EL0(15),
2462 PMU_PMEVCNTR_EL0(16),
2463 PMU_PMEVCNTR_EL0(17),
2464 PMU_PMEVCNTR_EL0(18),
2465 PMU_PMEVCNTR_EL0(19),
2466 PMU_PMEVCNTR_EL0(20),
2467 PMU_PMEVCNTR_EL0(21),
2468 PMU_PMEVCNTR_EL0(22),
2469 PMU_PMEVCNTR_EL0(23),
2470 PMU_PMEVCNTR_EL0(24),
2471 PMU_PMEVCNTR_EL0(25),
2472 PMU_PMEVCNTR_EL0(26),
2473 PMU_PMEVCNTR_EL0(27),
2474 PMU_PMEVCNTR_EL0(28),
2475 PMU_PMEVCNTR_EL0(29),
2476 PMU_PMEVCNTR_EL0(30),
9feb21ac
SZ		 2477 /* PMEVTYPERn_EL0 */
2478 PMU_PMEVTYPER_EL0(0),
2479 PMU_PMEVTYPER_EL0(1),
2480 PMU_PMEVTYPER_EL0(2),
2481 PMU_PMEVTYPER_EL0(3),
2482 PMU_PMEVTYPER_EL0(4),
2483 PMU_PMEVTYPER_EL0(5),
2484 PMU_PMEVTYPER_EL0(6),
2485 PMU_PMEVTYPER_EL0(7),
2486 PMU_PMEVTYPER_EL0(8),
2487 PMU_PMEVTYPER_EL0(9),
2488 PMU_PMEVTYPER_EL0(10),
2489 PMU_PMEVTYPER_EL0(11),
2490 PMU_PMEVTYPER_EL0(12),
2491 PMU_PMEVTYPER_EL0(13),
2492 PMU_PMEVTYPER_EL0(14),
2493 PMU_PMEVTYPER_EL0(15),
2494 PMU_PMEVTYPER_EL0(16),
2495 PMU_PMEVTYPER_EL0(17),
2496 PMU_PMEVTYPER_EL0(18),
2497 PMU_PMEVTYPER_EL0(19),
2498 PMU_PMEVTYPER_EL0(20),
2499 PMU_PMEVTYPER_EL0(21),
2500 PMU_PMEVTYPER_EL0(22),
2501 PMU_PMEVTYPER_EL0(23),
2502 PMU_PMEVTYPER_EL0(24),
2503 PMU_PMEVTYPER_EL0(25),
2504 PMU_PMEVTYPER_EL0(26),
2505 PMU_PMEVTYPER_EL0(27),
2506 PMU_PMEVTYPER_EL0(28),
2507 PMU_PMEVTYPER_EL0(29),
2508 PMU_PMEVTYPER_EL0(30),
174ed3e4
MR		 2509 /*
2510 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
9feb21ac
SZ		 2511 * in 32bit mode. Here we choose to reset it as zero for consistency.
2512 */
9d2a55b4 2513 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper,
11663111 2514 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
051ff581 2515
6ff9dc23
JL		 2516 EL2_REG(VPIDR_EL2, access_rw, reset_unknown, 0),
2517 EL2_REG(VMPIDR_EL2, access_rw, reset_unknown, 0),
2518 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),
2519 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),
2520 EL2_REG(HCR_EL2, access_rw, reset_val, 0),
2521 EL2_REG(MDCR_EL2, access_rw, reset_val, 0),
75c76ab5 2522 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
6ff9dc23 2523 EL2_REG(HSTR_EL2, access_rw, reset_val, 0),
50d2fe46
MZ		 2524 EL2_REG(HFGRTR_EL2, access_rw, reset_val, 0),
2525 EL2_REG(HFGWTR_EL2, access_rw, reset_val, 0),
2526 EL2_REG(HFGITR_EL2, access_rw, reset_val, 0),
6ff9dc23
JL		 2527 EL2_REG(HACR_EL2, access_rw, reset_val, 0),
2528
03fb54d0
MZ		 2529 EL2_REG(HCRX_EL2, access_rw, reset_val, 0),
2530
6ff9dc23
JL		 2531 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
2532 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
2533 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
2534 EL2_REG(VTTBR_EL2, access_rw, reset_val, 0),
2535 EL2_REG(VTCR_EL2, access_rw, reset_val, 0),
2536
c7d11a61 2537 { SYS_DESC(SYS_DACR32_EL2), trap_undef, reset_unknown, DACR32_EL2 },
50d2fe46
MZ		 2538 EL2_REG(HDFGRTR_EL2, access_rw, reset_val, 0),
2539 EL2_REG(HDFGWTR_EL2, access_rw, reset_val, 0),
6ff9dc23
JL		 2540 EL2_REG(SPSR_EL2, access_rw, reset_val, 0),
2541 EL2_REG(ELR_EL2, access_rw, reset_val, 0),
2542 { SYS_DESC(SYS_SP_EL1), access_sp_el1},
2543
3f7915cc
MZ		 2544 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */
2545 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi,
2546 .visibility = hidden_user_visibility },
2547 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi,
2548 .visibility = hidden_user_visibility },
2549 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi,
2550 .visibility = hidden_user_visibility },
2551 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi,
2552 .visibility = hidden_user_visibility },
2553
c7d11a61 2554 { SYS_DESC(SYS_IFSR32_EL2), trap_undef, reset_unknown, IFSR32_EL2 },
6ff9dc23
JL		 2555 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
2556 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
2557 EL2_REG(ESR_EL2, access_rw, reset_val, 0),
c7d11a61 2558 { SYS_DESC(SYS_FPEXC32_EL2), trap_undef, reset_val, FPEXC32_EL2, 0x700 },
6ff9dc23
JL		 2559
2560 EL2_REG(FAR_EL2, access_rw, reset_val, 0),
2561 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
2562
2563 EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
2564 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
2565
2566 EL2_REG(VBAR_EL2, access_rw, reset_val, 0),
2567 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0),
2568 { SYS_DESC(SYS_RMR_EL2), trap_undef },
2569
2570 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0),
2571 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0),
2572
2573 EL2_REG(CNTVOFF_EL2, access_rw, reset_val, 0),
2574 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0),
2575
280b748e
JL		 2576 EL12_REG(CNTKCTL, access_rw, reset_val, 0),
2577
6ff9dc23 2578 EL2_REG(SP_EL2, NULL, reset_unknown, 0),
62a89c44
MZ		 2579};
2580
47334146
JZ		 2581static const struct sys_reg_desc *first_idreg;
2582
8c358b29 2583static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
3fec037d 2584 struct sys_reg_params *p,
bdfb4b38
MZ		 2585 const struct sys_reg_desc *r)
2586{
2587 if (p->is_write) {
2588 return ignore_write(vcpu, p);
2589 } else {
8b6958d6
JZ		 2590 u64 dfr = IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1);
2591 u64 pfr = IDREG(vcpu->kvm, SYS_ID_AA64PFR0_EL1);
5a23e5c7 2592 u32 el3 = !!SYS_FIELD_GET(ID_AA64PFR0_EL1, EL3, pfr);
bdfb4b38 2593
5a23e5c7
OU		 2594 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) |
2595 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) |
2596 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) |
2597 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) |
2598 (1 << 15) | (el3 << 14) | (el3 << 12));
bdfb4b38
MZ		 2599 return true;
2600 }
2601}
2602
1da42c34
MZ		 2603/*
2604 * AArch32 debug register mappings
84e690bf
AB		 2605 *
2606 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
2607 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
2608 *
1da42c34
MZ		 2609 * None of the other registers share their location, so treat them as
2610 * if they were 64bit.
84e690bf 2611 */
1da42c34
MZ		 2612#define DBG_BCR_BVR_WCR_WVR(n) \
2613 /* DBGBVRn */ \
2614 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
2615 /* DBGBCRn */ \
2616 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
2617 /* DBGWVRn */ \
2618 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
2619 /* DBGWCRn */ \
84e690bf
AB		 2620 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
2621
1da42c34
MZ		 2622#define DBGBXVR(n) \
2623 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
bdfb4b38
MZ		 2624
2625/*
2626 * Trapped cp14 registers. We generally ignore most of the external
2627 * debug, on the principle that they don't really make sense to a
84e690bf 2628 * guest. Revisit this one day, would this principle change.
bdfb4b38 2629 */
72564016 2630static const struct sys_reg_desc cp14_regs[] = {
8c358b29
AE		 2631 /* DBGDIDR */
2632 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
bdfb4b38
MZ		 2633 /* DBGDTRRXext */
2634 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
2635
2636 DBG_BCR_BVR_WCR_WVR(0),
2637 /* DBGDSCRint */
2638 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
2639 DBG_BCR_BVR_WCR_WVR(1),
2640 /* DBGDCCINT */
1da42c34 2641 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
bdfb4b38 2642 /* DBGDSCRext */
1da42c34 2643 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
bdfb4b38
MZ		 2644 DBG_BCR_BVR_WCR_WVR(2),
2645 /* DBGDTR[RT]Xint */
2646 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
2647 /* DBGDTR[RT]Xext */
2648 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
2649 DBG_BCR_BVR_WCR_WVR(3),
2650 DBG_BCR_BVR_WCR_WVR(4),
2651 DBG_BCR_BVR_WCR_WVR(5),
2652 /* DBGWFAR */
2653 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
2654 /* DBGOSECCR */
2655 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
2656 DBG_BCR_BVR_WCR_WVR(6),
2657 /* DBGVCR */
1da42c34 2658 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
bdfb4b38
MZ		 2659 DBG_BCR_BVR_WCR_WVR(7),
2660 DBG_BCR_BVR_WCR_WVR(8),
2661 DBG_BCR_BVR_WCR_WVR(9),
2662 DBG_BCR_BVR_WCR_WVR(10),
2663 DBG_BCR_BVR_WCR_WVR(11),
2664 DBG_BCR_BVR_WCR_WVR(12),
2665 DBG_BCR_BVR_WCR_WVR(13),
2666 DBG_BCR_BVR_WCR_WVR(14),
2667 DBG_BCR_BVR_WCR_WVR(15),
2668
2669 /* DBGDRAR (32bit) */
2670 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
2671
2672 DBGBXVR(0),
2673 /* DBGOSLAR */
f24adc65 2674 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },
bdfb4b38
MZ		 2675 DBGBXVR(1),
2676 /* DBGOSLSR */
d42e2671 2677 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },
bdfb4b38
MZ		 2678 DBGBXVR(2),
2679 DBGBXVR(3),
2680 /* DBGOSDLR */
2681 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
2682 DBGBXVR(4),
2683 /* DBGPRCR */
2684 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
2685 DBGBXVR(5),
2686 DBGBXVR(6),
2687 DBGBXVR(7),
2688 DBGBXVR(8),
2689 DBGBXVR(9),
2690 DBGBXVR(10),
2691 DBGBXVR(11),
2692 DBGBXVR(12),
2693 DBGBXVR(13),
2694 DBGBXVR(14),
2695 DBGBXVR(15),
2696
2697 /* DBGDSAR (32bit) */
2698 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
2699
2700 /* DBGDEVID2 */
2701 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
2702 /* DBGDEVID1 */
2703 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
2704 /* DBGDEVID */
2705 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
2706 /* DBGCLAIMSET */
2707 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
2708 /* DBGCLAIMCLR */
2709 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
2710 /* DBGAUTHSTATUS */
2711 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
72564016
MZ		 2712};
2713
a9866ba0
MZ		 2714/* Trapped cp14 64bit registers */
2715static const struct sys_reg_desc cp14_64_regs[] = {
bdfb4b38
MZ		 2716 /* DBGDRAR (64bit) */
2717 { Op1( 0), CRm( 1), .access = trap_raz_wi },
2718
2719 /* DBGDSAR (64bit) */
2720 { Op1( 0), CRm( 2), .access = trap_raz_wi },
a9866ba0
MZ		 2721};
2722
a9e192cd
AE		 2723#define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \
2724 AA32(_map), \
2725 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \
2726 .visibility = pmu_visibility
2727
051ff581
SZ		 2728/* Macro to expand the PMEVCNTRn register */
2729#define PMU_PMEVCNTR(n) \
a9e192cd
AE		 2730 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
2731 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
2732 .access = access_pmu_evcntr }
051ff581 2733
9feb21ac
SZ		 2734/* Macro to expand the PMEVTYPERn register */
2735#define PMU_PMEVTYPER(n) \
a9e192cd
AE		 2736 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
2737 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
2738 .access = access_pmu_evtyper }
4d44923b
MZ		 2739/*
2740 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
2741 * depending on the way they are accessed (as a 32bit or a 64bit
2742 * register).
2743 */
62a89c44 2744static const struct sys_reg_desc cp15_regs[] = {
f7f2b15c 2745 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
b1ea1d76
MZ		 2746 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
2747 /* ACTLR */
2748 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
2749 /* ACTLR2 */
2750 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
2751 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2752 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
2753 /* TTBCR */
2754 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
2755 /* TTBCR2 */
2756 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
2757 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
2758 /* DFSR */
2759 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
2760 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
2761 /* ADFSR */
2762 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
2763 /* AIFSR */
2764 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
2765 /* DFAR */
2766 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
2767 /* IFAR */
2768 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
4d44923b 2769
62a89c44
MZ		 2770 /*
2771 * DC{C,I,CI}SW operations:
2772 */
2773 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
2774 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
2775 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
4d44923b 2776
7609c125 2777 /* PMU */
a9e192cd
AE		 2778 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr },
2779 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten },
2780 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten },
2781 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs },
2782 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc },
2783 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr },
2784 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid },
2785 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid },
2786 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr },
2787 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper },
2788 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr },
2789 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr },
2790 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten },
2791 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten },
2792 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs },
2793 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid },
2794 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid },
46081078 2795 /* PMMIR */
a9e192cd 2796 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi },
4d44923b 2797
b1ea1d76
MZ		 2798 /* PRRR/MAIR0 */
2799 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
2800 /* NMRR/MAIR1 */
2801 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
2802 /* AMAIR0 */
2803 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
2804 /* AMAIR1 */
2805 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
db7dedd0
CD		 2806
2807 /* ICC_SRE */
f7f6f2d9 2808 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
db7dedd0 2809
b1ea1d76 2810 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
051ff581 2811
84135d3d
AP		 2812 /* Arch Tmers */
2813 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
2814 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
eac137b4 2815
051ff581
SZ		 2816 /* PMEVCNTRn */
2817 PMU_PMEVCNTR(0),
2818 PMU_PMEVCNTR(1),
2819 PMU_PMEVCNTR(2),
2820 PMU_PMEVCNTR(3),
2821 PMU_PMEVCNTR(4),
2822 PMU_PMEVCNTR(5),
2823 PMU_PMEVCNTR(6),
2824 PMU_PMEVCNTR(7),
2825 PMU_PMEVCNTR(8),
2826 PMU_PMEVCNTR(9),
2827 PMU_PMEVCNTR(10),
2828 PMU_PMEVCNTR(11),
2829 PMU_PMEVCNTR(12),
2830 PMU_PMEVCNTR(13),
2831 PMU_PMEVCNTR(14),
2832 PMU_PMEVCNTR(15),
2833 PMU_PMEVCNTR(16),
2834 PMU_PMEVCNTR(17),
2835 PMU_PMEVCNTR(18),
2836 PMU_PMEVCNTR(19),
2837 PMU_PMEVCNTR(20),
2838 PMU_PMEVCNTR(21),
2839 PMU_PMEVCNTR(22),
2840 PMU_PMEVCNTR(23),
2841 PMU_PMEVCNTR(24),
2842 PMU_PMEVCNTR(25),
2843 PMU_PMEVCNTR(26),
2844 PMU_PMEVCNTR(27),
2845 PMU_PMEVCNTR(28),
2846 PMU_PMEVCNTR(29),
2847 PMU_PMEVCNTR(30),
9feb21ac
SZ		 2848 /* PMEVTYPERn */
2849 PMU_PMEVTYPER(0),
2850 PMU_PMEVTYPER(1),
2851 PMU_PMEVTYPER(2),
2852 PMU_PMEVTYPER(3),
2853 PMU_PMEVTYPER(4),
2854 PMU_PMEVTYPER(5),
2855 PMU_PMEVTYPER(6),
2856 PMU_PMEVTYPER(7),
2857 PMU_PMEVTYPER(8),
2858 PMU_PMEVTYPER(9),
2859 PMU_PMEVTYPER(10),
2860 PMU_PMEVTYPER(11),
2861 PMU_PMEVTYPER(12),
2862 PMU_PMEVTYPER(13),
2863 PMU_PMEVTYPER(14),
2864 PMU_PMEVTYPER(15),
2865 PMU_PMEVTYPER(16),
2866 PMU_PMEVTYPER(17),
2867 PMU_PMEVTYPER(18),
2868 PMU_PMEVTYPER(19),
2869 PMU_PMEVTYPER(20),
2870 PMU_PMEVTYPER(21),
2871 PMU_PMEVTYPER(22),
2872 PMU_PMEVTYPER(23),
2873 PMU_PMEVTYPER(24),
2874 PMU_PMEVTYPER(25),
2875 PMU_PMEVTYPER(26),
2876 PMU_PMEVTYPER(27),
2877 PMU_PMEVTYPER(28),
2878 PMU_PMEVTYPER(29),
2879 PMU_PMEVTYPER(30),
2880 /* PMCCFILTR */
a9e192cd 2881 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper },
f7f2b15c
AB		 2882
2883 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2884 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
bf48040c
AO		 2885
2886 /* CCSIDR2 */
2887 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access },
2888
b1ea1d76 2889 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
a9866ba0
MZ		 2890};
2891
2892static const struct sys_reg_desc cp15_64_regs[] = {
b1ea1d76 2893 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
a9e192cd 2894 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr },
03bd646d 2895 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
c605ee24 2896 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer },
b1ea1d76 2897 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
03bd646d
MZ		 2898 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2899 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
84135d3d 2900 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
a6610435 2901 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer },
7c8c5e6a
MZ		 2902};
2903
f1f0c0cf
AE		 2904static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2905 bool is_32)
bb44a8db
MZ		 2906{
2907 unsigned int i;
2908
2909 for (i = 0; i < n; i++) {
2910 if (!is_32 && table[i].reg && !table[i].reset) {
325031d4 2911 kvm_err("sys_reg table %pS entry %d lacks reset\n", &table[i], i);
f1f0c0cf 2912 return false;
bb44a8db
MZ		 2913 }
2914
2915 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
325031d4 2916 kvm_err("sys_reg table %pS entry %d out of order\n", &table[i - 1], i - 1);
f1f0c0cf 2917 return false;
bb44a8db
MZ		 2918 }
2919 }
2920
f1f0c0cf 2921 return true;
bb44a8db
MZ		 2922}
2923
74cc7e0c 2924int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
62a89c44
MZ		 2925{
2926 kvm_inject_undefined(vcpu);
2927 return 1;
2928}
2929
e70b9522
MZ		 2930static void perform_access(struct kvm_vcpu *vcpu,
2931 struct sys_reg_params *params,
2932 const struct sys_reg_desc *r)
2933{
599d79dc
MZ		 2934 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2935
7f34e409 2936 /* Check for regs disabled by runtime config */
01fe5ace 2937 if (sysreg_hidden(vcpu, r)) {
7f34e409
DM		 2938 kvm_inject_undefined(vcpu);
2939 return;
2940 }
2941
e70b9522
MZ		 2942 /*
2943 * Not having an accessor means that we have configured a trap
2944 * that we don't know how to handle. This certainly qualifies
2945 * as a gross bug that should be fixed right away.
2946 */
2947 BUG_ON(!r->access);
2948
2949 /* Skip instruction if instructed so */
2950 if (likely(r->access(vcpu, params, r)))
cdb5e02e 2951 kvm_incr_pc(vcpu);
e70b9522
MZ		 2952}
2953
72564016
MZ		 2954/*
2955 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2956 * call the corresponding trap handler.
2957 *
2958 * @params: pointer to the descriptor of the access
2959 * @table: array of trap descriptors
2960 * @num: size of the trap descriptor array
2961 *
001bb819 2962 * Return true if the access has been handled, false if not.
72564016 2963 */
001bb819
OU		 2964static bool emulate_cp(struct kvm_vcpu *vcpu,
2965 struct sys_reg_params *params,
2966 const struct sys_reg_desc *table,
2967 size_t num)
62a89c44 2968{
72564016 2969 const struct sys_reg_desc *r;
62a89c44 2970
72564016 2971 if (!table)
001bb819 2972 return false; /* Not handled */
62a89c44 2973
62a89c44 2974 r = find_reg(params, table, num);
62a89c44 2975
72564016 2976 if (r) {
e70b9522 2977 perform_access(vcpu, params, r);
001bb819 2978 return true;
72564016
MZ		 2979 }
2980
2981 /* Not handled */
001bb819 2982 return false;
72564016
MZ		 2983}
2984
2985static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2986 struct sys_reg_params *params)
2987{
3a949f4c 2988 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
40c4f8d2 2989 int cp = -1;
72564016 2990
3a949f4c 2991 switch (esr_ec) {
c6d01a94
MR		 2992 case ESR_ELx_EC_CP15_32:
2993 case ESR_ELx_EC_CP15_64:
72564016
MZ		 2994 cp = 15;
2995 break;
c6d01a94
MR		 2996 case ESR_ELx_EC_CP14_MR:
2997 case ESR_ELx_EC_CP14_64:
72564016
MZ		 2998 cp = 14;
2999 break;
3000 default:
40c4f8d2 3001 WARN_ON(1);
62a89c44
MZ		 3002 }
3003
bf4b96bb
MR		 3004 print_sys_reg_msg(params,
3005 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
3006 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
62a89c44
MZ		 3007 kvm_inject_undefined(vcpu);
3008}
3009
3010/**
7769db90 3011 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
62a89c44
MZ		 3012 * @vcpu: The VCPU pointer
3013 * @run: The kvm_run struct
3014 */
72564016
MZ		 3015static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
3016 const struct sys_reg_desc *global,
dcaffa7b 3017 size_t nr_global)
62a89c44
MZ		 3018{
3019 struct sys_reg_params params;
0b12620f 3020 u64 esr = kvm_vcpu_get_esr(vcpu);
c667186f 3021 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3a949f4c 3022 int Rt2 = (esr >> 10) & 0x1f;
62a89c44 3023
3a949f4c
GS		 3024 params.CRm = (esr >> 1) & 0xf;
3025 params.is_write = ((esr & 1) == 0);
62a89c44
MZ		 3026
3027 params.Op0 = 0;
3a949f4c 3028 params.Op1 = (esr >> 16) & 0xf;
62a89c44
MZ		 3029 params.Op2 = 0;
3030 params.CRn = 0;
3031
3032 /*
2ec5be3d 3033 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
62a89c44
MZ		 3034 * backends between AArch32 and AArch64, we get away with it.
3035 */
3036 if (params.is_write) {
2ec5be3d
PF		 3037 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
3038 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
62a89c44
MZ		 3039 }
3040
b6b7a806 3041 /*
dcaffa7b 3042 * If the table contains a handler, handle the
b6b7a806
MZ		 3043 * potential register operation in the case of a read and return
3044 * with success.
3045 */
001bb819 3046 if (emulate_cp(vcpu, &params, global, nr_global)) {
b6b7a806
MZ		 3047 /* Split up the value between registers for the read side */
3048 if (!params.is_write) {
3049 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
3050 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
3051 }
62a89c44 3052
b6b7a806 3053 return 1;
62a89c44
MZ		 3054 }
3055
b6b7a806 3056 unhandled_cp_access(vcpu, &params);
62a89c44
MZ		 3057 return 1;
3058}
3059
e6519766
OU		 3060static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
3061
9369bc5c
OU		 3062/*
3063 * The CP10 ID registers are architecturally mapped to AArch64 feature
3064 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses
3065 * from AArch32.
3066 */
ee87a9bd 3067static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params)
9369bc5c
OU		 3068{
3069 u8 reg_id = (esr >> 10) & 0xf;
3070 bool valid;
3071
3072 params->is_write = ((esr & 1) == 0);
3073 params->Op0 = 3;
3074 params->Op1 = 0;
3075 params->CRn = 0;
3076 params->CRm = 3;
3077
3078 /* CP10 ID registers are read-only */
3079 valid = !params->is_write;
3080
3081 switch (reg_id) {
3082 /* MVFR0 */
3083 case 0b0111:
3084 params->Op2 = 0;
3085 break;
3086 /* MVFR1 */
3087 case 0b0110:
3088 params->Op2 = 1;
3089 break;
3090 /* MVFR2 */
3091 case 0b0101:
3092 params->Op2 = 2;
3093 break;
3094 default:
3095 valid = false;
3096 }
3097
3098 if (valid)
3099 return true;
3100
3101 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n",
3102 params->is_write ? "write" : "read", reg_id);
3103 return false;
3104}
3105
3106/**
3107 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and
3108 * VFP Register' from AArch32.
3109 * @vcpu: The vCPU pointer
3110 *
3111 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers.
3112 * Work out the correct AArch64 system register encoding and reroute to the
3113 * AArch64 system register emulation.
3114 */
3115int kvm_handle_cp10_id(struct kvm_vcpu *vcpu)
3116{
3117 int Rt = kvm_vcpu_sys_get_rt(vcpu);
ee87a9bd 3118 u64 esr = kvm_vcpu_get_esr(vcpu);
9369bc5c
OU		 3119 struct sys_reg_params params;
3120
3121 /* UNDEF on any unhandled register access */
3122 if (!kvm_esr_cp10_id_to_sys64(esr, &params)) {
3123 kvm_inject_undefined(vcpu);
3124 return 1;
3125 }
3126
3127 if (emulate_sys_reg(vcpu, &params))
3128 vcpu_set_reg(vcpu, Rt, params.regval);
3129
3130 return 1;
3131}
3132
e6519766
OU		 3133/**
3134 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where
3135 * CRn=0, which corresponds to the AArch32 feature
3136 * registers.
3137 * @vcpu: the vCPU pointer
3138 * @params: the system register access parameters.
3139 *
3140 * Our cp15 system register tables do not enumerate the AArch32 feature
3141 * registers. Conveniently, our AArch64 table does, and the AArch32 system
3142 * register encoding can be trivially remapped into the AArch64 for the feature
3143 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same.
3144 *
3145 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit
3146 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this
3147 * range are either UNKNOWN or RES0. Rerouting remains architectural as we
3148 * treat undefined registers in this range as RAZ.
3149 */
3150static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu,
3151 struct sys_reg_params *params)
3152{
3153 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3154
3155 /* Treat impossible writes to RO registers as UNDEFINED */
3156 if (params->is_write) {
3157 unhandled_cp_access(vcpu, params);
3158 return 1;
3159 }
3160
3161 params->Op0 = 3;
3162
3163 /*
3164 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32.
3165 * Avoid conflicting with future expansion of AArch64 feature registers
3166 * and simply treat them as RAZ here.
3167 */
3168 if (params->CRm > 3)
3169 params->regval = 0;
3170 else if (!emulate_sys_reg(vcpu, params))
3171 return 1;
3172
3173 vcpu_set_reg(vcpu, Rt, params->regval);
3174 return 1;
3175}
3176
62a89c44 3177/**
7769db90 3178 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
62a89c44
MZ		 3179 * @vcpu: The VCPU pointer
3180 * @run: The kvm_run struct
3181 */
72564016 3182static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
e6519766 3183 struct sys_reg_params *params,
72564016 3184 const struct sys_reg_desc *global,
dcaffa7b 3185 size_t nr_global)
62a89c44 3186{
c667186f 3187 int Rt = kvm_vcpu_sys_get_rt(vcpu);
62a89c44 3188
e6519766 3189 params->regval = vcpu_get_reg(vcpu, Rt);
62a89c44 3190
e6519766
OU		 3191 if (emulate_cp(vcpu, params, global, nr_global)) {
3192 if (!params->is_write)
3193 vcpu_set_reg(vcpu, Rt, params->regval);
72564016 3194 return 1;
2ec5be3d 3195 }
72564016 3196
e6519766 3197 unhandled_cp_access(vcpu, params);
62a89c44
MZ		 3198 return 1;
3199}
3200
74cc7e0c 3201int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
72564016 3202{
dcaffa7b 3203 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
72564016
MZ		 3204}
3205
74cc7e0c 3206int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
72564016 3207{
e6519766
OU		 3208 struct sys_reg_params params;
3209
3210 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
3211
3212 /*
3213 * Certain AArch32 ID registers are handled by rerouting to the AArch64
3214 * system register table. Registers in the ID range where CRm=0 are
3215 * excluded from this scheme as they do not trivially map into AArch64
3216 * system register encodings.
3217 */
3218 if (params.Op1 == 0 && params.CRn == 0 && params.CRm)
3219 return kvm_emulate_cp15_id_reg(vcpu, &params);
3220
3221 return kvm_handle_cp_32(vcpu, &params, cp15_regs, ARRAY_SIZE(cp15_regs));
72564016
MZ		 3222}
3223
74cc7e0c 3224int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
72564016 3225{
dcaffa7b 3226 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
72564016
MZ		 3227}
3228
74cc7e0c 3229int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
72564016 3230{
e6519766
OU		 3231 struct sys_reg_params params;
3232
3233 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
3234
3235 return kvm_handle_cp_32(vcpu, &params, cp14_regs, ARRAY_SIZE(cp14_regs));
72564016
MZ		 3236}
3237
54ad68b7
MR		 3238static bool is_imp_def_sys_reg(struct sys_reg_params *params)
3239{
3240 // See ARM DDI 0487E.a, section D12.3.2
3241 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
3242}
3243
28eda7b5
OU		 3244/**
3245 * emulate_sys_reg - Emulate a guest access to an AArch64 system register
3246 * @vcpu: The VCPU pointer
3247 * @params: Decoded system register parameters
3248 *
3249 * Return: true if the system register access was successful, false otherwise.
3250 */
3251static bool emulate_sys_reg(struct kvm_vcpu *vcpu,
3fec037d 3252 struct sys_reg_params *params)
7c8c5e6a 3253{
dcaffa7b 3254 const struct sys_reg_desc *r;
7c8c5e6a 3255
dcaffa7b 3256 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
7c8c5e6a
MZ		 3257
3258 if (likely(r)) {
e70b9522 3259 perform_access(vcpu, params, r);
28eda7b5
OU		 3260 return true;
3261 }
3262
3263 if (is_imp_def_sys_reg(params)) {
54ad68b7 3264 kvm_inject_undefined(vcpu);
7c8c5e6a 3265 } else {
bf4b96bb
MR		 3266 print_sys_reg_msg(params,
3267 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
3268 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
e70b9522 3269 kvm_inject_undefined(vcpu);
7c8c5e6a 3270 }
28eda7b5 3271 return false;
7c8c5e6a
MZ		 3272}
3273
47334146
JZ		 3274static void kvm_reset_id_regs(struct kvm_vcpu *vcpu)
3275{
3276 const struct sys_reg_desc *idreg = first_idreg;
3277 u32 id = reg_to_encoding(idreg);
3278 struct kvm *kvm = vcpu->kvm;
3279
3280 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags))
3281 return;
3282
3283 lockdep_assert_held(&kvm->arch.config_lock);
3284
3285 /* Initialize all idregs */
3286 while (is_id_reg(id)) {
3287 IDREG(kvm, id) = idreg->reset(vcpu, idreg);
3288
3289 idreg++;
3290 id = reg_to_encoding(idreg);
3291 }
3292
3293 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags);
3294}
3295
750ed566
JM		 3296/**
3297 * kvm_reset_sys_regs - sets system registers to reset value
3298 * @vcpu: The VCPU pointer
3299 *
3300 * This function finds the right table above and sets the registers on the
3301 * virtual CPU struct to their architecturally defined reset values.
3302 */
3303void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
7c8c5e6a
MZ		 3304{
3305 unsigned long i;
3306
47334146
JZ		 3307 kvm_reset_id_regs(vcpu);
3308
3309 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
3310 const struct sys_reg_desc *r = &sys_reg_descs[i];
3311
3312 if (is_id_reg(reg_to_encoding(r)))
3313 continue;
3314
3315 if (r->reset)
3316 r->reset(vcpu, r);
3317 }
7c8c5e6a
MZ		 3318}
3319
3320/**
3321 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
3322 * @vcpu: The VCPU pointer
7c8c5e6a 3323 */
74cc7e0c 3324int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
7c8c5e6a
MZ		 3325{
3326 struct sys_reg_params params;
3a949f4c 3327 unsigned long esr = kvm_vcpu_get_esr(vcpu);
c667186f 3328 int Rt = kvm_vcpu_sys_get_rt(vcpu);
7c8c5e6a 3329
eef8c85a
AB		 3330 trace_kvm_handle_sys_reg(esr);
3331
e58ec47b
MZ		 3332 if (__check_nv_sr_forward(vcpu))
3333 return 1;
3334
f76f89e2 3335 params = esr_sys64_to_params(esr);
2ec5be3d 3336 params.regval = vcpu_get_reg(vcpu, Rt);
7c8c5e6a 3337
28eda7b5
OU		 3338 if (!emulate_sys_reg(vcpu, &params))
3339 return 1;
2ec5be3d
PF		 3340
3341 if (!params.is_write)
3342 vcpu_set_reg(vcpu, Rt, params.regval);
28eda7b5 3343 return 1;
7c8c5e6a
MZ		 3344}
3345
3346/******************************************************************************
3347 * Userspace API
3348 *****************************************************************************/
3349
3350static bool index_to_params(u64 id, struct sys_reg_params *params)
3351{
3352 switch (id & KVM_REG_SIZE_MASK) {
3353 case KVM_REG_SIZE_U64:
3354 /* Any unused index bits means it's not valid. */
3355 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
3356 | KVM_REG_ARM_COPROC_MASK
3357 | KVM_REG_ARM64_SYSREG_OP0_MASK
3358 | KVM_REG_ARM64_SYSREG_OP1_MASK
3359 | KVM_REG_ARM64_SYSREG_CRN_MASK
3360 | KVM_REG_ARM64_SYSREG_CRM_MASK
3361 | KVM_REG_ARM64_SYSREG_OP2_MASK))
3362 return false;
3363 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
3364 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
3365 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
3366 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
3367 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
3368 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
3369 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
3370 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
3371 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
3372 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
3373 return true;
3374 default:
3375 return false;
3376 }
3377}
3378
da8d120f
MZ		 3379const struct sys_reg_desc *get_reg_by_id(u64 id,
3380 const struct sys_reg_desc table[],
3381 unsigned int num)
4b927b94 3382{
da8d120f
MZ		 3383 struct sys_reg_params params;
3384
3385 if (!index_to_params(id, &params))
4b927b94
VK		 3386 return NULL;
3387
da8d120f 3388 return find_reg(&params, table, num);
4b927b94
VK		 3389}
3390
7c8c5e6a 3391/* Decode an index value, and find the sys_reg_desc entry. */
ba23aec9
MZ		 3392static const struct sys_reg_desc *
3393id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id,
3394 const struct sys_reg_desc table[], unsigned int num)
3395
7c8c5e6a 3396{
dcaffa7b 3397 const struct sys_reg_desc *r;
7c8c5e6a
MZ		 3398
3399 /* We only do sys_reg for now. */
3400 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
3401 return NULL;
3402
ba23aec9 3403 r = get_reg_by_id(id, table, num);
7c8c5e6a 3404
93390c0a 3405 /* Not saved in the sys_reg array and not otherwise accessible? */
ba23aec9 3406 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r)))
7c8c5e6a
MZ		 3407 r = NULL;
3408
3409 return r;
3410}
3411
3412/*
3413 * These are the invariant sys_reg registers: we let the guest see the
3414 * host versions of these, so they're part of the guest state.
3415 *
3416 * A future CPU may provide a mechanism to present different values to
3417 * the guest, or a future kvm may trap them.
3418 */
3419
3420#define FUNCTION_INVARIANT(reg) \
d86cde6e 3421 static u64 get_##reg(struct kvm_vcpu *v, \
7c8c5e6a
MZ		 3422 const struct sys_reg_desc *r) \
3423 { \
1f3d8699 3424 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
d86cde6e 3425 return ((struct sys_reg_desc *)r)->val; \
7c8c5e6a
MZ		 3426 }
3427
3428FUNCTION_INVARIANT(midr_el1)
7c8c5e6a 3429FUNCTION_INVARIANT(revidr_el1)
7c8c5e6a
MZ		 3430FUNCTION_INVARIANT(aidr_el1)
3431
d86cde6e 3432static u64 get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
f7f2b15c
AB		 3433{
3434 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
d86cde6e 3435 return ((struct sys_reg_desc *)r)->val;
f7f2b15c
AB		 3436}
3437
7c8c5e6a 3438/* ->val is filled in by kvm_sys_reg_table_init() */
8d20bd63 3439static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = {
0d449541
MR		 3440 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
3441 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
0d449541
MR		 3442 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
3443 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
7c8c5e6a
MZ		 3444};
3445
5a420ed9 3446static int get_invariant_sys_reg(u64 id, u64 __user *uaddr)
7c8c5e6a 3447{
7c8c5e6a
MZ		 3448 const struct sys_reg_desc *r;
3449
da8d120f
MZ		 3450 r = get_reg_by_id(id, invariant_sys_regs,
3451 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 3452 if (!r)
3453 return -ENOENT;
3454
5a420ed9 3455 return put_user(r->val, uaddr);
7c8c5e6a
MZ		 3456}
3457
5a420ed9 3458static int set_invariant_sys_reg(u64 id, u64 __user *uaddr)
7c8c5e6a 3459{
7c8c5e6a 3460 const struct sys_reg_desc *r;
5a420ed9 3461 u64 val;
7c8c5e6a 3462
da8d120f
MZ		 3463 r = get_reg_by_id(id, invariant_sys_regs,
3464 ARRAY_SIZE(invariant_sys_regs));
7c8c5e6a
MZ		 3465 if (!r)
3466 return -ENOENT;
3467
5a420ed9
MZ		 3468 if (get_user(val, uaddr))
3469 return -EFAULT;
7c8c5e6a
MZ		 3470
3471 /* This is what we mean by invariant: you can't change it. */
3472 if (r->val != val)
3473 return -EINVAL;
3474
3475 return 0;
3476}
3477
7af0c253 3478static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
7c8c5e6a
MZ		 3479{
3480 u32 val;
3481 u32 __user *uval = uaddr;
3482
3483 /* Fail if we have unknown bits set. */
3484 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
3485 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
3486 return -ENOENT;
3487
3488 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
3489 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
3490 if (KVM_REG_SIZE(id) != 4)
3491 return -ENOENT;
3492 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
3493 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
7af0c253 3494 if (val >= CSSELR_MAX)
7c8c5e6a
MZ		 3495 return -ENOENT;
3496
7af0c253 3497 return put_user(get_ccsidr(vcpu, val), uval);
7c8c5e6a
MZ		 3498 default:
3499 return -ENOENT;
3500 }
3501}
3502
7af0c253 3503static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
7c8c5e6a
MZ		 3504{
3505 u32 val, newval;
3506 u32 __user *uval = uaddr;
3507
3508 /* Fail if we have unknown bits set. */
3509 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
3510 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
3511 return -ENOENT;
3512
3513 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
3514 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
3515 if (KVM_REG_SIZE(id) != 4)
3516 return -ENOENT;
3517 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
3518 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
7af0c253 3519 if (val >= CSSELR_MAX)
7c8c5e6a
MZ		 3520 return -ENOENT;
3521
3522 if (get_user(newval, uval))
3523 return -EFAULT;
3524
7af0c253 3525 return set_ccsidr(vcpu, val, newval);
7c8c5e6a
MZ		 3526 default:
3527 return -ENOENT;
3528 }
3529}
3530
ba23aec9
MZ		 3531int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
3532 const struct sys_reg_desc table[], unsigned int num)
7c8c5e6a 3533{
978ceeb3 3534 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
7c8c5e6a 3535 const struct sys_reg_desc *r;
978ceeb3
MZ		 3536 u64 val;
3537 int ret;
ba23aec9
MZ		 3538
3539 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
e6b367db 3540 if (!r || sysreg_hidden_user(vcpu, r))
ba23aec9
MZ		 3541 return -ENOENT;
3542
978ceeb3
MZ		 3543 if (r->get_user) {
3544 ret = (r->get_user)(vcpu, r, &val);
3545 } else {
3546 val = __vcpu_sys_reg(vcpu, r->reg);
3547 ret = 0;
3548 }
3549
3550 if (!ret)
3551 ret = put_user(val, uaddr);
ba23aec9 3552
978ceeb3 3553 return ret;
ba23aec9
MZ		 3554}
3555
3556int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
3557{
7c8c5e6a 3558 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1deeffb5 3559 int err;
7c8c5e6a
MZ		 3560
3561 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
7af0c253 3562 return demux_c15_get(vcpu, reg->id, uaddr);
7c8c5e6a 3563
1deeffb5
MZ		 3564 err = get_invariant_sys_reg(reg->id, uaddr);
3565 if (err != -ENOENT)
3566 return err;
7c8c5e6a 3567
ba23aec9
MZ		 3568 return kvm_sys_reg_get_user(vcpu, reg,
3569 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
3570}
7c8c5e6a 3571
ba23aec9
MZ		 3572int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
3573 const struct sys_reg_desc table[], unsigned int num)
3574{
978ceeb3 3575 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
ba23aec9 3576 const struct sys_reg_desc *r;
978ceeb3
MZ		 3577 u64 val;
3578 int ret;
3579
3580 if (get_user(val, uaddr))
3581 return -EFAULT;
ba23aec9
MZ		 3582
3583 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
e6b367db 3584 if (!r || sysreg_hidden_user(vcpu, r))
7f34e409
DM		 3585 return -ENOENT;
3586
4de06e4c
OU		 3587 if (sysreg_user_write_ignore(vcpu, r))
3588 return 0;
3589
978ceeb3
MZ		 3590 if (r->set_user) {
3591 ret = (r->set_user)(vcpu, r, val);
3592 } else {
3593 __vcpu_sys_reg(vcpu, r->reg) = val;
3594 ret = 0;
3595 }
84e690bf 3596
978ceeb3 3597 return ret;
7c8c5e6a
MZ		 3598}
3599
3600int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
3601{
7c8c5e6a 3602 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1deeffb5 3603 int err;
7c8c5e6a
MZ		 3604
3605 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
7af0c253 3606 return demux_c15_set(vcpu, reg->id, uaddr);
7c8c5e6a 3607
1deeffb5
MZ		 3608 err = set_invariant_sys_reg(reg->id, uaddr);
3609 if (err != -ENOENT)
3610 return err;
84e690bf 3611
ba23aec9
MZ		 3612 return kvm_sys_reg_set_user(vcpu, reg,
3613 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
7c8c5e6a
MZ		 3614}
3615
3616static unsigned int num_demux_regs(void)
3617{
7af0c253 3618 return CSSELR_MAX;
7c8c5e6a
MZ		 3619}
3620
3621static int write_demux_regids(u64 __user *uindices)
3622{
efd48cea 3623 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
7c8c5e6a
MZ		 3624 unsigned int i;
3625
3626 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
3627 for (i = 0; i < CSSELR_MAX; i++) {
7c8c5e6a
MZ		 3628 if (put_user(val | i, uindices))
3629 return -EFAULT;
3630 uindices++;
3631 }
3632 return 0;
3633}
3634
3635static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
3636{
3637 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
3638 KVM_REG_ARM64_SYSREG |
3639 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
3640 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
3641 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
3642 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
3643 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
3644}
3645
3646static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
3647{
3648 if (!*uind)
3649 return true;
3650
3651 if (put_user(sys_reg_to_index(reg), *uind))
3652 return false;
3653
3654 (*uind)++;
3655 return true;
3656}
3657
7f34e409
DM		 3658static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
3659 const struct sys_reg_desc *rd,
93390c0a
DM		 3660 u64 __user **uind,
3661 unsigned int *total)
3662{
3663 /*
3664 * Ignore registers we trap but don't save,
3665 * and for which no custom user accessor is provided.
3666 */
3667 if (!(rd->reg || rd->get_user))
3668 return 0;
3669
e6b367db 3670 if (sysreg_hidden_user(vcpu, rd))
7f34e409
DM		 3671 return 0;
3672
93390c0a
DM		 3673 if (!copy_reg_to_user(rd, uind))
3674 return -EFAULT;
3675
3676 (*total)++;
3677 return 0;
3678}
3679
7c8c5e6a
MZ		 3680/* Assumed ordered tables, see kvm_sys_reg_table_init. */
3681static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
3682{
dcaffa7b 3683 const struct sys_reg_desc *i2, *end2;
7c8c5e6a 3684 unsigned int total = 0;
93390c0a 3685 int err;
7c8c5e6a 3686
7c8c5e6a
MZ		 3687 i2 = sys_reg_descs;
3688 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
3689
dcaffa7b
JM		 3690 while (i2 != end2) {
3691 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
93390c0a
DM		 3692 if (err)
3693 return err;
7c8c5e6a
MZ		 3694 }
3695 return total;
3696}
3697
3698unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
3699{
3700 return ARRAY_SIZE(invariant_sys_regs)
3701 + num_demux_regs()
3702 + walk_sys_regs(vcpu, (u64 __user *)NULL);
3703}
3704
3705int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
3706{
3707 unsigned int i;
3708 int err;
3709
3710 /* Then give them all the invariant registers' indices. */
3711 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
3712 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
3713 return -EFAULT;
3714 uindices++;
3715 }
3716
3717 err = walk_sys_regs(vcpu, uindices);
3718 if (err < 0)
3719 return err;
3720 uindices += err;
3721
3722 return write_demux_regids(uindices);
3723}
3724
3f9cd0ca
JZ		 3725#define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \
3726 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \
3727 sys_reg_Op1(r), \
3728 sys_reg_CRn(r), \
3729 sys_reg_CRm(r), \
3730 sys_reg_Op2(r))
3731
3732static bool is_feature_id_reg(u32 encoding)
3733{
3734 return (sys_reg_Op0(encoding) == 3 &&
3735 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) &&
3736 sys_reg_CRn(encoding) == 0 &&
3737 sys_reg_CRm(encoding) <= 7);
3738}
3739
3740int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range)
3741{
3742 const void *zero_page = page_to_virt(ZERO_PAGE(0));
3743 u64 __user *masks = (u64 __user *)range->addr;
3744
3745 /* Only feature id range is supported, reserved[13] must be zero. */
3746 if (range->range ||
3747 memcmp(range->reserved, zero_page, sizeof(range->reserved)))
3748 return -EINVAL;
3749
3750 /* Wipe the whole thing first */
3751 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64)))
3752 return -EFAULT;
3753
3754 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
3755 const struct sys_reg_desc *reg = &sys_reg_descs[i];
3756 u32 encoding = reg_to_encoding(reg);
3757 u64 val;
3758
3759 if (!is_feature_id_reg(encoding) || !reg->set_user)
3760 continue;
3761
3762 /*
3763 * For ID registers, we return the writable mask. Other feature
3764 * registers return a full 64bit mask. That's not necessary
3765 * compliant with a given revision of the architecture, but the
3766 * RES0/RES1 definitions allow us to do that.
3767 */
3768 if (is_id_reg(encoding)) {
3769 if (!reg->val ||
3770 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0()))
3771 continue;
3772 val = reg->val;
3773 } else {
3774 val = ~0UL;
3775 }
3776
3777 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding))))
3778 return -EFAULT;
3779 }
3780
3781 return 0;
3782}
3783
8d20bd63 3784int __init kvm_sys_reg_table_init(void)
7c8c5e6a 3785{
47334146 3786 struct sys_reg_params params;
f1f0c0cf 3787 bool valid = true;
7c8c5e6a 3788 unsigned int i;
7c8c5e6a
MZ		 3789
3790 /* Make sure tables are unique and in order. */
f1f0c0cf
AE		 3791 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false);
3792 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true);
3793 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true);
3794 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true);
3795 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true);
3796 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false);
3797
3798 if (!valid)
3799 return -EINVAL;
7c8c5e6a
MZ		 3800
3801 /* We abuse the reset function to overwrite the table itself. */
3802 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
3803 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
3804
47334146
JZ		 3805 /* Find the first idreg (SYS_ID_PFR0_EL1) in sys_reg_descs. */
3806 params = encoding_to_params(SYS_ID_PFR0_EL1);
3807 first_idreg = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
3808 if (!first_idreg)
3809 return -EINVAL;
3810
e58ec47b
MZ		 3811 if (kvm_get_mode() == KVM_MODE_NV)
3812 return populate_nv_trap_config();
3813
f1f0c0cf 3814 return 0;
7c8c5e6a 3815}
Linux 6.x block layer and io_uring tree(s)