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7c8c5e6a MZ |
1 | /* |
2 | * Copyright (C) 2012,2013 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * Derived from arch/arm/kvm/coproc.c: | |
6 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
7 | * Authors: Rusty Russell <rusty@rustcorp.com.au> | |
8 | * Christoffer Dall <c.dall@virtualopensystems.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License, version 2, as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
24 | #include <linux/kvm_host.h> | |
25 | #include <linux/uaccess.h> | |
26 | #include <asm/kvm_arm.h> | |
27 | #include <asm/kvm_host.h> | |
28 | #include <asm/kvm_emulate.h> | |
29 | #include <asm/kvm_coproc.h> | |
9d218a1f | 30 | #include <asm/kvm_mmu.h> |
7c8c5e6a MZ |
31 | #include <asm/cacheflush.h> |
32 | #include <asm/cputype.h> | |
33 | #include <trace/events/kvm.h> | |
34 | ||
35 | #include "sys_regs.h" | |
36 | ||
37 | /* | |
38 | * All of this file is extremly similar to the ARM coproc.c, but the | |
39 | * types are different. My gut feeling is that it should be pretty | |
40 | * easy to merge, but that would be an ABI breakage -- again. VFP | |
41 | * would also need to be abstracted. | |
62a89c44 MZ |
42 | * |
43 | * For AArch32, we only take care of what is being trapped. Anything | |
44 | * that has to do with init and userspace access has to go via the | |
45 | * 64bit interface. | |
7c8c5e6a MZ |
46 | */ |
47 | ||
48 | /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ | |
49 | static u32 cache_levels; | |
50 | ||
51 | /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ | |
52 | #define CSSELR_MAX 12 | |
53 | ||
54 | /* Which cache CCSIDR represents depends on CSSELR value. */ | |
55 | static u32 get_ccsidr(u32 csselr) | |
56 | { | |
57 | u32 ccsidr; | |
58 | ||
59 | /* Make sure noone else changes CSSELR during this! */ | |
60 | local_irq_disable(); | |
61 | /* Put value into CSSELR */ | |
62 | asm volatile("msr csselr_el1, %x0" : : "r" (csselr)); | |
63 | isb(); | |
64 | /* Read result out of CCSIDR */ | |
65 | asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr)); | |
66 | local_irq_enable(); | |
67 | ||
68 | return ccsidr; | |
69 | } | |
70 | ||
71 | static void do_dc_cisw(u32 val) | |
72 | { | |
73 | asm volatile("dc cisw, %x0" : : "r" (val)); | |
98f7685e | 74 | dsb(ish); |
7c8c5e6a MZ |
75 | } |
76 | ||
77 | static void do_dc_csw(u32 val) | |
78 | { | |
79 | asm volatile("dc csw, %x0" : : "r" (val)); | |
98f7685e | 80 | dsb(ish); |
7c8c5e6a MZ |
81 | } |
82 | ||
83 | /* See note at ARM ARM B1.14.4 */ | |
84 | static bool access_dcsw(struct kvm_vcpu *vcpu, | |
85 | const struct sys_reg_params *p, | |
86 | const struct sys_reg_desc *r) | |
87 | { | |
88 | unsigned long val; | |
89 | int cpu; | |
90 | ||
91 | if (!p->is_write) | |
92 | return read_from_write_only(vcpu, p); | |
93 | ||
94 | cpu = get_cpu(); | |
95 | ||
96 | cpumask_setall(&vcpu->arch.require_dcache_flush); | |
97 | cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush); | |
98 | ||
99 | /* If we were already preempted, take the long way around */ | |
100 | if (cpu != vcpu->arch.last_pcpu) { | |
101 | flush_cache_all(); | |
102 | goto done; | |
103 | } | |
104 | ||
105 | val = *vcpu_reg(vcpu, p->Rt); | |
106 | ||
107 | switch (p->CRm) { | |
108 | case 6: /* Upgrade DCISW to DCCISW, as per HCR.SWIO */ | |
109 | case 14: /* DCCISW */ | |
110 | do_dc_cisw(val); | |
111 | break; | |
112 | ||
113 | case 10: /* DCCSW */ | |
114 | do_dc_csw(val); | |
115 | break; | |
116 | } | |
117 | ||
118 | done: | |
119 | put_cpu(); | |
120 | ||
121 | return true; | |
122 | } | |
123 | ||
4d44923b MZ |
124 | /* |
125 | * Generic accessor for VM registers. Only called as long as HCR_TVM | |
126 | * is set. | |
127 | */ | |
128 | static bool access_vm_reg(struct kvm_vcpu *vcpu, | |
129 | const struct sys_reg_params *p, | |
130 | const struct sys_reg_desc *r) | |
131 | { | |
132 | unsigned long val; | |
133 | ||
134 | BUG_ON(!p->is_write); | |
135 | ||
136 | val = *vcpu_reg(vcpu, p->Rt); | |
137 | if (!p->is_aarch32) { | |
138 | vcpu_sys_reg(vcpu, r->reg) = val; | |
139 | } else { | |
140 | vcpu_cp15(vcpu, r->reg) = val & 0xffffffffUL; | |
141 | if (!p->is_32bit) | |
142 | vcpu_cp15(vcpu, r->reg + 1) = val >> 32; | |
143 | } | |
144 | return true; | |
145 | } | |
146 | ||
147 | /* | |
148 | * SCTLR_EL1 accessor. Only called as long as HCR_TVM is set. If the | |
149 | * guest enables the MMU, we stop trapping the VM sys_regs and leave | |
150 | * it in complete control of the caches. | |
151 | */ | |
152 | static bool access_sctlr(struct kvm_vcpu *vcpu, | |
153 | const struct sys_reg_params *p, | |
154 | const struct sys_reg_desc *r) | |
155 | { | |
156 | access_vm_reg(vcpu, p, r); | |
157 | ||
9d218a1f | 158 | if (vcpu_has_cache_enabled(vcpu)) { /* MMU+Caches enabled? */ |
4d44923b | 159 | vcpu->arch.hcr_el2 &= ~HCR_TVM; |
9d218a1f MZ |
160 | stage2_flush_vm(vcpu->kvm); |
161 | } | |
4d44923b MZ |
162 | |
163 | return true; | |
164 | } | |
165 | ||
7c8c5e6a MZ |
166 | /* |
167 | * We could trap ID_DFR0 and tell the guest we don't support performance | |
168 | * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was | |
169 | * NAKed, so it will read the PMCR anyway. | |
170 | * | |
171 | * Therefore we tell the guest we have 0 counters. Unfortunately, we | |
172 | * must always support PMCCNTR (the cycle counter): we just RAZ/WI for | |
173 | * all PM registers, which doesn't crash the guest kernel at least. | |
174 | */ | |
175 | static bool pm_fake(struct kvm_vcpu *vcpu, | |
176 | const struct sys_reg_params *p, | |
177 | const struct sys_reg_desc *r) | |
178 | { | |
179 | if (p->is_write) | |
180 | return ignore_write(vcpu, p); | |
181 | else | |
182 | return read_zero(vcpu, p); | |
183 | } | |
184 | ||
185 | static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) | |
186 | { | |
187 | u64 amair; | |
188 | ||
189 | asm volatile("mrs %0, amair_el1\n" : "=r" (amair)); | |
190 | vcpu_sys_reg(vcpu, AMAIR_EL1) = amair; | |
191 | } | |
192 | ||
193 | static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) | |
194 | { | |
195 | /* | |
196 | * Simply map the vcpu_id into the Aff0 field of the MPIDR. | |
197 | */ | |
198 | vcpu_sys_reg(vcpu, MPIDR_EL1) = (1UL << 31) | (vcpu->vcpu_id & 0xff); | |
199 | } | |
200 | ||
201 | /* | |
202 | * Architected system registers. | |
203 | * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 | |
204 | */ | |
205 | static const struct sys_reg_desc sys_reg_descs[] = { | |
206 | /* DC ISW */ | |
207 | { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010), | |
208 | access_dcsw }, | |
209 | /* DC CSW */ | |
210 | { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010), | |
211 | access_dcsw }, | |
212 | /* DC CISW */ | |
213 | { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010), | |
214 | access_dcsw }, | |
215 | ||
62a89c44 MZ |
216 | /* TEECR32_EL1 */ |
217 | { Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000), | |
218 | NULL, reset_val, TEECR32_EL1, 0 }, | |
219 | /* TEEHBR32_EL1 */ | |
220 | { Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000), | |
221 | NULL, reset_val, TEEHBR32_EL1, 0 }, | |
222 | /* DBGVCR32_EL2 */ | |
223 | { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000), | |
224 | NULL, reset_val, DBGVCR32_EL2, 0 }, | |
225 | ||
7c8c5e6a MZ |
226 | /* MPIDR_EL1 */ |
227 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101), | |
228 | NULL, reset_mpidr, MPIDR_EL1 }, | |
229 | /* SCTLR_EL1 */ | |
230 | { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000), | |
4d44923b | 231 | access_sctlr, reset_val, SCTLR_EL1, 0x00C50078 }, |
7c8c5e6a MZ |
232 | /* CPACR_EL1 */ |
233 | { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010), | |
234 | NULL, reset_val, CPACR_EL1, 0 }, | |
235 | /* TTBR0_EL1 */ | |
236 | { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000), | |
4d44923b | 237 | access_vm_reg, reset_unknown, TTBR0_EL1 }, |
7c8c5e6a MZ |
238 | /* TTBR1_EL1 */ |
239 | { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001), | |
4d44923b | 240 | access_vm_reg, reset_unknown, TTBR1_EL1 }, |
7c8c5e6a MZ |
241 | /* TCR_EL1 */ |
242 | { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010), | |
4d44923b | 243 | access_vm_reg, reset_val, TCR_EL1, 0 }, |
7c8c5e6a MZ |
244 | |
245 | /* AFSR0_EL1 */ | |
246 | { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000), | |
4d44923b | 247 | access_vm_reg, reset_unknown, AFSR0_EL1 }, |
7c8c5e6a MZ |
248 | /* AFSR1_EL1 */ |
249 | { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001), | |
4d44923b | 250 | access_vm_reg, reset_unknown, AFSR1_EL1 }, |
7c8c5e6a MZ |
251 | /* ESR_EL1 */ |
252 | { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000), | |
4d44923b | 253 | access_vm_reg, reset_unknown, ESR_EL1 }, |
7c8c5e6a MZ |
254 | /* FAR_EL1 */ |
255 | { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000), | |
4d44923b | 256 | access_vm_reg, reset_unknown, FAR_EL1 }, |
1bbd8054 MZ |
257 | /* PAR_EL1 */ |
258 | { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000), | |
259 | NULL, reset_unknown, PAR_EL1 }, | |
7c8c5e6a MZ |
260 | |
261 | /* PMINTENSET_EL1 */ | |
262 | { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001), | |
263 | pm_fake }, | |
264 | /* PMINTENCLR_EL1 */ | |
265 | { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010), | |
266 | pm_fake }, | |
267 | ||
268 | /* MAIR_EL1 */ | |
269 | { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000), | |
4d44923b | 270 | access_vm_reg, reset_unknown, MAIR_EL1 }, |
7c8c5e6a MZ |
271 | /* AMAIR_EL1 */ |
272 | { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000), | |
4d44923b | 273 | access_vm_reg, reset_amair_el1, AMAIR_EL1 }, |
7c8c5e6a MZ |
274 | |
275 | /* VBAR_EL1 */ | |
276 | { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000), | |
277 | NULL, reset_val, VBAR_EL1, 0 }, | |
278 | /* CONTEXTIDR_EL1 */ | |
279 | { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001), | |
4d44923b | 280 | access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, |
7c8c5e6a MZ |
281 | /* TPIDR_EL1 */ |
282 | { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100), | |
283 | NULL, reset_unknown, TPIDR_EL1 }, | |
284 | ||
285 | /* CNTKCTL_EL1 */ | |
286 | { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000), | |
287 | NULL, reset_val, CNTKCTL_EL1, 0}, | |
288 | ||
289 | /* CSSELR_EL1 */ | |
290 | { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000), | |
291 | NULL, reset_unknown, CSSELR_EL1 }, | |
292 | ||
293 | /* PMCR_EL0 */ | |
294 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000), | |
295 | pm_fake }, | |
296 | /* PMCNTENSET_EL0 */ | |
297 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001), | |
298 | pm_fake }, | |
299 | /* PMCNTENCLR_EL0 */ | |
300 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010), | |
301 | pm_fake }, | |
302 | /* PMOVSCLR_EL0 */ | |
303 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011), | |
304 | pm_fake }, | |
305 | /* PMSWINC_EL0 */ | |
306 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100), | |
307 | pm_fake }, | |
308 | /* PMSELR_EL0 */ | |
309 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101), | |
310 | pm_fake }, | |
311 | /* PMCEID0_EL0 */ | |
312 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110), | |
313 | pm_fake }, | |
314 | /* PMCEID1_EL0 */ | |
315 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111), | |
316 | pm_fake }, | |
317 | /* PMCCNTR_EL0 */ | |
318 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000), | |
319 | pm_fake }, | |
320 | /* PMXEVTYPER_EL0 */ | |
321 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001), | |
322 | pm_fake }, | |
323 | /* PMXEVCNTR_EL0 */ | |
324 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010), | |
325 | pm_fake }, | |
326 | /* PMUSERENR_EL0 */ | |
327 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000), | |
328 | pm_fake }, | |
329 | /* PMOVSSET_EL0 */ | |
330 | { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011), | |
331 | pm_fake }, | |
332 | ||
333 | /* TPIDR_EL0 */ | |
334 | { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010), | |
335 | NULL, reset_unknown, TPIDR_EL0 }, | |
336 | /* TPIDRRO_EL0 */ | |
337 | { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011), | |
338 | NULL, reset_unknown, TPIDRRO_EL0 }, | |
62a89c44 MZ |
339 | |
340 | /* DACR32_EL2 */ | |
341 | { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000), | |
342 | NULL, reset_unknown, DACR32_EL2 }, | |
343 | /* IFSR32_EL2 */ | |
344 | { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001), | |
345 | NULL, reset_unknown, IFSR32_EL2 }, | |
346 | /* FPEXC32_EL2 */ | |
347 | { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000), | |
348 | NULL, reset_val, FPEXC32_EL2, 0x70 }, | |
349 | }; | |
350 | ||
4d44923b MZ |
351 | /* |
352 | * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, | |
353 | * depending on the way they are accessed (as a 32bit or a 64bit | |
354 | * register). | |
355 | */ | |
62a89c44 | 356 | static const struct sys_reg_desc cp15_regs[] = { |
4d44923b MZ |
357 | { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, |
358 | { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_sctlr, NULL, c1_SCTLR }, | |
359 | { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, | |
360 | { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 }, | |
361 | { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR }, | |
362 | { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR }, | |
363 | { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR }, | |
364 | { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR }, | |
365 | { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR }, | |
366 | { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR }, | |
367 | { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR }, | |
368 | { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR }, | |
369 | ||
62a89c44 MZ |
370 | /* |
371 | * DC{C,I,CI}SW operations: | |
372 | */ | |
373 | { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, | |
374 | { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, | |
375 | { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, | |
4d44923b | 376 | |
62a89c44 MZ |
377 | { Op1( 0), CRn( 9), CRm(12), Op2( 0), pm_fake }, |
378 | { Op1( 0), CRn( 9), CRm(12), Op2( 1), pm_fake }, | |
379 | { Op1( 0), CRn( 9), CRm(12), Op2( 2), pm_fake }, | |
380 | { Op1( 0), CRn( 9), CRm(12), Op2( 3), pm_fake }, | |
381 | { Op1( 0), CRn( 9), CRm(12), Op2( 5), pm_fake }, | |
382 | { Op1( 0), CRn( 9), CRm(12), Op2( 6), pm_fake }, | |
383 | { Op1( 0), CRn( 9), CRm(12), Op2( 7), pm_fake }, | |
384 | { Op1( 0), CRn( 9), CRm(13), Op2( 0), pm_fake }, | |
385 | { Op1( 0), CRn( 9), CRm(13), Op2( 1), pm_fake }, | |
386 | { Op1( 0), CRn( 9), CRm(13), Op2( 2), pm_fake }, | |
387 | { Op1( 0), CRn( 9), CRm(14), Op2( 0), pm_fake }, | |
388 | { Op1( 0), CRn( 9), CRm(14), Op2( 1), pm_fake }, | |
389 | { Op1( 0), CRn( 9), CRm(14), Op2( 2), pm_fake }, | |
4d44923b MZ |
390 | |
391 | { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR }, | |
392 | { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR }, | |
393 | { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 }, | |
394 | { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 }, | |
395 | { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID }, | |
396 | ||
397 | { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 }, | |
7c8c5e6a MZ |
398 | }; |
399 | ||
400 | /* Target specific emulation tables */ | |
401 | static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS]; | |
402 | ||
403 | void kvm_register_target_sys_reg_table(unsigned int target, | |
404 | struct kvm_sys_reg_target_table *table) | |
405 | { | |
406 | target_tables[target] = table; | |
407 | } | |
408 | ||
409 | /* Get specific register table for this target. */ | |
62a89c44 MZ |
410 | static const struct sys_reg_desc *get_target_table(unsigned target, |
411 | bool mode_is_64, | |
412 | size_t *num) | |
7c8c5e6a MZ |
413 | { |
414 | struct kvm_sys_reg_target_table *table; | |
415 | ||
416 | table = target_tables[target]; | |
62a89c44 MZ |
417 | if (mode_is_64) { |
418 | *num = table->table64.num; | |
419 | return table->table64.table; | |
420 | } else { | |
421 | *num = table->table32.num; | |
422 | return table->table32.table; | |
423 | } | |
7c8c5e6a MZ |
424 | } |
425 | ||
426 | static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params, | |
427 | const struct sys_reg_desc table[], | |
428 | unsigned int num) | |
429 | { | |
430 | unsigned int i; | |
431 | ||
432 | for (i = 0; i < num; i++) { | |
433 | const struct sys_reg_desc *r = &table[i]; | |
434 | ||
435 | if (params->Op0 != r->Op0) | |
436 | continue; | |
437 | if (params->Op1 != r->Op1) | |
438 | continue; | |
439 | if (params->CRn != r->CRn) | |
440 | continue; | |
441 | if (params->CRm != r->CRm) | |
442 | continue; | |
443 | if (params->Op2 != r->Op2) | |
444 | continue; | |
445 | ||
446 | return r; | |
447 | } | |
448 | return NULL; | |
449 | } | |
450 | ||
62a89c44 MZ |
451 | int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run) |
452 | { | |
453 | kvm_inject_undefined(vcpu); | |
454 | return 1; | |
455 | } | |
456 | ||
457 | int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run) | |
458 | { | |
459 | kvm_inject_undefined(vcpu); | |
460 | return 1; | |
461 | } | |
462 | ||
463 | static void emulate_cp15(struct kvm_vcpu *vcpu, | |
464 | const struct sys_reg_params *params) | |
465 | { | |
466 | size_t num; | |
467 | const struct sys_reg_desc *table, *r; | |
468 | ||
469 | table = get_target_table(vcpu->arch.target, false, &num); | |
470 | ||
471 | /* Search target-specific then generic table. */ | |
472 | r = find_reg(params, table, num); | |
473 | if (!r) | |
474 | r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs)); | |
475 | ||
476 | if (likely(r)) { | |
477 | /* | |
478 | * Not having an accessor means that we have | |
479 | * configured a trap that we don't know how to | |
480 | * handle. This certainly qualifies as a gross bug | |
481 | * that should be fixed right away. | |
482 | */ | |
483 | BUG_ON(!r->access); | |
484 | ||
485 | if (likely(r->access(vcpu, params, r))) { | |
486 | /* Skip instruction, since it was emulated */ | |
487 | kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); | |
488 | return; | |
489 | } | |
490 | /* If access function fails, it should complain. */ | |
491 | } | |
492 | ||
493 | kvm_err("Unsupported guest CP15 access at: %08lx\n", *vcpu_pc(vcpu)); | |
494 | print_sys_reg_instr(params); | |
495 | kvm_inject_undefined(vcpu); | |
496 | } | |
497 | ||
498 | /** | |
499 | * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access | |
500 | * @vcpu: The VCPU pointer | |
501 | * @run: The kvm_run struct | |
502 | */ | |
503 | int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run) | |
504 | { | |
505 | struct sys_reg_params params; | |
506 | u32 hsr = kvm_vcpu_get_hsr(vcpu); | |
507 | int Rt2 = (hsr >> 10) & 0xf; | |
508 | ||
2072d29c MZ |
509 | params.is_aarch32 = true; |
510 | params.is_32bit = false; | |
62a89c44 MZ |
511 | params.CRm = (hsr >> 1) & 0xf; |
512 | params.Rt = (hsr >> 5) & 0xf; | |
513 | params.is_write = ((hsr & 1) == 0); | |
514 | ||
515 | params.Op0 = 0; | |
516 | params.Op1 = (hsr >> 16) & 0xf; | |
517 | params.Op2 = 0; | |
518 | params.CRn = 0; | |
519 | ||
520 | /* | |
521 | * Massive hack here. Store Rt2 in the top 32bits so we only | |
522 | * have one register to deal with. As we use the same trap | |
523 | * backends between AArch32 and AArch64, we get away with it. | |
524 | */ | |
525 | if (params.is_write) { | |
526 | u64 val = *vcpu_reg(vcpu, params.Rt); | |
527 | val &= 0xffffffff; | |
528 | val |= *vcpu_reg(vcpu, Rt2) << 32; | |
529 | *vcpu_reg(vcpu, params.Rt) = val; | |
530 | } | |
531 | ||
532 | emulate_cp15(vcpu, ¶ms); | |
533 | ||
534 | /* Do the opposite hack for the read side */ | |
535 | if (!params.is_write) { | |
536 | u64 val = *vcpu_reg(vcpu, params.Rt); | |
537 | val >>= 32; | |
538 | *vcpu_reg(vcpu, Rt2) = val; | |
539 | } | |
540 | ||
541 | return 1; | |
542 | } | |
543 | ||
544 | /** | |
545 | * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access | |
546 | * @vcpu: The VCPU pointer | |
547 | * @run: The kvm_run struct | |
548 | */ | |
549 | int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run) | |
550 | { | |
551 | struct sys_reg_params params; | |
552 | u32 hsr = kvm_vcpu_get_hsr(vcpu); | |
553 | ||
2072d29c MZ |
554 | params.is_aarch32 = true; |
555 | params.is_32bit = true; | |
62a89c44 MZ |
556 | params.CRm = (hsr >> 1) & 0xf; |
557 | params.Rt = (hsr >> 5) & 0xf; | |
558 | params.is_write = ((hsr & 1) == 0); | |
559 | params.CRn = (hsr >> 10) & 0xf; | |
560 | params.Op0 = 0; | |
561 | params.Op1 = (hsr >> 14) & 0x7; | |
562 | params.Op2 = (hsr >> 17) & 0x7; | |
563 | ||
564 | emulate_cp15(vcpu, ¶ms); | |
565 | return 1; | |
566 | } | |
567 | ||
7c8c5e6a MZ |
568 | static int emulate_sys_reg(struct kvm_vcpu *vcpu, |
569 | const struct sys_reg_params *params) | |
570 | { | |
571 | size_t num; | |
572 | const struct sys_reg_desc *table, *r; | |
573 | ||
62a89c44 | 574 | table = get_target_table(vcpu->arch.target, true, &num); |
7c8c5e6a MZ |
575 | |
576 | /* Search target-specific then generic table. */ | |
577 | r = find_reg(params, table, num); | |
578 | if (!r) | |
579 | r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); | |
580 | ||
581 | if (likely(r)) { | |
582 | /* | |
583 | * Not having an accessor means that we have | |
584 | * configured a trap that we don't know how to | |
585 | * handle. This certainly qualifies as a gross bug | |
586 | * that should be fixed right away. | |
587 | */ | |
588 | BUG_ON(!r->access); | |
589 | ||
590 | if (likely(r->access(vcpu, params, r))) { | |
591 | /* Skip instruction, since it was emulated */ | |
592 | kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); | |
593 | return 1; | |
594 | } | |
595 | /* If access function fails, it should complain. */ | |
596 | } else { | |
597 | kvm_err("Unsupported guest sys_reg access at: %lx\n", | |
598 | *vcpu_pc(vcpu)); | |
599 | print_sys_reg_instr(params); | |
600 | } | |
601 | kvm_inject_undefined(vcpu); | |
602 | return 1; | |
603 | } | |
604 | ||
605 | static void reset_sys_reg_descs(struct kvm_vcpu *vcpu, | |
606 | const struct sys_reg_desc *table, size_t num) | |
607 | { | |
608 | unsigned long i; | |
609 | ||
610 | for (i = 0; i < num; i++) | |
611 | if (table[i].reset) | |
612 | table[i].reset(vcpu, &table[i]); | |
613 | } | |
614 | ||
615 | /** | |
616 | * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access | |
617 | * @vcpu: The VCPU pointer | |
618 | * @run: The kvm_run struct | |
619 | */ | |
620 | int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run) | |
621 | { | |
622 | struct sys_reg_params params; | |
623 | unsigned long esr = kvm_vcpu_get_hsr(vcpu); | |
624 | ||
2072d29c MZ |
625 | params.is_aarch32 = false; |
626 | params.is_32bit = false; | |
7c8c5e6a MZ |
627 | params.Op0 = (esr >> 20) & 3; |
628 | params.Op1 = (esr >> 14) & 0x7; | |
629 | params.CRn = (esr >> 10) & 0xf; | |
630 | params.CRm = (esr >> 1) & 0xf; | |
631 | params.Op2 = (esr >> 17) & 0x7; | |
632 | params.Rt = (esr >> 5) & 0x1f; | |
633 | params.is_write = !(esr & 1); | |
634 | ||
635 | return emulate_sys_reg(vcpu, ¶ms); | |
636 | } | |
637 | ||
638 | /****************************************************************************** | |
639 | * Userspace API | |
640 | *****************************************************************************/ | |
641 | ||
642 | static bool index_to_params(u64 id, struct sys_reg_params *params) | |
643 | { | |
644 | switch (id & KVM_REG_SIZE_MASK) { | |
645 | case KVM_REG_SIZE_U64: | |
646 | /* Any unused index bits means it's not valid. */ | |
647 | if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | |
648 | | KVM_REG_ARM_COPROC_MASK | |
649 | | KVM_REG_ARM64_SYSREG_OP0_MASK | |
650 | | KVM_REG_ARM64_SYSREG_OP1_MASK | |
651 | | KVM_REG_ARM64_SYSREG_CRN_MASK | |
652 | | KVM_REG_ARM64_SYSREG_CRM_MASK | |
653 | | KVM_REG_ARM64_SYSREG_OP2_MASK)) | |
654 | return false; | |
655 | params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) | |
656 | >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); | |
657 | params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) | |
658 | >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); | |
659 | params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) | |
660 | >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); | |
661 | params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) | |
662 | >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); | |
663 | params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) | |
664 | >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); | |
665 | return true; | |
666 | default: | |
667 | return false; | |
668 | } | |
669 | } | |
670 | ||
671 | /* Decode an index value, and find the sys_reg_desc entry. */ | |
672 | static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, | |
673 | u64 id) | |
674 | { | |
675 | size_t num; | |
676 | const struct sys_reg_desc *table, *r; | |
677 | struct sys_reg_params params; | |
678 | ||
679 | /* We only do sys_reg for now. */ | |
680 | if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) | |
681 | return NULL; | |
682 | ||
683 | if (!index_to_params(id, ¶ms)) | |
684 | return NULL; | |
685 | ||
62a89c44 | 686 | table = get_target_table(vcpu->arch.target, true, &num); |
7c8c5e6a MZ |
687 | r = find_reg(¶ms, table, num); |
688 | if (!r) | |
689 | r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); | |
690 | ||
691 | /* Not saved in the sys_reg array? */ | |
692 | if (r && !r->reg) | |
693 | r = NULL; | |
694 | ||
695 | return r; | |
696 | } | |
697 | ||
698 | /* | |
699 | * These are the invariant sys_reg registers: we let the guest see the | |
700 | * host versions of these, so they're part of the guest state. | |
701 | * | |
702 | * A future CPU may provide a mechanism to present different values to | |
703 | * the guest, or a future kvm may trap them. | |
704 | */ | |
705 | ||
706 | #define FUNCTION_INVARIANT(reg) \ | |
707 | static void get_##reg(struct kvm_vcpu *v, \ | |
708 | const struct sys_reg_desc *r) \ | |
709 | { \ | |
710 | u64 val; \ | |
711 | \ | |
712 | asm volatile("mrs %0, " __stringify(reg) "\n" \ | |
713 | : "=r" (val)); \ | |
714 | ((struct sys_reg_desc *)r)->val = val; \ | |
715 | } | |
716 | ||
717 | FUNCTION_INVARIANT(midr_el1) | |
718 | FUNCTION_INVARIANT(ctr_el0) | |
719 | FUNCTION_INVARIANT(revidr_el1) | |
720 | FUNCTION_INVARIANT(id_pfr0_el1) | |
721 | FUNCTION_INVARIANT(id_pfr1_el1) | |
722 | FUNCTION_INVARIANT(id_dfr0_el1) | |
723 | FUNCTION_INVARIANT(id_afr0_el1) | |
724 | FUNCTION_INVARIANT(id_mmfr0_el1) | |
725 | FUNCTION_INVARIANT(id_mmfr1_el1) | |
726 | FUNCTION_INVARIANT(id_mmfr2_el1) | |
727 | FUNCTION_INVARIANT(id_mmfr3_el1) | |
728 | FUNCTION_INVARIANT(id_isar0_el1) | |
729 | FUNCTION_INVARIANT(id_isar1_el1) | |
730 | FUNCTION_INVARIANT(id_isar2_el1) | |
731 | FUNCTION_INVARIANT(id_isar3_el1) | |
732 | FUNCTION_INVARIANT(id_isar4_el1) | |
733 | FUNCTION_INVARIANT(id_isar5_el1) | |
734 | FUNCTION_INVARIANT(clidr_el1) | |
735 | FUNCTION_INVARIANT(aidr_el1) | |
736 | ||
737 | /* ->val is filled in by kvm_sys_reg_table_init() */ | |
738 | static struct sys_reg_desc invariant_sys_regs[] = { | |
739 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000), | |
740 | NULL, get_midr_el1 }, | |
741 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110), | |
742 | NULL, get_revidr_el1 }, | |
743 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000), | |
744 | NULL, get_id_pfr0_el1 }, | |
745 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001), | |
746 | NULL, get_id_pfr1_el1 }, | |
747 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010), | |
748 | NULL, get_id_dfr0_el1 }, | |
749 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011), | |
750 | NULL, get_id_afr0_el1 }, | |
751 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100), | |
752 | NULL, get_id_mmfr0_el1 }, | |
753 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101), | |
754 | NULL, get_id_mmfr1_el1 }, | |
755 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110), | |
756 | NULL, get_id_mmfr2_el1 }, | |
757 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111), | |
758 | NULL, get_id_mmfr3_el1 }, | |
759 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000), | |
760 | NULL, get_id_isar0_el1 }, | |
761 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001), | |
762 | NULL, get_id_isar1_el1 }, | |
763 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010), | |
764 | NULL, get_id_isar2_el1 }, | |
765 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011), | |
766 | NULL, get_id_isar3_el1 }, | |
767 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100), | |
768 | NULL, get_id_isar4_el1 }, | |
769 | { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101), | |
770 | NULL, get_id_isar5_el1 }, | |
771 | { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001), | |
772 | NULL, get_clidr_el1 }, | |
773 | { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111), | |
774 | NULL, get_aidr_el1 }, | |
775 | { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001), | |
776 | NULL, get_ctr_el0 }, | |
777 | }; | |
778 | ||
26c99af1 | 779 | static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) |
7c8c5e6a | 780 | { |
7c8c5e6a MZ |
781 | if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) |
782 | return -EFAULT; | |
783 | return 0; | |
784 | } | |
785 | ||
26c99af1 | 786 | static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) |
7c8c5e6a | 787 | { |
7c8c5e6a MZ |
788 | if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) |
789 | return -EFAULT; | |
790 | return 0; | |
791 | } | |
792 | ||
793 | static int get_invariant_sys_reg(u64 id, void __user *uaddr) | |
794 | { | |
795 | struct sys_reg_params params; | |
796 | const struct sys_reg_desc *r; | |
797 | ||
798 | if (!index_to_params(id, ¶ms)) | |
799 | return -ENOENT; | |
800 | ||
801 | r = find_reg(¶ms, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)); | |
802 | if (!r) | |
803 | return -ENOENT; | |
804 | ||
805 | return reg_to_user(uaddr, &r->val, id); | |
806 | } | |
807 | ||
808 | static int set_invariant_sys_reg(u64 id, void __user *uaddr) | |
809 | { | |
810 | struct sys_reg_params params; | |
811 | const struct sys_reg_desc *r; | |
812 | int err; | |
813 | u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ | |
814 | ||
815 | if (!index_to_params(id, ¶ms)) | |
816 | return -ENOENT; | |
817 | r = find_reg(¶ms, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)); | |
818 | if (!r) | |
819 | return -ENOENT; | |
820 | ||
821 | err = reg_from_user(&val, uaddr, id); | |
822 | if (err) | |
823 | return err; | |
824 | ||
825 | /* This is what we mean by invariant: you can't change it. */ | |
826 | if (r->val != val) | |
827 | return -EINVAL; | |
828 | ||
829 | return 0; | |
830 | } | |
831 | ||
832 | static bool is_valid_cache(u32 val) | |
833 | { | |
834 | u32 level, ctype; | |
835 | ||
836 | if (val >= CSSELR_MAX) | |
837 | return -ENOENT; | |
838 | ||
839 | /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ | |
840 | level = (val >> 1); | |
841 | ctype = (cache_levels >> (level * 3)) & 7; | |
842 | ||
843 | switch (ctype) { | |
844 | case 0: /* No cache */ | |
845 | return false; | |
846 | case 1: /* Instruction cache only */ | |
847 | return (val & 1); | |
848 | case 2: /* Data cache only */ | |
849 | case 4: /* Unified cache */ | |
850 | return !(val & 1); | |
851 | case 3: /* Separate instruction and data caches */ | |
852 | return true; | |
853 | default: /* Reserved: we can't know instruction or data. */ | |
854 | return false; | |
855 | } | |
856 | } | |
857 | ||
858 | static int demux_c15_get(u64 id, void __user *uaddr) | |
859 | { | |
860 | u32 val; | |
861 | u32 __user *uval = uaddr; | |
862 | ||
863 | /* Fail if we have unknown bits set. */ | |
864 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK | |
865 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) | |
866 | return -ENOENT; | |
867 | ||
868 | switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { | |
869 | case KVM_REG_ARM_DEMUX_ID_CCSIDR: | |
870 | if (KVM_REG_SIZE(id) != 4) | |
871 | return -ENOENT; | |
872 | val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) | |
873 | >> KVM_REG_ARM_DEMUX_VAL_SHIFT; | |
874 | if (!is_valid_cache(val)) | |
875 | return -ENOENT; | |
876 | ||
877 | return put_user(get_ccsidr(val), uval); | |
878 | default: | |
879 | return -ENOENT; | |
880 | } | |
881 | } | |
882 | ||
883 | static int demux_c15_set(u64 id, void __user *uaddr) | |
884 | { | |
885 | u32 val, newval; | |
886 | u32 __user *uval = uaddr; | |
887 | ||
888 | /* Fail if we have unknown bits set. */ | |
889 | if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK | |
890 | | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) | |
891 | return -ENOENT; | |
892 | ||
893 | switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { | |
894 | case KVM_REG_ARM_DEMUX_ID_CCSIDR: | |
895 | if (KVM_REG_SIZE(id) != 4) | |
896 | return -ENOENT; | |
897 | val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) | |
898 | >> KVM_REG_ARM_DEMUX_VAL_SHIFT; | |
899 | if (!is_valid_cache(val)) | |
900 | return -ENOENT; | |
901 | ||
902 | if (get_user(newval, uval)) | |
903 | return -EFAULT; | |
904 | ||
905 | /* This is also invariant: you can't change it. */ | |
906 | if (newval != get_ccsidr(val)) | |
907 | return -EINVAL; | |
908 | return 0; | |
909 | default: | |
910 | return -ENOENT; | |
911 | } | |
912 | } | |
913 | ||
914 | int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) | |
915 | { | |
916 | const struct sys_reg_desc *r; | |
917 | void __user *uaddr = (void __user *)(unsigned long)reg->addr; | |
918 | ||
919 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) | |
920 | return demux_c15_get(reg->id, uaddr); | |
921 | ||
922 | if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) | |
923 | return -ENOENT; | |
924 | ||
925 | r = index_to_sys_reg_desc(vcpu, reg->id); | |
926 | if (!r) | |
927 | return get_invariant_sys_reg(reg->id, uaddr); | |
928 | ||
929 | return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id); | |
930 | } | |
931 | ||
932 | int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) | |
933 | { | |
934 | const struct sys_reg_desc *r; | |
935 | void __user *uaddr = (void __user *)(unsigned long)reg->addr; | |
936 | ||
937 | if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) | |
938 | return demux_c15_set(reg->id, uaddr); | |
939 | ||
940 | if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) | |
941 | return -ENOENT; | |
942 | ||
943 | r = index_to_sys_reg_desc(vcpu, reg->id); | |
944 | if (!r) | |
945 | return set_invariant_sys_reg(reg->id, uaddr); | |
946 | ||
947 | return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); | |
948 | } | |
949 | ||
950 | static unsigned int num_demux_regs(void) | |
951 | { | |
952 | unsigned int i, count = 0; | |
953 | ||
954 | for (i = 0; i < CSSELR_MAX; i++) | |
955 | if (is_valid_cache(i)) | |
956 | count++; | |
957 | ||
958 | return count; | |
959 | } | |
960 | ||
961 | static int write_demux_regids(u64 __user *uindices) | |
962 | { | |
efd48cea | 963 | u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; |
7c8c5e6a MZ |
964 | unsigned int i; |
965 | ||
966 | val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; | |
967 | for (i = 0; i < CSSELR_MAX; i++) { | |
968 | if (!is_valid_cache(i)) | |
969 | continue; | |
970 | if (put_user(val | i, uindices)) | |
971 | return -EFAULT; | |
972 | uindices++; | |
973 | } | |
974 | return 0; | |
975 | } | |
976 | ||
977 | static u64 sys_reg_to_index(const struct sys_reg_desc *reg) | |
978 | { | |
979 | return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | | |
980 | KVM_REG_ARM64_SYSREG | | |
981 | (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | | |
982 | (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | | |
983 | (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | | |
984 | (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | | |
985 | (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); | |
986 | } | |
987 | ||
988 | static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) | |
989 | { | |
990 | if (!*uind) | |
991 | return true; | |
992 | ||
993 | if (put_user(sys_reg_to_index(reg), *uind)) | |
994 | return false; | |
995 | ||
996 | (*uind)++; | |
997 | return true; | |
998 | } | |
999 | ||
1000 | /* Assumed ordered tables, see kvm_sys_reg_table_init. */ | |
1001 | static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) | |
1002 | { | |
1003 | const struct sys_reg_desc *i1, *i2, *end1, *end2; | |
1004 | unsigned int total = 0; | |
1005 | size_t num; | |
1006 | ||
1007 | /* We check for duplicates here, to allow arch-specific overrides. */ | |
62a89c44 | 1008 | i1 = get_target_table(vcpu->arch.target, true, &num); |
7c8c5e6a MZ |
1009 | end1 = i1 + num; |
1010 | i2 = sys_reg_descs; | |
1011 | end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); | |
1012 | ||
1013 | BUG_ON(i1 == end1 || i2 == end2); | |
1014 | ||
1015 | /* Walk carefully, as both tables may refer to the same register. */ | |
1016 | while (i1 || i2) { | |
1017 | int cmp = cmp_sys_reg(i1, i2); | |
1018 | /* target-specific overrides generic entry. */ | |
1019 | if (cmp <= 0) { | |
1020 | /* Ignore registers we trap but don't save. */ | |
1021 | if (i1->reg) { | |
1022 | if (!copy_reg_to_user(i1, &uind)) | |
1023 | return -EFAULT; | |
1024 | total++; | |
1025 | } | |
1026 | } else { | |
1027 | /* Ignore registers we trap but don't save. */ | |
1028 | if (i2->reg) { | |
1029 | if (!copy_reg_to_user(i2, &uind)) | |
1030 | return -EFAULT; | |
1031 | total++; | |
1032 | } | |
1033 | } | |
1034 | ||
1035 | if (cmp <= 0 && ++i1 == end1) | |
1036 | i1 = NULL; | |
1037 | if (cmp >= 0 && ++i2 == end2) | |
1038 | i2 = NULL; | |
1039 | } | |
1040 | return total; | |
1041 | } | |
1042 | ||
1043 | unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) | |
1044 | { | |
1045 | return ARRAY_SIZE(invariant_sys_regs) | |
1046 | + num_demux_regs() | |
1047 | + walk_sys_regs(vcpu, (u64 __user *)NULL); | |
1048 | } | |
1049 | ||
1050 | int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) | |
1051 | { | |
1052 | unsigned int i; | |
1053 | int err; | |
1054 | ||
1055 | /* Then give them all the invariant registers' indices. */ | |
1056 | for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { | |
1057 | if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) | |
1058 | return -EFAULT; | |
1059 | uindices++; | |
1060 | } | |
1061 | ||
1062 | err = walk_sys_regs(vcpu, uindices); | |
1063 | if (err < 0) | |
1064 | return err; | |
1065 | uindices += err; | |
1066 | ||
1067 | return write_demux_regids(uindices); | |
1068 | } | |
1069 | ||
1070 | void kvm_sys_reg_table_init(void) | |
1071 | { | |
1072 | unsigned int i; | |
1073 | struct sys_reg_desc clidr; | |
1074 | ||
1075 | /* Make sure tables are unique and in order. */ | |
1076 | for (i = 1; i < ARRAY_SIZE(sys_reg_descs); i++) | |
1077 | BUG_ON(cmp_sys_reg(&sys_reg_descs[i-1], &sys_reg_descs[i]) >= 0); | |
1078 | ||
1079 | /* We abuse the reset function to overwrite the table itself. */ | |
1080 | for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) | |
1081 | invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); | |
1082 | ||
1083 | /* | |
1084 | * CLIDR format is awkward, so clean it up. See ARM B4.1.20: | |
1085 | * | |
1086 | * If software reads the Cache Type fields from Ctype1 | |
1087 | * upwards, once it has seen a value of 0b000, no caches | |
1088 | * exist at further-out levels of the hierarchy. So, for | |
1089 | * example, if Ctype3 is the first Cache Type field with a | |
1090 | * value of 0b000, the values of Ctype4 to Ctype7 must be | |
1091 | * ignored. | |
1092 | */ | |
1093 | get_clidr_el1(NULL, &clidr); /* Ugly... */ | |
1094 | cache_levels = clidr.val; | |
1095 | for (i = 0; i < 7; i++) | |
1096 | if (((cache_levels >> (i*3)) & 7) == 0) | |
1097 | break; | |
1098 | /* Clear all higher bits. */ | |
1099 | cache_levels &= (1 << (i*3))-1; | |
1100 | } | |
1101 | ||
1102 | /** | |
1103 | * kvm_reset_sys_regs - sets system registers to reset value | |
1104 | * @vcpu: The VCPU pointer | |
1105 | * | |
1106 | * This function finds the right table above and sets the registers on the | |
1107 | * virtual CPU struct to their architecturally defined reset values. | |
1108 | */ | |
1109 | void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) | |
1110 | { | |
1111 | size_t num; | |
1112 | const struct sys_reg_desc *table; | |
1113 | ||
1114 | /* Catch someone adding a register without putting in reset entry. */ | |
1115 | memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs)); | |
1116 | ||
1117 | /* Generic chip reset first (so target could override). */ | |
1118 | reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); | |
1119 | ||
62a89c44 | 1120 | table = get_target_table(vcpu->arch.target, true, &num); |
7c8c5e6a MZ |
1121 | reset_sys_reg_descs(vcpu, table, num); |
1122 | ||
1123 | for (num = 1; num < NR_SYS_REGS; num++) | |
1124 | if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242) | |
1125 | panic("Didn't reset vcpu_sys_reg(%zi)", num); | |
1126 | } |