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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
051ff581 SZ |
2 | /* |
3 | * Copyright (C) 2015 Linaro Ltd. | |
4 | * Author: Shannon Zhao <shannon.zhao@linaro.org> | |
051ff581 SZ |
5 | */ |
6 | ||
7 | #include <linux/cpu.h> | |
8 | #include <linux/kvm.h> | |
9 | #include <linux/kvm_host.h> | |
db858060 | 10 | #include <linux/list.h> |
051ff581 | 11 | #include <linux/perf_event.h> |
8c3252c0 | 12 | #include <linux/perf/arm_pmu.h> |
bb0c70bc | 13 | #include <linux/uaccess.h> |
051ff581 SZ |
14 | #include <asm/kvm_emulate.h> |
15 | #include <kvm/arm_pmu.h> | |
b02386eb | 16 | #include <kvm/arm_vgic.h> |
051ff581 | 17 | |
bead0220 MZ |
18 | #define PERF_ATTR_CFG1_COUNTER_64BIT BIT(0) |
19 | ||
be399d82 SC |
20 | DEFINE_STATIC_KEY_FALSE(kvm_arm_pmu_available); |
21 | ||
db858060 AE |
22 | static LIST_HEAD(arm_pmus); |
23 | static DEFINE_MUTEX(arm_pmus_lock); | |
24 | ||
30d97754 | 25 | static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx); |
9917264d | 26 | static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc); |
80f393a2 | 27 | |
fd65a3b5 MZ |
28 | static u32 kvm_pmu_event_mask(struct kvm *kvm) |
29 | { | |
46b18782 MZ |
30 | unsigned int pmuver; |
31 | ||
32 | pmuver = kvm->arch.arm_pmu->pmuver; | |
33 | ||
34 | switch (pmuver) { | |
121a8fc0 | 35 | case ID_AA64DFR0_EL1_PMUVer_IMP: |
fd65a3b5 | 36 | return GENMASK(9, 0); |
121a8fc0 MB |
37 | case ID_AA64DFR0_EL1_PMUVer_V3P1: |
38 | case ID_AA64DFR0_EL1_PMUVer_V3P4: | |
39 | case ID_AA64DFR0_EL1_PMUVer_V3P5: | |
40 | case ID_AA64DFR0_EL1_PMUVer_V3P7: | |
fd65a3b5 MZ |
41 | return GENMASK(15, 0); |
42 | default: /* Shouldn't be here, just for sanity */ | |
46b18782 | 43 | WARN_ONCE(1, "Unknown PMU version %d\n", pmuver); |
fd65a3b5 MZ |
44 | return 0; |
45 | } | |
46 | } | |
47 | ||
218907cb AM |
48 | /** |
49 | * kvm_pmu_idx_is_64bit - determine if select_idx is a 64bit counter | |
50 | * @vcpu: The vcpu pointer | |
51 | * @select_idx: The counter index | |
52 | */ | |
53 | static bool kvm_pmu_idx_is_64bit(struct kvm_vcpu *vcpu, u64 select_idx) | |
c82d28cb | 54 | { |
11af4c37 | 55 | return (select_idx == ARMV8_PMU_CYCLE_IDX || kvm_pmu_is_3p5(vcpu)); |
c82d28cb MZ |
56 | } |
57 | ||
58 | static bool kvm_pmu_idx_has_64bit_overflow(struct kvm_vcpu *vcpu, u64 select_idx) | |
218907cb | 59 | { |
11af4c37 MZ |
60 | u64 val = __vcpu_sys_reg(vcpu, PMCR_EL0); |
61 | ||
62 | return (select_idx < ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LP)) || | |
63 | (select_idx == ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LC)); | |
218907cb AM |
64 | } |
65 | ||
bead0220 MZ |
66 | static bool kvm_pmu_counter_can_chain(struct kvm_vcpu *vcpu, u64 idx) |
67 | { | |
c82d28cb MZ |
68 | return (!(idx & 1) && (idx + 1) < ARMV8_PMU_CYCLE_IDX && |
69 | !kvm_pmu_idx_has_64bit_overflow(vcpu, idx)); | |
bead0220 MZ |
70 | } |
71 | ||
80f393a2 AM |
72 | static struct kvm_vcpu *kvm_pmc_to_vcpu(struct kvm_pmc *pmc) |
73 | { | |
74 | struct kvm_pmu *pmu; | |
75 | struct kvm_vcpu_arch *vcpu_arch; | |
76 | ||
77 | pmc -= pmc->idx; | |
78 | pmu = container_of(pmc, struct kvm_pmu, pmc[0]); | |
79 | vcpu_arch = container_of(pmu, struct kvm_vcpu_arch, pmu); | |
80 | return container_of(vcpu_arch, struct kvm_vcpu, arch); | |
81 | } | |
82 | ||
0cb9c3c8 MZ |
83 | static u32 counter_index_to_reg(u64 idx) |
84 | { | |
85 | return (idx == ARMV8_PMU_CYCLE_IDX) ? PMCCNTR_EL0 : PMEVCNTR0_EL0 + idx; | |
86 | } | |
87 | ||
88 | static u32 counter_index_to_evtreg(u64 idx) | |
89 | { | |
90 | return (idx == ARMV8_PMU_CYCLE_IDX) ? PMCCFILTR_EL0 : PMEVTYPER0_EL0 + idx; | |
91 | } | |
92 | ||
051ff581 | 93 | /** |
bead0220 | 94 | * kvm_pmu_get_counter_value - get PMU counter value |
051ff581 SZ |
95 | * @vcpu: The vcpu pointer |
96 | * @select_idx: The counter index | |
97 | */ | |
bead0220 | 98 | u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx) |
80f393a2 | 99 | { |
bead0220 MZ |
100 | u64 counter, reg, enabled, running; |
101 | struct kvm_pmu *pmu = &vcpu->arch.pmu; | |
102 | struct kvm_pmc *pmc = &pmu->pmc[select_idx]; | |
80f393a2 | 103 | |
bead0220 MZ |
104 | if (!kvm_vcpu_has_pmu(vcpu)) |
105 | return 0; | |
80f393a2 | 106 | |
0cb9c3c8 | 107 | reg = counter_index_to_reg(select_idx); |
bead0220 | 108 | counter = __vcpu_sys_reg(vcpu, reg); |
80f393a2 AM |
109 | |
110 | /* | |
111 | * The real counter value is equal to the value of counter register plus | |
051ff581 SZ |
112 | * the value perf event counts. |
113 | */ | |
114 | if (pmc->perf_event) | |
115 | counter += perf_event_read_value(pmc->perf_event, &enabled, | |
116 | &running); | |
117 | ||
c82d28cb | 118 | if (!kvm_pmu_idx_is_64bit(vcpu, select_idx)) |
218907cb AM |
119 | counter = lower_32_bits(counter); |
120 | ||
121 | return counter; | |
051ff581 SZ |
122 | } |
123 | ||
26d2d059 MZ |
124 | static void kvm_pmu_set_counter(struct kvm_vcpu *vcpu, u64 select_idx, u64 val, |
125 | bool force) | |
051ff581 SZ |
126 | { |
127 | u64 reg; | |
128 | ||
8f6379e2 AE |
129 | if (!kvm_vcpu_has_pmu(vcpu)) |
130 | return; | |
131 | ||
9917264d MZ |
132 | kvm_pmu_release_perf_event(&vcpu->arch.pmu.pmc[select_idx]); |
133 | ||
0cb9c3c8 | 134 | reg = counter_index_to_reg(select_idx); |
26d2d059 MZ |
135 | |
136 | if (vcpu_mode_is_32bit(vcpu) && select_idx != ARMV8_PMU_CYCLE_IDX && | |
137 | !force) { | |
138 | /* | |
139 | * Even with PMUv3p5, AArch32 cannot write to the top | |
140 | * 32bit of the counters. The only possible course of | |
141 | * action is to use PMCR.P, which will reset them to | |
142 | * 0 (the only use of the 'force' parameter). | |
143 | */ | |
144 | val = __vcpu_sys_reg(vcpu, reg) & GENMASK(63, 32); | |
145 | val |= lower_32_bits(val); | |
146 | } | |
147 | ||
9917264d | 148 | __vcpu_sys_reg(vcpu, reg) = val; |
30d97754 AM |
149 | |
150 | /* Recreate the perf event to reflect the updated sample_period */ | |
151 | kvm_pmu_create_perf_event(vcpu, select_idx); | |
051ff581 | 152 | } |
96b0eebc | 153 | |
26d2d059 MZ |
154 | /** |
155 | * kvm_pmu_set_counter_value - set PMU counter value | |
156 | * @vcpu: The vcpu pointer | |
157 | * @select_idx: The counter index | |
158 | * @val: The counter value | |
159 | */ | |
160 | void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val) | |
161 | { | |
162 | kvm_pmu_set_counter(vcpu, select_idx, val, false); | |
163 | } | |
164 | ||
6f4d2a0b AM |
165 | /** |
166 | * kvm_pmu_release_perf_event - remove the perf event | |
167 | * @pmc: The PMU counter pointer | |
168 | */ | |
169 | static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc) | |
170 | { | |
171 | if (pmc->perf_event) { | |
172 | perf_event_disable(pmc->perf_event); | |
173 | perf_event_release_kernel(pmc->perf_event); | |
174 | pmc->perf_event = NULL; | |
175 | } | |
176 | } | |
177 | ||
7f766358 SZ |
178 | /** |
179 | * kvm_pmu_stop_counter - stop PMU counter | |
180 | * @pmc: The PMU counter pointer | |
181 | * | |
182 | * If this counter has been configured to monitor some event, release it here. | |
183 | */ | |
184 | static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu, struct kvm_pmc *pmc) | |
185 | { | |
0f1e172b | 186 | u64 reg, val; |
7f766358 | 187 | |
80f393a2 AM |
188 | if (!pmc->perf_event) |
189 | return; | |
190 | ||
0f1e172b | 191 | val = kvm_pmu_get_counter_value(vcpu, pmc->idx); |
80f393a2 | 192 | |
0cb9c3c8 | 193 | reg = counter_index_to_reg(pmc->idx); |
80f393a2 | 194 | |
f4e23cf9 MZ |
195 | __vcpu_sys_reg(vcpu, reg) = val; |
196 | ||
80f393a2 | 197 | kvm_pmu_release_perf_event(pmc); |
7f766358 SZ |
198 | } |
199 | ||
bca031e2 ZY |
200 | /** |
201 | * kvm_pmu_vcpu_init - assign pmu counter idx for cpu | |
202 | * @vcpu: The vcpu pointer | |
203 | * | |
204 | */ | |
205 | void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) | |
206 | { | |
207 | int i; | |
208 | struct kvm_pmu *pmu = &vcpu->arch.pmu; | |
209 | ||
210 | for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) | |
211 | pmu->pmc[i].idx = i; | |
212 | } | |
213 | ||
2aa36e98 SZ |
214 | /** |
215 | * kvm_pmu_vcpu_reset - reset pmu state for cpu | |
216 | * @vcpu: The vcpu pointer | |
217 | * | |
218 | */ | |
219 | void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) | |
220 | { | |
c01d6a18 | 221 | unsigned long mask = kvm_pmu_valid_counter_mask(vcpu); |
2aa36e98 | 222 | struct kvm_pmu *pmu = &vcpu->arch.pmu; |
c01d6a18 | 223 | int i; |
2aa36e98 | 224 | |
c01d6a18 | 225 | for_each_set_bit(i, &mask, 32) |
2aa36e98 | 226 | kvm_pmu_stop_counter(vcpu, &pmu->pmc[i]); |
2aa36e98 SZ |
227 | } |
228 | ||
5f0a714a SZ |
229 | /** |
230 | * kvm_pmu_vcpu_destroy - free perf event of PMU for cpu | |
231 | * @vcpu: The vcpu pointer | |
232 | * | |
233 | */ | |
234 | void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) | |
235 | { | |
236 | int i; | |
237 | struct kvm_pmu *pmu = &vcpu->arch.pmu; | |
238 | ||
6f4d2a0b AM |
239 | for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) |
240 | kvm_pmu_release_perf_event(&pmu->pmc[i]); | |
95e92e45 | 241 | irq_work_sync(&vcpu->arch.pmu.overflow_work); |
5f0a714a SZ |
242 | } |
243 | ||
96b0eebc SZ |
244 | u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu) |
245 | { | |
8d404c4c | 246 | u64 val = __vcpu_sys_reg(vcpu, PMCR_EL0) >> ARMV8_PMU_PMCR_N_SHIFT; |
96b0eebc SZ |
247 | |
248 | val &= ARMV8_PMU_PMCR_N_MASK; | |
249 | if (val == 0) | |
250 | return BIT(ARMV8_PMU_CYCLE_IDX); | |
251 | else | |
252 | return GENMASK(val - 1, 0) | BIT(ARMV8_PMU_CYCLE_IDX); | |
253 | } | |
254 | ||
255 | /** | |
418e5ca8 | 256 | * kvm_pmu_enable_counter_mask - enable selected PMU counters |
96b0eebc SZ |
257 | * @vcpu: The vcpu pointer |
258 | * @val: the value guest writes to PMCNTENSET register | |
259 | * | |
260 | * Call perf_event_enable to start counting the perf event | |
261 | */ | |
418e5ca8 | 262 | void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) |
96b0eebc SZ |
263 | { |
264 | int i; | |
265 | struct kvm_pmu *pmu = &vcpu->arch.pmu; | |
266 | struct kvm_pmc *pmc; | |
267 | ||
8f6379e2 AE |
268 | if (!kvm_vcpu_has_pmu(vcpu)) |
269 | return; | |
270 | ||
8d404c4c | 271 | if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) || !val) |
96b0eebc SZ |
272 | return; |
273 | ||
274 | for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) { | |
275 | if (!(val & BIT(i))) | |
276 | continue; | |
277 | ||
278 | pmc = &pmu->pmc[i]; | |
80f393a2 | 279 | |
bead0220 MZ |
280 | if (!pmc->perf_event) { |
281 | kvm_pmu_create_perf_event(vcpu, i); | |
282 | } else { | |
96b0eebc SZ |
283 | perf_event_enable(pmc->perf_event); |
284 | if (pmc->perf_event->state != PERF_EVENT_STATE_ACTIVE) | |
285 | kvm_debug("fail to enable perf event\n"); | |
286 | } | |
287 | } | |
288 | } | |
289 | ||
290 | /** | |
418e5ca8 | 291 | * kvm_pmu_disable_counter_mask - disable selected PMU counters |
96b0eebc SZ |
292 | * @vcpu: The vcpu pointer |
293 | * @val: the value guest writes to PMCNTENCLR register | |
294 | * | |
295 | * Call perf_event_disable to stop counting the perf event | |
296 | */ | |
418e5ca8 | 297 | void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) |
96b0eebc SZ |
298 | { |
299 | int i; | |
300 | struct kvm_pmu *pmu = &vcpu->arch.pmu; | |
301 | struct kvm_pmc *pmc; | |
302 | ||
8f6379e2 | 303 | if (!kvm_vcpu_has_pmu(vcpu) || !val) |
96b0eebc SZ |
304 | return; |
305 | ||
306 | for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) { | |
307 | if (!(val & BIT(i))) | |
308 | continue; | |
309 | ||
310 | pmc = &pmu->pmc[i]; | |
80f393a2 | 311 | |
96b0eebc SZ |
312 | if (pmc->perf_event) |
313 | perf_event_disable(pmc->perf_event); | |
314 | } | |
315 | } | |
7f766358 | 316 | |
76d883c4 SZ |
317 | static u64 kvm_pmu_overflow_status(struct kvm_vcpu *vcpu) |
318 | { | |
319 | u64 reg = 0; | |
320 | ||
8d404c4c CD |
321 | if ((__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E)) { |
322 | reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); | |
323 | reg &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); | |
324 | reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1); | |
7d4bd1d2 | 325 | } |
76d883c4 SZ |
326 | |
327 | return reg; | |
328 | } | |
329 | ||
d9f89b4e | 330 | static void kvm_pmu_update_state(struct kvm_vcpu *vcpu) |
b7484931 AJ |
331 | { |
332 | struct kvm_pmu *pmu = &vcpu->arch.pmu; | |
d9f89b4e AJ |
333 | bool overflow; |
334 | ||
46acf89d | 335 | if (!kvm_vcpu_has_pmu(vcpu)) |
d9f89b4e | 336 | return; |
b7484931 | 337 | |
d9f89b4e | 338 | overflow = !!kvm_pmu_overflow_status(vcpu); |
b7484931 AJ |
339 | if (pmu->irq_level == overflow) |
340 | return; | |
341 | ||
342 | pmu->irq_level = overflow; | |
343 | ||
344 | if (likely(irqchip_in_kernel(vcpu->kvm))) { | |
345 | int ret = kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, | |
d9f89b4e | 346 | pmu->irq_num, overflow, pmu); |
b7484931 AJ |
347 | WARN_ON(ret); |
348 | } | |
349 | } | |
350 | ||
3dbbdf78 CD |
351 | bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu) |
352 | { | |
353 | struct kvm_pmu *pmu = &vcpu->arch.pmu; | |
354 | struct kvm_sync_regs *sregs = &vcpu->run->s.regs; | |
355 | bool run_level = sregs->device_irq_level & KVM_ARM_DEV_PMU; | |
356 | ||
357 | if (likely(irqchip_in_kernel(vcpu->kvm))) | |
358 | return false; | |
359 | ||
360 | return pmu->irq_level != run_level; | |
361 | } | |
362 | ||
363 | /* | |
364 | * Reflect the PMU overflow interrupt output level into the kvm_run structure | |
365 | */ | |
366 | void kvm_pmu_update_run(struct kvm_vcpu *vcpu) | |
367 | { | |
368 | struct kvm_sync_regs *regs = &vcpu->run->s.regs; | |
369 | ||
370 | /* Populate the timer bitmap for user space */ | |
371 | regs->device_irq_level &= ~KVM_ARM_DEV_PMU; | |
372 | if (vcpu->arch.pmu.irq_level) | |
373 | regs->device_irq_level |= KVM_ARM_DEV_PMU; | |
374 | } | |
375 | ||
b02386eb SZ |
376 | /** |
377 | * kvm_pmu_flush_hwstate - flush pmu state to cpu | |
378 | * @vcpu: The vcpu pointer | |
379 | * | |
380 | * Check if the PMU has overflowed while we were running in the host, and inject | |
381 | * an interrupt if that was the case. | |
382 | */ | |
383 | void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) | |
384 | { | |
385 | kvm_pmu_update_state(vcpu); | |
386 | } | |
387 | ||
388 | /** | |
389 | * kvm_pmu_sync_hwstate - sync pmu state from cpu | |
390 | * @vcpu: The vcpu pointer | |
391 | * | |
392 | * Check if the PMU has overflowed while we were running in the guest, and | |
393 | * inject an interrupt if that was the case. | |
394 | */ | |
395 | void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) | |
396 | { | |
397 | kvm_pmu_update_state(vcpu); | |
398 | } | |
399 | ||
95e92e45 JT |
400 | /** |
401 | * When perf interrupt is an NMI, we cannot safely notify the vcpu corresponding | |
402 | * to the event. | |
403 | * This is why we need a callback to do it once outside of the NMI context. | |
404 | */ | |
405 | static void kvm_pmu_perf_overflow_notify_vcpu(struct irq_work *work) | |
406 | { | |
407 | struct kvm_vcpu *vcpu; | |
408 | struct kvm_pmu *pmu; | |
409 | ||
410 | pmu = container_of(work, struct kvm_pmu, overflow_work); | |
411 | vcpu = kvm_pmc_to_vcpu(pmu->pmc); | |
412 | ||
413 | kvm_vcpu_kick(vcpu); | |
414 | } | |
415 | ||
bead0220 MZ |
416 | /* |
417 | * Perform an increment on any of the counters described in @mask, | |
418 | * generating the overflow if required, and propagate it as a chained | |
419 | * event if possible. | |
420 | */ | |
421 | static void kvm_pmu_counter_increment(struct kvm_vcpu *vcpu, | |
422 | unsigned long mask, u32 event) | |
423 | { | |
424 | int i; | |
425 | ||
426 | if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E)) | |
427 | return; | |
428 | ||
429 | /* Weed out disabled counters */ | |
430 | mask &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); | |
431 | ||
432 | for_each_set_bit(i, &mask, ARMV8_PMU_CYCLE_IDX) { | |
433 | u64 type, reg; | |
434 | ||
435 | /* Filter on event type */ | |
0cb9c3c8 | 436 | type = __vcpu_sys_reg(vcpu, counter_index_to_evtreg(i)); |
bead0220 MZ |
437 | type &= kvm_pmu_event_mask(vcpu->kvm); |
438 | if (type != event) | |
439 | continue; | |
440 | ||
441 | /* Increment this counter */ | |
0cb9c3c8 | 442 | reg = __vcpu_sys_reg(vcpu, counter_index_to_reg(i)) + 1; |
0f1e172b MZ |
443 | if (!kvm_pmu_idx_is_64bit(vcpu, i)) |
444 | reg = lower_32_bits(reg); | |
0cb9c3c8 | 445 | __vcpu_sys_reg(vcpu, counter_index_to_reg(i)) = reg; |
bead0220 | 446 | |
001d85bd MZ |
447 | /* No overflow? move on */ |
448 | if (kvm_pmu_idx_has_64bit_overflow(vcpu, i) ? reg : lower_32_bits(reg)) | |
bead0220 MZ |
449 | continue; |
450 | ||
451 | /* Mark overflow */ | |
452 | __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(i); | |
453 | ||
454 | if (kvm_pmu_counter_can_chain(vcpu, i)) | |
455 | kvm_pmu_counter_increment(vcpu, BIT(i + 1), | |
456 | ARMV8_PMUV3_PERFCTR_CHAIN); | |
457 | } | |
458 | } | |
459 | ||
c82d28cb MZ |
460 | /* Compute the sample period for a given counter value */ |
461 | static u64 compute_period(struct kvm_vcpu *vcpu, u64 select_idx, u64 counter) | |
462 | { | |
463 | u64 val; | |
464 | ||
465 | if (kvm_pmu_idx_is_64bit(vcpu, select_idx)) { | |
466 | if (!kvm_pmu_idx_has_64bit_overflow(vcpu, select_idx)) | |
467 | val = -(counter & GENMASK(31, 0)); | |
468 | else | |
469 | val = (-counter) & GENMASK(63, 0); | |
470 | } else { | |
471 | val = (-counter) & GENMASK(31, 0); | |
472 | } | |
473 | ||
474 | return val; | |
475 | } | |
476 | ||
b02386eb | 477 | /** |
d9f89b4e | 478 | * When the perf event overflows, set the overflow status and inform the vcpu. |
b02386eb SZ |
479 | */ |
480 | static void kvm_pmu_perf_overflow(struct perf_event *perf_event, | |
481 | struct perf_sample_data *data, | |
482 | struct pt_regs *regs) | |
483 | { | |
484 | struct kvm_pmc *pmc = perf_event->overflow_handler_context; | |
8c3252c0 | 485 | struct arm_pmu *cpu_pmu = to_arm_pmu(perf_event->pmu); |
b02386eb SZ |
486 | struct kvm_vcpu *vcpu = kvm_pmc_to_vcpu(pmc); |
487 | int idx = pmc->idx; | |
8c3252c0 MZ |
488 | u64 period; |
489 | ||
490 | cpu_pmu->pmu.stop(perf_event, PERF_EF_UPDATE); | |
491 | ||
492 | /* | |
493 | * Reset the sample period to the architectural limit, | |
494 | * i.e. the point where the counter overflows. | |
495 | */ | |
c82d28cb | 496 | period = compute_period(vcpu, idx, local64_read(&perf_event->count)); |
8c3252c0 MZ |
497 | |
498 | local64_set(&perf_event->hw.period_left, 0); | |
499 | perf_event->attr.sample_period = period; | |
500 | perf_event->hw.sample_period = period; | |
b02386eb | 501 | |
8d404c4c | 502 | __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(idx); |
d9f89b4e | 503 | |
bead0220 MZ |
504 | if (kvm_pmu_counter_can_chain(vcpu, idx)) |
505 | kvm_pmu_counter_increment(vcpu, BIT(idx + 1), | |
506 | ARMV8_PMUV3_PERFCTR_CHAIN); | |
507 | ||
d9f89b4e AJ |
508 | if (kvm_pmu_overflow_status(vcpu)) { |
509 | kvm_make_request(KVM_REQ_IRQ_PENDING, vcpu); | |
95e92e45 JT |
510 | |
511 | if (!in_nmi()) | |
512 | kvm_vcpu_kick(vcpu); | |
513 | else | |
514 | irq_work_queue(&vcpu->arch.pmu.overflow_work); | |
d9f89b4e | 515 | } |
8c3252c0 MZ |
516 | |
517 | cpu_pmu->pmu.start(perf_event, PERF_EF_RELOAD); | |
b02386eb SZ |
518 | } |
519 | ||
7a0adc70 SZ |
520 | /** |
521 | * kvm_pmu_software_increment - do software increment | |
522 | * @vcpu: The vcpu pointer | |
523 | * @val: the value guest writes to PMSWINC register | |
524 | */ | |
525 | void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) | |
526 | { | |
bead0220 | 527 | kvm_pmu_counter_increment(vcpu, val, ARMV8_PMUV3_PERFCTR_SW_INCR); |
7a0adc70 SZ |
528 | } |
529 | ||
76993739 SZ |
530 | /** |
531 | * kvm_pmu_handle_pmcr - handle PMCR register | |
532 | * @vcpu: The vcpu pointer | |
533 | * @val: the value guest writes to PMCR register | |
534 | */ | |
535 | void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) | |
536 | { | |
76993739 SZ |
537 | int i; |
538 | ||
8f6379e2 AE |
539 | if (!kvm_vcpu_has_pmu(vcpu)) |
540 | return; | |
541 | ||
76993739 | 542 | if (val & ARMV8_PMU_PMCR_E) { |
418e5ca8 | 543 | kvm_pmu_enable_counter_mask(vcpu, |
f5eff400 | 544 | __vcpu_sys_reg(vcpu, PMCNTENSET_EL0)); |
76993739 | 545 | } else { |
ca4f202d AC |
546 | kvm_pmu_disable_counter_mask(vcpu, |
547 | __vcpu_sys_reg(vcpu, PMCNTENSET_EL0)); | |
76993739 SZ |
548 | } |
549 | ||
550 | if (val & ARMV8_PMU_PMCR_C) | |
551 | kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0); | |
552 | ||
553 | if (val & ARMV8_PMU_PMCR_P) { | |
ca4f202d | 554 | unsigned long mask = kvm_pmu_valid_counter_mask(vcpu); |
2a71fabf | 555 | mask &= ~BIT(ARMV8_PMU_CYCLE_IDX); |
c01d6a18 | 556 | for_each_set_bit(i, &mask, 32) |
26d2d059 | 557 | kvm_pmu_set_counter(vcpu, i, 0, true); |
76993739 | 558 | } |
76993739 SZ |
559 | } |
560 | ||
7f766358 SZ |
561 | static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u64 select_idx) |
562 | { | |
8d404c4c CD |
563 | return (__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) && |
564 | (__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & BIT(select_idx)); | |
7f766358 SZ |
565 | } |
566 | ||
567 | /** | |
30d97754 | 568 | * kvm_pmu_create_perf_event - create a perf event for a counter |
7f766358 | 569 | * @vcpu: The vcpu pointer |
7f766358 | 570 | * @select_idx: The number of selected counter |
7f766358 | 571 | */ |
30d97754 | 572 | static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) |
7f766358 | 573 | { |
46b18782 | 574 | struct arm_pmu *arm_pmu = vcpu->kvm->arch.arm_pmu; |
7f766358 | 575 | struct kvm_pmu *pmu = &vcpu->arch.pmu; |
bead0220 | 576 | struct kvm_pmc *pmc = &pmu->pmc[select_idx]; |
7f766358 SZ |
577 | struct perf_event *event; |
578 | struct perf_event_attr attr; | |
30d97754 AM |
579 | u64 eventsel, counter, reg, data; |
580 | ||
0cb9c3c8 | 581 | reg = counter_index_to_evtreg(select_idx); |
30d97754 | 582 | data = __vcpu_sys_reg(vcpu, reg); |
7f766358 SZ |
583 | |
584 | kvm_pmu_stop_counter(vcpu, pmc); | |
d7eec236 MZ |
585 | if (pmc->idx == ARMV8_PMU_CYCLE_IDX) |
586 | eventsel = ARMV8_PMUV3_PERFCTR_CPU_CYCLES; | |
587 | else | |
588 | eventsel = data & kvm_pmu_event_mask(vcpu->kvm); | |
589 | ||
bead0220 MZ |
590 | /* |
591 | * Neither SW increment nor chained events need to be backed | |
592 | * by a perf event. | |
593 | */ | |
594 | if (eventsel == ARMV8_PMUV3_PERFCTR_SW_INCR || | |
595 | eventsel == ARMV8_PMUV3_PERFCTR_CHAIN) | |
d7eec236 | 596 | return; |
7f766358 | 597 | |
d7eec236 MZ |
598 | /* |
599 | * If we have a filter in place and that the event isn't allowed, do | |
600 | * not install a perf event either. | |
601 | */ | |
602 | if (vcpu->kvm->arch.pmu_filter && | |
603 | !test_bit(eventsel, vcpu->kvm->arch.pmu_filter)) | |
7a0adc70 SZ |
604 | return; |
605 | ||
7f766358 | 606 | memset(&attr, 0, sizeof(struct perf_event_attr)); |
46b18782 | 607 | attr.type = arm_pmu->pmu.type; |
7f766358 SZ |
608 | attr.size = sizeof(attr); |
609 | attr.pinned = 1; | |
80f393a2 | 610 | attr.disabled = !kvm_pmu_counter_is_enabled(vcpu, pmc->idx); |
7f766358 SZ |
611 | attr.exclude_user = data & ARMV8_PMU_EXCLUDE_EL0 ? 1 : 0; |
612 | attr.exclude_kernel = data & ARMV8_PMU_EXCLUDE_EL1 ? 1 : 0; | |
613 | attr.exclude_hv = 1; /* Don't count EL2 events */ | |
614 | attr.exclude_host = 1; /* Don't count host events */ | |
d7eec236 | 615 | attr.config = eventsel; |
7f766358 | 616 | |
bead0220 | 617 | counter = kvm_pmu_get_counter_value(vcpu, select_idx); |
80f393a2 | 618 | |
bead0220 MZ |
619 | /* |
620 | * If counting with a 64bit counter, advertise it to the perf | |
c82d28cb MZ |
621 | * code, carefully dealing with the initial sample period |
622 | * which also depends on the overflow. | |
bead0220 | 623 | */ |
c82d28cb | 624 | if (kvm_pmu_idx_is_64bit(vcpu, select_idx)) |
bead0220 | 625 | attr.config1 |= PERF_ATTR_CFG1_COUNTER_64BIT; |
c82d28cb MZ |
626 | |
627 | attr.sample_period = compute_period(vcpu, select_idx, counter); | |
7f766358 | 628 | |
bead0220 | 629 | event = perf_event_create_kernel_counter(&attr, -1, current, |
b02386eb | 630 | kvm_pmu_perf_overflow, pmc); |
80f393a2 | 631 | |
7f766358 SZ |
632 | if (IS_ERR(event)) { |
633 | pr_err_once("kvm: pmu event creation failed %ld\n", | |
634 | PTR_ERR(event)); | |
635 | return; | |
636 | } | |
637 | ||
638 | pmc->perf_event = event; | |
639 | } | |
808e7381 | 640 | |
30d97754 AM |
641 | /** |
642 | * kvm_pmu_set_counter_event_type - set selected counter to monitor some event | |
643 | * @vcpu: The vcpu pointer | |
644 | * @data: The data guest writes to PMXEVTYPER_EL0 | |
645 | * @select_idx: The number of selected counter | |
646 | * | |
647 | * When OS accesses PMXEVTYPER_EL0, that means it wants to set a PMC to count an | |
648 | * event with given hardware event number. Here we call perf_event API to | |
649 | * emulate this action and create a kernel perf event for it. | |
650 | */ | |
651 | void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, | |
652 | u64 select_idx) | |
653 | { | |
fd65a3b5 MZ |
654 | u64 reg, mask; |
655 | ||
8f6379e2 AE |
656 | if (!kvm_vcpu_has_pmu(vcpu)) |
657 | return; | |
658 | ||
fd65a3b5 MZ |
659 | mask = ARMV8_PMU_EVTYPE_MASK; |
660 | mask &= ~ARMV8_PMU_EVTYPE_EVENT; | |
661 | mask |= kvm_pmu_event_mask(vcpu->kvm); | |
30d97754 | 662 | |
0cb9c3c8 | 663 | reg = counter_index_to_evtreg(select_idx); |
30d97754 | 664 | |
fd65a3b5 | 665 | __vcpu_sys_reg(vcpu, reg) = data & mask; |
80f393a2 | 666 | |
30d97754 AM |
667 | kvm_pmu_create_perf_event(vcpu, select_idx); |
668 | } | |
669 | ||
e840f42a MZ |
670 | void kvm_host_pmu_init(struct arm_pmu *pmu) |
671 | { | |
db858060 AE |
672 | struct arm_pmu_entry *entry; |
673 | ||
fcf37b38 | 674 | if (pmu->pmuver == 0 || pmu->pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) |
db858060 AE |
675 | return; |
676 | ||
677 | mutex_lock(&arm_pmus_lock); | |
678 | ||
679 | entry = kmalloc(sizeof(*entry), GFP_KERNEL); | |
680 | if (!entry) | |
681 | goto out_unlock; | |
682 | ||
683 | entry->arm_pmu = pmu; | |
684 | list_add_tail(&entry->entry, &arm_pmus); | |
685 | ||
686 | if (list_is_singular(&arm_pmus)) | |
e840f42a | 687 | static_branch_enable(&kvm_arm_pmu_available); |
db858060 AE |
688 | |
689 | out_unlock: | |
690 | mutex_unlock(&arm_pmus_lock); | |
e840f42a MZ |
691 | } |
692 | ||
46b18782 | 693 | static struct arm_pmu *kvm_pmu_probe_armpmu(void) |
fd65a3b5 MZ |
694 | { |
695 | struct perf_event_attr attr = { }; | |
696 | struct perf_event *event; | |
46b18782 | 697 | struct arm_pmu *pmu = NULL; |
fd65a3b5 MZ |
698 | |
699 | /* | |
700 | * Create a dummy event that only counts user cycles. As we'll never | |
701 | * leave this function with the event being live, it will never | |
702 | * count anything. But it allows us to probe some of the PMU | |
703 | * details. Yes, this is terrible. | |
704 | */ | |
705 | attr.type = PERF_TYPE_RAW; | |
706 | attr.size = sizeof(attr); | |
707 | attr.pinned = 1; | |
708 | attr.disabled = 0; | |
709 | attr.exclude_user = 0; | |
710 | attr.exclude_kernel = 1; | |
711 | attr.exclude_hv = 1; | |
712 | attr.exclude_host = 1; | |
713 | attr.config = ARMV8_PMUV3_PERFCTR_CPU_CYCLES; | |
714 | attr.sample_period = GENMASK(63, 0); | |
715 | ||
716 | event = perf_event_create_kernel_counter(&attr, -1, current, | |
717 | kvm_pmu_perf_overflow, &attr); | |
718 | ||
719 | if (IS_ERR(event)) { | |
720 | pr_err_once("kvm: pmu event creation failed %ld\n", | |
721 | PTR_ERR(event)); | |
46b18782 | 722 | return NULL; |
fd65a3b5 MZ |
723 | } |
724 | ||
725 | if (event->pmu) { | |
726 | pmu = to_arm_pmu(event->pmu); | |
46b18782 | 727 | if (pmu->pmuver == 0 || |
fcf37b38 | 728 | pmu->pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) |
46b18782 | 729 | pmu = NULL; |
fd65a3b5 MZ |
730 | } |
731 | ||
732 | perf_event_disable(event); | |
733 | perf_event_release_kernel(event); | |
734 | ||
46b18782 | 735 | return pmu; |
fd65a3b5 MZ |
736 | } |
737 | ||
88865bec MZ |
738 | u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) |
739 | { | |
740 | unsigned long *bmap = vcpu->kvm->arch.pmu_filter; | |
741 | u64 val, mask = 0; | |
9529aaa0 | 742 | int base, i, nr_events; |
88865bec | 743 | |
8f6379e2 AE |
744 | if (!kvm_vcpu_has_pmu(vcpu)) |
745 | return 0; | |
746 | ||
88865bec MZ |
747 | if (!pmceid1) { |
748 | val = read_sysreg(pmceid0_el0); | |
acdd8a4e MZ |
749 | /* always support CHAIN */ |
750 | val |= BIT(ARMV8_PMUV3_PERFCTR_CHAIN); | |
88865bec MZ |
751 | base = 0; |
752 | } else { | |
753 | val = read_sysreg(pmceid1_el0); | |
46081078 MZ |
754 | /* |
755 | * Don't advertise STALL_SLOT, as PMMIR_EL0 is handled | |
756 | * as RAZ | |
757 | */ | |
121a8fc0 | 758 | if (vcpu->kvm->arch.arm_pmu->pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4) |
46081078 | 759 | val &= ~BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32); |
88865bec MZ |
760 | base = 32; |
761 | } | |
762 | ||
763 | if (!bmap) | |
764 | return val; | |
765 | ||
9529aaa0 MZ |
766 | nr_events = kvm_pmu_event_mask(vcpu->kvm) + 1; |
767 | ||
88865bec MZ |
768 | for (i = 0; i < 32; i += 8) { |
769 | u64 byte; | |
770 | ||
771 | byte = bitmap_get_value8(bmap, base + i); | |
772 | mask |= byte << i; | |
9529aaa0 MZ |
773 | if (nr_events >= (0x4000 + base + 32)) { |
774 | byte = bitmap_get_value8(bmap, 0x4000 + base + i); | |
775 | mask |= byte << (32 + i); | |
776 | } | |
88865bec MZ |
777 | } |
778 | ||
779 | return val & mask; | |
780 | } | |
781 | ||
a2befacf | 782 | int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu) |
bb0c70bc | 783 | { |
9bbfa4b5 | 784 | if (!kvm_vcpu_has_pmu(vcpu)) |
a2befacf | 785 | return 0; |
bb0c70bc | 786 | |
9bbfa4b5 AE |
787 | if (!vcpu->arch.pmu.created) |
788 | return -EINVAL; | |
789 | ||
6fe407f2 | 790 | /* |
a2befacf CD |
791 | * A valid interrupt configuration for the PMU is either to have a |
792 | * properly configured interrupt number and using an in-kernel | |
ebb127f2 | 793 | * irqchip, or to not have an in-kernel GIC and not set an IRQ. |
6fe407f2 | 794 | */ |
ebb127f2 CD |
795 | if (irqchip_in_kernel(vcpu->kvm)) { |
796 | int irq = vcpu->arch.pmu.irq_num; | |
ebb127f2 CD |
797 | /* |
798 | * If we are using an in-kernel vgic, at this point we know | |
799 | * the vgic will be initialized, so we can check the PMU irq | |
800 | * number against the dimensions of the vgic and make sure | |
801 | * it's valid. | |
802 | */ | |
803 | if (!irq_is_ppi(irq) && !vgic_valid_spi(vcpu->kvm, irq)) | |
804 | return -EINVAL; | |
805 | } else if (kvm_arm_pmu_irq_initialized(vcpu)) { | |
806 | return -EINVAL; | |
807 | } | |
a2befacf | 808 | |
d0c94c49 MZ |
809 | /* One-off reload of the PMU on first run */ |
810 | kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); | |
811 | ||
a2befacf CD |
812 | return 0; |
813 | } | |
814 | ||
815 | static int kvm_arm_pmu_v3_init(struct kvm_vcpu *vcpu) | |
816 | { | |
a2befacf | 817 | if (irqchip_in_kernel(vcpu->kvm)) { |
abcb851d CD |
818 | int ret; |
819 | ||
a2befacf CD |
820 | /* |
821 | * If using the PMU with an in-kernel virtual GIC | |
822 | * implementation, we require the GIC to be already | |
823 | * initialized when initializing the PMU. | |
824 | */ | |
825 | if (!vgic_initialized(vcpu->kvm)) | |
826 | return -ENODEV; | |
827 | ||
828 | if (!kvm_arm_pmu_irq_initialized(vcpu)) | |
829 | return -ENXIO; | |
abcb851d CD |
830 | |
831 | ret = kvm_vgic_set_owner(vcpu, vcpu->arch.pmu.irq_num, | |
832 | &vcpu->arch.pmu); | |
833 | if (ret) | |
834 | return ret; | |
a2befacf | 835 | } |
bb0c70bc | 836 | |
95e92e45 JT |
837 | init_irq_work(&vcpu->arch.pmu.overflow_work, |
838 | kvm_pmu_perf_overflow_notify_vcpu); | |
839 | ||
a2befacf | 840 | vcpu->arch.pmu.created = true; |
bb0c70bc SZ |
841 | return 0; |
842 | } | |
843 | ||
2defaff4 AP |
844 | /* |
845 | * For one VM the interrupt type must be same for each vcpu. | |
846 | * As a PPI, the interrupt number is the same for all vcpus, | |
847 | * while as an SPI it must be a separate number per vcpu. | |
848 | */ | |
849 | static bool pmu_irq_is_valid(struct kvm *kvm, int irq) | |
bb0c70bc | 850 | { |
46808a4c | 851 | unsigned long i; |
bb0c70bc SZ |
852 | struct kvm_vcpu *vcpu; |
853 | ||
854 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
855 | if (!kvm_arm_pmu_irq_initialized(vcpu)) | |
856 | continue; | |
857 | ||
2defaff4 | 858 | if (irq_is_ppi(irq)) { |
bb0c70bc SZ |
859 | if (vcpu->arch.pmu.irq_num != irq) |
860 | return false; | |
861 | } else { | |
862 | if (vcpu->arch.pmu.irq_num == irq) | |
863 | return false; | |
864 | } | |
865 | } | |
866 | ||
867 | return true; | |
868 | } | |
869 | ||
6ee7fca2 AE |
870 | static int kvm_arm_pmu_v3_set_pmu(struct kvm_vcpu *vcpu, int pmu_id) |
871 | { | |
872 | struct kvm *kvm = vcpu->kvm; | |
873 | struct arm_pmu_entry *entry; | |
874 | struct arm_pmu *arm_pmu; | |
875 | int ret = -ENXIO; | |
876 | ||
877 | mutex_lock(&kvm->lock); | |
878 | mutex_lock(&arm_pmus_lock); | |
879 | ||
880 | list_for_each_entry(entry, &arm_pmus, entry) { | |
881 | arm_pmu = entry->arm_pmu; | |
882 | if (arm_pmu->pmu.type == pmu_id) { | |
06394531 | 883 | if (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &kvm->arch.flags) || |
6ee7fca2 AE |
884 | (kvm->arch.pmu_filter && kvm->arch.arm_pmu != arm_pmu)) { |
885 | ret = -EBUSY; | |
886 | break; | |
887 | } | |
888 | ||
889 | kvm->arch.arm_pmu = arm_pmu; | |
583cda1b | 890 | cpumask_copy(kvm->arch.supported_cpus, &arm_pmu->supported_cpus); |
6ee7fca2 AE |
891 | ret = 0; |
892 | break; | |
893 | } | |
894 | } | |
895 | ||
896 | mutex_unlock(&arm_pmus_lock); | |
897 | mutex_unlock(&kvm->lock); | |
898 | return ret; | |
899 | } | |
900 | ||
bb0c70bc SZ |
901 | int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) |
902 | { | |
5177fe91 MZ |
903 | struct kvm *kvm = vcpu->kvm; |
904 | ||
77da4303 | 905 | if (!kvm_vcpu_has_pmu(vcpu)) |
42223fb1 MZ |
906 | return -ENODEV; |
907 | ||
908 | if (vcpu->arch.pmu.created) | |
909 | return -EBUSY; | |
910 | ||
46b18782 MZ |
911 | mutex_lock(&kvm->lock); |
912 | if (!kvm->arch.arm_pmu) { | |
913 | /* No PMU set, get the default one */ | |
914 | kvm->arch.arm_pmu = kvm_pmu_probe_armpmu(); | |
915 | if (!kvm->arch.arm_pmu) { | |
916 | mutex_unlock(&kvm->lock); | |
917 | return -ENODEV; | |
918 | } | |
919 | } | |
920 | mutex_unlock(&kvm->lock); | |
fd65a3b5 | 921 | |
bb0c70bc SZ |
922 | switch (attr->attr) { |
923 | case KVM_ARM_VCPU_PMU_V3_IRQ: { | |
924 | int __user *uaddr = (int __user *)(long)attr->addr; | |
925 | int irq; | |
926 | ||
5177fe91 | 927 | if (!irqchip_in_kernel(kvm)) |
a2befacf CD |
928 | return -EINVAL; |
929 | ||
bb0c70bc SZ |
930 | if (get_user(irq, uaddr)) |
931 | return -EFAULT; | |
932 | ||
2defaff4 | 933 | /* The PMU overflow interrupt can be a PPI or a valid SPI. */ |
ebb127f2 | 934 | if (!(irq_is_ppi(irq) || irq_is_spi(irq))) |
2defaff4 AP |
935 | return -EINVAL; |
936 | ||
5177fe91 | 937 | if (!pmu_irq_is_valid(kvm, irq)) |
bb0c70bc SZ |
938 | return -EINVAL; |
939 | ||
940 | if (kvm_arm_pmu_irq_initialized(vcpu)) | |
941 | return -EBUSY; | |
942 | ||
943 | kvm_debug("Set kvm ARM PMU irq: %d\n", irq); | |
944 | vcpu->arch.pmu.irq_num = irq; | |
945 | return 0; | |
946 | } | |
d7eec236 MZ |
947 | case KVM_ARM_VCPU_PMU_V3_FILTER: { |
948 | struct kvm_pmu_event_filter __user *uaddr; | |
949 | struct kvm_pmu_event_filter filter; | |
950 | int nr_events; | |
951 | ||
5177fe91 | 952 | nr_events = kvm_pmu_event_mask(kvm) + 1; |
d7eec236 MZ |
953 | |
954 | uaddr = (struct kvm_pmu_event_filter __user *)(long)attr->addr; | |
955 | ||
956 | if (copy_from_user(&filter, uaddr, sizeof(filter))) | |
957 | return -EFAULT; | |
958 | ||
959 | if (((u32)filter.base_event + filter.nevents) > nr_events || | |
960 | (filter.action != KVM_PMU_EVENT_ALLOW && | |
961 | filter.action != KVM_PMU_EVENT_DENY)) | |
962 | return -EINVAL; | |
963 | ||
5177fe91 MZ |
964 | mutex_lock(&kvm->lock); |
965 | ||
06394531 | 966 | if (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &kvm->arch.flags)) { |
5177fe91 MZ |
967 | mutex_unlock(&kvm->lock); |
968 | return -EBUSY; | |
969 | } | |
d7eec236 | 970 | |
5177fe91 MZ |
971 | if (!kvm->arch.pmu_filter) { |
972 | kvm->arch.pmu_filter = bitmap_alloc(nr_events, GFP_KERNEL_ACCOUNT); | |
973 | if (!kvm->arch.pmu_filter) { | |
974 | mutex_unlock(&kvm->lock); | |
d7eec236 MZ |
975 | return -ENOMEM; |
976 | } | |
977 | ||
978 | /* | |
979 | * The default depends on the first applied filter. | |
980 | * If it allows events, the default is to deny. | |
981 | * Conversely, if the first filter denies a set of | |
982 | * events, the default is to allow. | |
983 | */ | |
984 | if (filter.action == KVM_PMU_EVENT_ALLOW) | |
5177fe91 | 985 | bitmap_zero(kvm->arch.pmu_filter, nr_events); |
d7eec236 | 986 | else |
5177fe91 | 987 | bitmap_fill(kvm->arch.pmu_filter, nr_events); |
d7eec236 MZ |
988 | } |
989 | ||
990 | if (filter.action == KVM_PMU_EVENT_ALLOW) | |
5177fe91 | 991 | bitmap_set(kvm->arch.pmu_filter, filter.base_event, filter.nevents); |
d7eec236 | 992 | else |
5177fe91 | 993 | bitmap_clear(kvm->arch.pmu_filter, filter.base_event, filter.nevents); |
d7eec236 | 994 | |
5177fe91 | 995 | mutex_unlock(&kvm->lock); |
d7eec236 MZ |
996 | |
997 | return 0; | |
998 | } | |
6ee7fca2 AE |
999 | case KVM_ARM_VCPU_PMU_V3_SET_PMU: { |
1000 | int __user *uaddr = (int __user *)(long)attr->addr; | |
1001 | int pmu_id; | |
1002 | ||
1003 | if (get_user(pmu_id, uaddr)) | |
1004 | return -EFAULT; | |
1005 | ||
1006 | return kvm_arm_pmu_v3_set_pmu(vcpu, pmu_id); | |
1007 | } | |
bb0c70bc SZ |
1008 | case KVM_ARM_VCPU_PMU_V3_INIT: |
1009 | return kvm_arm_pmu_v3_init(vcpu); | |
1010 | } | |
1011 | ||
1012 | return -ENXIO; | |
1013 | } | |
1014 | ||
1015 | int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) | |
1016 | { | |
1017 | switch (attr->attr) { | |
1018 | case KVM_ARM_VCPU_PMU_V3_IRQ: { | |
1019 | int __user *uaddr = (int __user *)(long)attr->addr; | |
1020 | int irq; | |
1021 | ||
a2befacf CD |
1022 | if (!irqchip_in_kernel(vcpu->kvm)) |
1023 | return -EINVAL; | |
1024 | ||
14bda7a9 | 1025 | if (!kvm_vcpu_has_pmu(vcpu)) |
bb0c70bc SZ |
1026 | return -ENODEV; |
1027 | ||
1028 | if (!kvm_arm_pmu_irq_initialized(vcpu)) | |
1029 | return -ENXIO; | |
1030 | ||
1031 | irq = vcpu->arch.pmu.irq_num; | |
1032 | return put_user(irq, uaddr); | |
1033 | } | |
1034 | } | |
1035 | ||
1036 | return -ENXIO; | |
1037 | } | |
1038 | ||
1039 | int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) | |
1040 | { | |
1041 | switch (attr->attr) { | |
1042 | case KVM_ARM_VCPU_PMU_V3_IRQ: | |
1043 | case KVM_ARM_VCPU_PMU_V3_INIT: | |
d7eec236 | 1044 | case KVM_ARM_VCPU_PMU_V3_FILTER: |
6ee7fca2 | 1045 | case KVM_ARM_VCPU_PMU_V3_SET_PMU: |
77da4303 | 1046 | if (kvm_vcpu_has_pmu(vcpu)) |
bb0c70bc SZ |
1047 | return 0; |
1048 | } | |
1049 | ||
1050 | return -ENXIO; | |
1051 | } | |
3d0dba57 MZ |
1052 | |
1053 | u8 kvm_arm_pmu_get_pmuver_limit(void) | |
1054 | { | |
1055 | u64 tmp; | |
1056 | ||
1057 | tmp = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); | |
1058 | tmp = cpuid_feature_cap_perfmon_field(tmp, | |
1059 | ID_AA64DFR0_EL1_PMUVer_SHIFT, | |
1060 | ID_AA64DFR0_EL1_PMUVer_V3P4); | |
1061 | return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), tmp); | |
1062 | } |