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d94d71cb | 1 | // SPDX-License-Identifier: GPL-2.0-only |
749cf76c CD |
2 | /* |
3 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
4 | * Author: Christoffer Dall <c.dall@virtualopensystems.com> | |
749cf76c | 5 | */ |
342cd0ab CD |
6 | |
7 | #include <linux/mman.h> | |
8 | #include <linux/kvm_host.h> | |
9 | #include <linux/io.h> | |
ad361f09 | 10 | #include <linux/hugetlb.h> |
196f878a | 11 | #include <linux/sched/signal.h> |
45e96ea6 | 12 | #include <trace/events/kvm.h> |
342cd0ab | 13 | #include <asm/pgalloc.h> |
94f8e641 | 14 | #include <asm/cacheflush.h> |
342cd0ab CD |
15 | #include <asm/kvm_arm.h> |
16 | #include <asm/kvm_mmu.h> | |
0db5e022 | 17 | #include <asm/kvm_ras.h> |
d5d8184d | 18 | #include <asm/kvm_asm.h> |
94f8e641 | 19 | #include <asm/kvm_emulate.h> |
1e947bad | 20 | #include <asm/virt.h> |
d5d8184d CD |
21 | |
22 | #include "trace.h" | |
342cd0ab | 23 | |
5a677ce0 | 24 | static pgd_t *boot_hyp_pgd; |
2fb41059 | 25 | static pgd_t *hyp_pgd; |
e4c5a685 | 26 | static pgd_t *merged_hyp_pgd; |
342cd0ab CD |
27 | static DEFINE_MUTEX(kvm_hyp_pgd_mutex); |
28 | ||
5a677ce0 MZ |
29 | static unsigned long hyp_idmap_start; |
30 | static unsigned long hyp_idmap_end; | |
31 | static phys_addr_t hyp_idmap_vector; | |
32 | ||
e3f019b3 MZ |
33 | static unsigned long io_map_base; |
34 | ||
38f791a4 | 35 | #define hyp_pgd_order get_order(PTRS_PER_PGD * sizeof(pgd_t)) |
5d4e08c4 | 36 | |
15a49a44 MS |
37 | #define KVM_S2PTE_FLAG_IS_IOMAP (1UL << 0) |
38 | #define KVM_S2_FLAG_LOGGING_ACTIVE (1UL << 1) | |
39 | ||
6d674e28 MZ |
40 | static bool is_iomap(unsigned long flags) |
41 | { | |
42 | return flags & KVM_S2PTE_FLAG_IS_IOMAP; | |
43 | } | |
44 | ||
15a49a44 MS |
45 | static bool memslot_is_logging(struct kvm_memory_slot *memslot) |
46 | { | |
15a49a44 | 47 | return memslot->dirty_bitmap && !(memslot->flags & KVM_MEM_READONLY); |
7276030a MS |
48 | } |
49 | ||
50 | /** | |
51 | * kvm_flush_remote_tlbs() - flush all VM TLB entries for v7/8 | |
52 | * @kvm: pointer to kvm structure. | |
53 | * | |
54 | * Interface to HYP function to flush all VM TLB entries | |
55 | */ | |
56 | void kvm_flush_remote_tlbs(struct kvm *kvm) | |
57 | { | |
58 | kvm_call_hyp(__kvm_tlb_flush_vmid, kvm); | |
15a49a44 | 59 | } |
ad361f09 | 60 | |
48762767 | 61 | static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) |
d5d8184d | 62 | { |
8684e701 | 63 | kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa); |
d5d8184d CD |
64 | } |
65 | ||
363ef89f MZ |
66 | /* |
67 | * D-Cache management functions. They take the page table entries by | |
68 | * value, as they are flushing the cache using the kernel mapping (or | |
69 | * kmap on 32bit). | |
70 | */ | |
71 | static void kvm_flush_dcache_pte(pte_t pte) | |
72 | { | |
73 | __kvm_flush_dcache_pte(pte); | |
74 | } | |
75 | ||
76 | static void kvm_flush_dcache_pmd(pmd_t pmd) | |
77 | { | |
78 | __kvm_flush_dcache_pmd(pmd); | |
79 | } | |
80 | ||
81 | static void kvm_flush_dcache_pud(pud_t pud) | |
82 | { | |
83 | __kvm_flush_dcache_pud(pud); | |
84 | } | |
85 | ||
e6fab544 AB |
86 | static bool kvm_is_device_pfn(unsigned long pfn) |
87 | { | |
88 | return !pfn_valid(pfn); | |
89 | } | |
90 | ||
15a49a44 MS |
91 | /** |
92 | * stage2_dissolve_pmd() - clear and flush huge PMD entry | |
93 | * @kvm: pointer to kvm structure. | |
94 | * @addr: IPA | |
95 | * @pmd: pmd pointer for IPA | |
96 | * | |
8324c3d5 | 97 | * Function clears a PMD entry, flushes addr 1st and 2nd stage TLBs. |
15a49a44 MS |
98 | */ |
99 | static void stage2_dissolve_pmd(struct kvm *kvm, phys_addr_t addr, pmd_t *pmd) | |
100 | { | |
bbb3b6b3 | 101 | if (!pmd_thp_or_huge(*pmd)) |
15a49a44 MS |
102 | return; |
103 | ||
104 | pmd_clear(pmd); | |
105 | kvm_tlb_flush_vmid_ipa(kvm, addr); | |
106 | put_page(virt_to_page(pmd)); | |
107 | } | |
108 | ||
b8e0ba7c PA |
109 | /** |
110 | * stage2_dissolve_pud() - clear and flush huge PUD entry | |
111 | * @kvm: pointer to kvm structure. | |
112 | * @addr: IPA | |
113 | * @pud: pud pointer for IPA | |
114 | * | |
8324c3d5 | 115 | * Function clears a PUD entry, flushes addr 1st and 2nd stage TLBs. |
b8e0ba7c PA |
116 | */ |
117 | static void stage2_dissolve_pud(struct kvm *kvm, phys_addr_t addr, pud_t *pudp) | |
118 | { | |
119 | if (!stage2_pud_huge(kvm, *pudp)) | |
120 | return; | |
121 | ||
122 | stage2_pud_clear(kvm, pudp); | |
123 | kvm_tlb_flush_vmid_ipa(kvm, addr); | |
124 | put_page(virt_to_page(pudp)); | |
125 | } | |
126 | ||
d5d8184d CD |
127 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
128 | int min, int max) | |
129 | { | |
130 | void *page; | |
131 | ||
132 | BUG_ON(max > KVM_NR_MEM_OBJS); | |
133 | if (cache->nobjs >= min) | |
134 | return 0; | |
135 | while (cache->nobjs < max) { | |
50f11a8a | 136 | page = (void *)__get_free_page(GFP_PGTABLE_USER); |
d5d8184d CD |
137 | if (!page) |
138 | return -ENOMEM; | |
139 | cache->objects[cache->nobjs++] = page; | |
140 | } | |
141 | return 0; | |
142 | } | |
143 | ||
144 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc) | |
145 | { | |
146 | while (mc->nobjs) | |
147 | free_page((unsigned long)mc->objects[--mc->nobjs]); | |
148 | } | |
149 | ||
150 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) | |
151 | { | |
152 | void *p; | |
153 | ||
154 | BUG_ON(!mc || !mc->nobjs); | |
155 | p = mc->objects[--mc->nobjs]; | |
156 | return p; | |
157 | } | |
158 | ||
7a1c831e | 159 | static void clear_stage2_pgd_entry(struct kvm *kvm, pgd_t *pgd, phys_addr_t addr) |
979acd5e | 160 | { |
e9f63768 | 161 | p4d_t *p4d_table __maybe_unused = stage2_p4d_offset(kvm, pgd, 0UL); |
e55cac5b | 162 | stage2_pgd_clear(kvm, pgd); |
4f853a71 | 163 | kvm_tlb_flush_vmid_ipa(kvm, addr); |
e9f63768 | 164 | stage2_p4d_free(kvm, p4d_table); |
4f853a71 | 165 | put_page(virt_to_page(pgd)); |
979acd5e MZ |
166 | } |
167 | ||
e9f63768 MR |
168 | static void clear_stage2_p4d_entry(struct kvm *kvm, p4d_t *p4d, phys_addr_t addr) |
169 | { | |
170 | pud_t *pud_table __maybe_unused = stage2_pud_offset(kvm, p4d, 0); | |
171 | stage2_p4d_clear(kvm, p4d); | |
172 | kvm_tlb_flush_vmid_ipa(kvm, addr); | |
173 | stage2_pud_free(kvm, pud_table); | |
174 | put_page(virt_to_page(p4d)); | |
175 | } | |
176 | ||
7a1c831e | 177 | static void clear_stage2_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_t addr) |
342cd0ab | 178 | { |
e55cac5b SP |
179 | pmd_t *pmd_table __maybe_unused = stage2_pmd_offset(kvm, pud, 0); |
180 | VM_BUG_ON(stage2_pud_huge(kvm, *pud)); | |
181 | stage2_pud_clear(kvm, pud); | |
4f853a71 | 182 | kvm_tlb_flush_vmid_ipa(kvm, addr); |
e55cac5b | 183 | stage2_pmd_free(kvm, pmd_table); |
4f728276 MZ |
184 | put_page(virt_to_page(pud)); |
185 | } | |
342cd0ab | 186 | |
7a1c831e | 187 | static void clear_stage2_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr) |
4f728276 | 188 | { |
4f853a71 | 189 | pte_t *pte_table = pte_offset_kernel(pmd, 0); |
bbb3b6b3 | 190 | VM_BUG_ON(pmd_thp_or_huge(*pmd)); |
4f853a71 CD |
191 | pmd_clear(pmd); |
192 | kvm_tlb_flush_vmid_ipa(kvm, addr); | |
14b94d07 | 193 | free_page((unsigned long)pte_table); |
4f728276 MZ |
194 | put_page(virt_to_page(pmd)); |
195 | } | |
196 | ||
88dc25e8 MZ |
197 | static inline void kvm_set_pte(pte_t *ptep, pte_t new_pte) |
198 | { | |
199 | WRITE_ONCE(*ptep, new_pte); | |
200 | dsb(ishst); | |
201 | } | |
202 | ||
203 | static inline void kvm_set_pmd(pmd_t *pmdp, pmd_t new_pmd) | |
204 | { | |
205 | WRITE_ONCE(*pmdp, new_pmd); | |
206 | dsb(ishst); | |
207 | } | |
208 | ||
0db9dd8a MZ |
209 | static inline void kvm_pmd_populate(pmd_t *pmdp, pte_t *ptep) |
210 | { | |
211 | kvm_set_pmd(pmdp, kvm_mk_pmd(ptep)); | |
212 | } | |
213 | ||
214 | static inline void kvm_pud_populate(pud_t *pudp, pmd_t *pmdp) | |
215 | { | |
216 | WRITE_ONCE(*pudp, kvm_mk_pud(pmdp)); | |
217 | dsb(ishst); | |
218 | } | |
219 | ||
e9f63768 | 220 | static inline void kvm_p4d_populate(p4d_t *p4dp, pud_t *pudp) |
0db9dd8a | 221 | { |
e9f63768 | 222 | WRITE_ONCE(*p4dp, kvm_mk_p4d(pudp)); |
0db9dd8a MZ |
223 | dsb(ishst); |
224 | } | |
225 | ||
e9f63768 MR |
226 | static inline void kvm_pgd_populate(pgd_t *pgdp, p4d_t *p4dp) |
227 | { | |
228 | #ifndef __PAGETABLE_P4D_FOLDED | |
229 | WRITE_ONCE(*pgdp, kvm_mk_pgd(p4dp)); | |
230 | dsb(ishst); | |
231 | #endif | |
232 | } | |
233 | ||
363ef89f MZ |
234 | /* |
235 | * Unmapping vs dcache management: | |
236 | * | |
237 | * If a guest maps certain memory pages as uncached, all writes will | |
238 | * bypass the data cache and go directly to RAM. However, the CPUs | |
239 | * can still speculate reads (not writes) and fill cache lines with | |
240 | * data. | |
241 | * | |
242 | * Those cache lines will be *clean* cache lines though, so a | |
243 | * clean+invalidate operation is equivalent to an invalidate | |
244 | * operation, because no cache lines are marked dirty. | |
245 | * | |
246 | * Those clean cache lines could be filled prior to an uncached write | |
247 | * by the guest, and the cache coherent IO subsystem would therefore | |
248 | * end up writing old data to disk. | |
249 | * | |
250 | * This is why right after unmapping a page/section and invalidating | |
251 | * the corresponding TLBs, we call kvm_flush_dcache_p*() to make sure | |
252 | * the IO subsystem will never hit in the cache. | |
e48d53a9 MZ |
253 | * |
254 | * This is all avoided on systems that have ARM64_HAS_STAGE2_FWB, as | |
255 | * we then fully enforce cacheability of RAM, no matter what the guest | |
256 | * does. | |
363ef89f | 257 | */ |
7a1c831e | 258 | static void unmap_stage2_ptes(struct kvm *kvm, pmd_t *pmd, |
4f853a71 | 259 | phys_addr_t addr, phys_addr_t end) |
4f728276 | 260 | { |
4f853a71 CD |
261 | phys_addr_t start_addr = addr; |
262 | pte_t *pte, *start_pte; | |
263 | ||
264 | start_pte = pte = pte_offset_kernel(pmd, addr); | |
265 | do { | |
266 | if (!pte_none(*pte)) { | |
363ef89f MZ |
267 | pte_t old_pte = *pte; |
268 | ||
4f853a71 | 269 | kvm_set_pte(pte, __pte(0)); |
4f853a71 | 270 | kvm_tlb_flush_vmid_ipa(kvm, addr); |
363ef89f MZ |
271 | |
272 | /* No need to invalidate the cache for device mappings */ | |
0de58f85 | 273 | if (!kvm_is_device_pfn(pte_pfn(old_pte))) |
363ef89f MZ |
274 | kvm_flush_dcache_pte(old_pte); |
275 | ||
276 | put_page(virt_to_page(pte)); | |
4f853a71 CD |
277 | } |
278 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
279 | ||
e55cac5b | 280 | if (stage2_pte_table_empty(kvm, start_pte)) |
7a1c831e | 281 | clear_stage2_pmd_entry(kvm, pmd, start_addr); |
342cd0ab CD |
282 | } |
283 | ||
7a1c831e | 284 | static void unmap_stage2_pmds(struct kvm *kvm, pud_t *pud, |
4f853a71 | 285 | phys_addr_t addr, phys_addr_t end) |
000d3996 | 286 | { |
4f853a71 CD |
287 | phys_addr_t next, start_addr = addr; |
288 | pmd_t *pmd, *start_pmd; | |
000d3996 | 289 | |
e55cac5b | 290 | start_pmd = pmd = stage2_pmd_offset(kvm, pud, addr); |
4f853a71 | 291 | do { |
e55cac5b | 292 | next = stage2_pmd_addr_end(kvm, addr, end); |
4f853a71 | 293 | if (!pmd_none(*pmd)) { |
bbb3b6b3 | 294 | if (pmd_thp_or_huge(*pmd)) { |
363ef89f MZ |
295 | pmd_t old_pmd = *pmd; |
296 | ||
4f853a71 CD |
297 | pmd_clear(pmd); |
298 | kvm_tlb_flush_vmid_ipa(kvm, addr); | |
363ef89f MZ |
299 | |
300 | kvm_flush_dcache_pmd(old_pmd); | |
301 | ||
4f853a71 CD |
302 | put_page(virt_to_page(pmd)); |
303 | } else { | |
7a1c831e | 304 | unmap_stage2_ptes(kvm, pmd, addr, next); |
4f853a71 | 305 | } |
ad361f09 | 306 | } |
4f853a71 | 307 | } while (pmd++, addr = next, addr != end); |
ad361f09 | 308 | |
e55cac5b | 309 | if (stage2_pmd_table_empty(kvm, start_pmd)) |
7a1c831e | 310 | clear_stage2_pud_entry(kvm, pud, start_addr); |
4f853a71 | 311 | } |
000d3996 | 312 | |
e9f63768 | 313 | static void unmap_stage2_puds(struct kvm *kvm, p4d_t *p4d, |
4f853a71 CD |
314 | phys_addr_t addr, phys_addr_t end) |
315 | { | |
316 | phys_addr_t next, start_addr = addr; | |
317 | pud_t *pud, *start_pud; | |
4f728276 | 318 | |
e9f63768 | 319 | start_pud = pud = stage2_pud_offset(kvm, p4d, addr); |
4f853a71 | 320 | do { |
e55cac5b SP |
321 | next = stage2_pud_addr_end(kvm, addr, end); |
322 | if (!stage2_pud_none(kvm, *pud)) { | |
323 | if (stage2_pud_huge(kvm, *pud)) { | |
363ef89f MZ |
324 | pud_t old_pud = *pud; |
325 | ||
e55cac5b | 326 | stage2_pud_clear(kvm, pud); |
4f853a71 | 327 | kvm_tlb_flush_vmid_ipa(kvm, addr); |
363ef89f | 328 | kvm_flush_dcache_pud(old_pud); |
4f853a71 CD |
329 | put_page(virt_to_page(pud)); |
330 | } else { | |
7a1c831e | 331 | unmap_stage2_pmds(kvm, pud, addr, next); |
4f728276 MZ |
332 | } |
333 | } | |
4f853a71 | 334 | } while (pud++, addr = next, addr != end); |
4f728276 | 335 | |
e55cac5b | 336 | if (stage2_pud_table_empty(kvm, start_pud)) |
e9f63768 MR |
337 | clear_stage2_p4d_entry(kvm, p4d, start_addr); |
338 | } | |
339 | ||
340 | static void unmap_stage2_p4ds(struct kvm *kvm, pgd_t *pgd, | |
341 | phys_addr_t addr, phys_addr_t end) | |
342 | { | |
343 | phys_addr_t next, start_addr = addr; | |
344 | p4d_t *p4d, *start_p4d; | |
345 | ||
346 | start_p4d = p4d = stage2_p4d_offset(kvm, pgd, addr); | |
347 | do { | |
348 | next = stage2_p4d_addr_end(kvm, addr, end); | |
349 | if (!stage2_p4d_none(kvm, *p4d)) | |
350 | unmap_stage2_puds(kvm, p4d, addr, next); | |
351 | } while (p4d++, addr = next, addr != end); | |
352 | ||
353 | if (stage2_p4d_table_empty(kvm, start_p4d)) | |
7a1c831e | 354 | clear_stage2_pgd_entry(kvm, pgd, start_addr); |
4f853a71 CD |
355 | } |
356 | ||
7a1c831e SP |
357 | /** |
358 | * unmap_stage2_range -- Clear stage2 page table entries to unmap a range | |
359 | * @kvm: The VM pointer | |
360 | * @start: The intermediate physical base address of the range to unmap | |
361 | * @size: The size of the area to unmap | |
362 | * | |
363 | * Clear a range of stage-2 mappings, lowering the various ref-counts. Must | |
364 | * be called while holding mmu_lock (unless for freeing the stage2 pgd before | |
365 | * destroying the VM), otherwise another faulting VCPU may come in and mess | |
366 | * with things behind our backs. | |
367 | */ | |
368 | static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size) | |
4f853a71 CD |
369 | { |
370 | pgd_t *pgd; | |
371 | phys_addr_t addr = start, end = start + size; | |
372 | phys_addr_t next; | |
373 | ||
8b3405e3 | 374 | assert_spin_locked(&kvm->mmu_lock); |
47a91b72 JH |
375 | WARN_ON(size & ~PAGE_MASK); |
376 | ||
e55cac5b | 377 | pgd = kvm->arch.pgd + stage2_pgd_index(kvm, addr); |
4f853a71 | 378 | do { |
0c428a6a SP |
379 | /* |
380 | * Make sure the page table is still active, as another thread | |
381 | * could have possibly freed the page table, while we released | |
382 | * the lock. | |
383 | */ | |
384 | if (!READ_ONCE(kvm->arch.pgd)) | |
385 | break; | |
e55cac5b SP |
386 | next = stage2_pgd_addr_end(kvm, addr, end); |
387 | if (!stage2_pgd_none(kvm, *pgd)) | |
e9f63768 | 388 | unmap_stage2_p4ds(kvm, pgd, addr, next); |
8b3405e3 SP |
389 | /* |
390 | * If the range is too large, release the kvm->mmu_lock | |
391 | * to prevent starvation and lockup detector warnings. | |
392 | */ | |
393 | if (next != end) | |
394 | cond_resched_lock(&kvm->mmu_lock); | |
4f853a71 | 395 | } while (pgd++, addr = next, addr != end); |
000d3996 MZ |
396 | } |
397 | ||
9d218a1f MZ |
398 | static void stage2_flush_ptes(struct kvm *kvm, pmd_t *pmd, |
399 | phys_addr_t addr, phys_addr_t end) | |
400 | { | |
401 | pte_t *pte; | |
402 | ||
403 | pte = pte_offset_kernel(pmd, addr); | |
404 | do { | |
0de58f85 | 405 | if (!pte_none(*pte) && !kvm_is_device_pfn(pte_pfn(*pte))) |
363ef89f | 406 | kvm_flush_dcache_pte(*pte); |
9d218a1f MZ |
407 | } while (pte++, addr += PAGE_SIZE, addr != end); |
408 | } | |
409 | ||
410 | static void stage2_flush_pmds(struct kvm *kvm, pud_t *pud, | |
411 | phys_addr_t addr, phys_addr_t end) | |
412 | { | |
413 | pmd_t *pmd; | |
414 | phys_addr_t next; | |
415 | ||
e55cac5b | 416 | pmd = stage2_pmd_offset(kvm, pud, addr); |
9d218a1f | 417 | do { |
e55cac5b | 418 | next = stage2_pmd_addr_end(kvm, addr, end); |
9d218a1f | 419 | if (!pmd_none(*pmd)) { |
bbb3b6b3 | 420 | if (pmd_thp_or_huge(*pmd)) |
363ef89f MZ |
421 | kvm_flush_dcache_pmd(*pmd); |
422 | else | |
9d218a1f | 423 | stage2_flush_ptes(kvm, pmd, addr, next); |
9d218a1f MZ |
424 | } |
425 | } while (pmd++, addr = next, addr != end); | |
426 | } | |
427 | ||
e9f63768 | 428 | static void stage2_flush_puds(struct kvm *kvm, p4d_t *p4d, |
9d218a1f MZ |
429 | phys_addr_t addr, phys_addr_t end) |
430 | { | |
431 | pud_t *pud; | |
432 | phys_addr_t next; | |
433 | ||
e9f63768 | 434 | pud = stage2_pud_offset(kvm, p4d, addr); |
9d218a1f | 435 | do { |
e55cac5b SP |
436 | next = stage2_pud_addr_end(kvm, addr, end); |
437 | if (!stage2_pud_none(kvm, *pud)) { | |
438 | if (stage2_pud_huge(kvm, *pud)) | |
363ef89f MZ |
439 | kvm_flush_dcache_pud(*pud); |
440 | else | |
9d218a1f | 441 | stage2_flush_pmds(kvm, pud, addr, next); |
9d218a1f MZ |
442 | } |
443 | } while (pud++, addr = next, addr != end); | |
444 | } | |
445 | ||
e9f63768 MR |
446 | static void stage2_flush_p4ds(struct kvm *kvm, pgd_t *pgd, |
447 | phys_addr_t addr, phys_addr_t end) | |
448 | { | |
449 | p4d_t *p4d; | |
450 | phys_addr_t next; | |
451 | ||
452 | p4d = stage2_p4d_offset(kvm, pgd, addr); | |
453 | do { | |
454 | next = stage2_p4d_addr_end(kvm, addr, end); | |
455 | if (!stage2_p4d_none(kvm, *p4d)) | |
456 | stage2_flush_puds(kvm, p4d, addr, next); | |
457 | } while (p4d++, addr = next, addr != end); | |
458 | } | |
459 | ||
9d218a1f MZ |
460 | static void stage2_flush_memslot(struct kvm *kvm, |
461 | struct kvm_memory_slot *memslot) | |
462 | { | |
463 | phys_addr_t addr = memslot->base_gfn << PAGE_SHIFT; | |
464 | phys_addr_t end = addr + PAGE_SIZE * memslot->npages; | |
465 | phys_addr_t next; | |
466 | pgd_t *pgd; | |
467 | ||
e55cac5b | 468 | pgd = kvm->arch.pgd + stage2_pgd_index(kvm, addr); |
9d218a1f | 469 | do { |
e55cac5b SP |
470 | next = stage2_pgd_addr_end(kvm, addr, end); |
471 | if (!stage2_pgd_none(kvm, *pgd)) | |
e9f63768 | 472 | stage2_flush_p4ds(kvm, pgd, addr, next); |
48c963e3 JY |
473 | |
474 | if (next != end) | |
475 | cond_resched_lock(&kvm->mmu_lock); | |
9d218a1f MZ |
476 | } while (pgd++, addr = next, addr != end); |
477 | } | |
478 | ||
479 | /** | |
480 | * stage2_flush_vm - Invalidate cache for pages mapped in stage 2 | |
481 | * @kvm: The struct kvm pointer | |
482 | * | |
483 | * Go through the stage 2 page tables and invalidate any cache lines | |
484 | * backing memory already mapped to the VM. | |
485 | */ | |
3c1e7165 | 486 | static void stage2_flush_vm(struct kvm *kvm) |
9d218a1f MZ |
487 | { |
488 | struct kvm_memslots *slots; | |
489 | struct kvm_memory_slot *memslot; | |
490 | int idx; | |
491 | ||
492 | idx = srcu_read_lock(&kvm->srcu); | |
493 | spin_lock(&kvm->mmu_lock); | |
494 | ||
495 | slots = kvm_memslots(kvm); | |
496 | kvm_for_each_memslot(memslot, slots) | |
497 | stage2_flush_memslot(kvm, memslot); | |
498 | ||
499 | spin_unlock(&kvm->mmu_lock); | |
500 | srcu_read_unlock(&kvm->srcu, idx); | |
501 | } | |
502 | ||
64f32497 SP |
503 | static void clear_hyp_pgd_entry(pgd_t *pgd) |
504 | { | |
e9f63768 | 505 | p4d_t *p4d_table __maybe_unused = p4d_offset(pgd, 0UL); |
64f32497 | 506 | pgd_clear(pgd); |
e9f63768 | 507 | p4d_free(NULL, p4d_table); |
64f32497 SP |
508 | put_page(virt_to_page(pgd)); |
509 | } | |
510 | ||
e9f63768 MR |
511 | static void clear_hyp_p4d_entry(p4d_t *p4d) |
512 | { | |
513 | pud_t *pud_table __maybe_unused = pud_offset(p4d, 0UL); | |
514 | VM_BUG_ON(p4d_huge(*p4d)); | |
515 | p4d_clear(p4d); | |
516 | pud_free(NULL, pud_table); | |
517 | put_page(virt_to_page(p4d)); | |
518 | } | |
519 | ||
64f32497 SP |
520 | static void clear_hyp_pud_entry(pud_t *pud) |
521 | { | |
522 | pmd_t *pmd_table __maybe_unused = pmd_offset(pud, 0); | |
523 | VM_BUG_ON(pud_huge(*pud)); | |
524 | pud_clear(pud); | |
525 | pmd_free(NULL, pmd_table); | |
526 | put_page(virt_to_page(pud)); | |
527 | } | |
528 | ||
529 | static void clear_hyp_pmd_entry(pmd_t *pmd) | |
530 | { | |
531 | pte_t *pte_table = pte_offset_kernel(pmd, 0); | |
532 | VM_BUG_ON(pmd_thp_or_huge(*pmd)); | |
533 | pmd_clear(pmd); | |
534 | pte_free_kernel(NULL, pte_table); | |
535 | put_page(virt_to_page(pmd)); | |
536 | } | |
537 | ||
538 | static void unmap_hyp_ptes(pmd_t *pmd, phys_addr_t addr, phys_addr_t end) | |
539 | { | |
540 | pte_t *pte, *start_pte; | |
541 | ||
542 | start_pte = pte = pte_offset_kernel(pmd, addr); | |
543 | do { | |
544 | if (!pte_none(*pte)) { | |
545 | kvm_set_pte(pte, __pte(0)); | |
546 | put_page(virt_to_page(pte)); | |
547 | } | |
548 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
549 | ||
550 | if (hyp_pte_table_empty(start_pte)) | |
551 | clear_hyp_pmd_entry(pmd); | |
552 | } | |
553 | ||
554 | static void unmap_hyp_pmds(pud_t *pud, phys_addr_t addr, phys_addr_t end) | |
555 | { | |
556 | phys_addr_t next; | |
557 | pmd_t *pmd, *start_pmd; | |
558 | ||
559 | start_pmd = pmd = pmd_offset(pud, addr); | |
560 | do { | |
561 | next = pmd_addr_end(addr, end); | |
562 | /* Hyp doesn't use huge pmds */ | |
563 | if (!pmd_none(*pmd)) | |
564 | unmap_hyp_ptes(pmd, addr, next); | |
565 | } while (pmd++, addr = next, addr != end); | |
566 | ||
567 | if (hyp_pmd_table_empty(start_pmd)) | |
568 | clear_hyp_pud_entry(pud); | |
569 | } | |
570 | ||
e9f63768 | 571 | static void unmap_hyp_puds(p4d_t *p4d, phys_addr_t addr, phys_addr_t end) |
64f32497 SP |
572 | { |
573 | phys_addr_t next; | |
574 | pud_t *pud, *start_pud; | |
575 | ||
e9f63768 | 576 | start_pud = pud = pud_offset(p4d, addr); |
64f32497 SP |
577 | do { |
578 | next = pud_addr_end(addr, end); | |
579 | /* Hyp doesn't use huge puds */ | |
580 | if (!pud_none(*pud)) | |
581 | unmap_hyp_pmds(pud, addr, next); | |
582 | } while (pud++, addr = next, addr != end); | |
583 | ||
584 | if (hyp_pud_table_empty(start_pud)) | |
e9f63768 MR |
585 | clear_hyp_p4d_entry(p4d); |
586 | } | |
587 | ||
588 | static void unmap_hyp_p4ds(pgd_t *pgd, phys_addr_t addr, phys_addr_t end) | |
589 | { | |
590 | phys_addr_t next; | |
591 | p4d_t *p4d, *start_p4d; | |
592 | ||
593 | start_p4d = p4d = p4d_offset(pgd, addr); | |
594 | do { | |
595 | next = p4d_addr_end(addr, end); | |
596 | /* Hyp doesn't use huge p4ds */ | |
597 | if (!p4d_none(*p4d)) | |
598 | unmap_hyp_puds(p4d, addr, next); | |
599 | } while (p4d++, addr = next, addr != end); | |
600 | ||
601 | if (hyp_p4d_table_empty(start_p4d)) | |
64f32497 SP |
602 | clear_hyp_pgd_entry(pgd); |
603 | } | |
604 | ||
3ddd4556 MZ |
605 | static unsigned int kvm_pgd_index(unsigned long addr, unsigned int ptrs_per_pgd) |
606 | { | |
607 | return (addr >> PGDIR_SHIFT) & (ptrs_per_pgd - 1); | |
608 | } | |
609 | ||
610 | static void __unmap_hyp_range(pgd_t *pgdp, unsigned long ptrs_per_pgd, | |
611 | phys_addr_t start, u64 size) | |
64f32497 SP |
612 | { |
613 | pgd_t *pgd; | |
614 | phys_addr_t addr = start, end = start + size; | |
615 | phys_addr_t next; | |
616 | ||
617 | /* | |
618 | * We don't unmap anything from HYP, except at the hyp tear down. | |
619 | * Hence, we don't have to invalidate the TLBs here. | |
620 | */ | |
3ddd4556 | 621 | pgd = pgdp + kvm_pgd_index(addr, ptrs_per_pgd); |
64f32497 SP |
622 | do { |
623 | next = pgd_addr_end(addr, end); | |
624 | if (!pgd_none(*pgd)) | |
e9f63768 | 625 | unmap_hyp_p4ds(pgd, addr, next); |
64f32497 SP |
626 | } while (pgd++, addr = next, addr != end); |
627 | } | |
628 | ||
3ddd4556 MZ |
629 | static void unmap_hyp_range(pgd_t *pgdp, phys_addr_t start, u64 size) |
630 | { | |
631 | __unmap_hyp_range(pgdp, PTRS_PER_PGD, start, size); | |
632 | } | |
633 | ||
634 | static void unmap_hyp_idmap_range(pgd_t *pgdp, phys_addr_t start, u64 size) | |
635 | { | |
636 | __unmap_hyp_range(pgdp, __kvm_idmap_ptrs_per_pgd(), start, size); | |
637 | } | |
638 | ||
342cd0ab | 639 | /** |
4f728276 | 640 | * free_hyp_pgds - free Hyp-mode page tables |
342cd0ab | 641 | * |
5a677ce0 MZ |
642 | * Assumes hyp_pgd is a page table used strictly in Hyp-mode and |
643 | * therefore contains either mappings in the kernel memory area (above | |
e3f019b3 | 644 | * PAGE_OFFSET), or device mappings in the idmap range. |
5a677ce0 | 645 | * |
e3f019b3 MZ |
646 | * boot_hyp_pgd should only map the idmap range, and is only used in |
647 | * the extended idmap case. | |
342cd0ab | 648 | */ |
4f728276 | 649 | void free_hyp_pgds(void) |
342cd0ab | 650 | { |
e3f019b3 MZ |
651 | pgd_t *id_pgd; |
652 | ||
d157f4a5 | 653 | mutex_lock(&kvm_hyp_pgd_mutex); |
5a677ce0 | 654 | |
e3f019b3 MZ |
655 | id_pgd = boot_hyp_pgd ? boot_hyp_pgd : hyp_pgd; |
656 | ||
657 | if (id_pgd) { | |
658 | /* In case we never called hyp_mmu_init() */ | |
659 | if (!io_map_base) | |
660 | io_map_base = hyp_idmap_start; | |
661 | unmap_hyp_idmap_range(id_pgd, io_map_base, | |
662 | hyp_idmap_start + PAGE_SIZE - io_map_base); | |
663 | } | |
664 | ||
26781f9c | 665 | if (boot_hyp_pgd) { |
26781f9c MZ |
666 | free_pages((unsigned long)boot_hyp_pgd, hyp_pgd_order); |
667 | boot_hyp_pgd = NULL; | |
668 | } | |
669 | ||
4f728276 | 670 | if (hyp_pgd) { |
7839c672 MZ |
671 | unmap_hyp_range(hyp_pgd, kern_hyp_va(PAGE_OFFSET), |
672 | (uintptr_t)high_memory - PAGE_OFFSET); | |
d4cb9df5 | 673 | |
38f791a4 | 674 | free_pages((unsigned long)hyp_pgd, hyp_pgd_order); |
d157f4a5 | 675 | hyp_pgd = NULL; |
4f728276 | 676 | } |
e4c5a685 AB |
677 | if (merged_hyp_pgd) { |
678 | clear_page(merged_hyp_pgd); | |
679 | free_page((unsigned long)merged_hyp_pgd); | |
680 | merged_hyp_pgd = NULL; | |
681 | } | |
4f728276 | 682 | |
342cd0ab CD |
683 | mutex_unlock(&kvm_hyp_pgd_mutex); |
684 | } | |
685 | ||
686 | static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start, | |
6060df84 MZ |
687 | unsigned long end, unsigned long pfn, |
688 | pgprot_t prot) | |
342cd0ab CD |
689 | { |
690 | pte_t *pte; | |
691 | unsigned long addr; | |
342cd0ab | 692 | |
3562c76d MZ |
693 | addr = start; |
694 | do { | |
6060df84 | 695 | pte = pte_offset_kernel(pmd, addr); |
f8df7338 | 696 | kvm_set_pte(pte, kvm_pfn_pte(pfn, prot)); |
4f728276 | 697 | get_page(virt_to_page(pte)); |
6060df84 | 698 | pfn++; |
3562c76d | 699 | } while (addr += PAGE_SIZE, addr != end); |
342cd0ab CD |
700 | } |
701 | ||
702 | static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start, | |
6060df84 MZ |
703 | unsigned long end, unsigned long pfn, |
704 | pgprot_t prot) | |
342cd0ab CD |
705 | { |
706 | pmd_t *pmd; | |
707 | pte_t *pte; | |
708 | unsigned long addr, next; | |
709 | ||
3562c76d MZ |
710 | addr = start; |
711 | do { | |
6060df84 | 712 | pmd = pmd_offset(pud, addr); |
342cd0ab CD |
713 | |
714 | BUG_ON(pmd_sect(*pmd)); | |
715 | ||
716 | if (pmd_none(*pmd)) { | |
4cf58924 | 717 | pte = pte_alloc_one_kernel(NULL); |
342cd0ab CD |
718 | if (!pte) { |
719 | kvm_err("Cannot allocate Hyp pte\n"); | |
720 | return -ENOMEM; | |
721 | } | |
0db9dd8a | 722 | kvm_pmd_populate(pmd, pte); |
4f728276 | 723 | get_page(virt_to_page(pmd)); |
342cd0ab CD |
724 | } |
725 | ||
726 | next = pmd_addr_end(addr, end); | |
727 | ||
6060df84 MZ |
728 | create_hyp_pte_mappings(pmd, addr, next, pfn, prot); |
729 | pfn += (next - addr) >> PAGE_SHIFT; | |
3562c76d | 730 | } while (addr = next, addr != end); |
342cd0ab CD |
731 | |
732 | return 0; | |
733 | } | |
734 | ||
e9f63768 | 735 | static int create_hyp_pud_mappings(p4d_t *p4d, unsigned long start, |
38f791a4 CD |
736 | unsigned long end, unsigned long pfn, |
737 | pgprot_t prot) | |
738 | { | |
739 | pud_t *pud; | |
740 | pmd_t *pmd; | |
741 | unsigned long addr, next; | |
742 | int ret; | |
743 | ||
744 | addr = start; | |
745 | do { | |
e9f63768 | 746 | pud = pud_offset(p4d, addr); |
38f791a4 CD |
747 | |
748 | if (pud_none_or_clear_bad(pud)) { | |
749 | pmd = pmd_alloc_one(NULL, addr); | |
750 | if (!pmd) { | |
751 | kvm_err("Cannot allocate Hyp pmd\n"); | |
752 | return -ENOMEM; | |
753 | } | |
0db9dd8a | 754 | kvm_pud_populate(pud, pmd); |
38f791a4 | 755 | get_page(virt_to_page(pud)); |
38f791a4 CD |
756 | } |
757 | ||
758 | next = pud_addr_end(addr, end); | |
759 | ret = create_hyp_pmd_mappings(pud, addr, next, pfn, prot); | |
760 | if (ret) | |
761 | return ret; | |
762 | pfn += (next - addr) >> PAGE_SHIFT; | |
763 | } while (addr = next, addr != end); | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
e9f63768 MR |
768 | static int create_hyp_p4d_mappings(pgd_t *pgd, unsigned long start, |
769 | unsigned long end, unsigned long pfn, | |
770 | pgprot_t prot) | |
771 | { | |
772 | p4d_t *p4d; | |
773 | pud_t *pud; | |
774 | unsigned long addr, next; | |
775 | int ret; | |
776 | ||
777 | addr = start; | |
778 | do { | |
779 | p4d = p4d_offset(pgd, addr); | |
780 | ||
781 | if (p4d_none(*p4d)) { | |
782 | pud = pud_alloc_one(NULL, addr); | |
783 | if (!pud) { | |
784 | kvm_err("Cannot allocate Hyp pud\n"); | |
785 | return -ENOMEM; | |
786 | } | |
787 | kvm_p4d_populate(p4d, pud); | |
788 | get_page(virt_to_page(p4d)); | |
789 | } | |
790 | ||
791 | next = p4d_addr_end(addr, end); | |
792 | ret = create_hyp_pud_mappings(p4d, addr, next, pfn, prot); | |
793 | if (ret) | |
794 | return ret; | |
795 | pfn += (next - addr) >> PAGE_SHIFT; | |
796 | } while (addr = next, addr != end); | |
797 | ||
798 | return 0; | |
799 | } | |
800 | ||
98732d1b | 801 | static int __create_hyp_mappings(pgd_t *pgdp, unsigned long ptrs_per_pgd, |
6060df84 MZ |
802 | unsigned long start, unsigned long end, |
803 | unsigned long pfn, pgprot_t prot) | |
342cd0ab | 804 | { |
342cd0ab | 805 | pgd_t *pgd; |
e9f63768 | 806 | p4d_t *p4d; |
342cd0ab CD |
807 | unsigned long addr, next; |
808 | int err = 0; | |
809 | ||
342cd0ab | 810 | mutex_lock(&kvm_hyp_pgd_mutex); |
3562c76d MZ |
811 | addr = start & PAGE_MASK; |
812 | end = PAGE_ALIGN(end); | |
813 | do { | |
3ddd4556 | 814 | pgd = pgdp + kvm_pgd_index(addr, ptrs_per_pgd); |
342cd0ab | 815 | |
38f791a4 | 816 | if (pgd_none(*pgd)) { |
e9f63768 MR |
817 | p4d = p4d_alloc_one(NULL, addr); |
818 | if (!p4d) { | |
819 | kvm_err("Cannot allocate Hyp p4d\n"); | |
342cd0ab CD |
820 | err = -ENOMEM; |
821 | goto out; | |
822 | } | |
e9f63768 | 823 | kvm_pgd_populate(pgd, p4d); |
38f791a4 | 824 | get_page(virt_to_page(pgd)); |
342cd0ab CD |
825 | } |
826 | ||
827 | next = pgd_addr_end(addr, end); | |
e9f63768 | 828 | err = create_hyp_p4d_mappings(pgd, addr, next, pfn, prot); |
342cd0ab CD |
829 | if (err) |
830 | goto out; | |
6060df84 | 831 | pfn += (next - addr) >> PAGE_SHIFT; |
3562c76d | 832 | } while (addr = next, addr != end); |
342cd0ab CD |
833 | out: |
834 | mutex_unlock(&kvm_hyp_pgd_mutex); | |
835 | return err; | |
836 | } | |
837 | ||
40c2729b CD |
838 | static phys_addr_t kvm_kaddr_to_phys(void *kaddr) |
839 | { | |
840 | if (!is_vmalloc_addr(kaddr)) { | |
841 | BUG_ON(!virt_addr_valid(kaddr)); | |
842 | return __pa(kaddr); | |
843 | } else { | |
844 | return page_to_phys(vmalloc_to_page(kaddr)) + | |
845 | offset_in_page(kaddr); | |
846 | } | |
847 | } | |
848 | ||
342cd0ab | 849 | /** |
06e8c3b0 | 850 | * create_hyp_mappings - duplicate a kernel virtual address range in Hyp mode |
342cd0ab CD |
851 | * @from: The virtual kernel start address of the range |
852 | * @to: The virtual kernel end address of the range (exclusive) | |
c8dddecd | 853 | * @prot: The protection to be applied to this range |
342cd0ab | 854 | * |
06e8c3b0 MZ |
855 | * The same virtual address as the kernel virtual address is also used |
856 | * in Hyp-mode mapping (modulo HYP_PAGE_OFFSET) to the same underlying | |
857 | * physical pages. | |
342cd0ab | 858 | */ |
c8dddecd | 859 | int create_hyp_mappings(void *from, void *to, pgprot_t prot) |
342cd0ab | 860 | { |
40c2729b CD |
861 | phys_addr_t phys_addr; |
862 | unsigned long virt_addr; | |
6c41a413 MZ |
863 | unsigned long start = kern_hyp_va((unsigned long)from); |
864 | unsigned long end = kern_hyp_va((unsigned long)to); | |
6060df84 | 865 | |
1e947bad MZ |
866 | if (is_kernel_in_hyp_mode()) |
867 | return 0; | |
868 | ||
40c2729b CD |
869 | start = start & PAGE_MASK; |
870 | end = PAGE_ALIGN(end); | |
6060df84 | 871 | |
40c2729b CD |
872 | for (virt_addr = start; virt_addr < end; virt_addr += PAGE_SIZE) { |
873 | int err; | |
6060df84 | 874 | |
40c2729b | 875 | phys_addr = kvm_kaddr_to_phys(from + virt_addr - start); |
98732d1b KM |
876 | err = __create_hyp_mappings(hyp_pgd, PTRS_PER_PGD, |
877 | virt_addr, virt_addr + PAGE_SIZE, | |
40c2729b | 878 | __phys_to_pfn(phys_addr), |
c8dddecd | 879 | prot); |
40c2729b CD |
880 | if (err) |
881 | return err; | |
882 | } | |
883 | ||
884 | return 0; | |
342cd0ab CD |
885 | } |
886 | ||
dc2e4633 MZ |
887 | static int __create_hyp_private_mapping(phys_addr_t phys_addr, size_t size, |
888 | unsigned long *haddr, pgprot_t prot) | |
342cd0ab | 889 | { |
e3f019b3 MZ |
890 | pgd_t *pgd = hyp_pgd; |
891 | unsigned long base; | |
892 | int ret = 0; | |
6060df84 | 893 | |
e3f019b3 | 894 | mutex_lock(&kvm_hyp_pgd_mutex); |
6060df84 | 895 | |
e3f019b3 | 896 | /* |
656012c7 | 897 | * This assumes that we have enough space below the idmap |
e3f019b3 MZ |
898 | * page to allocate our VAs. If not, the check below will |
899 | * kick. A potential alternative would be to detect that | |
900 | * overflow and switch to an allocation above the idmap. | |
901 | * | |
902 | * The allocated size is always a multiple of PAGE_SIZE. | |
903 | */ | |
904 | size = PAGE_ALIGN(size + offset_in_page(phys_addr)); | |
905 | base = io_map_base - size; | |
1bb32a44 | 906 | |
e3f019b3 MZ |
907 | /* |
908 | * Verify that BIT(VA_BITS - 1) hasn't been flipped by | |
909 | * allocating the new area, as it would indicate we've | |
910 | * overflowed the idmap/IO address range. | |
911 | */ | |
912 | if ((base ^ io_map_base) & BIT(VA_BITS - 1)) | |
913 | ret = -ENOMEM; | |
914 | else | |
915 | io_map_base = base; | |
916 | ||
917 | mutex_unlock(&kvm_hyp_pgd_mutex); | |
918 | ||
919 | if (ret) | |
920 | goto out; | |
921 | ||
922 | if (__kvm_cpu_uses_extended_idmap()) | |
923 | pgd = boot_hyp_pgd; | |
924 | ||
925 | ret = __create_hyp_mappings(pgd, __kvm_idmap_ptrs_per_pgd(), | |
926 | base, base + size, | |
dc2e4633 | 927 | __phys_to_pfn(phys_addr), prot); |
e3f019b3 MZ |
928 | if (ret) |
929 | goto out; | |
930 | ||
dc2e4633 | 931 | *haddr = base + offset_in_page(phys_addr); |
e3f019b3 MZ |
932 | |
933 | out: | |
dc2e4633 MZ |
934 | return ret; |
935 | } | |
936 | ||
937 | /** | |
938 | * create_hyp_io_mappings - Map IO into both kernel and HYP | |
939 | * @phys_addr: The physical start address which gets mapped | |
940 | * @size: Size of the region being mapped | |
941 | * @kaddr: Kernel VA for this mapping | |
942 | * @haddr: HYP VA for this mapping | |
943 | */ | |
944 | int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size, | |
945 | void __iomem **kaddr, | |
946 | void __iomem **haddr) | |
947 | { | |
948 | unsigned long addr; | |
949 | int ret; | |
950 | ||
951 | *kaddr = ioremap(phys_addr, size); | |
952 | if (!*kaddr) | |
953 | return -ENOMEM; | |
954 | ||
955 | if (is_kernel_in_hyp_mode()) { | |
956 | *haddr = *kaddr; | |
957 | return 0; | |
958 | } | |
959 | ||
960 | ret = __create_hyp_private_mapping(phys_addr, size, | |
961 | &addr, PAGE_HYP_DEVICE); | |
1bb32a44 MZ |
962 | if (ret) { |
963 | iounmap(*kaddr); | |
964 | *kaddr = NULL; | |
dc2e4633 MZ |
965 | *haddr = NULL; |
966 | return ret; | |
967 | } | |
968 | ||
969 | *haddr = (void __iomem *)addr; | |
970 | return 0; | |
971 | } | |
972 | ||
973 | /** | |
974 | * create_hyp_exec_mappings - Map an executable range into HYP | |
975 | * @phys_addr: The physical start address which gets mapped | |
976 | * @size: Size of the region being mapped | |
977 | * @haddr: HYP VA for this mapping | |
978 | */ | |
979 | int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size, | |
980 | void **haddr) | |
981 | { | |
982 | unsigned long addr; | |
983 | int ret; | |
984 | ||
985 | BUG_ON(is_kernel_in_hyp_mode()); | |
986 | ||
987 | ret = __create_hyp_private_mapping(phys_addr, size, | |
988 | &addr, PAGE_HYP_EXEC); | |
989 | if (ret) { | |
990 | *haddr = NULL; | |
1bb32a44 MZ |
991 | return ret; |
992 | } | |
993 | ||
dc2e4633 | 994 | *haddr = (void *)addr; |
1bb32a44 | 995 | return 0; |
342cd0ab CD |
996 | } |
997 | ||
d5d8184d CD |
998 | /** |
999 | * kvm_alloc_stage2_pgd - allocate level-1 table for stage-2 translation. | |
1000 | * @kvm: The KVM struct pointer for the VM. | |
1001 | * | |
8324c3d5 ZY |
1002 | * Allocates only the stage-2 HW PGD level table(s) of size defined by |
1003 | * stage2_pgd_size(kvm). | |
d5d8184d CD |
1004 | * |
1005 | * Note we don't need locking here as this is only called when the VM is | |
1006 | * created, which can only be done once. | |
1007 | */ | |
1008 | int kvm_alloc_stage2_pgd(struct kvm *kvm) | |
1009 | { | |
e329fb75 | 1010 | phys_addr_t pgd_phys; |
d5d8184d CD |
1011 | pgd_t *pgd; |
1012 | ||
1013 | if (kvm->arch.pgd != NULL) { | |
1014 | kvm_err("kvm_arch already initialized?\n"); | |
1015 | return -EINVAL; | |
1016 | } | |
1017 | ||
9163ee23 | 1018 | /* Allocate the HW PGD, making sure that each page gets its own refcount */ |
e55cac5b | 1019 | pgd = alloc_pages_exact(stage2_pgd_size(kvm), GFP_KERNEL | __GFP_ZERO); |
9163ee23 | 1020 | if (!pgd) |
a987370f MZ |
1021 | return -ENOMEM; |
1022 | ||
e329fb75 CD |
1023 | pgd_phys = virt_to_phys(pgd); |
1024 | if (WARN_ON(pgd_phys & ~kvm_vttbr_baddr_mask(kvm))) | |
1025 | return -EINVAL; | |
1026 | ||
d5d8184d | 1027 | kvm->arch.pgd = pgd; |
e329fb75 | 1028 | kvm->arch.pgd_phys = pgd_phys; |
d5d8184d CD |
1029 | return 0; |
1030 | } | |
1031 | ||
957db105 CD |
1032 | static void stage2_unmap_memslot(struct kvm *kvm, |
1033 | struct kvm_memory_slot *memslot) | |
1034 | { | |
1035 | hva_t hva = memslot->userspace_addr; | |
1036 | phys_addr_t addr = memslot->base_gfn << PAGE_SHIFT; | |
1037 | phys_addr_t size = PAGE_SIZE * memslot->npages; | |
1038 | hva_t reg_end = hva + size; | |
1039 | ||
1040 | /* | |
1041 | * A memory region could potentially cover multiple VMAs, and any holes | |
1042 | * between them, so iterate over all of them to find out if we should | |
1043 | * unmap any of them. | |
1044 | * | |
1045 | * +--------------------------------------------+ | |
1046 | * +---------------+----------------+ +----------------+ | |
1047 | * | : VMA 1 | VMA 2 | | VMA 3 : | | |
1048 | * +---------------+----------------+ +----------------+ | |
1049 | * | memory region | | |
1050 | * +--------------------------------------------+ | |
1051 | */ | |
1052 | do { | |
1053 | struct vm_area_struct *vma = find_vma(current->mm, hva); | |
1054 | hva_t vm_start, vm_end; | |
1055 | ||
1056 | if (!vma || vma->vm_start >= reg_end) | |
1057 | break; | |
1058 | ||
1059 | /* | |
1060 | * Take the intersection of this VMA with the memory region | |
1061 | */ | |
1062 | vm_start = max(hva, vma->vm_start); | |
1063 | vm_end = min(reg_end, vma->vm_end); | |
1064 | ||
1065 | if (!(vma->vm_flags & VM_PFNMAP)) { | |
1066 | gpa_t gpa = addr + (vm_start - memslot->userspace_addr); | |
1067 | unmap_stage2_range(kvm, gpa, vm_end - vm_start); | |
1068 | } | |
1069 | hva = vm_end; | |
1070 | } while (hva < reg_end); | |
1071 | } | |
1072 | ||
1073 | /** | |
1074 | * stage2_unmap_vm - Unmap Stage-2 RAM mappings | |
1075 | * @kvm: The struct kvm pointer | |
1076 | * | |
656012c7 | 1077 | * Go through the memregions and unmap any regular RAM |
957db105 CD |
1078 | * backing memory already mapped to the VM. |
1079 | */ | |
1080 | void stage2_unmap_vm(struct kvm *kvm) | |
1081 | { | |
1082 | struct kvm_memslots *slots; | |
1083 | struct kvm_memory_slot *memslot; | |
1084 | int idx; | |
1085 | ||
1086 | idx = srcu_read_lock(&kvm->srcu); | |
89154dd5 | 1087 | mmap_read_lock(current->mm); |
957db105 CD |
1088 | spin_lock(&kvm->mmu_lock); |
1089 | ||
1090 | slots = kvm_memslots(kvm); | |
1091 | kvm_for_each_memslot(memslot, slots) | |
1092 | stage2_unmap_memslot(kvm, memslot); | |
1093 | ||
1094 | spin_unlock(&kvm->mmu_lock); | |
89154dd5 | 1095 | mmap_read_unlock(current->mm); |
957db105 CD |
1096 | srcu_read_unlock(&kvm->srcu, idx); |
1097 | } | |
1098 | ||
d5d8184d CD |
1099 | /** |
1100 | * kvm_free_stage2_pgd - free all stage-2 tables | |
1101 | * @kvm: The KVM struct pointer for the VM. | |
1102 | * | |
1103 | * Walks the level-1 page table pointed to by kvm->arch.pgd and frees all | |
1104 | * underlying level-2 and level-3 tables before freeing the actual level-1 table | |
1105 | * and setting the struct pointer to NULL. | |
d5d8184d CD |
1106 | */ |
1107 | void kvm_free_stage2_pgd(struct kvm *kvm) | |
1108 | { | |
6c0d706b | 1109 | void *pgd = NULL; |
d5d8184d | 1110 | |
8b3405e3 | 1111 | spin_lock(&kvm->mmu_lock); |
6c0d706b | 1112 | if (kvm->arch.pgd) { |
e55cac5b | 1113 | unmap_stage2_range(kvm, 0, kvm_phys_size(kvm)); |
2952a607 | 1114 | pgd = READ_ONCE(kvm->arch.pgd); |
6c0d706b | 1115 | kvm->arch.pgd = NULL; |
e329fb75 | 1116 | kvm->arch.pgd_phys = 0; |
6c0d706b | 1117 | } |
8b3405e3 SP |
1118 | spin_unlock(&kvm->mmu_lock); |
1119 | ||
9163ee23 | 1120 | /* Free the HW pgd, one page at a time */ |
6c0d706b | 1121 | if (pgd) |
e55cac5b | 1122 | free_pages_exact(pgd, stage2_pgd_size(kvm)); |
d5d8184d CD |
1123 | } |
1124 | ||
e9f63768 | 1125 | static p4d_t *stage2_get_p4d(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, |
ad361f09 | 1126 | phys_addr_t addr) |
d5d8184d CD |
1127 | { |
1128 | pgd_t *pgd; | |
e9f63768 | 1129 | p4d_t *p4d; |
d5d8184d | 1130 | |
e55cac5b SP |
1131 | pgd = kvm->arch.pgd + stage2_pgd_index(kvm, addr); |
1132 | if (stage2_pgd_none(kvm, *pgd)) { | |
38f791a4 CD |
1133 | if (!cache) |
1134 | return NULL; | |
e9f63768 MR |
1135 | p4d = mmu_memory_cache_alloc(cache); |
1136 | stage2_pgd_populate(kvm, pgd, p4d); | |
38f791a4 CD |
1137 | get_page(virt_to_page(pgd)); |
1138 | } | |
1139 | ||
e9f63768 MR |
1140 | return stage2_p4d_offset(kvm, pgd, addr); |
1141 | } | |
1142 | ||
1143 | static pud_t *stage2_get_pud(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, | |
1144 | phys_addr_t addr) | |
1145 | { | |
1146 | p4d_t *p4d; | |
1147 | pud_t *pud; | |
1148 | ||
1149 | p4d = stage2_get_p4d(kvm, cache, addr); | |
1150 | if (stage2_p4d_none(kvm, *p4d)) { | |
1151 | if (!cache) | |
1152 | return NULL; | |
1153 | pud = mmu_memory_cache_alloc(cache); | |
1154 | stage2_p4d_populate(kvm, p4d, pud); | |
1155 | get_page(virt_to_page(p4d)); | |
1156 | } | |
1157 | ||
1158 | return stage2_pud_offset(kvm, p4d, addr); | |
38f791a4 CD |
1159 | } |
1160 | ||
1161 | static pmd_t *stage2_get_pmd(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, | |
1162 | phys_addr_t addr) | |
1163 | { | |
1164 | pud_t *pud; | |
1165 | pmd_t *pmd; | |
1166 | ||
1167 | pud = stage2_get_pud(kvm, cache, addr); | |
b8e0ba7c | 1168 | if (!pud || stage2_pud_huge(kvm, *pud)) |
d6dbdd3c MZ |
1169 | return NULL; |
1170 | ||
e55cac5b | 1171 | if (stage2_pud_none(kvm, *pud)) { |
d5d8184d | 1172 | if (!cache) |
ad361f09 | 1173 | return NULL; |
d5d8184d | 1174 | pmd = mmu_memory_cache_alloc(cache); |
e55cac5b | 1175 | stage2_pud_populate(kvm, pud, pmd); |
d5d8184d | 1176 | get_page(virt_to_page(pud)); |
c62ee2b2 MZ |
1177 | } |
1178 | ||
e55cac5b | 1179 | return stage2_pmd_offset(kvm, pud, addr); |
ad361f09 CD |
1180 | } |
1181 | ||
1182 | static int stage2_set_pmd_huge(struct kvm *kvm, struct kvm_mmu_memory_cache | |
1183 | *cache, phys_addr_t addr, const pmd_t *new_pmd) | |
1184 | { | |
1185 | pmd_t *pmd, old_pmd; | |
1186 | ||
3c3736cd | 1187 | retry: |
ad361f09 CD |
1188 | pmd = stage2_get_pmd(kvm, cache, addr); |
1189 | VM_BUG_ON(!pmd); | |
d5d8184d | 1190 | |
ad361f09 | 1191 | old_pmd = *pmd; |
3c3736cd SP |
1192 | /* |
1193 | * Multiple vcpus faulting on the same PMD entry, can | |
1194 | * lead to them sequentially updating the PMD with the | |
1195 | * same value. Following the break-before-make | |
1196 | * (pmd_clear() followed by tlb_flush()) process can | |
1197 | * hinder forward progress due to refaults generated | |
1198 | * on missing translations. | |
1199 | * | |
1200 | * Skip updating the page table if the entry is | |
1201 | * unchanged. | |
1202 | */ | |
1203 | if (pmd_val(old_pmd) == pmd_val(*new_pmd)) | |
1204 | return 0; | |
1205 | ||
d4b9e079 | 1206 | if (pmd_present(old_pmd)) { |
86658b81 | 1207 | /* |
3c3736cd SP |
1208 | * If we already have PTE level mapping for this block, |
1209 | * we must unmap it to avoid inconsistent TLB state and | |
1210 | * leaking the table page. We could end up in this situation | |
1211 | * if the memory slot was marked for dirty logging and was | |
1212 | * reverted, leaving PTE level mappings for the pages accessed | |
1213 | * during the period. So, unmap the PTE level mapping for this | |
1214 | * block and retry, as we could have released the upper level | |
1215 | * table in the process. | |
86658b81 | 1216 | * |
3c3736cd SP |
1217 | * Normal THP split/merge follows mmu_notifier callbacks and do |
1218 | * get handled accordingly. | |
86658b81 | 1219 | */ |
3c3736cd SP |
1220 | if (!pmd_thp_or_huge(old_pmd)) { |
1221 | unmap_stage2_range(kvm, addr & S2_PMD_MASK, S2_PMD_SIZE); | |
1222 | goto retry; | |
1223 | } | |
86658b81 PA |
1224 | /* |
1225 | * Mapping in huge pages should only happen through a | |
1226 | * fault. If a page is merged into a transparent huge | |
1227 | * page, the individual subpages of that huge page | |
1228 | * should be unmapped through MMU notifiers before we | |
1229 | * get here. | |
1230 | * | |
1231 | * Merging of CompoundPages is not supported; they | |
1232 | * should become splitting first, unmapped, merged, | |
1233 | * and mapped back in on-demand. | |
1234 | */ | |
3c3736cd | 1235 | WARN_ON_ONCE(pmd_pfn(old_pmd) != pmd_pfn(*new_pmd)); |
d4b9e079 | 1236 | pmd_clear(pmd); |
ad361f09 | 1237 | kvm_tlb_flush_vmid_ipa(kvm, addr); |
d4b9e079 | 1238 | } else { |
ad361f09 | 1239 | get_page(virt_to_page(pmd)); |
d4b9e079 MZ |
1240 | } |
1241 | ||
1242 | kvm_set_pmd(pmd, *new_pmd); | |
ad361f09 CD |
1243 | return 0; |
1244 | } | |
1245 | ||
b8e0ba7c PA |
1246 | static int stage2_set_pud_huge(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, |
1247 | phys_addr_t addr, const pud_t *new_pudp) | |
1248 | { | |
1249 | pud_t *pudp, old_pud; | |
1250 | ||
3c3736cd | 1251 | retry: |
b8e0ba7c PA |
1252 | pudp = stage2_get_pud(kvm, cache, addr); |
1253 | VM_BUG_ON(!pudp); | |
1254 | ||
1255 | old_pud = *pudp; | |
1256 | ||
1257 | /* | |
1258 | * A large number of vcpus faulting on the same stage 2 entry, | |
3c3736cd SP |
1259 | * can lead to a refault due to the stage2_pud_clear()/tlb_flush(). |
1260 | * Skip updating the page tables if there is no change. | |
b8e0ba7c PA |
1261 | */ |
1262 | if (pud_val(old_pud) == pud_val(*new_pudp)) | |
1263 | return 0; | |
1264 | ||
1265 | if (stage2_pud_present(kvm, old_pud)) { | |
3c3736cd SP |
1266 | /* |
1267 | * If we already have table level mapping for this block, unmap | |
1268 | * the range for this block and retry. | |
1269 | */ | |
1270 | if (!stage2_pud_huge(kvm, old_pud)) { | |
1271 | unmap_stage2_range(kvm, addr & S2_PUD_MASK, S2_PUD_SIZE); | |
1272 | goto retry; | |
1273 | } | |
1274 | ||
1275 | WARN_ON_ONCE(kvm_pud_pfn(old_pud) != kvm_pud_pfn(*new_pudp)); | |
b8e0ba7c PA |
1276 | stage2_pud_clear(kvm, pudp); |
1277 | kvm_tlb_flush_vmid_ipa(kvm, addr); | |
1278 | } else { | |
1279 | get_page(virt_to_page(pudp)); | |
1280 | } | |
1281 | ||
1282 | kvm_set_pud(pudp, *new_pudp); | |
1283 | return 0; | |
1284 | } | |
1285 | ||
86d1c55e PA |
1286 | /* |
1287 | * stage2_get_leaf_entry - walk the stage2 VM page tables and return | |
1288 | * true if a valid and present leaf-entry is found. A pointer to the | |
1289 | * leaf-entry is returned in the appropriate level variable - pudpp, | |
1290 | * pmdpp, ptepp. | |
1291 | */ | |
1292 | static bool stage2_get_leaf_entry(struct kvm *kvm, phys_addr_t addr, | |
1293 | pud_t **pudpp, pmd_t **pmdpp, pte_t **ptepp) | |
7a3796d2 | 1294 | { |
86d1c55e | 1295 | pud_t *pudp; |
7a3796d2 MZ |
1296 | pmd_t *pmdp; |
1297 | pte_t *ptep; | |
1298 | ||
86d1c55e PA |
1299 | *pudpp = NULL; |
1300 | *pmdpp = NULL; | |
1301 | *ptepp = NULL; | |
1302 | ||
1303 | pudp = stage2_get_pud(kvm, NULL, addr); | |
1304 | if (!pudp || stage2_pud_none(kvm, *pudp) || !stage2_pud_present(kvm, *pudp)) | |
1305 | return false; | |
1306 | ||
1307 | if (stage2_pud_huge(kvm, *pudp)) { | |
1308 | *pudpp = pudp; | |
1309 | return true; | |
1310 | } | |
1311 | ||
1312 | pmdp = stage2_pmd_offset(kvm, pudp, addr); | |
7a3796d2 MZ |
1313 | if (!pmdp || pmd_none(*pmdp) || !pmd_present(*pmdp)) |
1314 | return false; | |
1315 | ||
86d1c55e PA |
1316 | if (pmd_thp_or_huge(*pmdp)) { |
1317 | *pmdpp = pmdp; | |
1318 | return true; | |
1319 | } | |
7a3796d2 MZ |
1320 | |
1321 | ptep = pte_offset_kernel(pmdp, addr); | |
1322 | if (!ptep || pte_none(*ptep) || !pte_present(*ptep)) | |
1323 | return false; | |
1324 | ||
86d1c55e PA |
1325 | *ptepp = ptep; |
1326 | return true; | |
1327 | } | |
1328 | ||
1329 | static bool stage2_is_exec(struct kvm *kvm, phys_addr_t addr) | |
1330 | { | |
1331 | pud_t *pudp; | |
1332 | pmd_t *pmdp; | |
1333 | pte_t *ptep; | |
1334 | bool found; | |
1335 | ||
1336 | found = stage2_get_leaf_entry(kvm, addr, &pudp, &pmdp, &ptep); | |
1337 | if (!found) | |
1338 | return false; | |
1339 | ||
1340 | if (pudp) | |
1341 | return kvm_s2pud_exec(pudp); | |
1342 | else if (pmdp) | |
1343 | return kvm_s2pmd_exec(pmdp); | |
1344 | else | |
1345 | return kvm_s2pte_exec(ptep); | |
7a3796d2 MZ |
1346 | } |
1347 | ||
ad361f09 | 1348 | static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, |
15a49a44 MS |
1349 | phys_addr_t addr, const pte_t *new_pte, |
1350 | unsigned long flags) | |
ad361f09 | 1351 | { |
b8e0ba7c | 1352 | pud_t *pud; |
ad361f09 CD |
1353 | pmd_t *pmd; |
1354 | pte_t *pte, old_pte; | |
15a49a44 MS |
1355 | bool iomap = flags & KVM_S2PTE_FLAG_IS_IOMAP; |
1356 | bool logging_active = flags & KVM_S2_FLAG_LOGGING_ACTIVE; | |
1357 | ||
1358 | VM_BUG_ON(logging_active && !cache); | |
ad361f09 | 1359 | |
38f791a4 | 1360 | /* Create stage-2 page table mapping - Levels 0 and 1 */ |
b8e0ba7c PA |
1361 | pud = stage2_get_pud(kvm, cache, addr); |
1362 | if (!pud) { | |
1363 | /* | |
1364 | * Ignore calls from kvm_set_spte_hva for unallocated | |
1365 | * address ranges. | |
1366 | */ | |
1367 | return 0; | |
1368 | } | |
1369 | ||
1370 | /* | |
1371 | * While dirty page logging - dissolve huge PUD, then continue | |
1372 | * on to allocate page. | |
1373 | */ | |
1374 | if (logging_active) | |
1375 | stage2_dissolve_pud(kvm, addr, pud); | |
1376 | ||
1377 | if (stage2_pud_none(kvm, *pud)) { | |
1378 | if (!cache) | |
1379 | return 0; /* ignore calls from kvm_set_spte_hva */ | |
1380 | pmd = mmu_memory_cache_alloc(cache); | |
1381 | stage2_pud_populate(kvm, pud, pmd); | |
1382 | get_page(virt_to_page(pud)); | |
1383 | } | |
1384 | ||
1385 | pmd = stage2_pmd_offset(kvm, pud, addr); | |
ad361f09 CD |
1386 | if (!pmd) { |
1387 | /* | |
1388 | * Ignore calls from kvm_set_spte_hva for unallocated | |
1389 | * address ranges. | |
1390 | */ | |
1391 | return 0; | |
1392 | } | |
1393 | ||
15a49a44 MS |
1394 | /* |
1395 | * While dirty page logging - dissolve huge PMD, then continue on to | |
1396 | * allocate page. | |
1397 | */ | |
1398 | if (logging_active) | |
1399 | stage2_dissolve_pmd(kvm, addr, pmd); | |
1400 | ||
ad361f09 | 1401 | /* Create stage-2 page mappings - Level 2 */ |
d5d8184d CD |
1402 | if (pmd_none(*pmd)) { |
1403 | if (!cache) | |
1404 | return 0; /* ignore calls from kvm_set_spte_hva */ | |
1405 | pte = mmu_memory_cache_alloc(cache); | |
0db9dd8a | 1406 | kvm_pmd_populate(pmd, pte); |
d5d8184d | 1407 | get_page(virt_to_page(pmd)); |
c62ee2b2 MZ |
1408 | } |
1409 | ||
1410 | pte = pte_offset_kernel(pmd, addr); | |
d5d8184d CD |
1411 | |
1412 | if (iomap && pte_present(*pte)) | |
1413 | return -EFAULT; | |
1414 | ||
1415 | /* Create 2nd stage page table mapping - Level 3 */ | |
1416 | old_pte = *pte; | |
d4b9e079 | 1417 | if (pte_present(old_pte)) { |
976d34e2 PA |
1418 | /* Skip page table update if there is no change */ |
1419 | if (pte_val(old_pte) == pte_val(*new_pte)) | |
1420 | return 0; | |
1421 | ||
d4b9e079 | 1422 | kvm_set_pte(pte, __pte(0)); |
48762767 | 1423 | kvm_tlb_flush_vmid_ipa(kvm, addr); |
d4b9e079 | 1424 | } else { |
d5d8184d | 1425 | get_page(virt_to_page(pte)); |
d4b9e079 | 1426 | } |
d5d8184d | 1427 | |
d4b9e079 | 1428 | kvm_set_pte(pte, *new_pte); |
d5d8184d CD |
1429 | return 0; |
1430 | } | |
d5d8184d | 1431 | |
06485053 CM |
1432 | #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
1433 | static int stage2_ptep_test_and_clear_young(pte_t *pte) | |
1434 | { | |
1435 | if (pte_young(*pte)) { | |
1436 | *pte = pte_mkold(*pte); | |
1437 | return 1; | |
1438 | } | |
d5d8184d CD |
1439 | return 0; |
1440 | } | |
06485053 CM |
1441 | #else |
1442 | static int stage2_ptep_test_and_clear_young(pte_t *pte) | |
1443 | { | |
1444 | return __ptep_test_and_clear_young(pte); | |
1445 | } | |
1446 | #endif | |
1447 | ||
1448 | static int stage2_pmdp_test_and_clear_young(pmd_t *pmd) | |
1449 | { | |
1450 | return stage2_ptep_test_and_clear_young((pte_t *)pmd); | |
1451 | } | |
d5d8184d | 1452 | |
35a63966 PA |
1453 | static int stage2_pudp_test_and_clear_young(pud_t *pud) |
1454 | { | |
1455 | return stage2_ptep_test_and_clear_young((pte_t *)pud); | |
1456 | } | |
1457 | ||
d5d8184d CD |
1458 | /** |
1459 | * kvm_phys_addr_ioremap - map a device range to guest IPA | |
1460 | * | |
1461 | * @kvm: The KVM pointer | |
1462 | * @guest_ipa: The IPA at which to insert the mapping | |
1463 | * @pa: The physical address of the device | |
1464 | * @size: The size of the mapping | |
1465 | */ | |
1466 | int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, | |
c40f2f8f | 1467 | phys_addr_t pa, unsigned long size, bool writable) |
d5d8184d CD |
1468 | { |
1469 | phys_addr_t addr, end; | |
1470 | int ret = 0; | |
1471 | unsigned long pfn; | |
1472 | struct kvm_mmu_memory_cache cache = { 0, }; | |
1473 | ||
1474 | end = (guest_ipa + size + PAGE_SIZE - 1) & PAGE_MASK; | |
1475 | pfn = __phys_to_pfn(pa); | |
1476 | ||
1477 | for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) { | |
f8df7338 | 1478 | pte_t pte = kvm_pfn_pte(pfn, PAGE_S2_DEVICE); |
d5d8184d | 1479 | |
c40f2f8f | 1480 | if (writable) |
06485053 | 1481 | pte = kvm_s2pte_mkwrite(pte); |
c40f2f8f | 1482 | |
e55cac5b SP |
1483 | ret = mmu_topup_memory_cache(&cache, |
1484 | kvm_mmu_cache_min_pages(kvm), | |
1485 | KVM_NR_MEM_OBJS); | |
d5d8184d CD |
1486 | if (ret) |
1487 | goto out; | |
1488 | spin_lock(&kvm->mmu_lock); | |
15a49a44 MS |
1489 | ret = stage2_set_pte(kvm, &cache, addr, &pte, |
1490 | KVM_S2PTE_FLAG_IS_IOMAP); | |
d5d8184d CD |
1491 | spin_unlock(&kvm->mmu_lock); |
1492 | if (ret) | |
1493 | goto out; | |
1494 | ||
1495 | pfn++; | |
1496 | } | |
1497 | ||
1498 | out: | |
1499 | mmu_free_memory_cache(&cache); | |
1500 | return ret; | |
1501 | } | |
1502 | ||
c6473555 MS |
1503 | /** |
1504 | * stage2_wp_ptes - write protect PMD range | |
1505 | * @pmd: pointer to pmd entry | |
1506 | * @addr: range start address | |
1507 | * @end: range end address | |
1508 | */ | |
1509 | static void stage2_wp_ptes(pmd_t *pmd, phys_addr_t addr, phys_addr_t end) | |
1510 | { | |
1511 | pte_t *pte; | |
1512 | ||
1513 | pte = pte_offset_kernel(pmd, addr); | |
1514 | do { | |
1515 | if (!pte_none(*pte)) { | |
1516 | if (!kvm_s2pte_readonly(pte)) | |
1517 | kvm_set_s2pte_readonly(pte); | |
1518 | } | |
1519 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
1520 | } | |
1521 | ||
1522 | /** | |
1523 | * stage2_wp_pmds - write protect PUD range | |
e55cac5b | 1524 | * kvm: kvm instance for the VM |
c6473555 MS |
1525 | * @pud: pointer to pud entry |
1526 | * @addr: range start address | |
1527 | * @end: range end address | |
1528 | */ | |
e55cac5b SP |
1529 | static void stage2_wp_pmds(struct kvm *kvm, pud_t *pud, |
1530 | phys_addr_t addr, phys_addr_t end) | |
c6473555 MS |
1531 | { |
1532 | pmd_t *pmd; | |
1533 | phys_addr_t next; | |
1534 | ||
e55cac5b | 1535 | pmd = stage2_pmd_offset(kvm, pud, addr); |
c6473555 MS |
1536 | |
1537 | do { | |
e55cac5b | 1538 | next = stage2_pmd_addr_end(kvm, addr, end); |
c6473555 | 1539 | if (!pmd_none(*pmd)) { |
bbb3b6b3 | 1540 | if (pmd_thp_or_huge(*pmd)) { |
c6473555 MS |
1541 | if (!kvm_s2pmd_readonly(pmd)) |
1542 | kvm_set_s2pmd_readonly(pmd); | |
1543 | } else { | |
1544 | stage2_wp_ptes(pmd, addr, next); | |
1545 | } | |
1546 | } | |
1547 | } while (pmd++, addr = next, addr != end); | |
1548 | } | |
1549 | ||
1550 | /** | |
e9f63768 | 1551 | * stage2_wp_puds - write protect P4D range |
8324c3d5 ZY |
1552 | * @pgd: pointer to pgd entry |
1553 | * @addr: range start address | |
1554 | * @end: range end address | |
1555 | */ | |
e9f63768 | 1556 | static void stage2_wp_puds(struct kvm *kvm, p4d_t *p4d, |
e55cac5b | 1557 | phys_addr_t addr, phys_addr_t end) |
c6473555 MS |
1558 | { |
1559 | pud_t *pud; | |
1560 | phys_addr_t next; | |
1561 | ||
e9f63768 | 1562 | pud = stage2_pud_offset(kvm, p4d, addr); |
c6473555 | 1563 | do { |
e55cac5b SP |
1564 | next = stage2_pud_addr_end(kvm, addr, end); |
1565 | if (!stage2_pud_none(kvm, *pud)) { | |
4ea5af53 PA |
1566 | if (stage2_pud_huge(kvm, *pud)) { |
1567 | if (!kvm_s2pud_readonly(pud)) | |
1568 | kvm_set_s2pud_readonly(pud); | |
1569 | } else { | |
1570 | stage2_wp_pmds(kvm, pud, addr, next); | |
1571 | } | |
c6473555 MS |
1572 | } |
1573 | } while (pud++, addr = next, addr != end); | |
1574 | } | |
1575 | ||
e9f63768 MR |
1576 | /** |
1577 | * stage2_wp_p4ds - write protect PGD range | |
1578 | * @pgd: pointer to pgd entry | |
1579 | * @addr: range start address | |
1580 | * @end: range end address | |
1581 | */ | |
1582 | static void stage2_wp_p4ds(struct kvm *kvm, pgd_t *pgd, | |
1583 | phys_addr_t addr, phys_addr_t end) | |
1584 | { | |
1585 | p4d_t *p4d; | |
1586 | phys_addr_t next; | |
1587 | ||
1588 | p4d = stage2_p4d_offset(kvm, pgd, addr); | |
1589 | do { | |
1590 | next = stage2_p4d_addr_end(kvm, addr, end); | |
1591 | if (!stage2_p4d_none(kvm, *p4d)) | |
1592 | stage2_wp_puds(kvm, p4d, addr, next); | |
1593 | } while (p4d++, addr = next, addr != end); | |
1594 | } | |
1595 | ||
c6473555 MS |
1596 | /** |
1597 | * stage2_wp_range() - write protect stage2 memory region range | |
1598 | * @kvm: The KVM pointer | |
1599 | * @addr: Start address of range | |
1600 | * @end: End address of range | |
1601 | */ | |
1602 | static void stage2_wp_range(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) | |
1603 | { | |
1604 | pgd_t *pgd; | |
1605 | phys_addr_t next; | |
1606 | ||
e55cac5b | 1607 | pgd = kvm->arch.pgd + stage2_pgd_index(kvm, addr); |
c6473555 MS |
1608 | do { |
1609 | /* | |
1610 | * Release kvm_mmu_lock periodically if the memory region is | |
1611 | * large. Otherwise, we may see kernel panics with | |
227ea818 CD |
1612 | * CONFIG_DETECT_HUNG_TASK, CONFIG_LOCKUP_DETECTOR, |
1613 | * CONFIG_LOCKDEP. Additionally, holding the lock too long | |
0c428a6a SP |
1614 | * will also starve other vCPUs. We have to also make sure |
1615 | * that the page tables are not freed while we released | |
1616 | * the lock. | |
c6473555 | 1617 | */ |
0c428a6a SP |
1618 | cond_resched_lock(&kvm->mmu_lock); |
1619 | if (!READ_ONCE(kvm->arch.pgd)) | |
1620 | break; | |
e55cac5b SP |
1621 | next = stage2_pgd_addr_end(kvm, addr, end); |
1622 | if (stage2_pgd_present(kvm, *pgd)) | |
e9f63768 | 1623 | stage2_wp_p4ds(kvm, pgd, addr, next); |
c6473555 MS |
1624 | } while (pgd++, addr = next, addr != end); |
1625 | } | |
1626 | ||
1627 | /** | |
1628 | * kvm_mmu_wp_memory_region() - write protect stage 2 entries for memory slot | |
1629 | * @kvm: The KVM pointer | |
1630 | * @slot: The memory slot to write protect | |
1631 | * | |
1632 | * Called to start logging dirty pages after memory region | |
1633 | * KVM_MEM_LOG_DIRTY_PAGES operation is called. After this function returns | |
4ea5af53 | 1634 | * all present PUD, PMD and PTEs are write protected in the memory region. |
c6473555 MS |
1635 | * Afterwards read of dirty page log can be called. |
1636 | * | |
1637 | * Acquires kvm_mmu_lock. Called with kvm->slots_lock mutex acquired, | |
1638 | * serializing operations for VM memory regions. | |
1639 | */ | |
1640 | void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot) | |
1641 | { | |
9f6b8029 PB |
1642 | struct kvm_memslots *slots = kvm_memslots(kvm); |
1643 | struct kvm_memory_slot *memslot = id_to_memslot(slots, slot); | |
0577d1ab SC |
1644 | phys_addr_t start, end; |
1645 | ||
1646 | if (WARN_ON_ONCE(!memslot)) | |
1647 | return; | |
1648 | ||
1649 | start = memslot->base_gfn << PAGE_SHIFT; | |
1650 | end = (memslot->base_gfn + memslot->npages) << PAGE_SHIFT; | |
c6473555 MS |
1651 | |
1652 | spin_lock(&kvm->mmu_lock); | |
1653 | stage2_wp_range(kvm, start, end); | |
1654 | spin_unlock(&kvm->mmu_lock); | |
1655 | kvm_flush_remote_tlbs(kvm); | |
1656 | } | |
53c810c3 MS |
1657 | |
1658 | /** | |
3b0f1d01 | 1659 | * kvm_mmu_write_protect_pt_masked() - write protect dirty pages |
53c810c3 MS |
1660 | * @kvm: The KVM pointer |
1661 | * @slot: The memory slot associated with mask | |
1662 | * @gfn_offset: The gfn offset in memory slot | |
1663 | * @mask: The mask of dirty pages at offset 'gfn_offset' in this memory | |
1664 | * slot to be write protected | |
1665 | * | |
1666 | * Walks bits set in mask write protects the associated pte's. Caller must | |
1667 | * acquire kvm_mmu_lock. | |
1668 | */ | |
3b0f1d01 | 1669 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
53c810c3 MS |
1670 | struct kvm_memory_slot *slot, |
1671 | gfn_t gfn_offset, unsigned long mask) | |
1672 | { | |
1673 | phys_addr_t base_gfn = slot->base_gfn + gfn_offset; | |
1674 | phys_addr_t start = (base_gfn + __ffs(mask)) << PAGE_SHIFT; | |
1675 | phys_addr_t end = (base_gfn + __fls(mask) + 1) << PAGE_SHIFT; | |
1676 | ||
1677 | stage2_wp_range(kvm, start, end); | |
1678 | } | |
c6473555 | 1679 | |
3b0f1d01 KH |
1680 | /* |
1681 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1682 | * dirty pages. | |
1683 | * | |
1684 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1685 | * enable dirty logging for them. | |
1686 | */ | |
1687 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1688 | struct kvm_memory_slot *slot, | |
1689 | gfn_t gfn_offset, unsigned long mask) | |
1690 | { | |
1691 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
1692 | } | |
1693 | ||
17ab9d57 | 1694 | static void clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size) |
0d3e4d4f | 1695 | { |
17ab9d57 | 1696 | __clean_dcache_guest_page(pfn, size); |
a15f6939 MZ |
1697 | } |
1698 | ||
17ab9d57 | 1699 | static void invalidate_icache_guest_page(kvm_pfn_t pfn, unsigned long size) |
a15f6939 | 1700 | { |
17ab9d57 | 1701 | __invalidate_icache_guest_page(pfn, size); |
0d3e4d4f MZ |
1702 | } |
1703 | ||
1559b758 | 1704 | static void kvm_send_hwpoison_signal(unsigned long address, short lsb) |
196f878a | 1705 | { |
795a8371 | 1706 | send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, lsb, current); |
196f878a JM |
1707 | } |
1708 | ||
a80868f3 SP |
1709 | static bool fault_supports_stage2_huge_mapping(struct kvm_memory_slot *memslot, |
1710 | unsigned long hva, | |
1711 | unsigned long map_size) | |
6794ad54 | 1712 | { |
c2be79a0 | 1713 | gpa_t gpa_start; |
6794ad54 CD |
1714 | hva_t uaddr_start, uaddr_end; |
1715 | size_t size; | |
1716 | ||
9f283614 SP |
1717 | /* The memslot and the VMA are guaranteed to be aligned to PAGE_SIZE */ |
1718 | if (map_size == PAGE_SIZE) | |
1719 | return true; | |
1720 | ||
6794ad54 CD |
1721 | size = memslot->npages * PAGE_SIZE; |
1722 | ||
1723 | gpa_start = memslot->base_gfn << PAGE_SHIFT; | |
6794ad54 CD |
1724 | |
1725 | uaddr_start = memslot->userspace_addr; | |
1726 | uaddr_end = uaddr_start + size; | |
1727 | ||
1728 | /* | |
1729 | * Pages belonging to memslots that don't have the same alignment | |
a80868f3 SP |
1730 | * within a PMD/PUD for userspace and IPA cannot be mapped with stage-2 |
1731 | * PMD/PUD entries, because we'll end up mapping the wrong pages. | |
6794ad54 CD |
1732 | * |
1733 | * Consider a layout like the following: | |
1734 | * | |
1735 | * memslot->userspace_addr: | |
1736 | * +-----+--------------------+--------------------+---+ | |
a80868f3 | 1737 | * |abcde|fgh Stage-1 block | Stage-1 block tv|xyz| |
6794ad54 CD |
1738 | * +-----+--------------------+--------------------+---+ |
1739 | * | |
9f283614 | 1740 | * memslot->base_gfn << PAGE_SHIFT: |
6794ad54 | 1741 | * +---+--------------------+--------------------+-----+ |
a80868f3 | 1742 | * |abc|def Stage-2 block | Stage-2 block |tvxyz| |
6794ad54 CD |
1743 | * +---+--------------------+--------------------+-----+ |
1744 | * | |
a80868f3 | 1745 | * If we create those stage-2 blocks, we'll end up with this incorrect |
6794ad54 CD |
1746 | * mapping: |
1747 | * d -> f | |
1748 | * e -> g | |
1749 | * f -> h | |
1750 | */ | |
a80868f3 | 1751 | if ((gpa_start & (map_size - 1)) != (uaddr_start & (map_size - 1))) |
6794ad54 CD |
1752 | return false; |
1753 | ||
1754 | /* | |
1755 | * Next, let's make sure we're not trying to map anything not covered | |
a80868f3 SP |
1756 | * by the memslot. This means we have to prohibit block size mappings |
1757 | * for the beginning and end of a non-block aligned and non-block sized | |
6794ad54 CD |
1758 | * memory slot (illustrated by the head and tail parts of the |
1759 | * userspace view above containing pages 'abcde' and 'xyz', | |
1760 | * respectively). | |
1761 | * | |
1762 | * Note that it doesn't matter if we do the check using the | |
1763 | * userspace_addr or the base_gfn, as both are equally aligned (per | |
1764 | * the check above) and equally sized. | |
1765 | */ | |
a80868f3 SP |
1766 | return (hva & ~(map_size - 1)) >= uaddr_start && |
1767 | (hva & ~(map_size - 1)) + map_size <= uaddr_end; | |
6794ad54 CD |
1768 | } |
1769 | ||
0529c902 SP |
1770 | /* |
1771 | * Check if the given hva is backed by a transparent huge page (THP) and | |
1772 | * whether it can be mapped using block mapping in stage2. If so, adjust | |
1773 | * the stage2 PFN and IPA accordingly. Only PMD_SIZE THPs are currently | |
1774 | * supported. This will need to be updated to support other THP sizes. | |
1775 | * | |
1776 | * Returns the size of the mapping. | |
1777 | */ | |
1778 | static unsigned long | |
1779 | transparent_hugepage_adjust(struct kvm_memory_slot *memslot, | |
1780 | unsigned long hva, kvm_pfn_t *pfnp, | |
1781 | phys_addr_t *ipap) | |
1782 | { | |
1783 | kvm_pfn_t pfn = *pfnp; | |
1784 | ||
1785 | /* | |
1786 | * Make sure the adjustment is done only for THP pages. Also make | |
1787 | * sure that the HVA and IPA are sufficiently aligned and that the | |
1788 | * block map is contained within the memslot. | |
1789 | */ | |
1790 | if (kvm_is_transparent_hugepage(pfn) && | |
1791 | fault_supports_stage2_huge_mapping(memslot, hva, PMD_SIZE)) { | |
1792 | /* | |
1793 | * The address we faulted on is backed by a transparent huge | |
1794 | * page. However, because we map the compound huge page and | |
1795 | * not the individual tail page, we need to transfer the | |
1796 | * refcount to the head page. We have to be careful that the | |
1797 | * THP doesn't start to split while we are adjusting the | |
1798 | * refcounts. | |
1799 | * | |
1800 | * We are sure this doesn't happen, because mmu_notifier_retry | |
1801 | * was successful and we are holding the mmu_lock, so if this | |
1802 | * THP is trying to split, it will be blocked in the mmu | |
1803 | * notifier before touching any of the pages, specifically | |
1804 | * before being able to call __split_huge_page_refcount(). | |
1805 | * | |
1806 | * We can therefore safely transfer the refcount from PG_tail | |
1807 | * to PG_head and switch the pfn from a tail page to the head | |
1808 | * page accordingly. | |
1809 | */ | |
1810 | *ipap &= PMD_MASK; | |
1811 | kvm_release_pfn_clean(pfn); | |
1812 | pfn &= ~(PTRS_PER_PMD - 1); | |
1813 | kvm_get_pfn(pfn); | |
1814 | *pfnp = pfn; | |
1815 | ||
1816 | return PMD_SIZE; | |
1817 | } | |
1818 | ||
1819 | /* Use page mapping if we cannot use block mapping. */ | |
1820 | return PAGE_SIZE; | |
1821 | } | |
1822 | ||
94f8e641 | 1823 | static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, |
98047888 | 1824 | struct kvm_memory_slot *memslot, unsigned long hva, |
94f8e641 CD |
1825 | unsigned long fault_status) |
1826 | { | |
94f8e641 | 1827 | int ret; |
6396b852 PA |
1828 | bool write_fault, writable, force_pte = false; |
1829 | bool exec_fault, needs_exec; | |
94f8e641 | 1830 | unsigned long mmu_seq; |
ad361f09 | 1831 | gfn_t gfn = fault_ipa >> PAGE_SHIFT; |
ad361f09 | 1832 | struct kvm *kvm = vcpu->kvm; |
94f8e641 | 1833 | struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache; |
ad361f09 | 1834 | struct vm_area_struct *vma; |
1559b758 | 1835 | short vma_shift; |
ba049e93 | 1836 | kvm_pfn_t pfn; |
b8865767 | 1837 | pgprot_t mem_type = PAGE_S2; |
15a49a44 | 1838 | bool logging_active = memslot_is_logging(memslot); |
3f58bf63 | 1839 | unsigned long vma_pagesize, flags = 0; |
94f8e641 | 1840 | |
a7d079ce | 1841 | write_fault = kvm_is_write_fault(vcpu); |
d0e22b4a MZ |
1842 | exec_fault = kvm_vcpu_trap_is_iabt(vcpu); |
1843 | VM_BUG_ON(write_fault && exec_fault); | |
1844 | ||
1845 | if (fault_status == FSC_PERM && !write_fault && !exec_fault) { | |
94f8e641 CD |
1846 | kvm_err("Unexpected L2 read permission error\n"); |
1847 | return -EFAULT; | |
1848 | } | |
1849 | ||
ad361f09 | 1850 | /* Let's check if we will get back a huge page backed by hugetlbfs */ |
89154dd5 | 1851 | mmap_read_lock(current->mm); |
ad361f09 | 1852 | vma = find_vma_intersection(current->mm, hva, hva + 1); |
37b54408 AB |
1853 | if (unlikely(!vma)) { |
1854 | kvm_err("Failed to find VMA for hva 0x%lx\n", hva); | |
89154dd5 | 1855 | mmap_read_unlock(current->mm); |
37b54408 AB |
1856 | return -EFAULT; |
1857 | } | |
1858 | ||
1559b758 JM |
1859 | if (is_vm_hugetlb_page(vma)) |
1860 | vma_shift = huge_page_shift(hstate_vma(vma)); | |
1861 | else | |
1862 | vma_shift = PAGE_SHIFT; | |
1863 | ||
1864 | vma_pagesize = 1ULL << vma_shift; | |
a80868f3 | 1865 | if (logging_active || |
6d674e28 | 1866 | (vma->vm_flags & VM_PFNMAP) || |
a80868f3 SP |
1867 | !fault_supports_stage2_huge_mapping(memslot, hva, vma_pagesize)) { |
1868 | force_pte = true; | |
1869 | vma_pagesize = PAGE_SIZE; | |
1870 | } | |
1871 | ||
b8e0ba7c | 1872 | /* |
280cebfd SP |
1873 | * The stage2 has a minimum of 2 level table (For arm64 see |
1874 | * kvm_arm_setup_stage2()). Hence, we are guaranteed that we can | |
1875 | * use PMD_SIZE huge mappings (even when the PMD is folded into PGD). | |
1876 | * As for PUD huge maps, we must make sure that we have at least | |
1877 | * 3 levels, i.e, PMD is not folded. | |
b8e0ba7c | 1878 | */ |
a80868f3 SP |
1879 | if (vma_pagesize == PMD_SIZE || |
1880 | (vma_pagesize == PUD_SIZE && kvm_stage2_has_pmd(kvm))) | |
b8e0ba7c | 1881 | gfn = (fault_ipa & huge_page_mask(hstate_vma(vma))) >> PAGE_SHIFT; |
89154dd5 | 1882 | mmap_read_unlock(current->mm); |
ad361f09 | 1883 | |
94f8e641 | 1884 | /* We need minimum second+third level pages */ |
e55cac5b | 1885 | ret = mmu_topup_memory_cache(memcache, kvm_mmu_cache_min_pages(kvm), |
38f791a4 | 1886 | KVM_NR_MEM_OBJS); |
94f8e641 CD |
1887 | if (ret) |
1888 | return ret; | |
1889 | ||
1890 | mmu_seq = vcpu->kvm->mmu_notifier_seq; | |
1891 | /* | |
1892 | * Ensure the read of mmu_notifier_seq happens before we call | |
1893 | * gfn_to_pfn_prot (which calls get_user_pages), so that we don't risk | |
1894 | * the page we just got a reference to gets unmapped before we have a | |
1895 | * chance to grab the mmu_lock, which ensure that if the page gets | |
1896 | * unmapped afterwards, the call to kvm_unmap_hva will take it away | |
1897 | * from us again properly. This smp_rmb() interacts with the smp_wmb() | |
1898 | * in kvm_mmu_notifier_invalidate_<page|range_end>. | |
1899 | */ | |
1900 | smp_rmb(); | |
1901 | ||
ad361f09 | 1902 | pfn = gfn_to_pfn_prot(kvm, gfn, write_fault, &writable); |
196f878a | 1903 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
1559b758 | 1904 | kvm_send_hwpoison_signal(hva, vma_shift); |
196f878a JM |
1905 | return 0; |
1906 | } | |
9ac71595 | 1907 | if (is_error_noslot_pfn(pfn)) |
94f8e641 CD |
1908 | return -EFAULT; |
1909 | ||
15a49a44 | 1910 | if (kvm_is_device_pfn(pfn)) { |
b8865767 | 1911 | mem_type = PAGE_S2_DEVICE; |
15a49a44 MS |
1912 | flags |= KVM_S2PTE_FLAG_IS_IOMAP; |
1913 | } else if (logging_active) { | |
1914 | /* | |
1915 | * Faults on pages in a memslot with logging enabled | |
1916 | * should not be mapped with huge pages (it introduces churn | |
1917 | * and performance degradation), so force a pte mapping. | |
1918 | */ | |
15a49a44 MS |
1919 | flags |= KVM_S2_FLAG_LOGGING_ACTIVE; |
1920 | ||
1921 | /* | |
1922 | * Only actually map the page as writable if this was a write | |
1923 | * fault. | |
1924 | */ | |
1925 | if (!write_fault) | |
1926 | writable = false; | |
1927 | } | |
b8865767 | 1928 | |
6d674e28 MZ |
1929 | if (exec_fault && is_iomap(flags)) |
1930 | return -ENOEXEC; | |
1931 | ||
ad361f09 CD |
1932 | spin_lock(&kvm->mmu_lock); |
1933 | if (mmu_notifier_retry(kvm, mmu_seq)) | |
94f8e641 | 1934 | goto out_unlock; |
15a49a44 | 1935 | |
0529c902 SP |
1936 | /* |
1937 | * If we are not forced to use page mapping, check if we are | |
1938 | * backed by a THP and thus use block mapping if possible. | |
1939 | */ | |
1940 | if (vma_pagesize == PAGE_SIZE && !force_pte) | |
1941 | vma_pagesize = transparent_hugepage_adjust(memslot, hva, | |
1942 | &pfn, &fault_ipa); | |
3f58bf63 PA |
1943 | if (writable) |
1944 | kvm_set_pfn_dirty(pfn); | |
ad361f09 | 1945 | |
6d674e28 | 1946 | if (fault_status != FSC_PERM && !is_iomap(flags)) |
3f58bf63 PA |
1947 | clean_dcache_guest_page(pfn, vma_pagesize); |
1948 | ||
1949 | if (exec_fault) | |
1950 | invalidate_icache_guest_page(pfn, vma_pagesize); | |
1951 | ||
6396b852 PA |
1952 | /* |
1953 | * If we took an execution fault we have made the | |
1954 | * icache/dcache coherent above and should now let the s2 | |
1955 | * mapping be executable. | |
1956 | * | |
1957 | * Write faults (!exec_fault && FSC_PERM) are orthogonal to | |
1958 | * execute permissions, and we preserve whatever we have. | |
1959 | */ | |
1960 | needs_exec = exec_fault || | |
1961 | (fault_status == FSC_PERM && stage2_is_exec(kvm, fault_ipa)); | |
1962 | ||
b8e0ba7c PA |
1963 | if (vma_pagesize == PUD_SIZE) { |
1964 | pud_t new_pud = kvm_pfn_pud(pfn, mem_type); | |
1965 | ||
1966 | new_pud = kvm_pud_mkhuge(new_pud); | |
1967 | if (writable) | |
1968 | new_pud = kvm_s2pud_mkwrite(new_pud); | |
1969 | ||
1970 | if (needs_exec) | |
1971 | new_pud = kvm_s2pud_mkexec(new_pud); | |
1972 | ||
1973 | ret = stage2_set_pud_huge(kvm, memcache, fault_ipa, &new_pud); | |
1974 | } else if (vma_pagesize == PMD_SIZE) { | |
f8df7338 PA |
1975 | pmd_t new_pmd = kvm_pfn_pmd(pfn, mem_type); |
1976 | ||
1977 | new_pmd = kvm_pmd_mkhuge(new_pmd); | |
1978 | ||
3f58bf63 | 1979 | if (writable) |
06485053 | 1980 | new_pmd = kvm_s2pmd_mkwrite(new_pmd); |
d0e22b4a | 1981 | |
6396b852 | 1982 | if (needs_exec) |
d0e22b4a | 1983 | new_pmd = kvm_s2pmd_mkexec(new_pmd); |
a15f6939 | 1984 | |
ad361f09 CD |
1985 | ret = stage2_set_pmd_huge(kvm, memcache, fault_ipa, &new_pmd); |
1986 | } else { | |
f8df7338 | 1987 | pte_t new_pte = kvm_pfn_pte(pfn, mem_type); |
15a49a44 | 1988 | |
ad361f09 | 1989 | if (writable) { |
06485053 | 1990 | new_pte = kvm_s2pte_mkwrite(new_pte); |
15a49a44 | 1991 | mark_page_dirty(kvm, gfn); |
ad361f09 | 1992 | } |
a9c0e12e | 1993 | |
6396b852 | 1994 | if (needs_exec) |
d0e22b4a | 1995 | new_pte = kvm_s2pte_mkexec(new_pte); |
a15f6939 | 1996 | |
15a49a44 | 1997 | ret = stage2_set_pte(kvm, memcache, fault_ipa, &new_pte, flags); |
94f8e641 | 1998 | } |
ad361f09 | 1999 | |
94f8e641 | 2000 | out_unlock: |
ad361f09 | 2001 | spin_unlock(&kvm->mmu_lock); |
35307b9a | 2002 | kvm_set_pfn_accessed(pfn); |
94f8e641 | 2003 | kvm_release_pfn_clean(pfn); |
ad361f09 | 2004 | return ret; |
94f8e641 CD |
2005 | } |
2006 | ||
aeda9130 MZ |
2007 | /* |
2008 | * Resolve the access fault by making the page young again. | |
2009 | * Note that because the faulting entry is guaranteed not to be | |
2010 | * cached in the TLB, we don't need to invalidate anything. | |
06485053 CM |
2011 | * Only the HW Access Flag updates are supported for Stage 2 (no DBM), |
2012 | * so there is no need for atomic (pte|pmd)_mkyoung operations. | |
aeda9130 MZ |
2013 | */ |
2014 | static void handle_access_fault(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa) | |
2015 | { | |
eb3f0624 | 2016 | pud_t *pud; |
aeda9130 MZ |
2017 | pmd_t *pmd; |
2018 | pte_t *pte; | |
ba049e93 | 2019 | kvm_pfn_t pfn; |
aeda9130 MZ |
2020 | bool pfn_valid = false; |
2021 | ||
2022 | trace_kvm_access_fault(fault_ipa); | |
2023 | ||
2024 | spin_lock(&vcpu->kvm->mmu_lock); | |
2025 | ||
eb3f0624 | 2026 | if (!stage2_get_leaf_entry(vcpu->kvm, fault_ipa, &pud, &pmd, &pte)) |
aeda9130 MZ |
2027 | goto out; |
2028 | ||
eb3f0624 PA |
2029 | if (pud) { /* HugeTLB */ |
2030 | *pud = kvm_s2pud_mkyoung(*pud); | |
2031 | pfn = kvm_pud_pfn(*pud); | |
2032 | pfn_valid = true; | |
2033 | } else if (pmd) { /* THP, HugeTLB */ | |
aeda9130 MZ |
2034 | *pmd = pmd_mkyoung(*pmd); |
2035 | pfn = pmd_pfn(*pmd); | |
2036 | pfn_valid = true; | |
eb3f0624 PA |
2037 | } else { |
2038 | *pte = pte_mkyoung(*pte); /* Just a page... */ | |
2039 | pfn = pte_pfn(*pte); | |
2040 | pfn_valid = true; | |
aeda9130 MZ |
2041 | } |
2042 | ||
aeda9130 MZ |
2043 | out: |
2044 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2045 | if (pfn_valid) | |
2046 | kvm_set_pfn_accessed(pfn); | |
2047 | } | |
2048 | ||
94f8e641 CD |
2049 | /** |
2050 | * kvm_handle_guest_abort - handles all 2nd stage aborts | |
2051 | * @vcpu: the VCPU pointer | |
2052 | * @run: the kvm_run structure | |
2053 | * | |
2054 | * Any abort that gets to the host is almost guaranteed to be caused by a | |
2055 | * missing second stage translation table entry, which can mean that either the | |
2056 | * guest simply needs more memory and we must allocate an appropriate page or it | |
2057 | * can mean that the guest tried to access I/O memory, which is emulated by user | |
2058 | * space. The distinction is based on the IPA causing the fault and whether this | |
2059 | * memory region has been registered as standard RAM by user space. | |
2060 | */ | |
342cd0ab CD |
2061 | int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run) |
2062 | { | |
94f8e641 CD |
2063 | unsigned long fault_status; |
2064 | phys_addr_t fault_ipa; | |
2065 | struct kvm_memory_slot *memslot; | |
98047888 CD |
2066 | unsigned long hva; |
2067 | bool is_iabt, write_fault, writable; | |
94f8e641 CD |
2068 | gfn_t gfn; |
2069 | int ret, idx; | |
2070 | ||
621f48e4 TB |
2071 | fault_status = kvm_vcpu_trap_get_fault_type(vcpu); |
2072 | ||
2073 | fault_ipa = kvm_vcpu_get_fault_ipa(vcpu); | |
bb428921 | 2074 | is_iabt = kvm_vcpu_trap_is_iabt(vcpu); |
621f48e4 | 2075 | |
bb428921 | 2076 | /* Synchronous External Abort? */ |
c9a636f2 | 2077 | if (kvm_vcpu_abt_issea(vcpu)) { |
bb428921 JM |
2078 | /* |
2079 | * For RAS the host kernel may handle this abort. | |
2080 | * There is no need to pass the error into the guest. | |
2081 | */ | |
84b951a8 | 2082 | if (kvm_handle_guest_sea(fault_ipa, kvm_vcpu_get_esr(vcpu))) |
bb428921 | 2083 | kvm_inject_vabt(vcpu); |
84b951a8 WD |
2084 | |
2085 | return 1; | |
4055710b MZ |
2086 | } |
2087 | ||
3a949f4c | 2088 | trace_kvm_guest_fault(*vcpu_pc(vcpu), kvm_vcpu_get_esr(vcpu), |
7393b599 | 2089 | kvm_vcpu_get_hfar(vcpu), fault_ipa); |
94f8e641 CD |
2090 | |
2091 | /* Check the stage-2 fault is trans. fault or write fault */ | |
35307b9a MZ |
2092 | if (fault_status != FSC_FAULT && fault_status != FSC_PERM && |
2093 | fault_status != FSC_ACCESS) { | |
0496daa5 CD |
2094 | kvm_err("Unsupported FSC: EC=%#x xFSC=%#lx ESR_EL2=%#lx\n", |
2095 | kvm_vcpu_trap_get_class(vcpu), | |
2096 | (unsigned long)kvm_vcpu_trap_get_fault(vcpu), | |
3a949f4c | 2097 | (unsigned long)kvm_vcpu_get_esr(vcpu)); |
94f8e641 CD |
2098 | return -EFAULT; |
2099 | } | |
2100 | ||
2101 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
2102 | ||
2103 | gfn = fault_ipa >> PAGE_SHIFT; | |
98047888 CD |
2104 | memslot = gfn_to_memslot(vcpu->kvm, gfn); |
2105 | hva = gfn_to_hva_memslot_prot(memslot, gfn, &writable); | |
a7d079ce | 2106 | write_fault = kvm_is_write_fault(vcpu); |
98047888 | 2107 | if (kvm_is_error_hva(hva) || (write_fault && !writable)) { |
94f8e641 CD |
2108 | if (is_iabt) { |
2109 | /* Prefetch Abort on I/O address */ | |
6d674e28 MZ |
2110 | ret = -ENOEXEC; |
2111 | goto out; | |
94f8e641 CD |
2112 | } |
2113 | ||
57c841f1 MZ |
2114 | /* |
2115 | * Check for a cache maintenance operation. Since we | |
2116 | * ended-up here, we know it is outside of any memory | |
2117 | * slot. But we can't find out if that is for a device, | |
2118 | * or if the guest is just being stupid. The only thing | |
2119 | * we know for sure is that this range cannot be cached. | |
2120 | * | |
2121 | * So let's assume that the guest is just being | |
2122 | * cautious, and skip the instruction. | |
2123 | */ | |
2124 | if (kvm_vcpu_dabt_is_cm(vcpu)) { | |
2125 | kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); | |
2126 | ret = 1; | |
2127 | goto out_unlock; | |
2128 | } | |
2129 | ||
cfe3950c MZ |
2130 | /* |
2131 | * The IPA is reported as [MAX:12], so we need to | |
2132 | * complement it with the bottom 12 bits from the | |
2133 | * faulting VA. This is always 12 bits, irrespective | |
2134 | * of the page size. | |
2135 | */ | |
2136 | fault_ipa |= kvm_vcpu_get_hfar(vcpu) & ((1 << 12) - 1); | |
45e96ea6 | 2137 | ret = io_mem_abort(vcpu, run, fault_ipa); |
94f8e641 CD |
2138 | goto out_unlock; |
2139 | } | |
2140 | ||
c3058d5d | 2141 | /* Userspace should not be able to register out-of-bounds IPAs */ |
e55cac5b | 2142 | VM_BUG_ON(fault_ipa >= kvm_phys_size(vcpu->kvm)); |
c3058d5d | 2143 | |
aeda9130 MZ |
2144 | if (fault_status == FSC_ACCESS) { |
2145 | handle_access_fault(vcpu, fault_ipa); | |
2146 | ret = 1; | |
2147 | goto out_unlock; | |
2148 | } | |
2149 | ||
98047888 | 2150 | ret = user_mem_abort(vcpu, fault_ipa, memslot, hva, fault_status); |
94f8e641 CD |
2151 | if (ret == 0) |
2152 | ret = 1; | |
6d674e28 MZ |
2153 | out: |
2154 | if (ret == -ENOEXEC) { | |
2155 | kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu)); | |
2156 | ret = 1; | |
2157 | } | |
94f8e641 CD |
2158 | out_unlock: |
2159 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
2160 | return ret; | |
342cd0ab CD |
2161 | } |
2162 | ||
1d2ebacc MZ |
2163 | static int handle_hva_to_gpa(struct kvm *kvm, |
2164 | unsigned long start, | |
2165 | unsigned long end, | |
2166 | int (*handler)(struct kvm *kvm, | |
056aad67 SP |
2167 | gpa_t gpa, u64 size, |
2168 | void *data), | |
1d2ebacc | 2169 | void *data) |
d5d8184d CD |
2170 | { |
2171 | struct kvm_memslots *slots; | |
2172 | struct kvm_memory_slot *memslot; | |
1d2ebacc | 2173 | int ret = 0; |
d5d8184d CD |
2174 | |
2175 | slots = kvm_memslots(kvm); | |
2176 | ||
2177 | /* we only care about the pages that the guest sees */ | |
2178 | kvm_for_each_memslot(memslot, slots) { | |
2179 | unsigned long hva_start, hva_end; | |
056aad67 | 2180 | gfn_t gpa; |
d5d8184d CD |
2181 | |
2182 | hva_start = max(start, memslot->userspace_addr); | |
2183 | hva_end = min(end, memslot->userspace_addr + | |
2184 | (memslot->npages << PAGE_SHIFT)); | |
2185 | if (hva_start >= hva_end) | |
2186 | continue; | |
2187 | ||
056aad67 SP |
2188 | gpa = hva_to_gfn_memslot(hva_start, memslot) << PAGE_SHIFT; |
2189 | ret |= handler(kvm, gpa, (u64)(hva_end - hva_start), data); | |
d5d8184d | 2190 | } |
1d2ebacc MZ |
2191 | |
2192 | return ret; | |
d5d8184d CD |
2193 | } |
2194 | ||
056aad67 | 2195 | static int kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, u64 size, void *data) |
d5d8184d | 2196 | { |
056aad67 | 2197 | unmap_stage2_range(kvm, gpa, size); |
1d2ebacc | 2198 | return 0; |
d5d8184d CD |
2199 | } |
2200 | ||
d5d8184d CD |
2201 | int kvm_unmap_hva_range(struct kvm *kvm, |
2202 | unsigned long start, unsigned long end) | |
2203 | { | |
2204 | if (!kvm->arch.pgd) | |
2205 | return 0; | |
2206 | ||
2207 | trace_kvm_unmap_hva_range(start, end); | |
2208 | handle_hva_to_gpa(kvm, start, end, &kvm_unmap_hva_handler, NULL); | |
2209 | return 0; | |
2210 | } | |
2211 | ||
056aad67 | 2212 | static int kvm_set_spte_handler(struct kvm *kvm, gpa_t gpa, u64 size, void *data) |
d5d8184d CD |
2213 | { |
2214 | pte_t *pte = (pte_t *)data; | |
2215 | ||
056aad67 | 2216 | WARN_ON(size != PAGE_SIZE); |
15a49a44 MS |
2217 | /* |
2218 | * We can always call stage2_set_pte with KVM_S2PTE_FLAG_LOGGING_ACTIVE | |
2219 | * flag clear because MMU notifiers will have unmapped a huge PMD before | |
2220 | * calling ->change_pte() (which in turn calls kvm_set_spte_hva()) and | |
2221 | * therefore stage2_set_pte() never needs to clear out a huge PMD | |
2222 | * through this calling path. | |
2223 | */ | |
2224 | stage2_set_pte(kvm, NULL, gpa, pte, 0); | |
1d2ebacc | 2225 | return 0; |
d5d8184d CD |
2226 | } |
2227 | ||
2228 | ||
748c0e31 | 2229 | int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
d5d8184d CD |
2230 | { |
2231 | unsigned long end = hva + PAGE_SIZE; | |
694556d5 | 2232 | kvm_pfn_t pfn = pte_pfn(pte); |
d5d8184d CD |
2233 | pte_t stage2_pte; |
2234 | ||
2235 | if (!kvm->arch.pgd) | |
748c0e31 | 2236 | return 0; |
d5d8184d CD |
2237 | |
2238 | trace_kvm_set_spte_hva(hva); | |
694556d5 MZ |
2239 | |
2240 | /* | |
2241 | * We've moved a page around, probably through CoW, so let's treat it | |
2242 | * just like a translation fault and clean the cache to the PoC. | |
2243 | */ | |
2244 | clean_dcache_guest_page(pfn, PAGE_SIZE); | |
f8df7338 | 2245 | stage2_pte = kvm_pfn_pte(pfn, PAGE_S2); |
d5d8184d | 2246 | handle_hva_to_gpa(kvm, hva, end, &kvm_set_spte_handler, &stage2_pte); |
748c0e31 LT |
2247 | |
2248 | return 0; | |
d5d8184d CD |
2249 | } |
2250 | ||
056aad67 | 2251 | static int kvm_age_hva_handler(struct kvm *kvm, gpa_t gpa, u64 size, void *data) |
35307b9a | 2252 | { |
35a63966 | 2253 | pud_t *pud; |
35307b9a MZ |
2254 | pmd_t *pmd; |
2255 | pte_t *pte; | |
2256 | ||
35a63966 PA |
2257 | WARN_ON(size != PAGE_SIZE && size != PMD_SIZE && size != PUD_SIZE); |
2258 | if (!stage2_get_leaf_entry(kvm, gpa, &pud, &pmd, &pte)) | |
35307b9a MZ |
2259 | return 0; |
2260 | ||
35a63966 PA |
2261 | if (pud) |
2262 | return stage2_pudp_test_and_clear_young(pud); | |
2263 | else if (pmd) | |
06485053 | 2264 | return stage2_pmdp_test_and_clear_young(pmd); |
35a63966 PA |
2265 | else |
2266 | return stage2_ptep_test_and_clear_young(pte); | |
35307b9a MZ |
2267 | } |
2268 | ||
056aad67 | 2269 | static int kvm_test_age_hva_handler(struct kvm *kvm, gpa_t gpa, u64 size, void *data) |
35307b9a | 2270 | { |
35a63966 | 2271 | pud_t *pud; |
35307b9a MZ |
2272 | pmd_t *pmd; |
2273 | pte_t *pte; | |
2274 | ||
35a63966 PA |
2275 | WARN_ON(size != PAGE_SIZE && size != PMD_SIZE && size != PUD_SIZE); |
2276 | if (!stage2_get_leaf_entry(kvm, gpa, &pud, &pmd, &pte)) | |
35307b9a MZ |
2277 | return 0; |
2278 | ||
35a63966 PA |
2279 | if (pud) |
2280 | return kvm_s2pud_young(*pud); | |
2281 | else if (pmd) | |
35307b9a | 2282 | return pmd_young(*pmd); |
35a63966 | 2283 | else |
35307b9a | 2284 | return pte_young(*pte); |
35307b9a MZ |
2285 | } |
2286 | ||
2287 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) | |
2288 | { | |
7e5a6722 SP |
2289 | if (!kvm->arch.pgd) |
2290 | return 0; | |
35307b9a MZ |
2291 | trace_kvm_age_hva(start, end); |
2292 | return handle_hva_to_gpa(kvm, start, end, kvm_age_hva_handler, NULL); | |
2293 | } | |
2294 | ||
2295 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) | |
2296 | { | |
7e5a6722 SP |
2297 | if (!kvm->arch.pgd) |
2298 | return 0; | |
35307b9a | 2299 | trace_kvm_test_age_hva(hva); |
cf2d23e0 GS |
2300 | return handle_hva_to_gpa(kvm, hva, hva + PAGE_SIZE, |
2301 | kvm_test_age_hva_handler, NULL); | |
35307b9a MZ |
2302 | } |
2303 | ||
d5d8184d CD |
2304 | void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu) |
2305 | { | |
2306 | mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); | |
2307 | } | |
2308 | ||
342cd0ab CD |
2309 | phys_addr_t kvm_mmu_get_httbr(void) |
2310 | { | |
e4c5a685 AB |
2311 | if (__kvm_cpu_uses_extended_idmap()) |
2312 | return virt_to_phys(merged_hyp_pgd); | |
2313 | else | |
2314 | return virt_to_phys(hyp_pgd); | |
342cd0ab CD |
2315 | } |
2316 | ||
5a677ce0 MZ |
2317 | phys_addr_t kvm_get_idmap_vector(void) |
2318 | { | |
2319 | return hyp_idmap_vector; | |
2320 | } | |
2321 | ||
0535a3e2 MZ |
2322 | static int kvm_map_idmap_text(pgd_t *pgd) |
2323 | { | |
2324 | int err; | |
2325 | ||
2326 | /* Create the idmap in the boot page tables */ | |
98732d1b | 2327 | err = __create_hyp_mappings(pgd, __kvm_idmap_ptrs_per_pgd(), |
0535a3e2 MZ |
2328 | hyp_idmap_start, hyp_idmap_end, |
2329 | __phys_to_pfn(hyp_idmap_start), | |
2330 | PAGE_HYP_EXEC); | |
2331 | if (err) | |
2332 | kvm_err("Failed to idmap %lx-%lx\n", | |
2333 | hyp_idmap_start, hyp_idmap_end); | |
2334 | ||
2335 | return err; | |
2336 | } | |
2337 | ||
342cd0ab CD |
2338 | int kvm_mmu_init(void) |
2339 | { | |
2fb41059 MZ |
2340 | int err; |
2341 | ||
0a78791c | 2342 | hyp_idmap_start = __pa_symbol(__hyp_idmap_text_start); |
46fef158 | 2343 | hyp_idmap_start = ALIGN_DOWN(hyp_idmap_start, PAGE_SIZE); |
0a78791c | 2344 | hyp_idmap_end = __pa_symbol(__hyp_idmap_text_end); |
46fef158 | 2345 | hyp_idmap_end = ALIGN(hyp_idmap_end, PAGE_SIZE); |
0a78791c | 2346 | hyp_idmap_vector = __pa_symbol(__kvm_hyp_init); |
5a677ce0 | 2347 | |
06f75a1f AB |
2348 | /* |
2349 | * We rely on the linker script to ensure at build time that the HYP | |
2350 | * init code does not cross a page boundary. | |
2351 | */ | |
2352 | BUG_ON((hyp_idmap_start ^ (hyp_idmap_end - 1)) & PAGE_MASK); | |
5a677ce0 | 2353 | |
b4ef0499 MZ |
2354 | kvm_debug("IDMAP page: %lx\n", hyp_idmap_start); |
2355 | kvm_debug("HYP VA range: %lx:%lx\n", | |
2356 | kern_hyp_va(PAGE_OFFSET), | |
2357 | kern_hyp_va((unsigned long)high_memory - 1)); | |
eac378a9 | 2358 | |
6c41a413 | 2359 | if (hyp_idmap_start >= kern_hyp_va(PAGE_OFFSET) && |
ed57cac8 | 2360 | hyp_idmap_start < kern_hyp_va((unsigned long)high_memory - 1) && |
d2896d4b | 2361 | hyp_idmap_start != (unsigned long)__hyp_idmap_text_start) { |
eac378a9 MZ |
2362 | /* |
2363 | * The idmap page is intersecting with the VA space, | |
2364 | * it is not safe to continue further. | |
2365 | */ | |
2366 | kvm_err("IDMAP intersecting with HYP VA, unable to continue\n"); | |
2367 | err = -EINVAL; | |
2368 | goto out; | |
2369 | } | |
2370 | ||
38f791a4 | 2371 | hyp_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, hyp_pgd_order); |
0535a3e2 | 2372 | if (!hyp_pgd) { |
d5d8184d | 2373 | kvm_err("Hyp mode PGD not allocated\n"); |
2fb41059 MZ |
2374 | err = -ENOMEM; |
2375 | goto out; | |
2376 | } | |
2377 | ||
0535a3e2 MZ |
2378 | if (__kvm_cpu_uses_extended_idmap()) { |
2379 | boot_hyp_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
2380 | hyp_pgd_order); | |
2381 | if (!boot_hyp_pgd) { | |
2382 | kvm_err("Hyp boot PGD not allocated\n"); | |
2383 | err = -ENOMEM; | |
2384 | goto out; | |
2385 | } | |
2fb41059 | 2386 | |
0535a3e2 MZ |
2387 | err = kvm_map_idmap_text(boot_hyp_pgd); |
2388 | if (err) | |
2389 | goto out; | |
d5d8184d | 2390 | |
e4c5a685 AB |
2391 | merged_hyp_pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO); |
2392 | if (!merged_hyp_pgd) { | |
2393 | kvm_err("Failed to allocate extra HYP pgd\n"); | |
2394 | goto out; | |
2395 | } | |
2396 | __kvm_extend_hypmap(boot_hyp_pgd, hyp_pgd, merged_hyp_pgd, | |
2397 | hyp_idmap_start); | |
0535a3e2 MZ |
2398 | } else { |
2399 | err = kvm_map_idmap_text(hyp_pgd); | |
2400 | if (err) | |
2401 | goto out; | |
5a677ce0 MZ |
2402 | } |
2403 | ||
e3f019b3 | 2404 | io_map_base = hyp_idmap_start; |
d5d8184d | 2405 | return 0; |
2fb41059 | 2406 | out: |
4f728276 | 2407 | free_hyp_pgds(); |
2fb41059 | 2408 | return err; |
342cd0ab | 2409 | } |
df6ce24f EA |
2410 | |
2411 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
09170a49 | 2412 | const struct kvm_userspace_memory_region *mem, |
9d4c197c | 2413 | struct kvm_memory_slot *old, |
f36f3f28 | 2414 | const struct kvm_memory_slot *new, |
df6ce24f EA |
2415 | enum kvm_mr_change change) |
2416 | { | |
c6473555 MS |
2417 | /* |
2418 | * At this point memslot has been committed and there is an | |
656012c7 | 2419 | * allocated dirty_bitmap[], dirty pages will be tracked while the |
c6473555 MS |
2420 | * memory slot is write protected. |
2421 | */ | |
c862626e KZ |
2422 | if (change != KVM_MR_DELETE && mem->flags & KVM_MEM_LOG_DIRTY_PAGES) { |
2423 | /* | |
2424 | * If we're with initial-all-set, we don't need to write | |
2425 | * protect any pages because they're all reported as dirty. | |
2426 | * Huge pages and normal pages will be write protect gradually. | |
2427 | */ | |
2428 | if (!kvm_dirty_log_manual_protect_and_init_set(kvm)) { | |
2429 | kvm_mmu_wp_memory_region(kvm, mem->slot); | |
2430 | } | |
2431 | } | |
df6ce24f EA |
2432 | } |
2433 | ||
2434 | int kvm_arch_prepare_memory_region(struct kvm *kvm, | |
2435 | struct kvm_memory_slot *memslot, | |
09170a49 | 2436 | const struct kvm_userspace_memory_region *mem, |
df6ce24f EA |
2437 | enum kvm_mr_change change) |
2438 | { | |
8eef9123 AB |
2439 | hva_t hva = mem->userspace_addr; |
2440 | hva_t reg_end = hva + mem->memory_size; | |
2441 | bool writable = !(mem->flags & KVM_MEM_READONLY); | |
2442 | int ret = 0; | |
2443 | ||
15a49a44 MS |
2444 | if (change != KVM_MR_CREATE && change != KVM_MR_MOVE && |
2445 | change != KVM_MR_FLAGS_ONLY) | |
8eef9123 AB |
2446 | return 0; |
2447 | ||
c3058d5d CD |
2448 | /* |
2449 | * Prevent userspace from creating a memory region outside of the IPA | |
2450 | * space addressable by the KVM guest IPA space. | |
2451 | */ | |
2452 | if (memslot->base_gfn + memslot->npages >= | |
e55cac5b | 2453 | (kvm_phys_size(kvm) >> PAGE_SHIFT)) |
c3058d5d CD |
2454 | return -EFAULT; |
2455 | ||
89154dd5 | 2456 | mmap_read_lock(current->mm); |
8eef9123 AB |
2457 | /* |
2458 | * A memory region could potentially cover multiple VMAs, and any holes | |
2459 | * between them, so iterate over all of them to find out if we can map | |
2460 | * any of them right now. | |
2461 | * | |
2462 | * +--------------------------------------------+ | |
2463 | * +---------------+----------------+ +----------------+ | |
2464 | * | : VMA 1 | VMA 2 | | VMA 3 : | | |
2465 | * +---------------+----------------+ +----------------+ | |
2466 | * | memory region | | |
2467 | * +--------------------------------------------+ | |
2468 | */ | |
2469 | do { | |
2470 | struct vm_area_struct *vma = find_vma(current->mm, hva); | |
2471 | hva_t vm_start, vm_end; | |
2472 | ||
2473 | if (!vma || vma->vm_start >= reg_end) | |
2474 | break; | |
2475 | ||
8eef9123 AB |
2476 | /* |
2477 | * Take the intersection of this VMA with the memory region | |
2478 | */ | |
2479 | vm_start = max(hva, vma->vm_start); | |
2480 | vm_end = min(reg_end, vma->vm_end); | |
2481 | ||
2482 | if (vma->vm_flags & VM_PFNMAP) { | |
2483 | gpa_t gpa = mem->guest_phys_addr + | |
2484 | (vm_start - mem->userspace_addr); | |
ca09f02f MM |
2485 | phys_addr_t pa; |
2486 | ||
2487 | pa = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT; | |
2488 | pa += vm_start - vma->vm_start; | |
8eef9123 | 2489 | |
15a49a44 | 2490 | /* IO region dirty page logging not allowed */ |
72f31048 MZ |
2491 | if (memslot->flags & KVM_MEM_LOG_DIRTY_PAGES) { |
2492 | ret = -EINVAL; | |
2493 | goto out; | |
2494 | } | |
15a49a44 | 2495 | |
8eef9123 AB |
2496 | ret = kvm_phys_addr_ioremap(kvm, gpa, pa, |
2497 | vm_end - vm_start, | |
2498 | writable); | |
2499 | if (ret) | |
2500 | break; | |
2501 | } | |
2502 | hva = vm_end; | |
2503 | } while (hva < reg_end); | |
2504 | ||
15a49a44 | 2505 | if (change == KVM_MR_FLAGS_ONLY) |
72f31048 | 2506 | goto out; |
15a49a44 | 2507 | |
849260c7 AB |
2508 | spin_lock(&kvm->mmu_lock); |
2509 | if (ret) | |
8eef9123 | 2510 | unmap_stage2_range(kvm, mem->guest_phys_addr, mem->memory_size); |
849260c7 AB |
2511 | else |
2512 | stage2_flush_memslot(kvm, memslot); | |
2513 | spin_unlock(&kvm->mmu_lock); | |
72f31048 | 2514 | out: |
89154dd5 | 2515 | mmap_read_unlock(current->mm); |
8eef9123 | 2516 | return ret; |
df6ce24f EA |
2517 | } |
2518 | ||
e96c81ee | 2519 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
df6ce24f EA |
2520 | { |
2521 | } | |
2522 | ||
15248258 | 2523 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
df6ce24f EA |
2524 | { |
2525 | } | |
2526 | ||
2527 | void kvm_arch_flush_shadow_all(struct kvm *kvm) | |
2528 | { | |
293f2936 | 2529 | kvm_free_stage2_pgd(kvm); |
df6ce24f EA |
2530 | } |
2531 | ||
2532 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, | |
2533 | struct kvm_memory_slot *slot) | |
2534 | { | |
8eef9123 AB |
2535 | gpa_t gpa = slot->base_gfn << PAGE_SHIFT; |
2536 | phys_addr_t size = slot->npages << PAGE_SHIFT; | |
2537 | ||
2538 | spin_lock(&kvm->mmu_lock); | |
2539 | unmap_stage2_range(kvm, gpa, size); | |
2540 | spin_unlock(&kvm->mmu_lock); | |
df6ce24f | 2541 | } |
3c1e7165 MZ |
2542 | |
2543 | /* | |
2544 | * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). | |
2545 | * | |
2546 | * Main problems: | |
2547 | * - S/W ops are local to a CPU (not broadcast) | |
2548 | * - We have line migration behind our back (speculation) | |
2549 | * - System caches don't support S/W at all (damn!) | |
2550 | * | |
2551 | * In the face of the above, the best we can do is to try and convert | |
2552 | * S/W ops to VA ops. Because the guest is not allowed to infer the | |
2553 | * S/W to PA mapping, it can only use S/W to nuke the whole cache, | |
2554 | * which is a rather good thing for us. | |
2555 | * | |
2556 | * Also, it is only used when turning caches on/off ("The expected | |
2557 | * usage of the cache maintenance instructions that operate by set/way | |
2558 | * is associated with the cache maintenance instructions associated | |
2559 | * with the powerdown and powerup of caches, if this is required by | |
2560 | * the implementation."). | |
2561 | * | |
2562 | * We use the following policy: | |
2563 | * | |
2564 | * - If we trap a S/W operation, we enable VM trapping to detect | |
2565 | * caches being turned on/off, and do a full clean. | |
2566 | * | |
2567 | * - We flush the caches on both caches being turned on and off. | |
2568 | * | |
2569 | * - Once the caches are enabled, we stop trapping VM ops. | |
2570 | */ | |
2571 | void kvm_set_way_flush(struct kvm_vcpu *vcpu) | |
2572 | { | |
3df59d8d | 2573 | unsigned long hcr = *vcpu_hcr(vcpu); |
3c1e7165 MZ |
2574 | |
2575 | /* | |
2576 | * If this is the first time we do a S/W operation | |
2577 | * (i.e. HCR_TVM not set) flush the whole memory, and set the | |
2578 | * VM trapping. | |
2579 | * | |
2580 | * Otherwise, rely on the VM trapping to wait for the MMU + | |
2581 | * Caches to be turned off. At that point, we'll be able to | |
2582 | * clean the caches again. | |
2583 | */ | |
2584 | if (!(hcr & HCR_TVM)) { | |
2585 | trace_kvm_set_way_flush(*vcpu_pc(vcpu), | |
2586 | vcpu_has_cache_enabled(vcpu)); | |
2587 | stage2_flush_vm(vcpu->kvm); | |
3df59d8d | 2588 | *vcpu_hcr(vcpu) = hcr | HCR_TVM; |
3c1e7165 MZ |
2589 | } |
2590 | } | |
2591 | ||
2592 | void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled) | |
2593 | { | |
2594 | bool now_enabled = vcpu_has_cache_enabled(vcpu); | |
2595 | ||
2596 | /* | |
2597 | * If switching the MMU+caches on, need to invalidate the caches. | |
2598 | * If switching it off, need to clean the caches. | |
2599 | * Clean + invalidate does the trick always. | |
2600 | */ | |
2601 | if (now_enabled != was_enabled) | |
2602 | stage2_flush_vm(vcpu->kvm); | |
2603 | ||
2604 | /* Caches are now on, stop trapping VM ops (until a S/W op) */ | |
2605 | if (now_enabled) | |
3df59d8d | 2606 | *vcpu_hcr(vcpu) &= ~HCR_TVM; |
3c1e7165 MZ |
2607 | |
2608 | trace_kvm_toggle_cache(*vcpu_pc(vcpu), was_enabled, now_enabled); | |
2609 | } |