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1 | /* |
2 | * Copyright (C) 2012-2015 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include <linux/compiler.h> | |
19 | #include <linux/irqchip/arm-gic-v3.h> | |
20 | #include <linux/kvm_host.h> | |
21 | ||
22 | #include <asm/kvm_mmu.h> | |
23 | ||
24 | #include "hyp.h" | |
25 | ||
26 | #define vtr_to_max_lr_idx(v) ((v) & 0xf) | |
27 | #define vtr_to_nr_pri_bits(v) (((u32)(v) >> 29) + 1) | |
28 | ||
29 | #define read_gicreg(r) \ | |
30 | ({ \ | |
31 | u64 reg; \ | |
32 | asm volatile("mrs_s %0, " __stringify(r) : "=r" (reg)); \ | |
33 | reg; \ | |
34 | }) | |
35 | ||
36 | #define write_gicreg(v,r) \ | |
37 | do { \ | |
38 | u64 __val = (v); \ | |
39 | asm volatile("msr_s " __stringify(r) ", %0" : : "r" (__val));\ | |
40 | } while (0) | |
41 | ||
42 | /* vcpu is already in the HYP VA space */ | |
43 | void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu) | |
44 | { | |
45 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; | |
46 | u64 val; | |
47 | u32 max_lr_idx, nr_pri_bits; | |
48 | ||
49 | /* | |
50 | * Make sure stores to the GIC via the memory mapped interface | |
51 | * are now visible to the system register interface. | |
52 | */ | |
53 | dsb(st); | |
54 | ||
55 | cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2); | |
56 | cpu_if->vgic_misr = read_gicreg(ICH_MISR_EL2); | |
57 | cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2); | |
58 | cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2); | |
59 | ||
60 | write_gicreg(0, ICH_HCR_EL2); | |
61 | val = read_gicreg(ICH_VTR_EL2); | |
62 | max_lr_idx = vtr_to_max_lr_idx(val); | |
63 | nr_pri_bits = vtr_to_nr_pri_bits(val); | |
64 | ||
65 | switch (max_lr_idx) { | |
66 | case 15: | |
67 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(15)] = read_gicreg(ICH_LR15_EL2); | |
68 | case 14: | |
69 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(14)] = read_gicreg(ICH_LR14_EL2); | |
70 | case 13: | |
71 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(13)] = read_gicreg(ICH_LR13_EL2); | |
72 | case 12: | |
73 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(12)] = read_gicreg(ICH_LR12_EL2); | |
74 | case 11: | |
75 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(11)] = read_gicreg(ICH_LR11_EL2); | |
76 | case 10: | |
77 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(10)] = read_gicreg(ICH_LR10_EL2); | |
78 | case 9: | |
79 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(9)] = read_gicreg(ICH_LR9_EL2); | |
80 | case 8: | |
81 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(8)] = read_gicreg(ICH_LR8_EL2); | |
82 | case 7: | |
83 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(7)] = read_gicreg(ICH_LR7_EL2); | |
84 | case 6: | |
85 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(6)] = read_gicreg(ICH_LR6_EL2); | |
86 | case 5: | |
87 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(5)] = read_gicreg(ICH_LR5_EL2); | |
88 | case 4: | |
89 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(4)] = read_gicreg(ICH_LR4_EL2); | |
90 | case 3: | |
91 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(3)] = read_gicreg(ICH_LR3_EL2); | |
92 | case 2: | |
93 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(2)] = read_gicreg(ICH_LR2_EL2); | |
94 | case 1: | |
95 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(1)] = read_gicreg(ICH_LR1_EL2); | |
96 | case 0: | |
97 | cpu_if->vgic_lr[VGIC_V3_LR_INDEX(0)] = read_gicreg(ICH_LR0_EL2); | |
98 | } | |
99 | ||
100 | switch (nr_pri_bits) { | |
101 | case 7: | |
102 | cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2); | |
103 | cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2); | |
104 | case 6: | |
105 | cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2); | |
106 | default: | |
107 | cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2); | |
108 | } | |
109 | ||
110 | switch (nr_pri_bits) { | |
111 | case 7: | |
112 | cpu_if->vgic_ap1r[3] = read_gicreg(ICH_AP1R3_EL2); | |
113 | cpu_if->vgic_ap1r[2] = read_gicreg(ICH_AP1R2_EL2); | |
114 | case 6: | |
115 | cpu_if->vgic_ap1r[1] = read_gicreg(ICH_AP1R1_EL2); | |
116 | default: | |
117 | cpu_if->vgic_ap1r[0] = read_gicreg(ICH_AP1R0_EL2); | |
118 | } | |
119 | ||
120 | val = read_gicreg(ICC_SRE_EL2); | |
121 | write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2); | |
122 | isb(); /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */ | |
123 | write_gicreg(1, ICC_SRE_EL1); | |
124 | } | |
125 | ||
126 | void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu) | |
127 | { | |
128 | struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; | |
129 | u64 val; | |
130 | u32 max_lr_idx, nr_pri_bits; | |
131 | ||
132 | /* | |
133 | * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a | |
134 | * Group0 interrupt (as generated in GICv2 mode) to be | |
135 | * delivered as a FIQ to the guest, with potentially fatal | |
136 | * consequences. So we must make sure that ICC_SRE_EL1 has | |
137 | * been actually programmed with the value we want before | |
138 | * starting to mess with the rest of the GIC. | |
139 | */ | |
140 | write_gicreg(cpu_if->vgic_sre, ICC_SRE_EL1); | |
141 | isb(); | |
142 | ||
143 | write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2); | |
144 | write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2); | |
145 | ||
146 | val = read_gicreg(ICH_VTR_EL2); | |
147 | max_lr_idx = vtr_to_max_lr_idx(val); | |
148 | nr_pri_bits = vtr_to_nr_pri_bits(val); | |
149 | ||
f68d2b1b MZ |
150 | switch (nr_pri_bits) { |
151 | case 7: | |
152 | write_gicreg(cpu_if->vgic_ap0r[3], ICH_AP0R3_EL2); | |
153 | write_gicreg(cpu_if->vgic_ap0r[2], ICH_AP0R2_EL2); | |
154 | case 6: | |
155 | write_gicreg(cpu_if->vgic_ap0r[1], ICH_AP0R1_EL2); | |
156 | default: | |
157 | write_gicreg(cpu_if->vgic_ap0r[0], ICH_AP0R0_EL2); | |
158 | } | |
159 | ||
fd451b90 MZ |
160 | switch (nr_pri_bits) { |
161 | case 7: | |
162 | write_gicreg(cpu_if->vgic_ap1r[3], ICH_AP1R3_EL2); | |
163 | write_gicreg(cpu_if->vgic_ap1r[2], ICH_AP1R2_EL2); | |
164 | case 6: | |
165 | write_gicreg(cpu_if->vgic_ap1r[1], ICH_AP1R1_EL2); | |
166 | default: | |
167 | write_gicreg(cpu_if->vgic_ap1r[0], ICH_AP1R0_EL2); | |
168 | } | |
169 | ||
f68d2b1b MZ |
170 | switch (max_lr_idx) { |
171 | case 15: | |
172 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(15)], ICH_LR15_EL2); | |
173 | case 14: | |
174 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(14)], ICH_LR14_EL2); | |
175 | case 13: | |
176 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(13)], ICH_LR13_EL2); | |
177 | case 12: | |
178 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(12)], ICH_LR12_EL2); | |
179 | case 11: | |
180 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(11)], ICH_LR11_EL2); | |
181 | case 10: | |
182 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(10)], ICH_LR10_EL2); | |
183 | case 9: | |
184 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(9)], ICH_LR9_EL2); | |
185 | case 8: | |
186 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(8)], ICH_LR8_EL2); | |
187 | case 7: | |
188 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(7)], ICH_LR7_EL2); | |
189 | case 6: | |
190 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(6)], ICH_LR6_EL2); | |
191 | case 5: | |
192 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(5)], ICH_LR5_EL2); | |
193 | case 4: | |
194 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(4)], ICH_LR4_EL2); | |
195 | case 3: | |
196 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(3)], ICH_LR3_EL2); | |
197 | case 2: | |
198 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(2)], ICH_LR2_EL2); | |
199 | case 1: | |
200 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(1)], ICH_LR1_EL2); | |
201 | case 0: | |
202 | write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(0)], ICH_LR0_EL2); | |
203 | } | |
204 | ||
205 | /* | |
206 | * Ensures that the above will have reached the | |
207 | * (re)distributors. This ensure the guest will read the | |
208 | * correct values from the memory-mapped interface. | |
209 | */ | |
210 | isb(); | |
211 | dsb(sy); | |
212 | ||
213 | /* | |
214 | * Prevent the guest from touching the GIC system registers if | |
215 | * SRE isn't enabled for GICv3 emulation. | |
216 | */ | |
217 | if (!cpu_if->vgic_sre) { | |
218 | write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE, | |
219 | ICC_SRE_EL2); | |
220 | } | |
221 | } | |
222 | ||
3ffa75cd | 223 | static u64 __hyp_text __vgic_v3_read_ich_vtr_el2(void) |
f68d2b1b MZ |
224 | { |
225 | return read_gicreg(ICH_VTR_EL2); | |
226 | } | |
044ac37d | 227 | |
3ffa75cd | 228 | __alias(__vgic_v3_read_ich_vtr_el2) u64 __vgic_v3_get_ich_vtr_el2(void); |