Commit | Line | Data |
---|---|---|
caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
08e875c1 CM |
2 | /* |
3 | * SMP initialisation and IPI support | |
4 | * Based on arch/arm/kernel/smp.c | |
5 | * | |
6 | * Copyright (C) 2012 ARM Ltd. | |
08e875c1 CM |
7 | */ |
8 | ||
0f078336 | 9 | #include <linux/acpi.h> |
f5df2696 | 10 | #include <linux/arm_sdei.h> |
08e875c1 CM |
11 | #include <linux/delay.h> |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
68e21be2 | 14 | #include <linux/sched/mm.h> |
ef8bd77f | 15 | #include <linux/sched/hotplug.h> |
68db0cf1 | 16 | #include <linux/sched/task_stack.h> |
08e875c1 CM |
17 | #include <linux/interrupt.h> |
18 | #include <linux/cache.h> | |
19 | #include <linux/profile.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/cpu.h> | |
24 | #include <linux/smp.h> | |
25 | #include <linux/seq_file.h> | |
26 | #include <linux/irq.h> | |
e7932188 | 27 | #include <linux/irqchip/arm-gic-v3.h> |
08e875c1 CM |
28 | #include <linux/percpu.h> |
29 | #include <linux/clockchips.h> | |
30 | #include <linux/completion.h> | |
31 | #include <linux/of.h> | |
eb631bb5 | 32 | #include <linux/irq_work.h> |
a2638815 | 33 | #include <linux/kernel_stat.h> |
78fd584c | 34 | #include <linux/kexec.h> |
2f5cd0c7 | 35 | #include <linux/kgdb.h> |
0492747c | 36 | #include <linux/kvm_host.h> |
331a1b3a | 37 | #include <linux/nmi.h> |
08e875c1 | 38 | |
e039ee4e | 39 | #include <asm/alternative.h> |
08e875c1 CM |
40 | #include <asm/atomic.h> |
41 | #include <asm/cacheflush.h> | |
df857416 | 42 | #include <asm/cpu.h> |
08e875c1 | 43 | #include <asm/cputype.h> |
cd1aebf5 | 44 | #include <asm/cpu_ops.h> |
0fbeb318 | 45 | #include <asm/daifflags.h> |
0492747c | 46 | #include <asm/kvm_mmu.h> |
08e875c1 | 47 | #include <asm/mmu_context.h> |
1a2db300 | 48 | #include <asm/numa.h> |
08e875c1 | 49 | #include <asm/processor.h> |
4c7aa002 | 50 | #include <asm/smp_plat.h> |
08e875c1 CM |
51 | #include <asm/sections.h> |
52 | #include <asm/tlbflush.h> | |
53 | #include <asm/ptrace.h> | |
377bcff9 | 54 | #include <asm/virt.h> |
08e875c1 | 55 | |
45ed695a NP |
56 | #include <trace/events/ipi.h> |
57 | ||
08e875c1 CM |
58 | /* |
59 | * as from 2.5, kernels no longer have an init_tasks structure | |
60 | * so we need some other way of telling a new secondary core | |
61 | * where to place its SVC stack | |
62 | */ | |
63 | struct secondary_data secondary_data; | |
bb905274 | 64 | /* Number of CPUs which aren't online, but looping in kernel text. */ |
2eaf63ba | 65 | static int cpus_stuck_in_kernel; |
08e875c1 CM |
66 | |
67 | enum ipi_msg_type { | |
68 | IPI_RESCHEDULE, | |
69 | IPI_CALL_FUNC, | |
08e875c1 | 70 | IPI_CPU_STOP, |
78fd584c | 71 | IPI_CPU_CRASH_STOP, |
1f85008e | 72 | IPI_TIMER, |
eb631bb5 | 73 | IPI_IRQ_WORK, |
331a1b3a DA |
74 | NR_IPI, |
75 | /* | |
76 | * Any enum >= NR_IPI and < MAX_IPI is special and not tracable | |
77 | * with trace_ipi_* | |
78 | */ | |
79 | IPI_CPU_BACKTRACE = NR_IPI, | |
2f5cd0c7 | 80 | IPI_KGDB_ROUNDUP, |
331a1b3a | 81 | MAX_IPI |
08e875c1 CM |
82 | }; |
83 | ||
62817d5b DA |
84 | static int ipi_irq_base __ro_after_init; |
85 | static int nr_ipi __ro_after_init = NR_IPI; | |
86 | static struct irq_desc *ipi_desc[MAX_IPI] __ro_after_init; | |
d3afc7f1 MZ |
87 | |
88 | static void ipi_setup(int cpu); | |
d3afc7f1 | 89 | |
bb905274 | 90 | #ifdef CONFIG_HOTPLUG_CPU |
9d9edb96 | 91 | static void ipi_teardown(int cpu); |
bb905274 SP |
92 | static int op_cpu_kill(unsigned int cpu); |
93 | #else | |
94 | static inline int op_cpu_kill(unsigned int cpu) | |
95 | { | |
96 | return -ENOSYS; | |
97 | } | |
98 | #endif | |
99 | ||
100 | ||
08e875c1 CM |
101 | /* |
102 | * Boot a secondary CPU, and assign it the specified idle task. | |
103 | * This also gives us the initial stack to use for this CPU. | |
104 | */ | |
b8c6453a | 105 | static int boot_secondary(unsigned int cpu, struct task_struct *idle) |
08e875c1 | 106 | { |
de58ed5e GS |
107 | const struct cpu_operations *ops = get_cpu_ops(cpu); |
108 | ||
109 | if (ops->cpu_boot) | |
110 | return ops->cpu_boot(cpu); | |
08e875c1 | 111 | |
652af899 | 112 | return -EOPNOTSUPP; |
08e875c1 CM |
113 | } |
114 | ||
115 | static DECLARE_COMPLETION(cpu_running); | |
116 | ||
b8c6453a | 117 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
08e875c1 CM |
118 | { |
119 | int ret; | |
bb905274 | 120 | long status; |
08e875c1 CM |
121 | |
122 | /* | |
123 | * We need to tell the secondary core where to find its stack and the | |
124 | * page tables. | |
125 | */ | |
c02433dd | 126 | secondary_data.task = idle; |
bb905274 | 127 | update_cpu_boot_status(CPU_MMU_OFF); |
08e875c1 | 128 | |
d22b115c | 129 | /* Now bring the CPU into our world */ |
08e875c1 | 130 | ret = boot_secondary(cpu, idle); |
d22b115c | 131 | if (ret) { |
643e12da JPB |
132 | if (ret != -EPERM) |
133 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
f357b3a7 | 134 | return ret; |
08e875c1 CM |
135 | } |
136 | ||
d22b115c GS |
137 | /* |
138 | * CPU was successfully started, wait for it to come online or | |
139 | * time out. | |
140 | */ | |
141 | wait_for_completion_timeout(&cpu_running, | |
142 | msecs_to_jiffies(5000)); | |
143 | if (cpu_online(cpu)) | |
144 | return 0; | |
145 | ||
146 | pr_crit("CPU%u: failed to come online\n", cpu); | |
c02433dd | 147 | secondary_data.task = NULL; |
bb905274 | 148 | status = READ_ONCE(secondary_data.status); |
d22b115c GS |
149 | if (status == CPU_MMU_OFF) |
150 | status = READ_ONCE(__early_cpu_boot_status); | |
bb905274 | 151 | |
d22b115c GS |
152 | switch (status & CPU_BOOT_STATUS_MASK) { |
153 | default: | |
154 | pr_err("CPU%u: failed in unknown state : 0x%lx\n", | |
155 | cpu, status); | |
156 | cpus_stuck_in_kernel++; | |
157 | break; | |
158 | case CPU_KILL_ME: | |
159 | if (!op_cpu_kill(cpu)) { | |
160 | pr_crit("CPU%u: died during early boot\n", cpu); | |
bb905274 | 161 | break; |
bb905274 | 162 | } |
d22b115c | 163 | pr_crit("CPU%u: may not have shut down cleanly\n", cpu); |
df561f66 | 164 | fallthrough; |
d22b115c GS |
165 | case CPU_STUCK_IN_KERNEL: |
166 | pr_crit("CPU%u: is stuck in kernel\n", cpu); | |
167 | if (status & CPU_STUCK_REASON_52_BIT_VA) | |
168 | pr_crit("CPU%u: does not support 52-bit VAs\n", cpu); | |
169 | if (status & CPU_STUCK_REASON_NO_GRAN) { | |
170 | pr_crit("CPU%u: does not support %luK granule\n", | |
171 | cpu, PAGE_SIZE / SZ_1K); | |
172 | } | |
173 | cpus_stuck_in_kernel++; | |
174 | break; | |
175 | case CPU_PANIC_KERNEL: | |
176 | panic("CPU%u detected unsupported configuration\n", cpu); | |
bb905274 | 177 | } |
08e875c1 | 178 | |
ba051f09 | 179 | return -EIO; |
08e875c1 CM |
180 | } |
181 | ||
e7932188 JT |
182 | static void init_gic_priority_masking(void) |
183 | { | |
184 | u32 cpuflags; | |
185 | ||
186 | if (WARN_ON(!gic_enable_sre())) | |
187 | return; | |
188 | ||
189 | cpuflags = read_sysreg(daif); | |
190 | ||
191 | WARN_ON(!(cpuflags & PSR_I_BIT)); | |
f0098155 | 192 | WARN_ON(!(cpuflags & PSR_F_BIT)); |
e7932188 | 193 | |
e1d22385 | 194 | gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); |
e7932188 JT |
195 | } |
196 | ||
08e875c1 CM |
197 | /* |
198 | * This is the secondary CPU boot entry. We're using this CPUs | |
199 | * idle thread stack, but a set of temporary page tables. | |
200 | */ | |
b154886f | 201 | asmlinkage notrace void secondary_start_kernel(void) |
08e875c1 | 202 | { |
ccaac162 | 203 | u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; |
08e875c1 | 204 | struct mm_struct *mm = &init_mm; |
de58ed5e | 205 | const struct cpu_operations *ops; |
3d8c1a01 | 206 | unsigned int cpu = smp_processor_id(); |
08e875c1 | 207 | |
08e875c1 CM |
208 | /* |
209 | * All kernel threads share the same mm context; grab a | |
210 | * reference and switch to it. | |
211 | */ | |
f1f10076 | 212 | mmgrab(mm); |
08e875c1 | 213 | current->active_mm = mm; |
08e875c1 CM |
214 | |
215 | /* | |
216 | * TTBR0 is only used for the identity mapping at this stage. Make it | |
217 | * point to zero page to avoid speculatively fetching new entries. | |
218 | */ | |
9e8e865b | 219 | cpu_uninstall_idmap(); |
08e875c1 | 220 | |
e7932188 JT |
221 | if (system_uses_irq_prio_masking()) |
222 | init_gic_priority_masking(); | |
223 | ||
448e9f34 | 224 | rcutree_report_cpu_starting(cpu); |
08e875c1 CM |
225 | trace_hardirqs_off(); |
226 | ||
dbb4e152 SP |
227 | /* |
228 | * If the system has established the capabilities, make sure | |
229 | * this CPU ticks all of those. If it doesn't, the CPU will | |
230 | * fail to come online. | |
231 | */ | |
c47a1900 | 232 | check_local_cpu_capabilities(); |
dbb4e152 | 233 | |
de58ed5e GS |
234 | ops = get_cpu_ops(cpu); |
235 | if (ops->cpu_postboot) | |
236 | ops->cpu_postboot(); | |
08e875c1 | 237 | |
df857416 MR |
238 | /* |
239 | * Log the CPU info before it is marked online and might get read. | |
240 | */ | |
241 | cpuinfo_store_cpu(); | |
5524cbb1 | 242 | store_cpu_topology(cpu); |
df857416 | 243 | |
7ade67b5 MZ |
244 | /* |
245 | * Enable GIC and timers. | |
246 | */ | |
247 | notify_cpu_starting(cpu); | |
248 | ||
d3afc7f1 MZ |
249 | ipi_setup(cpu); |
250 | ||
97fd6016 | 251 | numa_add_cpu(cpu); |
f6e763b9 | 252 | |
08e875c1 CM |
253 | /* |
254 | * OK, now it's safe to let the boot CPU continue. Wait for | |
255 | * the CPU migration code to notice that the CPU is online | |
256 | * before we continue. | |
257 | */ | |
ccaac162 MR |
258 | pr_info("CPU%u: Booted secondary processor 0x%010lx [0x%08x]\n", |
259 | cpu, (unsigned long)mpidr, | |
260 | read_cpuid_id()); | |
bb905274 | 261 | update_cpu_boot_status(CPU_BOOT_SUCCESS); |
08e875c1 | 262 | set_cpu_online(cpu, true); |
b3770b32 | 263 | complete(&cpu_running); |
08e875c1 | 264 | |
080297be MR |
265 | /* |
266 | * Secondary CPUs enter the kernel with all DAIF exceptions masked. | |
267 | * | |
268 | * As with setup_arch() we must unmask Debug and SError exceptions, and | |
269 | * as the root irqchip has already been detected and initialized we can | |
270 | * unmask IRQ and FIQ at the same time. | |
271 | */ | |
41bd5b5d | 272 | local_daif_restore(DAIF_PROCCTX); |
53ae3acd | 273 | |
08e875c1 CM |
274 | /* |
275 | * OK, it's off to the idle thread for us | |
276 | */ | |
fc6d73d6 | 277 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
08e875c1 CM |
278 | } |
279 | ||
9327e2c6 MR |
280 | #ifdef CONFIG_HOTPLUG_CPU |
281 | static int op_cpu_disable(unsigned int cpu) | |
282 | { | |
de58ed5e GS |
283 | const struct cpu_operations *ops = get_cpu_ops(cpu); |
284 | ||
9327e2c6 MR |
285 | /* |
286 | * If we don't have a cpu_die method, abort before we reach the point | |
287 | * of no return. CPU0 may not have an cpu_ops, so test for it. | |
288 | */ | |
de58ed5e | 289 | if (!ops || !ops->cpu_die) |
9327e2c6 MR |
290 | return -EOPNOTSUPP; |
291 | ||
292 | /* | |
293 | * We may need to abort a hot unplug for some other mechanism-specific | |
294 | * reason. | |
295 | */ | |
de58ed5e GS |
296 | if (ops->cpu_disable) |
297 | return ops->cpu_disable(cpu); | |
9327e2c6 MR |
298 | |
299 | return 0; | |
300 | } | |
301 | ||
302 | /* | |
303 | * __cpu_disable runs on the processor to be shutdown. | |
304 | */ | |
305 | int __cpu_disable(void) | |
306 | { | |
307 | unsigned int cpu = smp_processor_id(); | |
308 | int ret; | |
309 | ||
310 | ret = op_cpu_disable(cpu); | |
311 | if (ret) | |
312 | return ret; | |
313 | ||
7f9545aa SH |
314 | remove_cpu_topology(cpu); |
315 | numa_remove_cpu(cpu); | |
316 | ||
9327e2c6 MR |
317 | /* |
318 | * Take this CPU offline. Once we clear this, we can't return, | |
319 | * and we must not schedule until we're ready to give up the cpu. | |
320 | */ | |
321 | set_cpu_online(cpu, false); | |
d3afc7f1 | 322 | ipi_teardown(cpu); |
9327e2c6 MR |
323 | |
324 | /* | |
325 | * OK - migrate IRQs away from this CPU | |
326 | */ | |
217d453d YY |
327 | irq_migrate_all_off_this_cpu(); |
328 | ||
9327e2c6 MR |
329 | return 0; |
330 | } | |
331 | ||
c814ca02 AC |
332 | static int op_cpu_kill(unsigned int cpu) |
333 | { | |
de58ed5e GS |
334 | const struct cpu_operations *ops = get_cpu_ops(cpu); |
335 | ||
c814ca02 AC |
336 | /* |
337 | * If we have no means of synchronising with the dying CPU, then assume | |
338 | * that it is really dead. We can only wait for an arbitrary length of | |
339 | * time and hope that it's dead, so let's skip the wait and just hope. | |
340 | */ | |
de58ed5e | 341 | if (!ops->cpu_kill) |
6b99c68c | 342 | return 0; |
c814ca02 | 343 | |
de58ed5e | 344 | return ops->cpu_kill(cpu); |
c814ca02 AC |
345 | } |
346 | ||
9327e2c6 | 347 | /* |
b3091f17 TG |
348 | * Called on the thread which is asking for a CPU to be shutdown after the |
349 | * shutdown completed. | |
9327e2c6 | 350 | */ |
b3091f17 | 351 | void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) |
9327e2c6 | 352 | { |
6b99c68c MR |
353 | int err; |
354 | ||
cf814bcf | 355 | pr_debug("CPU%u: shutdown\n", cpu); |
c814ca02 AC |
356 | |
357 | /* | |
358 | * Now that the dying CPU is beyond the point of no return w.r.t. | |
359 | * in-kernel synchronisation, try to get the firwmare to help us to | |
360 | * verify that it has really left the kernel before we consider | |
361 | * clobbering anything it might still be using. | |
362 | */ | |
6b99c68c MR |
363 | err = op_cpu_kill(cpu); |
364 | if (err) | |
a74ec64a | 365 | pr_warn("CPU%d may not have shut down cleanly: %d\n", cpu, err); |
9327e2c6 MR |
366 | } |
367 | ||
368 | /* | |
369 | * Called from the idle thread for the CPU which has been shutdown. | |
370 | * | |
9327e2c6 | 371 | */ |
9bdc61ef | 372 | void __noreturn cpu_die(void) |
9327e2c6 MR |
373 | { |
374 | unsigned int cpu = smp_processor_id(); | |
de58ed5e | 375 | const struct cpu_operations *ops = get_cpu_ops(cpu); |
9327e2c6 MR |
376 | |
377 | idle_task_exit(); | |
378 | ||
0fbeb318 | 379 | local_daif_mask(); |
9327e2c6 | 380 | |
b3091f17 TG |
381 | /* Tell cpuhp_bp_sync_dead() that this CPU is now safe to dispose of */ |
382 | cpuhp_ap_report_dead(); | |
9327e2c6 MR |
383 | |
384 | /* | |
385 | * Actually shutdown the CPU. This must never fail. The specific hotplug | |
386 | * mechanism must perform all required cache maintenance to ensure that | |
387 | * no dirty lines are lost in the process of shutting down the CPU. | |
388 | */ | |
de58ed5e | 389 | ops->cpu_die(cpu); |
9327e2c6 MR |
390 | |
391 | BUG(); | |
392 | } | |
393 | #endif | |
394 | ||
de58ed5e GS |
395 | static void __cpu_try_die(int cpu) |
396 | { | |
397 | #ifdef CONFIG_HOTPLUG_CPU | |
398 | const struct cpu_operations *ops = get_cpu_ops(cpu); | |
399 | ||
400 | if (ops && ops->cpu_die) | |
401 | ops->cpu_die(cpu); | |
402 | #endif | |
403 | } | |
404 | ||
fce6361f SP |
405 | /* |
406 | * Kill the calling secondary CPU, early in bringup before it is turned | |
407 | * online. | |
408 | */ | |
5ab6876c | 409 | void __noreturn cpu_die_early(void) |
fce6361f SP |
410 | { |
411 | int cpu = smp_processor_id(); | |
412 | ||
413 | pr_crit("CPU%d: will not boot\n", cpu); | |
414 | ||
415 | /* Mark this CPU absent */ | |
416 | set_cpu_present(cpu, 0); | |
448e9f34 | 417 | rcutree_report_cpu_dead(); |
fce6361f | 418 | |
de58ed5e GS |
419 | if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) { |
420 | update_cpu_boot_status(CPU_KILL_ME); | |
421 | __cpu_try_die(cpu); | |
422 | } | |
423 | ||
bb905274 | 424 | update_cpu_boot_status(CPU_STUCK_IN_KERNEL); |
fce6361f SP |
425 | |
426 | cpu_park_loop(); | |
427 | } | |
428 | ||
377bcff9 JR |
429 | static void __init hyp_mode_check(void) |
430 | { | |
431 | if (is_hyp_mode_available()) | |
432 | pr_info("CPU: All CPU(s) started at EL2\n"); | |
433 | else if (is_hyp_mode_mismatched()) | |
434 | WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC, | |
435 | "CPU: CPUs started in inconsistent modes"); | |
436 | else | |
437 | pr_info("CPU: All CPU(s) started at EL1\n"); | |
6ec6259d | 438 | if (IS_ENABLED(CONFIG_KVM) && !is_kernel_in_hyp_mode()) { |
0492747c | 439 | kvm_compute_layout(); |
6ec6259d DB |
440 | kvm_apply_hyp_relocations(); |
441 | } | |
377bcff9 JR |
442 | } |
443 | ||
08e875c1 CM |
444 | void __init smp_cpus_done(unsigned int max_cpus) |
445 | { | |
326b16db | 446 | pr_info("SMP: Total of %d processors activated.\n", num_online_cpus()); |
377bcff9 | 447 | hyp_mode_check(); |
63a2d92e | 448 | setup_system_features(); |
075f48c9 | 449 | setup_user_features(); |
5ea5306c | 450 | mark_linear_text_alias_ro(); |
08e875c1 CM |
451 | } |
452 | ||
453 | void __init smp_prepare_boot_cpu(void) | |
454 | { | |
3d8c1a01 MR |
455 | /* |
456 | * The runtime per-cpu areas have been allocated by | |
457 | * setup_per_cpu_areas(), and CPU0's boot time per-cpu area will be | |
458 | * freed shortly, so we must move over to the runtime per-cpu area. | |
459 | */ | |
9113c2aa | 460 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
0ceb0d56 | 461 | |
eb15d707 MR |
462 | cpuinfo_store_boot_cpu(); |
463 | setup_boot_cpu_features(); | |
e7932188 JT |
464 | |
465 | /* Conditionally switch to GIC PMR for interrupt masking */ | |
466 | if (system_uses_irq_prio_masking()) | |
467 | init_gic_priority_masking(); | |
2e903b91 AK |
468 | |
469 | kasan_init_hw_tags(); | |
f75c2355 SH |
470 | /* Init percpu seeds for random tags after cpus are set up. */ |
471 | kasan_init_sw_tags(); | |
08e875c1 CM |
472 | } |
473 | ||
0f078336 LP |
474 | /* |
475 | * Duplicate MPIDRs are a recipe for disaster. Scan all initialized | |
476 | * entries and check for duplicates. If any is found just ignore the | |
477 | * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid | |
478 | * matching valid MPIDR values. | |
479 | */ | |
480 | static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid) | |
481 | { | |
482 | unsigned int i; | |
483 | ||
484 | for (i = 1; (i < cpu) && (i < NR_CPUS); i++) | |
485 | if (cpu_logical_map(i) == hwid) | |
486 | return true; | |
487 | return false; | |
488 | } | |
489 | ||
819a8826 LP |
490 | /* |
491 | * Initialize cpu operations for a logical cpu and | |
492 | * set it in the possible mask on success | |
493 | */ | |
494 | static int __init smp_cpu_setup(int cpu) | |
495 | { | |
de58ed5e GS |
496 | const struct cpu_operations *ops; |
497 | ||
6885fb12 | 498 | if (init_cpu_ops(cpu)) |
819a8826 LP |
499 | return -ENODEV; |
500 | ||
de58ed5e GS |
501 | ops = get_cpu_ops(cpu); |
502 | if (ops->cpu_init(cpu)) | |
819a8826 LP |
503 | return -ENODEV; |
504 | ||
505 | set_cpu_possible(cpu, true); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
0f078336 LP |
510 | static bool bootcpu_valid __initdata; |
511 | static unsigned int cpu_count = 1; | |
512 | ||
eba46750 JC |
513 | int arch_register_cpu(int cpu) |
514 | { | |
515 | acpi_handle acpi_handle = acpi_get_processor_handle(cpu); | |
516 | struct cpu *c = &per_cpu(cpu_devices, cpu); | |
517 | ||
518 | if (!acpi_disabled && !acpi_handle && | |
519 | IS_ENABLED(CONFIG_ACPI_HOTPLUG_CPU)) | |
520 | return -EPROBE_DEFER; | |
521 | ||
522 | #ifdef CONFIG_ACPI_HOTPLUG_CPU | |
523 | /* For now block anything that looks like physical CPU Hotplug */ | |
524 | if (invalid_logical_cpuid(cpu) || !cpu_present(cpu)) { | |
525 | pr_err_once("Changing CPU present bit is not supported\n"); | |
526 | return -ENODEV; | |
527 | } | |
528 | #endif | |
529 | ||
530 | /* | |
531 | * Availability of the acpi handle is sufficient to establish | |
532 | * that _STA has aleady been checked. No need to recheck here. | |
533 | */ | |
534 | c->hotpluggable = arch_cpu_is_hotpluggable(cpu); | |
535 | ||
536 | return register_cpu(c, cpu); | |
537 | } | |
538 | ||
539 | #ifdef CONFIG_ACPI_HOTPLUG_CPU | |
540 | void arch_unregister_cpu(int cpu) | |
541 | { | |
542 | acpi_handle acpi_handle = acpi_get_processor_handle(cpu); | |
543 | struct cpu *c = &per_cpu(cpu_devices, cpu); | |
544 | acpi_status status; | |
545 | unsigned long long sta; | |
546 | ||
547 | if (!acpi_handle) { | |
548 | pr_err_once("Removing a CPU without associated ACPI handle\n"); | |
549 | return; | |
550 | } | |
551 | ||
552 | status = acpi_evaluate_integer(acpi_handle, "_STA", NULL, &sta); | |
553 | if (ACPI_FAILURE(status)) | |
554 | return; | |
555 | ||
556 | /* For now do not allow anything that looks like physical CPU HP */ | |
557 | if (cpu_present(cpu) && !(sta & ACPI_STA_DEVICE_PRESENT)) { | |
558 | pr_err_once("Changing CPU present bit is not supported\n"); | |
559 | return; | |
560 | } | |
561 | ||
562 | unregister_cpu(c); | |
563 | } | |
564 | #endif /* CONFIG_ACPI_HOTPLUG_CPU */ | |
565 | ||
0f078336 | 566 | #ifdef CONFIG_ACPI |
e0013aed MR |
567 | static struct acpi_madt_generic_interrupt cpu_madt_gicc[NR_CPUS]; |
568 | ||
569 | struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu) | |
570 | { | |
571 | return &cpu_madt_gicc[cpu]; | |
572 | } | |
d3c3db41 | 573 | EXPORT_SYMBOL_GPL(acpi_cpu_get_madt_gicc); |
e0013aed | 574 | |
0f078336 LP |
575 | /* |
576 | * acpi_map_gic_cpu_interface - parse processor MADT entry | |
577 | * | |
578 | * Carry out sanity checks on MADT processor entry and initialize | |
579 | * cpu_logical_map on success | |
580 | */ | |
581 | static void __init | |
582 | acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) | |
583 | { | |
584 | u64 hwid = processor->arm_mpidr; | |
585 | ||
d633da5d JM |
586 | if (!(processor->flags & |
587 | (ACPI_MADT_ENABLED | ACPI_MADT_GICC_ONLINE_CAPABLE))) { | |
f9058929 | 588 | pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); |
0f078336 LP |
589 | return; |
590 | } | |
591 | ||
f9058929 HG |
592 | if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { |
593 | pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); | |
0f078336 LP |
594 | return; |
595 | } | |
596 | ||
597 | if (is_mpidr_duplicate(cpu_count, hwid)) { | |
598 | pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid); | |
599 | return; | |
600 | } | |
601 | ||
602 | /* Check if GICC structure of boot CPU is available in the MADT */ | |
603 | if (cpu_logical_map(0) == hwid) { | |
604 | if (bootcpu_valid) { | |
605 | pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n", | |
606 | hwid); | |
607 | return; | |
608 | } | |
609 | bootcpu_valid = true; | |
e0013aed | 610 | cpu_madt_gicc[0] = *processor; |
0f078336 LP |
611 | return; |
612 | } | |
613 | ||
614 | if (cpu_count >= NR_CPUS) | |
615 | return; | |
616 | ||
617 | /* map the logical cpu id to cpu MPIDR */ | |
eaecca9e | 618 | set_cpu_logical_map(cpu_count, hwid); |
0f078336 | 619 | |
e0013aed MR |
620 | cpu_madt_gicc[cpu_count] = *processor; |
621 | ||
5e89c55e LP |
622 | /* |
623 | * Set-up the ACPI parking protocol cpu entries | |
624 | * while initializing the cpu_logical_map to | |
625 | * avoid parsing MADT entries multiple times for | |
626 | * nothing (ie a valid cpu_logical_map entry should | |
627 | * contain a valid parking protocol data set to | |
628 | * initialize the cpu if the parking protocol is | |
629 | * the only available enable method). | |
630 | */ | |
631 | acpi_set_mailbox_entry(cpu_count, processor); | |
632 | ||
0f078336 LP |
633 | cpu_count++; |
634 | } | |
635 | ||
636 | static int __init | |
60574d1e | 637 | acpi_parse_gic_cpu_interface(union acpi_subtable_headers *header, |
0f078336 LP |
638 | const unsigned long end) |
639 | { | |
640 | struct acpi_madt_generic_interrupt *processor; | |
641 | ||
642 | processor = (struct acpi_madt_generic_interrupt *)header; | |
99e3e3ae | 643 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
0f078336 LP |
644 | return -EINVAL; |
645 | ||
60574d1e | 646 | acpi_table_print_madt_entry(&header->common); |
0f078336 LP |
647 | |
648 | acpi_map_gic_cpu_interface(processor); | |
649 | ||
650 | return 0; | |
651 | } | |
e1896249 LP |
652 | |
653 | static void __init acpi_parse_and_init_cpus(void) | |
654 | { | |
655 | int i; | |
656 | ||
657 | /* | |
658 | * do a walk of MADT to determine how many CPUs | |
659 | * we have including disabled CPUs, and get information | |
660 | * we need for SMP init. | |
661 | */ | |
662 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
663 | acpi_parse_gic_cpu_interface, 0); | |
664 | ||
665 | /* | |
666 | * In ACPI, SMP and CPU NUMA information is provided in separate | |
667 | * static tables, namely the MADT and the SRAT. | |
668 | * | |
669 | * Thus, it is simpler to first create the cpu logical map through | |
670 | * an MADT walk and then map the logical cpus to their node ids | |
671 | * as separate steps. | |
672 | */ | |
673 | acpi_map_cpus_to_nodes(); | |
674 | ||
675 | for (i = 0; i < nr_cpu_ids; i++) | |
676 | early_map_cpu_to_node(i, acpi_numa_get_nid(i)); | |
677 | } | |
0f078336 | 678 | #else |
e1896249 | 679 | #define acpi_parse_and_init_cpus(...) do { } while (0) |
0f078336 LP |
680 | #endif |
681 | ||
08e875c1 | 682 | /* |
4c7aa002 JM |
683 | * Enumerate the possible CPU set from the device tree and build the |
684 | * cpu logical map array containing MPIDR values related to logical | |
685 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
08e875c1 | 686 | */ |
29b8302b | 687 | static void __init of_parse_and_init_cpus(void) |
08e875c1 | 688 | { |
3d29a9a0 | 689 | struct device_node *dn; |
08e875c1 | 690 | |
de76e70a | 691 | for_each_of_cpu_node(dn) { |
4d97b929 | 692 | u64 hwid = of_get_cpu_hwid(dn, 0); |
4c7aa002 | 693 | |
4d97b929 | 694 | if (hwid & ~MPIDR_HWID_BITMASK) |
4c7aa002 | 695 | goto next; |
4c7aa002 | 696 | |
0f078336 | 697 | if (is_mpidr_duplicate(cpu_count, hwid)) { |
a270f327 RH |
698 | pr_err("%pOF: duplicate cpu reg properties in the DT\n", |
699 | dn); | |
4c7aa002 JM |
700 | goto next; |
701 | } | |
702 | ||
4c7aa002 JM |
703 | /* |
704 | * The numbering scheme requires that the boot CPU | |
705 | * must be assigned logical id 0. Record it so that | |
706 | * the logical map built from DT is validated and can | |
707 | * be used. | |
708 | */ | |
709 | if (hwid == cpu_logical_map(0)) { | |
710 | if (bootcpu_valid) { | |
a270f327 RH |
711 | pr_err("%pOF: duplicate boot cpu reg property in DT\n", |
712 | dn); | |
4c7aa002 JM |
713 | goto next; |
714 | } | |
715 | ||
716 | bootcpu_valid = true; | |
7ba5f605 | 717 | early_map_cpu_to_node(0, of_node_to_nid(dn)); |
4c7aa002 JM |
718 | |
719 | /* | |
720 | * cpu_logical_map has already been | |
721 | * initialized and the boot cpu doesn't need | |
722 | * the enable-method so continue without | |
723 | * incrementing cpu. | |
724 | */ | |
725 | continue; | |
726 | } | |
727 | ||
0f078336 | 728 | if (cpu_count >= NR_CPUS) |
08e875c1 CM |
729 | goto next; |
730 | ||
4c7aa002 | 731 | pr_debug("cpu logical map 0x%llx\n", hwid); |
eaecca9e | 732 | set_cpu_logical_map(cpu_count, hwid); |
1a2db300 GK |
733 | |
734 | early_map_cpu_to_node(cpu_count, of_node_to_nid(dn)); | |
08e875c1 | 735 | next: |
0f078336 | 736 | cpu_count++; |
08e875c1 | 737 | } |
0f078336 LP |
738 | } |
739 | ||
740 | /* | |
741 | * Enumerate the possible CPU set from the device tree or ACPI and build the | |
742 | * cpu logical map array containing MPIDR values related to logical | |
743 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
744 | */ | |
745 | void __init smp_init_cpus(void) | |
746 | { | |
747 | int i; | |
748 | ||
749 | if (acpi_disabled) | |
750 | of_parse_and_init_cpus(); | |
751 | else | |
e1896249 | 752 | acpi_parse_and_init_cpus(); |
08e875c1 | 753 | |
50ee91bd | 754 | if (cpu_count > nr_cpu_ids) |
9b130ad5 | 755 | pr_warn("Number of cores (%d) exceeds configured maximum of %u - clipping\n", |
50ee91bd | 756 | cpu_count, nr_cpu_ids); |
4c7aa002 JM |
757 | |
758 | if (!bootcpu_valid) { | |
0f078336 | 759 | pr_err("missing boot CPU MPIDR, not enabling secondaries\n"); |
4c7aa002 JM |
760 | return; |
761 | } | |
762 | ||
763 | /* | |
819a8826 LP |
764 | * We need to set the cpu_logical_map entries before enabling |
765 | * the cpus so that cpu processor description entries (DT cpu nodes | |
766 | * and ACPI MADT entries) can be retrieved by matching the cpu hwid | |
767 | * with entries in cpu_logical_map while initializing the cpus. | |
768 | * If the cpu set-up fails, invalidate the cpu_logical_map entry. | |
4c7aa002 | 769 | */ |
50ee91bd | 770 | for (i = 1; i < nr_cpu_ids; i++) { |
819a8826 LP |
771 | if (cpu_logical_map(i) != INVALID_HWID) { |
772 | if (smp_cpu_setup(i)) | |
eaecca9e | 773 | set_cpu_logical_map(i, INVALID_HWID); |
819a8826 LP |
774 | } |
775 | } | |
08e875c1 CM |
776 | } |
777 | ||
778 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
779 | { | |
de58ed5e | 780 | const struct cpu_operations *ops; |
cd1aebf5 | 781 | int err; |
44dbcc93 | 782 | unsigned int cpu; |
c18df0ad | 783 | unsigned int this_cpu; |
08e875c1 | 784 | |
f6e763b9 MB |
785 | init_cpu_topology(); |
786 | ||
c18df0ad DD |
787 | this_cpu = smp_processor_id(); |
788 | store_cpu_topology(this_cpu); | |
789 | numa_store_cpu_info(this_cpu); | |
97fd6016 | 790 | numa_add_cpu(this_cpu); |
f6e763b9 | 791 | |
e75118a7 SP |
792 | /* |
793 | * If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set | |
794 | * secondary CPUs present. | |
795 | */ | |
796 | if (max_cpus == 0) | |
797 | return; | |
798 | ||
08e875c1 CM |
799 | /* |
800 | * Initialise the present map (which describes the set of CPUs | |
801 | * actually populated at the present time) and release the | |
802 | * secondaries from the bootloader. | |
803 | */ | |
804 | for_each_possible_cpu(cpu) { | |
08e875c1 | 805 | |
d329de3f MZ |
806 | if (cpu == smp_processor_id()) |
807 | continue; | |
808 | ||
de58ed5e GS |
809 | ops = get_cpu_ops(cpu); |
810 | if (!ops) | |
08e875c1 CM |
811 | continue; |
812 | ||
de58ed5e | 813 | err = ops->cpu_prepare(cpu); |
d329de3f MZ |
814 | if (err) |
815 | continue; | |
08e875c1 CM |
816 | |
817 | set_cpu_present(cpu, true); | |
c18df0ad | 818 | numa_store_cpu_info(cpu); |
08e875c1 | 819 | } |
08e875c1 CM |
820 | } |
821 | ||
916b93f4 | 822 | static const char *ipi_types[MAX_IPI] __tracepoint_string = { |
0edaee42 AK |
823 | [IPI_RESCHEDULE] = "Rescheduling interrupts", |
824 | [IPI_CALL_FUNC] = "Function call interrupts", | |
825 | [IPI_CPU_STOP] = "CPU stop interrupts", | |
826 | [IPI_CPU_CRASH_STOP] = "CPU stop (for crash dump) interrupts", | |
827 | [IPI_TIMER] = "Timer broadcast interrupts", | |
828 | [IPI_IRQ_WORK] = "IRQ work interrupts", | |
916b93f4 JR |
829 | [IPI_CPU_BACKTRACE] = "CPU backtrace interrupts", |
830 | [IPI_KGDB_ROUNDUP] = "KGDB roundup interrupts", | |
08e875c1 CM |
831 | }; |
832 | ||
5cebfd2d | 833 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr); |
45ed695a | 834 | |
a2638815 MZ |
835 | unsigned long irq_err_count; |
836 | ||
837 | int arch_show_interrupts(struct seq_file *p, int prec) | |
08e875c1 CM |
838 | { |
839 | unsigned int cpu, i; | |
840 | ||
916b93f4 | 841 | for (i = 0; i < MAX_IPI; i++) { |
45ed695a | 842 | seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, |
08e875c1 | 843 | prec >= 4 ? " " : ""); |
67317c26 | 844 | for_each_online_cpu(cpu) |
5089bc51 | 845 | seq_printf(p, "%10u ", irq_desc_kstat_cpu(ipi_desc[i], cpu)); |
08e875c1 CM |
846 | seq_printf(p, " %s\n", ipi_types[i]); |
847 | } | |
08e875c1 | 848 | |
a2638815 MZ |
849 | seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); |
850 | return 0; | |
08e875c1 CM |
851 | } |
852 | ||
45ed695a NP |
853 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
854 | { | |
855 | smp_cross_call(mask, IPI_CALL_FUNC); | |
856 | } | |
857 | ||
858 | void arch_send_call_function_single_ipi(int cpu) | |
859 | { | |
0aaf0dae | 860 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
45ed695a NP |
861 | } |
862 | ||
863 | #ifdef CONFIG_IRQ_WORK | |
864 | void arch_irq_work_raise(void) | |
865 | { | |
5cebfd2d | 866 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); |
45ed695a NP |
867 | } |
868 | #endif | |
869 | ||
5ab6876c | 870 | static void __noreturn local_cpu_stop(void) |
08e875c1 | 871 | { |
d914d4d4 | 872 | set_cpu_online(smp_processor_id(), false); |
08e875c1 | 873 | |
0fbeb318 | 874 | local_daif_mask(); |
f5df2696 | 875 | sdei_mask_local_cpu(); |
dccc9da2 | 876 | cpu_park_loop(); |
08e875c1 | 877 | } |
08e875c1 | 878 | |
d914d4d4 AK |
879 | /* |
880 | * We need to implement panic_smp_self_stop() for parallel panic() calls, so | |
881 | * that cpu_online_mask gets correctly updated and smp_send_stop() can skip | |
882 | * CPUs that have already stopped themselves. | |
883 | */ | |
7412a60d | 884 | void __noreturn panic_smp_self_stop(void) |
d914d4d4 AK |
885 | { |
886 | local_cpu_stop(); | |
08e875c1 CM |
887 | } |
888 | ||
78fd584c AT |
889 | #ifdef CONFIG_KEXEC_CORE |
890 | static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0); | |
891 | #endif | |
892 | ||
5ab6876c | 893 | static void __noreturn ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) |
78fd584c AT |
894 | { |
895 | #ifdef CONFIG_KEXEC_CORE | |
896 | crash_save_cpu(regs, cpu); | |
897 | ||
898 | atomic_dec(&waiting_for_crash_ipi); | |
899 | ||
900 | local_irq_disable(); | |
f5df2696 | 901 | sdei_mask_local_cpu(); |
78fd584c | 902 | |
de58ed5e GS |
903 | if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) |
904 | __cpu_try_die(cpu); | |
78fd584c AT |
905 | |
906 | /* just in case */ | |
907 | cpu_park_loop(); | |
5ab6876c JP |
908 | #else |
909 | BUG(); | |
78fd584c AT |
910 | #endif |
911 | } | |
912 | ||
331a1b3a DA |
913 | static void arm64_backtrace_ipi(cpumask_t *mask) |
914 | { | |
915 | __ipi_send_mask(ipi_desc[IPI_CPU_BACKTRACE], mask); | |
916 | } | |
917 | ||
918 | void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu) | |
919 | { | |
920 | /* | |
921 | * NOTE: though nmi_trigger_cpumask_backtrace() has "nmi_" in the name, | |
922 | * nothing about it truly needs to be implemented using an NMI, it's | |
923 | * just that it's _allowed_ to work with NMIs. If ipi_should_be_nmi() | |
924 | * returned false our backtrace attempt will just use a regular IPI. | |
925 | */ | |
926 | nmi_trigger_cpumask_backtrace(mask, exclude_cpu, arm64_backtrace_ipi); | |
927 | } | |
928 | ||
2f5cd0c7 DA |
929 | #ifdef CONFIG_KGDB |
930 | void kgdb_roundup_cpus(void) | |
931 | { | |
932 | int this_cpu = raw_smp_processor_id(); | |
933 | int cpu; | |
934 | ||
935 | for_each_online_cpu(cpu) { | |
936 | /* No need to roundup ourselves */ | |
937 | if (cpu == this_cpu) | |
938 | continue; | |
939 | ||
940 | __ipi_send_single(ipi_desc[IPI_KGDB_ROUNDUP], cpu); | |
941 | } | |
942 | } | |
943 | #endif | |
944 | ||
08e875c1 CM |
945 | /* |
946 | * Main handler for inter-processor interrupts | |
947 | */ | |
d3afc7f1 | 948 | static void do_handle_IPI(int ipinr) |
08e875c1 CM |
949 | { |
950 | unsigned int cpu = smp_processor_id(); | |
08e875c1 | 951 | |
a2638815 | 952 | if ((unsigned)ipinr < NR_IPI) |
4a3182e6 | 953 | trace_ipi_entry(ipi_types[ipinr]); |
08e875c1 CM |
954 | |
955 | switch (ipinr) { | |
956 | case IPI_RESCHEDULE: | |
957 | scheduler_ipi(); | |
958 | break; | |
959 | ||
960 | case IPI_CALL_FUNC: | |
08e875c1 | 961 | generic_smp_call_function_interrupt(); |
08e875c1 CM |
962 | break; |
963 | ||
08e875c1 | 964 | case IPI_CPU_STOP: |
d914d4d4 | 965 | local_cpu_stop(); |
08e875c1 CM |
966 | break; |
967 | ||
78fd584c AT |
968 | case IPI_CPU_CRASH_STOP: |
969 | if (IS_ENABLED(CONFIG_KEXEC_CORE)) { | |
d3afc7f1 | 970 | ipi_cpu_crash_stop(cpu, get_irq_regs()); |
78fd584c AT |
971 | |
972 | unreachable(); | |
973 | } | |
974 | break; | |
975 | ||
1f85008e LP |
976 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
977 | case IPI_TIMER: | |
1f85008e | 978 | tick_receive_broadcast(); |
1f85008e LP |
979 | break; |
980 | #endif | |
981 | ||
eb631bb5 LB |
982 | #ifdef CONFIG_IRQ_WORK |
983 | case IPI_IRQ_WORK: | |
eb631bb5 | 984 | irq_work_run(); |
eb631bb5 LB |
985 | break; |
986 | #endif | |
987 | ||
331a1b3a DA |
988 | case IPI_CPU_BACKTRACE: |
989 | /* | |
990 | * NOTE: in some cases this _won't_ be NMI context. See the | |
991 | * comment in arch_trigger_cpumask_backtrace(). | |
992 | */ | |
993 | nmi_cpu_backtrace(get_irq_regs()); | |
994 | break; | |
995 | ||
2f5cd0c7 DA |
996 | case IPI_KGDB_ROUNDUP: |
997 | kgdb_nmicallback(cpu, get_irq_regs()); | |
5e89c55e | 998 | break; |
5e89c55e | 999 | |
08e875c1 CM |
1000 | default: |
1001 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); | |
1002 | break; | |
1003 | } | |
45ed695a NP |
1004 | |
1005 | if ((unsigned)ipinr < NR_IPI) | |
4a3182e6 | 1006 | trace_ipi_exit(ipi_types[ipinr]); |
d3afc7f1 MZ |
1007 | } |
1008 | ||
d3afc7f1 MZ |
1009 | static irqreturn_t ipi_handler(int irq, void *data) |
1010 | { | |
1011 | do_handle_IPI(irq - ipi_irq_base); | |
1012 | return IRQ_HANDLED; | |
1013 | } | |
1014 | ||
5cebfd2d | 1015 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
d3afc7f1 | 1016 | { |
5cebfd2d MZ |
1017 | trace_ipi_raise(target, ipi_types[ipinr]); |
1018 | __ipi_send_mask(ipi_desc[ipinr], target); | |
d3afc7f1 MZ |
1019 | } |
1020 | ||
331a1b3a DA |
1021 | static bool ipi_should_be_nmi(enum ipi_msg_type ipi) |
1022 | { | |
4bb49009 | 1023 | if (!system_uses_irq_prio_masking()) |
331a1b3a DA |
1024 | return false; |
1025 | ||
1026 | switch (ipi) { | |
d7402513 DA |
1027 | case IPI_CPU_STOP: |
1028 | case IPI_CPU_CRASH_STOP: | |
331a1b3a | 1029 | case IPI_CPU_BACKTRACE: |
2f5cd0c7 | 1030 | case IPI_KGDB_ROUNDUP: |
331a1b3a DA |
1031 | return true; |
1032 | default: | |
1033 | return false; | |
1034 | } | |
1035 | } | |
1036 | ||
d3afc7f1 MZ |
1037 | static void ipi_setup(int cpu) |
1038 | { | |
1039 | int i; | |
1040 | ||
5cebfd2d | 1041 | if (WARN_ON_ONCE(!ipi_irq_base)) |
d3afc7f1 MZ |
1042 | return; |
1043 | ||
331a1b3a DA |
1044 | for (i = 0; i < nr_ipi; i++) { |
1045 | if (ipi_should_be_nmi(i)) { | |
1046 | prepare_percpu_nmi(ipi_irq_base + i); | |
1047 | enable_percpu_nmi(ipi_irq_base + i, 0); | |
1048 | } else { | |
1049 | enable_percpu_irq(ipi_irq_base + i, 0); | |
1050 | } | |
1051 | } | |
d3afc7f1 MZ |
1052 | } |
1053 | ||
9d9edb96 | 1054 | #ifdef CONFIG_HOTPLUG_CPU |
d3afc7f1 MZ |
1055 | static void ipi_teardown(int cpu) |
1056 | { | |
1057 | int i; | |
1058 | ||
5cebfd2d | 1059 | if (WARN_ON_ONCE(!ipi_irq_base)) |
d3afc7f1 MZ |
1060 | return; |
1061 | ||
331a1b3a DA |
1062 | for (i = 0; i < nr_ipi; i++) { |
1063 | if (ipi_should_be_nmi(i)) { | |
1064 | disable_percpu_nmi(ipi_irq_base + i); | |
1065 | teardown_percpu_nmi(ipi_irq_base + i); | |
1066 | } else { | |
1067 | disable_percpu_irq(ipi_irq_base + i); | |
1068 | } | |
1069 | } | |
d3afc7f1 | 1070 | } |
9d9edb96 | 1071 | #endif |
d3afc7f1 MZ |
1072 | |
1073 | void __init set_smp_ipi_range(int ipi_base, int n) | |
1074 | { | |
1075 | int i; | |
1076 | ||
331a1b3a DA |
1077 | WARN_ON(n < MAX_IPI); |
1078 | nr_ipi = min(n, MAX_IPI); | |
d3afc7f1 MZ |
1079 | |
1080 | for (i = 0; i < nr_ipi; i++) { | |
1081 | int err; | |
1082 | ||
331a1b3a DA |
1083 | if (ipi_should_be_nmi(i)) { |
1084 | err = request_percpu_nmi(ipi_base + i, ipi_handler, | |
bf0baa5b | 1085 | "IPI", &irq_stat); |
331a1b3a DA |
1086 | WARN(err, "Could not request IPI %d as NMI, err=%d\n", |
1087 | i, err); | |
1088 | } else { | |
1089 | err = request_percpu_irq(ipi_base + i, ipi_handler, | |
bf0baa5b | 1090 | "IPI", &irq_stat); |
331a1b3a DA |
1091 | WARN(err, "Could not request IPI %d as IRQ, err=%d\n", |
1092 | i, err); | |
1093 | } | |
d3afc7f1 MZ |
1094 | |
1095 | ipi_desc[i] = irq_to_desc(ipi_base + i); | |
1096 | irq_set_status_flags(ipi_base + i, IRQ_HIDDEN); | |
1097 | } | |
1098 | ||
1099 | ipi_irq_base = ipi_base; | |
d3afc7f1 MZ |
1100 | |
1101 | /* Setup the boot CPU immediately */ | |
1102 | ipi_setup(smp_processor_id()); | |
1103 | } | |
1104 | ||
4c8c3c7f | 1105 | void arch_smp_send_reschedule(int cpu) |
08e875c1 CM |
1106 | { |
1107 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); | |
1108 | } | |
1109 | ||
2b2d0a7a MR |
1110 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
1111 | void arch_send_wakeup_ipi(unsigned int cpu) | |
1112 | { | |
1113 | /* | |
1114 | * We use a scheduler IPI to wake the CPU as this avoids the need for a | |
1115 | * dedicated IPI and we can safely handle spurious scheduler IPIs. | |
1116 | */ | |
ef31b8ce | 1117 | smp_send_reschedule(cpu); |
2b2d0a7a MR |
1118 | } |
1119 | #endif | |
1120 | ||
1f85008e LP |
1121 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
1122 | void tick_broadcast(const struct cpumask *mask) | |
1123 | { | |
1124 | smp_cross_call(mask, IPI_TIMER); | |
1125 | } | |
1126 | #endif | |
1127 | ||
d0bab0c3 CM |
1128 | /* |
1129 | * The number of CPUs online, not counting this CPU (which may not be | |
1130 | * fully online and so not counted in num_online_cpus()). | |
1131 | */ | |
1132 | static inline unsigned int num_other_online_cpus(void) | |
1133 | { | |
1134 | unsigned int this_cpu_online = cpu_online(smp_processor_id()); | |
1135 | ||
1136 | return num_online_cpus() - this_cpu_online; | |
1137 | } | |
1138 | ||
08e875c1 CM |
1139 | void smp_send_stop(void) |
1140 | { | |
1141 | unsigned long timeout; | |
1142 | ||
d0bab0c3 | 1143 | if (num_other_online_cpus()) { |
08e875c1 CM |
1144 | cpumask_t mask; |
1145 | ||
1146 | cpumask_copy(&mask, cpu_online_mask); | |
434ed7f4 | 1147 | cpumask_clear_cpu(smp_processor_id(), &mask); |
08e875c1 | 1148 | |
ef284f5c | 1149 | if (system_state <= SYSTEM_RUNNING) |
82611c14 | 1150 | pr_crit("SMP: stopping secondary CPUs\n"); |
08e875c1 CM |
1151 | smp_cross_call(&mask, IPI_CPU_STOP); |
1152 | } | |
1153 | ||
1154 | /* Wait up to one second for other CPUs to stop */ | |
1155 | timeout = USEC_PER_SEC; | |
d0bab0c3 | 1156 | while (num_other_online_cpus() && timeout--) |
08e875c1 CM |
1157 | udelay(1); |
1158 | ||
d0bab0c3 | 1159 | if (num_other_online_cpus()) |
a74ec64a KW |
1160 | pr_warn("SMP: failed to stop secondary CPUs %*pbl\n", |
1161 | cpumask_pr_args(cpu_online_mask)); | |
f5df2696 JM |
1162 | |
1163 | sdei_mask_local_cpu(); | |
08e875c1 CM |
1164 | } |
1165 | ||
78fd584c | 1166 | #ifdef CONFIG_KEXEC_CORE |
a88ce63b | 1167 | void crash_smp_send_stop(void) |
78fd584c | 1168 | { |
a88ce63b | 1169 | static int cpus_stopped; |
78fd584c AT |
1170 | cpumask_t mask; |
1171 | unsigned long timeout; | |
1172 | ||
a88ce63b HR |
1173 | /* |
1174 | * This function can be called twice in panic path, but obviously | |
1175 | * we execute this only once. | |
1176 | */ | |
1177 | if (cpus_stopped) | |
1178 | return; | |
1179 | ||
1180 | cpus_stopped = 1; | |
1181 | ||
f50b7dac CM |
1182 | /* |
1183 | * If this cpu is the only one alive at this point in time, online or | |
1184 | * not, there are no stop messages to be sent around, so just back out. | |
1185 | */ | |
5cd474e5 SP |
1186 | if (num_other_online_cpus() == 0) |
1187 | goto skip_ipi; | |
78fd584c AT |
1188 | |
1189 | cpumask_copy(&mask, cpu_online_mask); | |
1190 | cpumask_clear_cpu(smp_processor_id(), &mask); | |
1191 | ||
f50b7dac | 1192 | atomic_set(&waiting_for_crash_ipi, num_other_online_cpus()); |
78fd584c AT |
1193 | |
1194 | pr_crit("SMP: stopping secondary CPUs\n"); | |
1195 | smp_cross_call(&mask, IPI_CPU_CRASH_STOP); | |
1196 | ||
1197 | /* Wait up to one second for other CPUs to stop */ | |
1198 | timeout = USEC_PER_SEC; | |
1199 | while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--) | |
1200 | udelay(1); | |
1201 | ||
1202 | if (atomic_read(&waiting_for_crash_ipi) > 0) | |
a74ec64a KW |
1203 | pr_warn("SMP: failed to stop secondary CPUs %*pbl\n", |
1204 | cpumask_pr_args(&mask)); | |
f5df2696 | 1205 | |
5cd474e5 | 1206 | skip_ipi: |
f5df2696 | 1207 | sdei_mask_local_cpu(); |
5cd474e5 | 1208 | sdei_handler_abort(); |
78fd584c AT |
1209 | } |
1210 | ||
1211 | bool smp_crash_stop_failed(void) | |
1212 | { | |
1213 | return (atomic_read(&waiting_for_crash_ipi) > 0); | |
1214 | } | |
1215 | #endif | |
1216 | ||
5c492c3f JM |
1217 | static bool have_cpu_die(void) |
1218 | { | |
1219 | #ifdef CONFIG_HOTPLUG_CPU | |
1220 | int any_cpu = raw_smp_processor_id(); | |
de58ed5e | 1221 | const struct cpu_operations *ops = get_cpu_ops(any_cpu); |
5c492c3f | 1222 | |
de58ed5e | 1223 | if (ops && ops->cpu_die) |
5c492c3f JM |
1224 | return true; |
1225 | #endif | |
1226 | return false; | |
1227 | } | |
1228 | ||
1229 | bool cpus_are_stuck_in_kernel(void) | |
1230 | { | |
1231 | bool smp_spin_tables = (num_possible_cpus() > 1 && !have_cpu_die()); | |
1232 | ||
8f4566f1 WD |
1233 | return !!cpus_stuck_in_kernel || smp_spin_tables || |
1234 | is_protected_kvm_enabled(); | |
5c492c3f | 1235 | } |