treewide: Use fallthrough pseudo-keyword
[linux-block.git] / arch / arm64 / kernel / smp.c
CommitLineData
caab277b 1// SPDX-License-Identifier: GPL-2.0-only
08e875c1
CM
2/*
3 * SMP initialisation and IPI support
4 * Based on arch/arm/kernel/smp.c
5 *
6 * Copyright (C) 2012 ARM Ltd.
08e875c1
CM
7 */
8
0f078336 9#include <linux/acpi.h>
f5df2696 10#include <linux/arm_sdei.h>
08e875c1
CM
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
68e21be2 14#include <linux/sched/mm.h>
ef8bd77f 15#include <linux/sched/hotplug.h>
68db0cf1 16#include <linux/sched/task_stack.h>
08e875c1
CM
17#include <linux/interrupt.h>
18#include <linux/cache.h>
19#include <linux/profile.h>
20#include <linux/errno.h>
21#include <linux/mm.h>
22#include <linux/err.h>
23#include <linux/cpu.h>
24#include <linux/smp.h>
25#include <linux/seq_file.h>
26#include <linux/irq.h>
e7932188 27#include <linux/irqchip/arm-gic-v3.h>
08e875c1
CM
28#include <linux/percpu.h>
29#include <linux/clockchips.h>
30#include <linux/completion.h>
31#include <linux/of.h>
eb631bb5 32#include <linux/irq_work.h>
78fd584c 33#include <linux/kexec.h>
0492747c 34#include <linux/kvm_host.h>
08e875c1 35
e039ee4e 36#include <asm/alternative.h>
08e875c1
CM
37#include <asm/atomic.h>
38#include <asm/cacheflush.h>
df857416 39#include <asm/cpu.h>
08e875c1 40#include <asm/cputype.h>
cd1aebf5 41#include <asm/cpu_ops.h>
0fbeb318 42#include <asm/daifflags.h>
0492747c 43#include <asm/kvm_mmu.h>
08e875c1 44#include <asm/mmu_context.h>
1a2db300 45#include <asm/numa.h>
08e875c1 46#include <asm/processor.h>
4c7aa002 47#include <asm/smp_plat.h>
08e875c1
CM
48#include <asm/sections.h>
49#include <asm/tlbflush.h>
50#include <asm/ptrace.h>
377bcff9 51#include <asm/virt.h>
08e875c1 52
45ed695a
NP
53#define CREATE_TRACE_POINTS
54#include <trace/events/ipi.h>
55
57c82954
MR
56DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number);
57EXPORT_PER_CPU_SYMBOL(cpu_number);
58
08e875c1
CM
59/*
60 * as from 2.5, kernels no longer have an init_tasks structure
61 * so we need some other way of telling a new secondary core
62 * where to place its SVC stack
63 */
64struct secondary_data secondary_data;
bb905274 65/* Number of CPUs which aren't online, but looping in kernel text. */
2eaf63ba 66static int cpus_stuck_in_kernel;
08e875c1
CM
67
68enum ipi_msg_type {
69 IPI_RESCHEDULE,
70 IPI_CALL_FUNC,
08e875c1 71 IPI_CPU_STOP,
78fd584c 72 IPI_CPU_CRASH_STOP,
1f85008e 73 IPI_TIMER,
eb631bb5 74 IPI_IRQ_WORK,
5e89c55e 75 IPI_WAKEUP
08e875c1
CM
76};
77
bb905274
SP
78#ifdef CONFIG_HOTPLUG_CPU
79static int op_cpu_kill(unsigned int cpu);
80#else
81static inline int op_cpu_kill(unsigned int cpu)
82{
83 return -ENOSYS;
84}
85#endif
86
87
08e875c1
CM
88/*
89 * Boot a secondary CPU, and assign it the specified idle task.
90 * This also gives us the initial stack to use for this CPU.
91 */
b8c6453a 92static int boot_secondary(unsigned int cpu, struct task_struct *idle)
08e875c1 93{
de58ed5e
GS
94 const struct cpu_operations *ops = get_cpu_ops(cpu);
95
96 if (ops->cpu_boot)
97 return ops->cpu_boot(cpu);
08e875c1 98
652af899 99 return -EOPNOTSUPP;
08e875c1
CM
100}
101
102static DECLARE_COMPLETION(cpu_running);
103
b8c6453a 104int __cpu_up(unsigned int cpu, struct task_struct *idle)
08e875c1
CM
105{
106 int ret;
bb905274 107 long status;
08e875c1
CM
108
109 /*
110 * We need to tell the secondary core where to find its stack and the
111 * page tables.
112 */
c02433dd 113 secondary_data.task = idle;
34be98f4 114 secondary_data.stack = task_stack_page(idle) + THREAD_SIZE;
bb905274 115 update_cpu_boot_status(CPU_MMU_OFF);
08e875c1
CM
116 __flush_dcache_area(&secondary_data, sizeof(secondary_data));
117
d22b115c 118 /* Now bring the CPU into our world */
08e875c1 119 ret = boot_secondary(cpu, idle);
d22b115c 120 if (ret) {
08e875c1 121 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
f357b3a7 122 return ret;
08e875c1
CM
123 }
124
d22b115c
GS
125 /*
126 * CPU was successfully started, wait for it to come online or
127 * time out.
128 */
129 wait_for_completion_timeout(&cpu_running,
130 msecs_to_jiffies(5000));
131 if (cpu_online(cpu))
132 return 0;
133
134 pr_crit("CPU%u: failed to come online\n", cpu);
c02433dd 135 secondary_data.task = NULL;
08e875c1 136 secondary_data.stack = NULL;
5b1cfe3a 137 __flush_dcache_area(&secondary_data, sizeof(secondary_data));
bb905274 138 status = READ_ONCE(secondary_data.status);
d22b115c
GS
139 if (status == CPU_MMU_OFF)
140 status = READ_ONCE(__early_cpu_boot_status);
bb905274 141
d22b115c
GS
142 switch (status & CPU_BOOT_STATUS_MASK) {
143 default:
144 pr_err("CPU%u: failed in unknown state : 0x%lx\n",
145 cpu, status);
146 cpus_stuck_in_kernel++;
147 break;
148 case CPU_KILL_ME:
149 if (!op_cpu_kill(cpu)) {
150 pr_crit("CPU%u: died during early boot\n", cpu);
bb905274 151 break;
bb905274 152 }
d22b115c 153 pr_crit("CPU%u: may not have shut down cleanly\n", cpu);
df561f66 154 fallthrough;
d22b115c
GS
155 case CPU_STUCK_IN_KERNEL:
156 pr_crit("CPU%u: is stuck in kernel\n", cpu);
157 if (status & CPU_STUCK_REASON_52_BIT_VA)
158 pr_crit("CPU%u: does not support 52-bit VAs\n", cpu);
159 if (status & CPU_STUCK_REASON_NO_GRAN) {
160 pr_crit("CPU%u: does not support %luK granule\n",
161 cpu, PAGE_SIZE / SZ_1K);
162 }
163 cpus_stuck_in_kernel++;
164 break;
165 case CPU_PANIC_KERNEL:
166 panic("CPU%u detected unsupported configuration\n", cpu);
bb905274 167 }
08e875c1 168
ba051f09 169 return -EIO;
08e875c1
CM
170}
171
e7932188
JT
172static void init_gic_priority_masking(void)
173{
174 u32 cpuflags;
175
176 if (WARN_ON(!gic_enable_sre()))
177 return;
178
179 cpuflags = read_sysreg(daif);
180
181 WARN_ON(!(cpuflags & PSR_I_BIT));
182
e1d22385 183 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
e7932188
JT
184}
185
08e875c1
CM
186/*
187 * This is the secondary CPU boot entry. We're using this CPUs
188 * idle thread stack, but a set of temporary page tables.
189 */
b154886f 190asmlinkage notrace void secondary_start_kernel(void)
08e875c1 191{
ccaac162 192 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
08e875c1 193 struct mm_struct *mm = &init_mm;
de58ed5e 194 const struct cpu_operations *ops;
580efaa7
MR
195 unsigned int cpu;
196
197 cpu = task_cpu(current);
198 set_my_cpu_offset(per_cpu_offset(cpu));
08e875c1 199
08e875c1
CM
200 /*
201 * All kernel threads share the same mm context; grab a
202 * reference and switch to it.
203 */
f1f10076 204 mmgrab(mm);
08e875c1 205 current->active_mm = mm;
08e875c1
CM
206
207 /*
208 * TTBR0 is only used for the identity mapping at this stage. Make it
209 * point to zero page to avoid speculatively fetching new entries.
210 */
9e8e865b 211 cpu_uninstall_idmap();
08e875c1 212
e7932188
JT
213 if (system_uses_irq_prio_masking())
214 init_gic_priority_masking();
215
08e875c1
CM
216 preempt_disable();
217 trace_hardirqs_off();
218
dbb4e152
SP
219 /*
220 * If the system has established the capabilities, make sure
221 * this CPU ticks all of those. If it doesn't, the CPU will
222 * fail to come online.
223 */
c47a1900 224 check_local_cpu_capabilities();
dbb4e152 225
de58ed5e
GS
226 ops = get_cpu_ops(cpu);
227 if (ops->cpu_postboot)
228 ops->cpu_postboot();
08e875c1 229
df857416
MR
230 /*
231 * Log the CPU info before it is marked online and might get read.
232 */
233 cpuinfo_store_cpu();
234
7ade67b5
MZ
235 /*
236 * Enable GIC and timers.
237 */
238 notify_cpu_starting(cpu);
239
c18df0ad 240 store_cpu_topology(cpu);
97fd6016 241 numa_add_cpu(cpu);
f6e763b9 242
08e875c1
CM
243 /*
244 * OK, now it's safe to let the boot CPU continue. Wait for
245 * the CPU migration code to notice that the CPU is online
246 * before we continue.
247 */
ccaac162
MR
248 pr_info("CPU%u: Booted secondary processor 0x%010lx [0x%08x]\n",
249 cpu, (unsigned long)mpidr,
250 read_cpuid_id());
bb905274 251 update_cpu_boot_status(CPU_BOOT_SUCCESS);
08e875c1 252 set_cpu_online(cpu, true);
b3770b32 253 complete(&cpu_running);
08e875c1 254
41bd5b5d 255 local_daif_restore(DAIF_PROCCTX);
53ae3acd 256
08e875c1
CM
257 /*
258 * OK, it's off to the idle thread for us
259 */
fc6d73d6 260 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
08e875c1
CM
261}
262
9327e2c6
MR
263#ifdef CONFIG_HOTPLUG_CPU
264static int op_cpu_disable(unsigned int cpu)
265{
de58ed5e
GS
266 const struct cpu_operations *ops = get_cpu_ops(cpu);
267
9327e2c6
MR
268 /*
269 * If we don't have a cpu_die method, abort before we reach the point
270 * of no return. CPU0 may not have an cpu_ops, so test for it.
271 */
de58ed5e 272 if (!ops || !ops->cpu_die)
9327e2c6
MR
273 return -EOPNOTSUPP;
274
275 /*
276 * We may need to abort a hot unplug for some other mechanism-specific
277 * reason.
278 */
de58ed5e
GS
279 if (ops->cpu_disable)
280 return ops->cpu_disable(cpu);
9327e2c6
MR
281
282 return 0;
283}
284
285/*
286 * __cpu_disable runs on the processor to be shutdown.
287 */
288int __cpu_disable(void)
289{
290 unsigned int cpu = smp_processor_id();
291 int ret;
292
293 ret = op_cpu_disable(cpu);
294 if (ret)
295 return ret;
296
7f9545aa
SH
297 remove_cpu_topology(cpu);
298 numa_remove_cpu(cpu);
299
9327e2c6
MR
300 /*
301 * Take this CPU offline. Once we clear this, we can't return,
302 * and we must not schedule until we're ready to give up the cpu.
303 */
304 set_cpu_online(cpu, false);
305
306 /*
307 * OK - migrate IRQs away from this CPU
308 */
217d453d
YY
309 irq_migrate_all_off_this_cpu();
310
9327e2c6
MR
311 return 0;
312}
313
c814ca02
AC
314static int op_cpu_kill(unsigned int cpu)
315{
de58ed5e
GS
316 const struct cpu_operations *ops = get_cpu_ops(cpu);
317
c814ca02
AC
318 /*
319 * If we have no means of synchronising with the dying CPU, then assume
320 * that it is really dead. We can only wait for an arbitrary length of
321 * time and hope that it's dead, so let's skip the wait and just hope.
322 */
de58ed5e 323 if (!ops->cpu_kill)
6b99c68c 324 return 0;
c814ca02 325
de58ed5e 326 return ops->cpu_kill(cpu);
c814ca02
AC
327}
328
9327e2c6
MR
329/*
330 * called on the thread which is asking for a CPU to be shutdown -
331 * waits until shutdown has completed, or it is timed out.
332 */
333void __cpu_die(unsigned int cpu)
334{
6b99c68c
MR
335 int err;
336
05981277 337 if (!cpu_wait_death(cpu, 5)) {
9327e2c6
MR
338 pr_crit("CPU%u: cpu didn't die\n", cpu);
339 return;
340 }
341 pr_notice("CPU%u: shutdown\n", cpu);
c814ca02
AC
342
343 /*
344 * Now that the dying CPU is beyond the point of no return w.r.t.
345 * in-kernel synchronisation, try to get the firwmare to help us to
346 * verify that it has really left the kernel before we consider
347 * clobbering anything it might still be using.
348 */
6b99c68c
MR
349 err = op_cpu_kill(cpu);
350 if (err)
a74ec64a 351 pr_warn("CPU%d may not have shut down cleanly: %d\n", cpu, err);
9327e2c6
MR
352}
353
354/*
355 * Called from the idle thread for the CPU which has been shutdown.
356 *
9327e2c6
MR
357 */
358void cpu_die(void)
359{
360 unsigned int cpu = smp_processor_id();
de58ed5e 361 const struct cpu_operations *ops = get_cpu_ops(cpu);
9327e2c6
MR
362
363 idle_task_exit();
364
0fbeb318 365 local_daif_mask();
9327e2c6
MR
366
367 /* Tell __cpu_die() that this CPU is now safe to dispose of */
05981277 368 (void)cpu_report_death();
9327e2c6
MR
369
370 /*
371 * Actually shutdown the CPU. This must never fail. The specific hotplug
372 * mechanism must perform all required cache maintenance to ensure that
373 * no dirty lines are lost in the process of shutting down the CPU.
374 */
de58ed5e 375 ops->cpu_die(cpu);
9327e2c6
MR
376
377 BUG();
378}
379#endif
380
de58ed5e
GS
381static void __cpu_try_die(int cpu)
382{
383#ifdef CONFIG_HOTPLUG_CPU
384 const struct cpu_operations *ops = get_cpu_ops(cpu);
385
386 if (ops && ops->cpu_die)
387 ops->cpu_die(cpu);
388#endif
389}
390
fce6361f
SP
391/*
392 * Kill the calling secondary CPU, early in bringup before it is turned
393 * online.
394 */
395void cpu_die_early(void)
396{
397 int cpu = smp_processor_id();
398
399 pr_crit("CPU%d: will not boot\n", cpu);
400
401 /* Mark this CPU absent */
402 set_cpu_present(cpu, 0);
403
de58ed5e
GS
404 if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) {
405 update_cpu_boot_status(CPU_KILL_ME);
406 __cpu_try_die(cpu);
407 }
408
bb905274 409 update_cpu_boot_status(CPU_STUCK_IN_KERNEL);
fce6361f
SP
410
411 cpu_park_loop();
412}
413
377bcff9
JR
414static void __init hyp_mode_check(void)
415{
416 if (is_hyp_mode_available())
417 pr_info("CPU: All CPU(s) started at EL2\n");
418 else if (is_hyp_mode_mismatched())
419 WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC,
420 "CPU: CPUs started in inconsistent modes");
421 else
422 pr_info("CPU: All CPU(s) started at EL1\n");
d82755b2 423 if (IS_ENABLED(CONFIG_KVM))
0492747c 424 kvm_compute_layout();
377bcff9
JR
425}
426
08e875c1
CM
427void __init smp_cpus_done(unsigned int max_cpus)
428{
326b16db 429 pr_info("SMP: Total of %d processors activated.\n", num_online_cpus());
3a75578e 430 setup_cpu_features();
377bcff9
JR
431 hyp_mode_check();
432 apply_alternatives_all();
5ea5306c 433 mark_linear_text_alias_ro();
08e875c1
CM
434}
435
436void __init smp_prepare_boot_cpu(void)
437{
9113c2aa 438 set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
4b998ff1 439 cpuinfo_store_boot_cpu();
0ceb0d56
DT
440
441 /*
442 * We now know enough about the boot CPU to apply the
443 * alternatives that cannot wait until interrupt handling
444 * and/or scheduling is enabled.
445 */
446 apply_boot_alternatives();
e7932188
JT
447
448 /* Conditionally switch to GIC PMR for interrupt masking */
449 if (system_uses_irq_prio_masking())
450 init_gic_priority_masking();
08e875c1
CM
451}
452
0f078336
LP
453static u64 __init of_get_cpu_mpidr(struct device_node *dn)
454{
455 const __be32 *cell;
456 u64 hwid;
457
458 /*
459 * A cpu node with missing "reg" property is
460 * considered invalid to build a cpu_logical_map
461 * entry.
462 */
463 cell = of_get_property(dn, "reg", NULL);
464 if (!cell) {
a270f327 465 pr_err("%pOF: missing reg property\n", dn);
0f078336
LP
466 return INVALID_HWID;
467 }
468
469 hwid = of_read_number(cell, of_n_addr_cells(dn));
470 /*
471 * Non affinity bits must be set to 0 in the DT
472 */
473 if (hwid & ~MPIDR_HWID_BITMASK) {
a270f327 474 pr_err("%pOF: invalid reg property\n", dn);
0f078336
LP
475 return INVALID_HWID;
476 }
477 return hwid;
478}
479
480/*
481 * Duplicate MPIDRs are a recipe for disaster. Scan all initialized
482 * entries and check for duplicates. If any is found just ignore the
483 * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid
484 * matching valid MPIDR values.
485 */
486static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid)
487{
488 unsigned int i;
489
490 for (i = 1; (i < cpu) && (i < NR_CPUS); i++)
491 if (cpu_logical_map(i) == hwid)
492 return true;
493 return false;
494}
495
819a8826
LP
496/*
497 * Initialize cpu operations for a logical cpu and
498 * set it in the possible mask on success
499 */
500static int __init smp_cpu_setup(int cpu)
501{
de58ed5e
GS
502 const struct cpu_operations *ops;
503
6885fb12 504 if (init_cpu_ops(cpu))
819a8826
LP
505 return -ENODEV;
506
de58ed5e
GS
507 ops = get_cpu_ops(cpu);
508 if (ops->cpu_init(cpu))
819a8826
LP
509 return -ENODEV;
510
511 set_cpu_possible(cpu, true);
512
513 return 0;
514}
515
0f078336
LP
516static bool bootcpu_valid __initdata;
517static unsigned int cpu_count = 1;
518
519#ifdef CONFIG_ACPI
e0013aed
MR
520static struct acpi_madt_generic_interrupt cpu_madt_gicc[NR_CPUS];
521
522struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu)
523{
524 return &cpu_madt_gicc[cpu];
525}
526
0f078336
LP
527/*
528 * acpi_map_gic_cpu_interface - parse processor MADT entry
529 *
530 * Carry out sanity checks on MADT processor entry and initialize
531 * cpu_logical_map on success
532 */
533static void __init
534acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
535{
536 u64 hwid = processor->arm_mpidr;
537
f9058929
HG
538 if (!(processor->flags & ACPI_MADT_ENABLED)) {
539 pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid);
0f078336
LP
540 return;
541 }
542
f9058929
HG
543 if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) {
544 pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid);
0f078336
LP
545 return;
546 }
547
548 if (is_mpidr_duplicate(cpu_count, hwid)) {
549 pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid);
550 return;
551 }
552
553 /* Check if GICC structure of boot CPU is available in the MADT */
554 if (cpu_logical_map(0) == hwid) {
555 if (bootcpu_valid) {
556 pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n",
557 hwid);
558 return;
559 }
560 bootcpu_valid = true;
e0013aed 561 cpu_madt_gicc[0] = *processor;
0f078336
LP
562 return;
563 }
564
565 if (cpu_count >= NR_CPUS)
566 return;
567
568 /* map the logical cpu id to cpu MPIDR */
eaecca9e 569 set_cpu_logical_map(cpu_count, hwid);
0f078336 570
e0013aed
MR
571 cpu_madt_gicc[cpu_count] = *processor;
572
5e89c55e
LP
573 /*
574 * Set-up the ACPI parking protocol cpu entries
575 * while initializing the cpu_logical_map to
576 * avoid parsing MADT entries multiple times for
577 * nothing (ie a valid cpu_logical_map entry should
578 * contain a valid parking protocol data set to
579 * initialize the cpu if the parking protocol is
580 * the only available enable method).
581 */
582 acpi_set_mailbox_entry(cpu_count, processor);
583
0f078336
LP
584 cpu_count++;
585}
586
587static int __init
60574d1e 588acpi_parse_gic_cpu_interface(union acpi_subtable_headers *header,
0f078336
LP
589 const unsigned long end)
590{
591 struct acpi_madt_generic_interrupt *processor;
592
593 processor = (struct acpi_madt_generic_interrupt *)header;
99e3e3ae 594 if (BAD_MADT_GICC_ENTRY(processor, end))
0f078336
LP
595 return -EINVAL;
596
60574d1e 597 acpi_table_print_madt_entry(&header->common);
0f078336
LP
598
599 acpi_map_gic_cpu_interface(processor);
600
601 return 0;
602}
e1896249
LP
603
604static void __init acpi_parse_and_init_cpus(void)
605{
606 int i;
607
608 /*
609 * do a walk of MADT to determine how many CPUs
610 * we have including disabled CPUs, and get information
611 * we need for SMP init.
612 */
613 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
614 acpi_parse_gic_cpu_interface, 0);
615
616 /*
617 * In ACPI, SMP and CPU NUMA information is provided in separate
618 * static tables, namely the MADT and the SRAT.
619 *
620 * Thus, it is simpler to first create the cpu logical map through
621 * an MADT walk and then map the logical cpus to their node ids
622 * as separate steps.
623 */
624 acpi_map_cpus_to_nodes();
625
626 for (i = 0; i < nr_cpu_ids; i++)
627 early_map_cpu_to_node(i, acpi_numa_get_nid(i));
628}
0f078336 629#else
e1896249 630#define acpi_parse_and_init_cpus(...) do { } while (0)
0f078336
LP
631#endif
632
08e875c1 633/*
4c7aa002
JM
634 * Enumerate the possible CPU set from the device tree and build the
635 * cpu logical map array containing MPIDR values related to logical
636 * cpus. Assumes that cpu_logical_map(0) has already been initialized.
08e875c1 637 */
29b8302b 638static void __init of_parse_and_init_cpus(void)
08e875c1 639{
3d29a9a0 640 struct device_node *dn;
08e875c1 641
de76e70a 642 for_each_of_cpu_node(dn) {
0f078336 643 u64 hwid = of_get_cpu_mpidr(dn);
4c7aa002 644
0f078336 645 if (hwid == INVALID_HWID)
4c7aa002 646 goto next;
4c7aa002 647
0f078336 648 if (is_mpidr_duplicate(cpu_count, hwid)) {
a270f327
RH
649 pr_err("%pOF: duplicate cpu reg properties in the DT\n",
650 dn);
4c7aa002
JM
651 goto next;
652 }
653
4c7aa002
JM
654 /*
655 * The numbering scheme requires that the boot CPU
656 * must be assigned logical id 0. Record it so that
657 * the logical map built from DT is validated and can
658 * be used.
659 */
660 if (hwid == cpu_logical_map(0)) {
661 if (bootcpu_valid) {
a270f327
RH
662 pr_err("%pOF: duplicate boot cpu reg property in DT\n",
663 dn);
4c7aa002
JM
664 goto next;
665 }
666
667 bootcpu_valid = true;
7ba5f605 668 early_map_cpu_to_node(0, of_node_to_nid(dn));
4c7aa002
JM
669
670 /*
671 * cpu_logical_map has already been
672 * initialized and the boot cpu doesn't need
673 * the enable-method so continue without
674 * incrementing cpu.
675 */
676 continue;
677 }
678
0f078336 679 if (cpu_count >= NR_CPUS)
08e875c1
CM
680 goto next;
681
4c7aa002 682 pr_debug("cpu logical map 0x%llx\n", hwid);
eaecca9e 683 set_cpu_logical_map(cpu_count, hwid);
1a2db300
GK
684
685 early_map_cpu_to_node(cpu_count, of_node_to_nid(dn));
08e875c1 686next:
0f078336 687 cpu_count++;
08e875c1 688 }
0f078336
LP
689}
690
691/*
692 * Enumerate the possible CPU set from the device tree or ACPI and build the
693 * cpu logical map array containing MPIDR values related to logical
694 * cpus. Assumes that cpu_logical_map(0) has already been initialized.
695 */
696void __init smp_init_cpus(void)
697{
698 int i;
699
700 if (acpi_disabled)
701 of_parse_and_init_cpus();
702 else
e1896249 703 acpi_parse_and_init_cpus();
08e875c1 704
50ee91bd 705 if (cpu_count > nr_cpu_ids)
9b130ad5 706 pr_warn("Number of cores (%d) exceeds configured maximum of %u - clipping\n",
50ee91bd 707 cpu_count, nr_cpu_ids);
4c7aa002
JM
708
709 if (!bootcpu_valid) {
0f078336 710 pr_err("missing boot CPU MPIDR, not enabling secondaries\n");
4c7aa002
JM
711 return;
712 }
713
714 /*
819a8826
LP
715 * We need to set the cpu_logical_map entries before enabling
716 * the cpus so that cpu processor description entries (DT cpu nodes
717 * and ACPI MADT entries) can be retrieved by matching the cpu hwid
718 * with entries in cpu_logical_map while initializing the cpus.
719 * If the cpu set-up fails, invalidate the cpu_logical_map entry.
4c7aa002 720 */
50ee91bd 721 for (i = 1; i < nr_cpu_ids; i++) {
819a8826
LP
722 if (cpu_logical_map(i) != INVALID_HWID) {
723 if (smp_cpu_setup(i))
eaecca9e 724 set_cpu_logical_map(i, INVALID_HWID);
819a8826
LP
725 }
726 }
08e875c1
CM
727}
728
729void __init smp_prepare_cpus(unsigned int max_cpus)
730{
de58ed5e 731 const struct cpu_operations *ops;
cd1aebf5 732 int err;
44dbcc93 733 unsigned int cpu;
c18df0ad 734 unsigned int this_cpu;
08e875c1 735
f6e763b9
MB
736 init_cpu_topology();
737
c18df0ad
DD
738 this_cpu = smp_processor_id();
739 store_cpu_topology(this_cpu);
740 numa_store_cpu_info(this_cpu);
97fd6016 741 numa_add_cpu(this_cpu);
f6e763b9 742
e75118a7
SP
743 /*
744 * If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set
745 * secondary CPUs present.
746 */
747 if (max_cpus == 0)
748 return;
749
08e875c1
CM
750 /*
751 * Initialise the present map (which describes the set of CPUs
752 * actually populated at the present time) and release the
753 * secondaries from the bootloader.
754 */
755 for_each_possible_cpu(cpu) {
08e875c1 756
57c82954
MR
757 per_cpu(cpu_number, cpu) = cpu;
758
d329de3f
MZ
759 if (cpu == smp_processor_id())
760 continue;
761
de58ed5e
GS
762 ops = get_cpu_ops(cpu);
763 if (!ops)
08e875c1
CM
764 continue;
765
de58ed5e 766 err = ops->cpu_prepare(cpu);
d329de3f
MZ
767 if (err)
768 continue;
08e875c1
CM
769
770 set_cpu_present(cpu, true);
c18df0ad 771 numa_store_cpu_info(cpu);
08e875c1 772 }
08e875c1
CM
773}
774
36310736 775void (*__smp_cross_call)(const struct cpumask *, unsigned int);
08e875c1
CM
776
777void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
778{
45ed695a 779 __smp_cross_call = fn;
08e875c1
CM
780}
781
45ed695a
NP
782static const char *ipi_types[NR_IPI] __tracepoint_string = {
783#define S(x,s) [x] = s
08e875c1
CM
784 S(IPI_RESCHEDULE, "Rescheduling interrupts"),
785 S(IPI_CALL_FUNC, "Function call interrupts"),
08e875c1 786 S(IPI_CPU_STOP, "CPU stop interrupts"),
78fd584c 787 S(IPI_CPU_CRASH_STOP, "CPU stop (for crash dump) interrupts"),
1f85008e 788 S(IPI_TIMER, "Timer broadcast interrupts"),
eb631bb5 789 S(IPI_IRQ_WORK, "IRQ work interrupts"),
5e89c55e 790 S(IPI_WAKEUP, "CPU wake-up interrupts"),
08e875c1
CM
791};
792
45ed695a
NP
793static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
794{
795 trace_ipi_raise(target, ipi_types[ipinr]);
796 __smp_cross_call(target, ipinr);
797}
798
08e875c1
CM
799void show_ipi_list(struct seq_file *p, int prec)
800{
801 unsigned int cpu, i;
802
803 for (i = 0; i < NR_IPI; i++) {
45ed695a 804 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i,
08e875c1 805 prec >= 4 ? " " : "");
67317c26 806 for_each_online_cpu(cpu)
08e875c1
CM
807 seq_printf(p, "%10u ",
808 __get_irq_stat(cpu, ipi_irqs[i]));
809 seq_printf(p, " %s\n", ipi_types[i]);
810 }
811}
812
813u64 smp_irq_stat_cpu(unsigned int cpu)
814{
815 u64 sum = 0;
816 int i;
817
818 for (i = 0; i < NR_IPI; i++)
819 sum += __get_irq_stat(cpu, ipi_irqs[i]);
820
821 return sum;
822}
823
45ed695a
NP
824void arch_send_call_function_ipi_mask(const struct cpumask *mask)
825{
826 smp_cross_call(mask, IPI_CALL_FUNC);
827}
828
829void arch_send_call_function_single_ipi(int cpu)
830{
0aaf0dae 831 smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC);
45ed695a
NP
832}
833
5e89c55e
LP
834#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL
835void arch_send_wakeup_ipi_mask(const struct cpumask *mask)
836{
837 smp_cross_call(mask, IPI_WAKEUP);
838}
839#endif
840
45ed695a
NP
841#ifdef CONFIG_IRQ_WORK
842void arch_irq_work_raise(void)
843{
844 if (__smp_cross_call)
845 smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK);
846}
847#endif
848
d914d4d4 849static void local_cpu_stop(void)
08e875c1 850{
d914d4d4 851 set_cpu_online(smp_processor_id(), false);
08e875c1 852
0fbeb318 853 local_daif_mask();
f5df2696 854 sdei_mask_local_cpu();
dccc9da2 855 cpu_park_loop();
08e875c1 856}
08e875c1 857
d914d4d4
AK
858/*
859 * We need to implement panic_smp_self_stop() for parallel panic() calls, so
860 * that cpu_online_mask gets correctly updated and smp_send_stop() can skip
861 * CPUs that have already stopped themselves.
862 */
863void panic_smp_self_stop(void)
864{
865 local_cpu_stop();
08e875c1
CM
866}
867
78fd584c
AT
868#ifdef CONFIG_KEXEC_CORE
869static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0);
870#endif
871
872static void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
873{
874#ifdef CONFIG_KEXEC_CORE
875 crash_save_cpu(regs, cpu);
876
877 atomic_dec(&waiting_for_crash_ipi);
878
879 local_irq_disable();
f5df2696 880 sdei_mask_local_cpu();
78fd584c 881
de58ed5e
GS
882 if (IS_ENABLED(CONFIG_HOTPLUG_CPU))
883 __cpu_try_die(cpu);
78fd584c
AT
884
885 /* just in case */
886 cpu_park_loop();
887#endif
888}
889
08e875c1
CM
890/*
891 * Main handler for inter-processor interrupts
892 */
893void handle_IPI(int ipinr, struct pt_regs *regs)
894{
895 unsigned int cpu = smp_processor_id();
896 struct pt_regs *old_regs = set_irq_regs(regs);
897
45ed695a 898 if ((unsigned)ipinr < NR_IPI) {
be081d9b 899 trace_ipi_entry_rcuidle(ipi_types[ipinr]);
45ed695a
NP
900 __inc_irq_stat(cpu, ipi_irqs[ipinr]);
901 }
08e875c1
CM
902
903 switch (ipinr) {
904 case IPI_RESCHEDULE:
905 scheduler_ipi();
906 break;
907
908 case IPI_CALL_FUNC:
909 irq_enter();
910 generic_smp_call_function_interrupt();
911 irq_exit();
912 break;
913
08e875c1
CM
914 case IPI_CPU_STOP:
915 irq_enter();
d914d4d4 916 local_cpu_stop();
08e875c1
CM
917 irq_exit();
918 break;
919
78fd584c
AT
920 case IPI_CPU_CRASH_STOP:
921 if (IS_ENABLED(CONFIG_KEXEC_CORE)) {
922 irq_enter();
923 ipi_cpu_crash_stop(cpu, regs);
924
925 unreachable();
926 }
927 break;
928
1f85008e
LP
929#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
930 case IPI_TIMER:
931 irq_enter();
932 tick_receive_broadcast();
933 irq_exit();
934 break;
935#endif
936
eb631bb5
LB
937#ifdef CONFIG_IRQ_WORK
938 case IPI_IRQ_WORK:
939 irq_enter();
940 irq_work_run();
941 irq_exit();
942 break;
943#endif
944
5e89c55e
LP
945#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL
946 case IPI_WAKEUP:
947 WARN_ONCE(!acpi_parking_protocol_valid(cpu),
948 "CPU%u: Wake-up IPI outside the ACPI parking protocol\n",
949 cpu);
950 break;
951#endif
952
08e875c1
CM
953 default:
954 pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
955 break;
956 }
45ed695a
NP
957
958 if ((unsigned)ipinr < NR_IPI)
be081d9b 959 trace_ipi_exit_rcuidle(ipi_types[ipinr]);
08e875c1
CM
960 set_irq_regs(old_regs);
961}
962
963void smp_send_reschedule(int cpu)
964{
965 smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
966}
967
1f85008e
LP
968#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
969void tick_broadcast(const struct cpumask *mask)
970{
971 smp_cross_call(mask, IPI_TIMER);
972}
973#endif
974
d0bab0c3
CM
975/*
976 * The number of CPUs online, not counting this CPU (which may not be
977 * fully online and so not counted in num_online_cpus()).
978 */
979static inline unsigned int num_other_online_cpus(void)
980{
981 unsigned int this_cpu_online = cpu_online(smp_processor_id());
982
983 return num_online_cpus() - this_cpu_online;
984}
985
08e875c1
CM
986void smp_send_stop(void)
987{
988 unsigned long timeout;
989
d0bab0c3 990 if (num_other_online_cpus()) {
08e875c1
CM
991 cpumask_t mask;
992
993 cpumask_copy(&mask, cpu_online_mask);
434ed7f4 994 cpumask_clear_cpu(smp_processor_id(), &mask);
08e875c1 995
ef284f5c 996 if (system_state <= SYSTEM_RUNNING)
82611c14 997 pr_crit("SMP: stopping secondary CPUs\n");
08e875c1
CM
998 smp_cross_call(&mask, IPI_CPU_STOP);
999 }
1000
1001 /* Wait up to one second for other CPUs to stop */
1002 timeout = USEC_PER_SEC;
d0bab0c3 1003 while (num_other_online_cpus() && timeout--)
08e875c1
CM
1004 udelay(1);
1005
d0bab0c3 1006 if (num_other_online_cpus())
a74ec64a
KW
1007 pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
1008 cpumask_pr_args(cpu_online_mask));
f5df2696
JM
1009
1010 sdei_mask_local_cpu();
08e875c1
CM
1011}
1012
78fd584c 1013#ifdef CONFIG_KEXEC_CORE
a88ce63b 1014void crash_smp_send_stop(void)
78fd584c 1015{
a88ce63b 1016 static int cpus_stopped;
78fd584c
AT
1017 cpumask_t mask;
1018 unsigned long timeout;
1019
a88ce63b
HR
1020 /*
1021 * This function can be called twice in panic path, but obviously
1022 * we execute this only once.
1023 */
1024 if (cpus_stopped)
1025 return;
1026
1027 cpus_stopped = 1;
1028
f50b7dac
CM
1029 /*
1030 * If this cpu is the only one alive at this point in time, online or
1031 * not, there are no stop messages to be sent around, so just back out.
1032 */
1033 if (num_other_online_cpus() == 0) {
f5df2696 1034 sdei_mask_local_cpu();
78fd584c 1035 return;
f5df2696 1036 }
78fd584c
AT
1037
1038 cpumask_copy(&mask, cpu_online_mask);
1039 cpumask_clear_cpu(smp_processor_id(), &mask);
1040
f50b7dac 1041 atomic_set(&waiting_for_crash_ipi, num_other_online_cpus());
78fd584c
AT
1042
1043 pr_crit("SMP: stopping secondary CPUs\n");
1044 smp_cross_call(&mask, IPI_CPU_CRASH_STOP);
1045
1046 /* Wait up to one second for other CPUs to stop */
1047 timeout = USEC_PER_SEC;
1048 while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--)
1049 udelay(1);
1050
1051 if (atomic_read(&waiting_for_crash_ipi) > 0)
a74ec64a
KW
1052 pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
1053 cpumask_pr_args(&mask));
f5df2696
JM
1054
1055 sdei_mask_local_cpu();
78fd584c
AT
1056}
1057
1058bool smp_crash_stop_failed(void)
1059{
1060 return (atomic_read(&waiting_for_crash_ipi) > 0);
1061}
1062#endif
1063
08e875c1
CM
1064/*
1065 * not supported here
1066 */
1067int setup_profiling_timer(unsigned int multiplier)
1068{
1069 return -EINVAL;
1070}
5c492c3f
JM
1071
1072static bool have_cpu_die(void)
1073{
1074#ifdef CONFIG_HOTPLUG_CPU
1075 int any_cpu = raw_smp_processor_id();
de58ed5e 1076 const struct cpu_operations *ops = get_cpu_ops(any_cpu);
5c492c3f 1077
de58ed5e 1078 if (ops && ops->cpu_die)
5c492c3f
JM
1079 return true;
1080#endif
1081 return false;
1082}
1083
1084bool cpus_are_stuck_in_kernel(void)
1085{
1086 bool smp_spin_tables = (num_possible_cpus() > 1 && !have_cpu_die());
1087
1088 return !!cpus_stuck_in_kernel || smp_spin_tables;
1089}