Commit | Line | Data |
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08e875c1 CM |
1 | /* |
2 | * SMP initialisation and IPI support | |
3 | * Based on arch/arm/kernel/smp.c | |
4 | * | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/sched.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/cache.h> | |
26 | #include <linux/profile.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/mm.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/smp.h> | |
32 | #include <linux/seq_file.h> | |
33 | #include <linux/irq.h> | |
34 | #include <linux/percpu.h> | |
35 | #include <linux/clockchips.h> | |
36 | #include <linux/completion.h> | |
37 | #include <linux/of.h> | |
38 | ||
39 | #include <asm/atomic.h> | |
40 | #include <asm/cacheflush.h> | |
41 | #include <asm/cputype.h> | |
42 | #include <asm/mmu_context.h> | |
43 | #include <asm/pgtable.h> | |
44 | #include <asm/pgalloc.h> | |
45 | #include <asm/processor.h> | |
4c7aa002 | 46 | #include <asm/smp_plat.h> |
08e875c1 CM |
47 | #include <asm/sections.h> |
48 | #include <asm/tlbflush.h> | |
49 | #include <asm/ptrace.h> | |
08e875c1 CM |
50 | |
51 | /* | |
52 | * as from 2.5, kernels no longer have an init_tasks structure | |
53 | * so we need some other way of telling a new secondary core | |
54 | * where to place its SVC stack | |
55 | */ | |
56 | struct secondary_data secondary_data; | |
3e98fdac | 57 | volatile unsigned long secondary_holding_pen_release = INVALID_HWID; |
08e875c1 CM |
58 | |
59 | enum ipi_msg_type { | |
60 | IPI_RESCHEDULE, | |
61 | IPI_CALL_FUNC, | |
62 | IPI_CALL_FUNC_SINGLE, | |
63 | IPI_CPU_STOP, | |
64 | }; | |
65 | ||
66 | static DEFINE_RAW_SPINLOCK(boot_lock); | |
67 | ||
68 | /* | |
69 | * Write secondary_holding_pen_release in a way that is guaranteed to be | |
70 | * visible to all observers, irrespective of whether they're taking part | |
71 | * in coherency or not. This is necessary for the hotplug code to work | |
72 | * reliably. | |
73 | */ | |
3e98fdac | 74 | static void __cpuinit write_pen_release(u64 val) |
08e875c1 CM |
75 | { |
76 | void *start = (void *)&secondary_holding_pen_release; | |
77 | unsigned long size = sizeof(secondary_holding_pen_release); | |
78 | ||
79 | secondary_holding_pen_release = val; | |
80 | __flush_dcache_area(start, size); | |
81 | } | |
82 | ||
83 | /* | |
84 | * Boot a secondary CPU, and assign it the specified idle task. | |
85 | * This also gives us the initial stack to use for this CPU. | |
86 | */ | |
87 | static int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
88 | { | |
89 | unsigned long timeout; | |
90 | ||
91 | /* | |
92 | * Set synchronisation state between this boot processor | |
93 | * and the secondary one | |
94 | */ | |
95 | raw_spin_lock(&boot_lock); | |
96 | ||
97 | /* | |
98 | * Update the pen release flag. | |
99 | */ | |
4c7aa002 | 100 | write_pen_release(cpu_logical_map(cpu)); |
08e875c1 CM |
101 | |
102 | /* | |
103 | * Send an event, causing the secondaries to read pen_release. | |
104 | */ | |
105 | sev(); | |
106 | ||
107 | timeout = jiffies + (1 * HZ); | |
108 | while (time_before(jiffies, timeout)) { | |
3e98fdac | 109 | if (secondary_holding_pen_release == INVALID_HWID) |
08e875c1 CM |
110 | break; |
111 | udelay(10); | |
112 | } | |
113 | ||
114 | /* | |
115 | * Now the secondary core is starting up let it run its | |
116 | * calibrations, then wait for it to finish | |
117 | */ | |
118 | raw_spin_unlock(&boot_lock); | |
119 | ||
3e98fdac | 120 | return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0; |
08e875c1 CM |
121 | } |
122 | ||
123 | static DECLARE_COMPLETION(cpu_running); | |
124 | ||
125 | int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle) | |
126 | { | |
127 | int ret; | |
128 | ||
129 | /* | |
130 | * We need to tell the secondary core where to find its stack and the | |
131 | * page tables. | |
132 | */ | |
133 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; | |
134 | __flush_dcache_area(&secondary_data, sizeof(secondary_data)); | |
135 | ||
136 | /* | |
137 | * Now bring the CPU into our world. | |
138 | */ | |
139 | ret = boot_secondary(cpu, idle); | |
140 | if (ret == 0) { | |
141 | /* | |
142 | * CPU was successfully started, wait for it to come online or | |
143 | * time out. | |
144 | */ | |
145 | wait_for_completion_timeout(&cpu_running, | |
146 | msecs_to_jiffies(1000)); | |
147 | ||
148 | if (!cpu_online(cpu)) { | |
149 | pr_crit("CPU%u: failed to come online\n", cpu); | |
150 | ret = -EIO; | |
151 | } | |
152 | } else { | |
153 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
154 | } | |
155 | ||
156 | secondary_data.stack = NULL; | |
157 | ||
158 | return ret; | |
159 | } | |
160 | ||
161 | /* | |
162 | * This is the secondary CPU boot entry. We're using this CPUs | |
163 | * idle thread stack, but a set of temporary page tables. | |
164 | */ | |
165 | asmlinkage void __cpuinit secondary_start_kernel(void) | |
166 | { | |
167 | struct mm_struct *mm = &init_mm; | |
168 | unsigned int cpu = smp_processor_id(); | |
169 | ||
170 | printk("CPU%u: Booted secondary processor\n", cpu); | |
171 | ||
172 | /* | |
173 | * All kernel threads share the same mm context; grab a | |
174 | * reference and switch to it. | |
175 | */ | |
176 | atomic_inc(&mm->mm_count); | |
177 | current->active_mm = mm; | |
178 | cpumask_set_cpu(cpu, mm_cpumask(mm)); | |
179 | ||
180 | /* | |
181 | * TTBR0 is only used for the identity mapping at this stage. Make it | |
182 | * point to zero page to avoid speculatively fetching new entries. | |
183 | */ | |
184 | cpu_set_reserved_ttbr0(); | |
185 | flush_tlb_all(); | |
186 | ||
187 | preempt_disable(); | |
188 | trace_hardirqs_off(); | |
189 | ||
190 | /* | |
191 | * Let the primary processor know we're out of the | |
192 | * pen, then head off into the C entry point | |
193 | */ | |
3e98fdac | 194 | write_pen_release(INVALID_HWID); |
08e875c1 CM |
195 | |
196 | /* | |
197 | * Synchronise with the boot thread. | |
198 | */ | |
199 | raw_spin_lock(&boot_lock); | |
200 | raw_spin_unlock(&boot_lock); | |
201 | ||
202 | /* | |
203 | * Enable local interrupts. | |
204 | */ | |
205 | notify_cpu_starting(cpu); | |
206 | local_irq_enable(); | |
207 | local_fiq_enable(); | |
208 | ||
209 | /* | |
210 | * OK, now it's safe to let the boot CPU continue. Wait for | |
211 | * the CPU migration code to notice that the CPU is online | |
212 | * before we continue. | |
213 | */ | |
214 | set_cpu_online(cpu, true); | |
b3770b32 | 215 | complete(&cpu_running); |
08e875c1 CM |
216 | |
217 | /* | |
218 | * OK, it's off to the idle thread for us | |
219 | */ | |
220 | cpu_idle(); | |
221 | } | |
222 | ||
223 | void __init smp_cpus_done(unsigned int max_cpus) | |
224 | { | |
225 | unsigned long bogosum = loops_per_jiffy * num_online_cpus(); | |
226 | ||
227 | pr_info("SMP: Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
228 | num_online_cpus(), bogosum / (500000/HZ), | |
229 | (bogosum / (5000/HZ)) % 100); | |
230 | } | |
231 | ||
232 | void __init smp_prepare_boot_cpu(void) | |
233 | { | |
234 | } | |
235 | ||
236 | static void (*smp_cross_call)(const struct cpumask *, unsigned int); | |
d329de3f MZ |
237 | |
238 | static const struct smp_enable_ops *enable_ops[] __initconst = { | |
239 | &smp_spin_table_ops, | |
0459ca9b | 240 | &smp_psci_ops, |
d329de3f MZ |
241 | NULL, |
242 | }; | |
243 | ||
244 | static const struct smp_enable_ops *smp_enable_ops[NR_CPUS]; | |
245 | ||
246 | static const struct smp_enable_ops * __init smp_get_enable_ops(const char *name) | |
247 | { | |
248 | const struct smp_enable_ops *ops = enable_ops[0]; | |
249 | ||
250 | while (ops) { | |
251 | if (!strcmp(name, ops->name)) | |
252 | return ops; | |
253 | ||
254 | ops++; | |
255 | } | |
256 | ||
257 | return NULL; | |
258 | } | |
08e875c1 CM |
259 | |
260 | /* | |
4c7aa002 JM |
261 | * Enumerate the possible CPU set from the device tree and build the |
262 | * cpu logical map array containing MPIDR values related to logical | |
263 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
08e875c1 CM |
264 | */ |
265 | void __init smp_init_cpus(void) | |
266 | { | |
267 | const char *enable_method; | |
268 | struct device_node *dn = NULL; | |
4c7aa002 JM |
269 | int i, cpu = 1; |
270 | bool bootcpu_valid = false; | |
08e875c1 CM |
271 | |
272 | while ((dn = of_find_node_by_type(dn, "cpu"))) { | |
4c7aa002 JM |
273 | u64 hwid; |
274 | ||
275 | /* | |
276 | * A cpu node with missing "reg" property is | |
277 | * considered invalid to build a cpu_logical_map | |
278 | * entry. | |
279 | */ | |
280 | if (of_property_read_u64(dn, "reg", &hwid)) { | |
281 | pr_err("%s: missing reg property\n", dn->full_name); | |
282 | goto next; | |
283 | } | |
284 | ||
285 | /* | |
286 | * Non affinity bits must be set to 0 in the DT | |
287 | */ | |
288 | if (hwid & ~MPIDR_HWID_BITMASK) { | |
289 | pr_err("%s: invalid reg property\n", dn->full_name); | |
290 | goto next; | |
291 | } | |
292 | ||
293 | /* | |
294 | * Duplicate MPIDRs are a recipe for disaster. Scan | |
295 | * all initialized entries and check for | |
296 | * duplicates. If any is found just ignore the cpu. | |
297 | * cpu_logical_map was initialized to INVALID_HWID to | |
298 | * avoid matching valid MPIDR values. | |
299 | */ | |
300 | for (i = 1; (i < cpu) && (i < NR_CPUS); i++) { | |
301 | if (cpu_logical_map(i) == hwid) { | |
302 | pr_err("%s: duplicate cpu reg properties in the DT\n", | |
303 | dn->full_name); | |
304 | goto next; | |
305 | } | |
306 | } | |
307 | ||
308 | /* | |
309 | * The numbering scheme requires that the boot CPU | |
310 | * must be assigned logical id 0. Record it so that | |
311 | * the logical map built from DT is validated and can | |
312 | * be used. | |
313 | */ | |
314 | if (hwid == cpu_logical_map(0)) { | |
315 | if (bootcpu_valid) { | |
316 | pr_err("%s: duplicate boot cpu reg property in DT\n", | |
317 | dn->full_name); | |
318 | goto next; | |
319 | } | |
320 | ||
321 | bootcpu_valid = true; | |
322 | ||
323 | /* | |
324 | * cpu_logical_map has already been | |
325 | * initialized and the boot cpu doesn't need | |
326 | * the enable-method so continue without | |
327 | * incrementing cpu. | |
328 | */ | |
329 | continue; | |
330 | } | |
331 | ||
08e875c1 CM |
332 | if (cpu >= NR_CPUS) |
333 | goto next; | |
334 | ||
335 | /* | |
336 | * We currently support only the "spin-table" enable-method. | |
337 | */ | |
338 | enable_method = of_get_property(dn, "enable-method", NULL); | |
d329de3f | 339 | if (!enable_method) { |
4c7aa002 JM |
340 | pr_err("%s: missing enable-method property\n", |
341 | dn->full_name); | |
08e875c1 CM |
342 | goto next; |
343 | } | |
344 | ||
d329de3f MZ |
345 | smp_enable_ops[cpu] = smp_get_enable_ops(enable_method); |
346 | ||
347 | if (!smp_enable_ops[cpu]) { | |
4c7aa002 JM |
348 | pr_err("%s: invalid enable-method property: %s\n", |
349 | dn->full_name, enable_method); | |
08e875c1 CM |
350 | goto next; |
351 | } | |
352 | ||
d329de3f MZ |
353 | if (smp_enable_ops[cpu]->init_cpu(dn, cpu)) |
354 | goto next; | |
355 | ||
4c7aa002 JM |
356 | pr_debug("cpu logical map 0x%llx\n", hwid); |
357 | cpu_logical_map(cpu) = hwid; | |
08e875c1 CM |
358 | next: |
359 | cpu++; | |
360 | } | |
361 | ||
362 | /* sanity check */ | |
363 | if (cpu > NR_CPUS) | |
364 | pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n", | |
365 | cpu, NR_CPUS); | |
4c7aa002 JM |
366 | |
367 | if (!bootcpu_valid) { | |
368 | pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n"); | |
369 | return; | |
370 | } | |
371 | ||
372 | /* | |
373 | * All the cpus that made it to the cpu_logical_map have been | |
374 | * validated so set them as possible cpus. | |
375 | */ | |
376 | for (i = 0; i < NR_CPUS; i++) | |
377 | if (cpu_logical_map(i) != INVALID_HWID) | |
378 | set_cpu_possible(i, true); | |
08e875c1 CM |
379 | } |
380 | ||
381 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
382 | { | |
d329de3f | 383 | int cpu, err; |
08e875c1 CM |
384 | unsigned int ncores = num_possible_cpus(); |
385 | ||
386 | /* | |
387 | * are we trying to boot more cores than exist? | |
388 | */ | |
389 | if (max_cpus > ncores) | |
390 | max_cpus = ncores; | |
391 | ||
d329de3f MZ |
392 | /* Don't bother if we're effectively UP */ |
393 | if (max_cpus <= 1) | |
394 | return; | |
395 | ||
08e875c1 CM |
396 | /* |
397 | * Initialise the present map (which describes the set of CPUs | |
398 | * actually populated at the present time) and release the | |
399 | * secondaries from the bootloader. | |
d329de3f MZ |
400 | * |
401 | * Make sure we online at most (max_cpus - 1) additional CPUs. | |
08e875c1 | 402 | */ |
d329de3f | 403 | max_cpus--; |
08e875c1 CM |
404 | for_each_possible_cpu(cpu) { |
405 | if (max_cpus == 0) | |
406 | break; | |
407 | ||
d329de3f MZ |
408 | if (cpu == smp_processor_id()) |
409 | continue; | |
410 | ||
411 | if (!smp_enable_ops[cpu]) | |
08e875c1 CM |
412 | continue; |
413 | ||
d329de3f MZ |
414 | err = smp_enable_ops[cpu]->prepare_cpu(cpu); |
415 | if (err) | |
416 | continue; | |
08e875c1 CM |
417 | |
418 | set_cpu_present(cpu, true); | |
419 | max_cpus--; | |
420 | } | |
08e875c1 CM |
421 | } |
422 | ||
423 | ||
424 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
425 | { | |
426 | smp_cross_call = fn; | |
427 | } | |
428 | ||
429 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) | |
430 | { | |
431 | smp_cross_call(mask, IPI_CALL_FUNC); | |
432 | } | |
433 | ||
434 | void arch_send_call_function_single_ipi(int cpu) | |
435 | { | |
436 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); | |
437 | } | |
438 | ||
439 | static const char *ipi_types[NR_IPI] = { | |
440 | #define S(x,s) [x - IPI_RESCHEDULE] = s | |
441 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), | |
442 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
443 | S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"), | |
444 | S(IPI_CPU_STOP, "CPU stop interrupts"), | |
445 | }; | |
446 | ||
447 | void show_ipi_list(struct seq_file *p, int prec) | |
448 | { | |
449 | unsigned int cpu, i; | |
450 | ||
451 | for (i = 0; i < NR_IPI; i++) { | |
452 | seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i + IPI_RESCHEDULE, | |
453 | prec >= 4 ? " " : ""); | |
454 | for_each_present_cpu(cpu) | |
455 | seq_printf(p, "%10u ", | |
456 | __get_irq_stat(cpu, ipi_irqs[i])); | |
457 | seq_printf(p, " %s\n", ipi_types[i]); | |
458 | } | |
459 | } | |
460 | ||
461 | u64 smp_irq_stat_cpu(unsigned int cpu) | |
462 | { | |
463 | u64 sum = 0; | |
464 | int i; | |
465 | ||
466 | for (i = 0; i < NR_IPI; i++) | |
467 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
468 | ||
469 | return sum; | |
470 | } | |
471 | ||
472 | static DEFINE_RAW_SPINLOCK(stop_lock); | |
473 | ||
474 | /* | |
475 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
476 | */ | |
477 | static void ipi_cpu_stop(unsigned int cpu) | |
478 | { | |
479 | if (system_state == SYSTEM_BOOTING || | |
480 | system_state == SYSTEM_RUNNING) { | |
481 | raw_spin_lock(&stop_lock); | |
482 | pr_crit("CPU%u: stopping\n", cpu); | |
483 | dump_stack(); | |
484 | raw_spin_unlock(&stop_lock); | |
485 | } | |
486 | ||
487 | set_cpu_online(cpu, false); | |
488 | ||
489 | local_fiq_disable(); | |
490 | local_irq_disable(); | |
491 | ||
492 | while (1) | |
493 | cpu_relax(); | |
494 | } | |
495 | ||
496 | /* | |
497 | * Main handler for inter-processor interrupts | |
498 | */ | |
499 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
500 | { | |
501 | unsigned int cpu = smp_processor_id(); | |
502 | struct pt_regs *old_regs = set_irq_regs(regs); | |
503 | ||
504 | if (ipinr >= IPI_RESCHEDULE && ipinr < IPI_RESCHEDULE + NR_IPI) | |
505 | __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_RESCHEDULE]); | |
506 | ||
507 | switch (ipinr) { | |
508 | case IPI_RESCHEDULE: | |
509 | scheduler_ipi(); | |
510 | break; | |
511 | ||
512 | case IPI_CALL_FUNC: | |
513 | irq_enter(); | |
514 | generic_smp_call_function_interrupt(); | |
515 | irq_exit(); | |
516 | break; | |
517 | ||
518 | case IPI_CALL_FUNC_SINGLE: | |
519 | irq_enter(); | |
520 | generic_smp_call_function_single_interrupt(); | |
521 | irq_exit(); | |
522 | break; | |
523 | ||
524 | case IPI_CPU_STOP: | |
525 | irq_enter(); | |
526 | ipi_cpu_stop(cpu); | |
527 | irq_exit(); | |
528 | break; | |
529 | ||
530 | default: | |
531 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); | |
532 | break; | |
533 | } | |
534 | set_irq_regs(old_regs); | |
535 | } | |
536 | ||
537 | void smp_send_reschedule(int cpu) | |
538 | { | |
539 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); | |
540 | } | |
541 | ||
542 | void smp_send_stop(void) | |
543 | { | |
544 | unsigned long timeout; | |
545 | ||
546 | if (num_online_cpus() > 1) { | |
547 | cpumask_t mask; | |
548 | ||
549 | cpumask_copy(&mask, cpu_online_mask); | |
550 | cpu_clear(smp_processor_id(), mask); | |
551 | ||
552 | smp_cross_call(&mask, IPI_CPU_STOP); | |
553 | } | |
554 | ||
555 | /* Wait up to one second for other CPUs to stop */ | |
556 | timeout = USEC_PER_SEC; | |
557 | while (num_online_cpus() > 1 && timeout--) | |
558 | udelay(1); | |
559 | ||
560 | if (num_online_cpus() > 1) | |
561 | pr_warning("SMP: failed to stop secondary CPUs\n"); | |
562 | } | |
563 | ||
564 | /* | |
565 | * not supported here | |
566 | */ | |
567 | int setup_profiling_timer(unsigned int multiplier) | |
568 | { | |
569 | return -EINVAL; | |
570 | } |