Commit | Line | Data |
---|---|---|
caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
08e875c1 CM |
2 | /* |
3 | * SMP initialisation and IPI support | |
4 | * Based on arch/arm/kernel/smp.c | |
5 | * | |
6 | * Copyright (C) 2012 ARM Ltd. | |
08e875c1 CM |
7 | */ |
8 | ||
0f078336 | 9 | #include <linux/acpi.h> |
f5df2696 | 10 | #include <linux/arm_sdei.h> |
08e875c1 CM |
11 | #include <linux/delay.h> |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
68e21be2 | 14 | #include <linux/sched/mm.h> |
ef8bd77f | 15 | #include <linux/sched/hotplug.h> |
68db0cf1 | 16 | #include <linux/sched/task_stack.h> |
08e875c1 CM |
17 | #include <linux/interrupt.h> |
18 | #include <linux/cache.h> | |
19 | #include <linux/profile.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/cpu.h> | |
24 | #include <linux/smp.h> | |
25 | #include <linux/seq_file.h> | |
26 | #include <linux/irq.h> | |
e7932188 | 27 | #include <linux/irqchip/arm-gic-v3.h> |
08e875c1 CM |
28 | #include <linux/percpu.h> |
29 | #include <linux/clockchips.h> | |
30 | #include <linux/completion.h> | |
31 | #include <linux/of.h> | |
eb631bb5 | 32 | #include <linux/irq_work.h> |
a2638815 | 33 | #include <linux/kernel_stat.h> |
78fd584c | 34 | #include <linux/kexec.h> |
2f5cd0c7 | 35 | #include <linux/kgdb.h> |
0492747c | 36 | #include <linux/kvm_host.h> |
331a1b3a | 37 | #include <linux/nmi.h> |
08e875c1 | 38 | |
e039ee4e | 39 | #include <asm/alternative.h> |
08e875c1 CM |
40 | #include <asm/atomic.h> |
41 | #include <asm/cacheflush.h> | |
df857416 | 42 | #include <asm/cpu.h> |
08e875c1 | 43 | #include <asm/cputype.h> |
cd1aebf5 | 44 | #include <asm/cpu_ops.h> |
0fbeb318 | 45 | #include <asm/daifflags.h> |
0492747c | 46 | #include <asm/kvm_mmu.h> |
08e875c1 | 47 | #include <asm/mmu_context.h> |
1a2db300 | 48 | #include <asm/numa.h> |
08e875c1 | 49 | #include <asm/processor.h> |
4c7aa002 | 50 | #include <asm/smp_plat.h> |
08e875c1 CM |
51 | #include <asm/sections.h> |
52 | #include <asm/tlbflush.h> | |
53 | #include <asm/ptrace.h> | |
377bcff9 | 54 | #include <asm/virt.h> |
08e875c1 | 55 | |
45ed695a NP |
56 | #include <trace/events/ipi.h> |
57 | ||
57c82954 MR |
58 | DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number); |
59 | EXPORT_PER_CPU_SYMBOL(cpu_number); | |
60 | ||
08e875c1 CM |
61 | /* |
62 | * as from 2.5, kernels no longer have an init_tasks structure | |
63 | * so we need some other way of telling a new secondary core | |
64 | * where to place its SVC stack | |
65 | */ | |
66 | struct secondary_data secondary_data; | |
bb905274 | 67 | /* Number of CPUs which aren't online, but looping in kernel text. */ |
2eaf63ba | 68 | static int cpus_stuck_in_kernel; |
08e875c1 CM |
69 | |
70 | enum ipi_msg_type { | |
71 | IPI_RESCHEDULE, | |
72 | IPI_CALL_FUNC, | |
08e875c1 | 73 | IPI_CPU_STOP, |
78fd584c | 74 | IPI_CPU_CRASH_STOP, |
1f85008e | 75 | IPI_TIMER, |
eb631bb5 | 76 | IPI_IRQ_WORK, |
331a1b3a DA |
77 | NR_IPI, |
78 | /* | |
79 | * Any enum >= NR_IPI and < MAX_IPI is special and not tracable | |
80 | * with trace_ipi_* | |
81 | */ | |
82 | IPI_CPU_BACKTRACE = NR_IPI, | |
2f5cd0c7 | 83 | IPI_KGDB_ROUNDUP, |
331a1b3a | 84 | MAX_IPI |
08e875c1 CM |
85 | }; |
86 | ||
62817d5b DA |
87 | static int ipi_irq_base __ro_after_init; |
88 | static int nr_ipi __ro_after_init = NR_IPI; | |
89 | static struct irq_desc *ipi_desc[MAX_IPI] __ro_after_init; | |
d3afc7f1 MZ |
90 | |
91 | static void ipi_setup(int cpu); | |
d3afc7f1 | 92 | |
bb905274 | 93 | #ifdef CONFIG_HOTPLUG_CPU |
9d9edb96 | 94 | static void ipi_teardown(int cpu); |
bb905274 SP |
95 | static int op_cpu_kill(unsigned int cpu); |
96 | #else | |
97 | static inline int op_cpu_kill(unsigned int cpu) | |
98 | { | |
99 | return -ENOSYS; | |
100 | } | |
101 | #endif | |
102 | ||
103 | ||
08e875c1 CM |
104 | /* |
105 | * Boot a secondary CPU, and assign it the specified idle task. | |
106 | * This also gives us the initial stack to use for this CPU. | |
107 | */ | |
b8c6453a | 108 | static int boot_secondary(unsigned int cpu, struct task_struct *idle) |
08e875c1 | 109 | { |
de58ed5e GS |
110 | const struct cpu_operations *ops = get_cpu_ops(cpu); |
111 | ||
112 | if (ops->cpu_boot) | |
113 | return ops->cpu_boot(cpu); | |
08e875c1 | 114 | |
652af899 | 115 | return -EOPNOTSUPP; |
08e875c1 CM |
116 | } |
117 | ||
118 | static DECLARE_COMPLETION(cpu_running); | |
119 | ||
b8c6453a | 120 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
08e875c1 CM |
121 | { |
122 | int ret; | |
bb905274 | 123 | long status; |
08e875c1 CM |
124 | |
125 | /* | |
126 | * We need to tell the secondary core where to find its stack and the | |
127 | * page tables. | |
128 | */ | |
c02433dd | 129 | secondary_data.task = idle; |
bb905274 | 130 | update_cpu_boot_status(CPU_MMU_OFF); |
08e875c1 | 131 | |
d22b115c | 132 | /* Now bring the CPU into our world */ |
08e875c1 | 133 | ret = boot_secondary(cpu, idle); |
d22b115c | 134 | if (ret) { |
08e875c1 | 135 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); |
f357b3a7 | 136 | return ret; |
08e875c1 CM |
137 | } |
138 | ||
d22b115c GS |
139 | /* |
140 | * CPU was successfully started, wait for it to come online or | |
141 | * time out. | |
142 | */ | |
143 | wait_for_completion_timeout(&cpu_running, | |
144 | msecs_to_jiffies(5000)); | |
145 | if (cpu_online(cpu)) | |
146 | return 0; | |
147 | ||
148 | pr_crit("CPU%u: failed to come online\n", cpu); | |
c02433dd | 149 | secondary_data.task = NULL; |
bb905274 | 150 | status = READ_ONCE(secondary_data.status); |
d22b115c GS |
151 | if (status == CPU_MMU_OFF) |
152 | status = READ_ONCE(__early_cpu_boot_status); | |
bb905274 | 153 | |
d22b115c GS |
154 | switch (status & CPU_BOOT_STATUS_MASK) { |
155 | default: | |
156 | pr_err("CPU%u: failed in unknown state : 0x%lx\n", | |
157 | cpu, status); | |
158 | cpus_stuck_in_kernel++; | |
159 | break; | |
160 | case CPU_KILL_ME: | |
161 | if (!op_cpu_kill(cpu)) { | |
162 | pr_crit("CPU%u: died during early boot\n", cpu); | |
bb905274 | 163 | break; |
bb905274 | 164 | } |
d22b115c | 165 | pr_crit("CPU%u: may not have shut down cleanly\n", cpu); |
df561f66 | 166 | fallthrough; |
d22b115c GS |
167 | case CPU_STUCK_IN_KERNEL: |
168 | pr_crit("CPU%u: is stuck in kernel\n", cpu); | |
169 | if (status & CPU_STUCK_REASON_52_BIT_VA) | |
170 | pr_crit("CPU%u: does not support 52-bit VAs\n", cpu); | |
171 | if (status & CPU_STUCK_REASON_NO_GRAN) { | |
172 | pr_crit("CPU%u: does not support %luK granule\n", | |
173 | cpu, PAGE_SIZE / SZ_1K); | |
174 | } | |
175 | cpus_stuck_in_kernel++; | |
176 | break; | |
177 | case CPU_PANIC_KERNEL: | |
178 | panic("CPU%u detected unsupported configuration\n", cpu); | |
bb905274 | 179 | } |
08e875c1 | 180 | |
ba051f09 | 181 | return -EIO; |
08e875c1 CM |
182 | } |
183 | ||
e7932188 JT |
184 | static void init_gic_priority_masking(void) |
185 | { | |
186 | u32 cpuflags; | |
187 | ||
188 | if (WARN_ON(!gic_enable_sre())) | |
189 | return; | |
190 | ||
191 | cpuflags = read_sysreg(daif); | |
192 | ||
193 | WARN_ON(!(cpuflags & PSR_I_BIT)); | |
f0098155 | 194 | WARN_ON(!(cpuflags & PSR_F_BIT)); |
e7932188 | 195 | |
e1d22385 | 196 | gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); |
e7932188 JT |
197 | } |
198 | ||
08e875c1 CM |
199 | /* |
200 | * This is the secondary CPU boot entry. We're using this CPUs | |
201 | * idle thread stack, but a set of temporary page tables. | |
202 | */ | |
b154886f | 203 | asmlinkage notrace void secondary_start_kernel(void) |
08e875c1 | 204 | { |
ccaac162 | 205 | u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; |
08e875c1 | 206 | struct mm_struct *mm = &init_mm; |
de58ed5e | 207 | const struct cpu_operations *ops; |
3d8c1a01 | 208 | unsigned int cpu = smp_processor_id(); |
08e875c1 | 209 | |
08e875c1 CM |
210 | /* |
211 | * All kernel threads share the same mm context; grab a | |
212 | * reference and switch to it. | |
213 | */ | |
f1f10076 | 214 | mmgrab(mm); |
08e875c1 | 215 | current->active_mm = mm; |
08e875c1 CM |
216 | |
217 | /* | |
218 | * TTBR0 is only used for the identity mapping at this stage. Make it | |
219 | * point to zero page to avoid speculatively fetching new entries. | |
220 | */ | |
9e8e865b | 221 | cpu_uninstall_idmap(); |
08e875c1 | 222 | |
e7932188 JT |
223 | if (system_uses_irq_prio_masking()) |
224 | init_gic_priority_masking(); | |
225 | ||
ce3d31ad | 226 | rcu_cpu_starting(cpu); |
08e875c1 CM |
227 | trace_hardirqs_off(); |
228 | ||
dbb4e152 SP |
229 | /* |
230 | * If the system has established the capabilities, make sure | |
231 | * this CPU ticks all of those. If it doesn't, the CPU will | |
232 | * fail to come online. | |
233 | */ | |
c47a1900 | 234 | check_local_cpu_capabilities(); |
dbb4e152 | 235 | |
de58ed5e GS |
236 | ops = get_cpu_ops(cpu); |
237 | if (ops->cpu_postboot) | |
238 | ops->cpu_postboot(); | |
08e875c1 | 239 | |
df857416 MR |
240 | /* |
241 | * Log the CPU info before it is marked online and might get read. | |
242 | */ | |
243 | cpuinfo_store_cpu(); | |
5524cbb1 | 244 | store_cpu_topology(cpu); |
df857416 | 245 | |
7ade67b5 MZ |
246 | /* |
247 | * Enable GIC and timers. | |
248 | */ | |
249 | notify_cpu_starting(cpu); | |
250 | ||
d3afc7f1 MZ |
251 | ipi_setup(cpu); |
252 | ||
97fd6016 | 253 | numa_add_cpu(cpu); |
f6e763b9 | 254 | |
08e875c1 CM |
255 | /* |
256 | * OK, now it's safe to let the boot CPU continue. Wait for | |
257 | * the CPU migration code to notice that the CPU is online | |
258 | * before we continue. | |
259 | */ | |
ccaac162 MR |
260 | pr_info("CPU%u: Booted secondary processor 0x%010lx [0x%08x]\n", |
261 | cpu, (unsigned long)mpidr, | |
262 | read_cpuid_id()); | |
bb905274 | 263 | update_cpu_boot_status(CPU_BOOT_SUCCESS); |
08e875c1 | 264 | set_cpu_online(cpu, true); |
b3770b32 | 265 | complete(&cpu_running); |
08e875c1 | 266 | |
41bd5b5d | 267 | local_daif_restore(DAIF_PROCCTX); |
53ae3acd | 268 | |
08e875c1 CM |
269 | /* |
270 | * OK, it's off to the idle thread for us | |
271 | */ | |
fc6d73d6 | 272 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
08e875c1 CM |
273 | } |
274 | ||
9327e2c6 MR |
275 | #ifdef CONFIG_HOTPLUG_CPU |
276 | static int op_cpu_disable(unsigned int cpu) | |
277 | { | |
de58ed5e GS |
278 | const struct cpu_operations *ops = get_cpu_ops(cpu); |
279 | ||
9327e2c6 MR |
280 | /* |
281 | * If we don't have a cpu_die method, abort before we reach the point | |
282 | * of no return. CPU0 may not have an cpu_ops, so test for it. | |
283 | */ | |
de58ed5e | 284 | if (!ops || !ops->cpu_die) |
9327e2c6 MR |
285 | return -EOPNOTSUPP; |
286 | ||
287 | /* | |
288 | * We may need to abort a hot unplug for some other mechanism-specific | |
289 | * reason. | |
290 | */ | |
de58ed5e GS |
291 | if (ops->cpu_disable) |
292 | return ops->cpu_disable(cpu); | |
9327e2c6 MR |
293 | |
294 | return 0; | |
295 | } | |
296 | ||
297 | /* | |
298 | * __cpu_disable runs on the processor to be shutdown. | |
299 | */ | |
300 | int __cpu_disable(void) | |
301 | { | |
302 | unsigned int cpu = smp_processor_id(); | |
303 | int ret; | |
304 | ||
305 | ret = op_cpu_disable(cpu); | |
306 | if (ret) | |
307 | return ret; | |
308 | ||
7f9545aa SH |
309 | remove_cpu_topology(cpu); |
310 | numa_remove_cpu(cpu); | |
311 | ||
9327e2c6 MR |
312 | /* |
313 | * Take this CPU offline. Once we clear this, we can't return, | |
314 | * and we must not schedule until we're ready to give up the cpu. | |
315 | */ | |
316 | set_cpu_online(cpu, false); | |
d3afc7f1 | 317 | ipi_teardown(cpu); |
9327e2c6 MR |
318 | |
319 | /* | |
320 | * OK - migrate IRQs away from this CPU | |
321 | */ | |
217d453d YY |
322 | irq_migrate_all_off_this_cpu(); |
323 | ||
9327e2c6 MR |
324 | return 0; |
325 | } | |
326 | ||
c814ca02 AC |
327 | static int op_cpu_kill(unsigned int cpu) |
328 | { | |
de58ed5e GS |
329 | const struct cpu_operations *ops = get_cpu_ops(cpu); |
330 | ||
c814ca02 AC |
331 | /* |
332 | * If we have no means of synchronising with the dying CPU, then assume | |
333 | * that it is really dead. We can only wait for an arbitrary length of | |
334 | * time and hope that it's dead, so let's skip the wait and just hope. | |
335 | */ | |
de58ed5e | 336 | if (!ops->cpu_kill) |
6b99c68c | 337 | return 0; |
c814ca02 | 338 | |
de58ed5e | 339 | return ops->cpu_kill(cpu); |
c814ca02 AC |
340 | } |
341 | ||
9327e2c6 | 342 | /* |
b3091f17 TG |
343 | * Called on the thread which is asking for a CPU to be shutdown after the |
344 | * shutdown completed. | |
9327e2c6 | 345 | */ |
b3091f17 | 346 | void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) |
9327e2c6 | 347 | { |
6b99c68c MR |
348 | int err; |
349 | ||
cf814bcf | 350 | pr_debug("CPU%u: shutdown\n", cpu); |
c814ca02 AC |
351 | |
352 | /* | |
353 | * Now that the dying CPU is beyond the point of no return w.r.t. | |
354 | * in-kernel synchronisation, try to get the firwmare to help us to | |
355 | * verify that it has really left the kernel before we consider | |
356 | * clobbering anything it might still be using. | |
357 | */ | |
6b99c68c MR |
358 | err = op_cpu_kill(cpu); |
359 | if (err) | |
a74ec64a | 360 | pr_warn("CPU%d may not have shut down cleanly: %d\n", cpu, err); |
9327e2c6 MR |
361 | } |
362 | ||
363 | /* | |
364 | * Called from the idle thread for the CPU which has been shutdown. | |
365 | * | |
9327e2c6 | 366 | */ |
9bdc61ef | 367 | void __noreturn cpu_die(void) |
9327e2c6 MR |
368 | { |
369 | unsigned int cpu = smp_processor_id(); | |
de58ed5e | 370 | const struct cpu_operations *ops = get_cpu_ops(cpu); |
9327e2c6 MR |
371 | |
372 | idle_task_exit(); | |
373 | ||
0fbeb318 | 374 | local_daif_mask(); |
9327e2c6 | 375 | |
b3091f17 TG |
376 | /* Tell cpuhp_bp_sync_dead() that this CPU is now safe to dispose of */ |
377 | cpuhp_ap_report_dead(); | |
9327e2c6 MR |
378 | |
379 | /* | |
380 | * Actually shutdown the CPU. This must never fail. The specific hotplug | |
381 | * mechanism must perform all required cache maintenance to ensure that | |
382 | * no dirty lines are lost in the process of shutting down the CPU. | |
383 | */ | |
de58ed5e | 384 | ops->cpu_die(cpu); |
9327e2c6 MR |
385 | |
386 | BUG(); | |
387 | } | |
388 | #endif | |
389 | ||
de58ed5e GS |
390 | static void __cpu_try_die(int cpu) |
391 | { | |
392 | #ifdef CONFIG_HOTPLUG_CPU | |
393 | const struct cpu_operations *ops = get_cpu_ops(cpu); | |
394 | ||
395 | if (ops && ops->cpu_die) | |
396 | ops->cpu_die(cpu); | |
397 | #endif | |
398 | } | |
399 | ||
fce6361f SP |
400 | /* |
401 | * Kill the calling secondary CPU, early in bringup before it is turned | |
402 | * online. | |
403 | */ | |
5ab6876c | 404 | void __noreturn cpu_die_early(void) |
fce6361f SP |
405 | { |
406 | int cpu = smp_processor_id(); | |
407 | ||
408 | pr_crit("CPU%d: will not boot\n", cpu); | |
409 | ||
410 | /* Mark this CPU absent */ | |
411 | set_cpu_present(cpu, 0); | |
04e613de | 412 | rcu_report_dead(cpu); |
fce6361f | 413 | |
de58ed5e GS |
414 | if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) { |
415 | update_cpu_boot_status(CPU_KILL_ME); | |
416 | __cpu_try_die(cpu); | |
417 | } | |
418 | ||
bb905274 | 419 | update_cpu_boot_status(CPU_STUCK_IN_KERNEL); |
fce6361f SP |
420 | |
421 | cpu_park_loop(); | |
422 | } | |
423 | ||
377bcff9 JR |
424 | static void __init hyp_mode_check(void) |
425 | { | |
426 | if (is_hyp_mode_available()) | |
427 | pr_info("CPU: All CPU(s) started at EL2\n"); | |
428 | else if (is_hyp_mode_mismatched()) | |
429 | WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC, | |
430 | "CPU: CPUs started in inconsistent modes"); | |
431 | else | |
432 | pr_info("CPU: All CPU(s) started at EL1\n"); | |
6ec6259d | 433 | if (IS_ENABLED(CONFIG_KVM) && !is_kernel_in_hyp_mode()) { |
0492747c | 434 | kvm_compute_layout(); |
6ec6259d DB |
435 | kvm_apply_hyp_relocations(); |
436 | } | |
377bcff9 JR |
437 | } |
438 | ||
08e875c1 CM |
439 | void __init smp_cpus_done(unsigned int max_cpus) |
440 | { | |
326b16db | 441 | pr_info("SMP: Total of %d processors activated.\n", num_online_cpus()); |
3a75578e | 442 | setup_cpu_features(); |
377bcff9 JR |
443 | hyp_mode_check(); |
444 | apply_alternatives_all(); | |
5ea5306c | 445 | mark_linear_text_alias_ro(); |
08e875c1 CM |
446 | } |
447 | ||
448 | void __init smp_prepare_boot_cpu(void) | |
449 | { | |
3d8c1a01 MR |
450 | /* |
451 | * The runtime per-cpu areas have been allocated by | |
452 | * setup_per_cpu_areas(), and CPU0's boot time per-cpu area will be | |
453 | * freed shortly, so we must move over to the runtime per-cpu area. | |
454 | */ | |
9113c2aa | 455 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
4b998ff1 | 456 | cpuinfo_store_boot_cpu(); |
0ceb0d56 DT |
457 | |
458 | /* | |
459 | * We now know enough about the boot CPU to apply the | |
460 | * alternatives that cannot wait until interrupt handling | |
461 | * and/or scheduling is enabled. | |
462 | */ | |
463 | apply_boot_alternatives(); | |
e7932188 JT |
464 | |
465 | /* Conditionally switch to GIC PMR for interrupt masking */ | |
466 | if (system_uses_irq_prio_masking()) | |
467 | init_gic_priority_masking(); | |
2e903b91 AK |
468 | |
469 | kasan_init_hw_tags(); | |
08e875c1 CM |
470 | } |
471 | ||
0f078336 LP |
472 | /* |
473 | * Duplicate MPIDRs are a recipe for disaster. Scan all initialized | |
474 | * entries and check for duplicates. If any is found just ignore the | |
475 | * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid | |
476 | * matching valid MPIDR values. | |
477 | */ | |
478 | static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid) | |
479 | { | |
480 | unsigned int i; | |
481 | ||
482 | for (i = 1; (i < cpu) && (i < NR_CPUS); i++) | |
483 | if (cpu_logical_map(i) == hwid) | |
484 | return true; | |
485 | return false; | |
486 | } | |
487 | ||
819a8826 LP |
488 | /* |
489 | * Initialize cpu operations for a logical cpu and | |
490 | * set it in the possible mask on success | |
491 | */ | |
492 | static int __init smp_cpu_setup(int cpu) | |
493 | { | |
de58ed5e GS |
494 | const struct cpu_operations *ops; |
495 | ||
6885fb12 | 496 | if (init_cpu_ops(cpu)) |
819a8826 LP |
497 | return -ENODEV; |
498 | ||
de58ed5e GS |
499 | ops = get_cpu_ops(cpu); |
500 | if (ops->cpu_init(cpu)) | |
819a8826 LP |
501 | return -ENODEV; |
502 | ||
503 | set_cpu_possible(cpu, true); | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
0f078336 LP |
508 | static bool bootcpu_valid __initdata; |
509 | static unsigned int cpu_count = 1; | |
510 | ||
511 | #ifdef CONFIG_ACPI | |
e0013aed MR |
512 | static struct acpi_madt_generic_interrupt cpu_madt_gicc[NR_CPUS]; |
513 | ||
514 | struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu) | |
515 | { | |
516 | return &cpu_madt_gicc[cpu]; | |
517 | } | |
d3c3db41 | 518 | EXPORT_SYMBOL_GPL(acpi_cpu_get_madt_gicc); |
e0013aed | 519 | |
0f078336 LP |
520 | /* |
521 | * acpi_map_gic_cpu_interface - parse processor MADT entry | |
522 | * | |
523 | * Carry out sanity checks on MADT processor entry and initialize | |
524 | * cpu_logical_map on success | |
525 | */ | |
526 | static void __init | |
527 | acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) | |
528 | { | |
529 | u64 hwid = processor->arm_mpidr; | |
530 | ||
f9058929 HG |
531 | if (!(processor->flags & ACPI_MADT_ENABLED)) { |
532 | pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); | |
0f078336 LP |
533 | return; |
534 | } | |
535 | ||
f9058929 HG |
536 | if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { |
537 | pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); | |
0f078336 LP |
538 | return; |
539 | } | |
540 | ||
541 | if (is_mpidr_duplicate(cpu_count, hwid)) { | |
542 | pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid); | |
543 | return; | |
544 | } | |
545 | ||
546 | /* Check if GICC structure of boot CPU is available in the MADT */ | |
547 | if (cpu_logical_map(0) == hwid) { | |
548 | if (bootcpu_valid) { | |
549 | pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n", | |
550 | hwid); | |
551 | return; | |
552 | } | |
553 | bootcpu_valid = true; | |
e0013aed | 554 | cpu_madt_gicc[0] = *processor; |
0f078336 LP |
555 | return; |
556 | } | |
557 | ||
558 | if (cpu_count >= NR_CPUS) | |
559 | return; | |
560 | ||
561 | /* map the logical cpu id to cpu MPIDR */ | |
eaecca9e | 562 | set_cpu_logical_map(cpu_count, hwid); |
0f078336 | 563 | |
e0013aed MR |
564 | cpu_madt_gicc[cpu_count] = *processor; |
565 | ||
5e89c55e LP |
566 | /* |
567 | * Set-up the ACPI parking protocol cpu entries | |
568 | * while initializing the cpu_logical_map to | |
569 | * avoid parsing MADT entries multiple times for | |
570 | * nothing (ie a valid cpu_logical_map entry should | |
571 | * contain a valid parking protocol data set to | |
572 | * initialize the cpu if the parking protocol is | |
573 | * the only available enable method). | |
574 | */ | |
575 | acpi_set_mailbox_entry(cpu_count, processor); | |
576 | ||
0f078336 LP |
577 | cpu_count++; |
578 | } | |
579 | ||
580 | static int __init | |
60574d1e | 581 | acpi_parse_gic_cpu_interface(union acpi_subtable_headers *header, |
0f078336 LP |
582 | const unsigned long end) |
583 | { | |
584 | struct acpi_madt_generic_interrupt *processor; | |
585 | ||
586 | processor = (struct acpi_madt_generic_interrupt *)header; | |
99e3e3ae | 587 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
0f078336 LP |
588 | return -EINVAL; |
589 | ||
60574d1e | 590 | acpi_table_print_madt_entry(&header->common); |
0f078336 LP |
591 | |
592 | acpi_map_gic_cpu_interface(processor); | |
593 | ||
594 | return 0; | |
595 | } | |
e1896249 LP |
596 | |
597 | static void __init acpi_parse_and_init_cpus(void) | |
598 | { | |
599 | int i; | |
600 | ||
601 | /* | |
602 | * do a walk of MADT to determine how many CPUs | |
603 | * we have including disabled CPUs, and get information | |
604 | * we need for SMP init. | |
605 | */ | |
606 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
607 | acpi_parse_gic_cpu_interface, 0); | |
608 | ||
609 | /* | |
610 | * In ACPI, SMP and CPU NUMA information is provided in separate | |
611 | * static tables, namely the MADT and the SRAT. | |
612 | * | |
613 | * Thus, it is simpler to first create the cpu logical map through | |
614 | * an MADT walk and then map the logical cpus to their node ids | |
615 | * as separate steps. | |
616 | */ | |
617 | acpi_map_cpus_to_nodes(); | |
618 | ||
619 | for (i = 0; i < nr_cpu_ids; i++) | |
620 | early_map_cpu_to_node(i, acpi_numa_get_nid(i)); | |
621 | } | |
0f078336 | 622 | #else |
e1896249 | 623 | #define acpi_parse_and_init_cpus(...) do { } while (0) |
0f078336 LP |
624 | #endif |
625 | ||
08e875c1 | 626 | /* |
4c7aa002 JM |
627 | * Enumerate the possible CPU set from the device tree and build the |
628 | * cpu logical map array containing MPIDR values related to logical | |
629 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
08e875c1 | 630 | */ |
29b8302b | 631 | static void __init of_parse_and_init_cpus(void) |
08e875c1 | 632 | { |
3d29a9a0 | 633 | struct device_node *dn; |
08e875c1 | 634 | |
de76e70a | 635 | for_each_of_cpu_node(dn) { |
4d97b929 | 636 | u64 hwid = of_get_cpu_hwid(dn, 0); |
4c7aa002 | 637 | |
4d97b929 | 638 | if (hwid & ~MPIDR_HWID_BITMASK) |
4c7aa002 | 639 | goto next; |
4c7aa002 | 640 | |
0f078336 | 641 | if (is_mpidr_duplicate(cpu_count, hwid)) { |
a270f327 RH |
642 | pr_err("%pOF: duplicate cpu reg properties in the DT\n", |
643 | dn); | |
4c7aa002 JM |
644 | goto next; |
645 | } | |
646 | ||
4c7aa002 JM |
647 | /* |
648 | * The numbering scheme requires that the boot CPU | |
649 | * must be assigned logical id 0. Record it so that | |
650 | * the logical map built from DT is validated and can | |
651 | * be used. | |
652 | */ | |
653 | if (hwid == cpu_logical_map(0)) { | |
654 | if (bootcpu_valid) { | |
a270f327 RH |
655 | pr_err("%pOF: duplicate boot cpu reg property in DT\n", |
656 | dn); | |
4c7aa002 JM |
657 | goto next; |
658 | } | |
659 | ||
660 | bootcpu_valid = true; | |
7ba5f605 | 661 | early_map_cpu_to_node(0, of_node_to_nid(dn)); |
4c7aa002 JM |
662 | |
663 | /* | |
664 | * cpu_logical_map has already been | |
665 | * initialized and the boot cpu doesn't need | |
666 | * the enable-method so continue without | |
667 | * incrementing cpu. | |
668 | */ | |
669 | continue; | |
670 | } | |
671 | ||
0f078336 | 672 | if (cpu_count >= NR_CPUS) |
08e875c1 CM |
673 | goto next; |
674 | ||
4c7aa002 | 675 | pr_debug("cpu logical map 0x%llx\n", hwid); |
eaecca9e | 676 | set_cpu_logical_map(cpu_count, hwid); |
1a2db300 GK |
677 | |
678 | early_map_cpu_to_node(cpu_count, of_node_to_nid(dn)); | |
08e875c1 | 679 | next: |
0f078336 | 680 | cpu_count++; |
08e875c1 | 681 | } |
0f078336 LP |
682 | } |
683 | ||
684 | /* | |
685 | * Enumerate the possible CPU set from the device tree or ACPI and build the | |
686 | * cpu logical map array containing MPIDR values related to logical | |
687 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
688 | */ | |
689 | void __init smp_init_cpus(void) | |
690 | { | |
691 | int i; | |
692 | ||
693 | if (acpi_disabled) | |
694 | of_parse_and_init_cpus(); | |
695 | else | |
e1896249 | 696 | acpi_parse_and_init_cpus(); |
08e875c1 | 697 | |
50ee91bd | 698 | if (cpu_count > nr_cpu_ids) |
9b130ad5 | 699 | pr_warn("Number of cores (%d) exceeds configured maximum of %u - clipping\n", |
50ee91bd | 700 | cpu_count, nr_cpu_ids); |
4c7aa002 JM |
701 | |
702 | if (!bootcpu_valid) { | |
0f078336 | 703 | pr_err("missing boot CPU MPIDR, not enabling secondaries\n"); |
4c7aa002 JM |
704 | return; |
705 | } | |
706 | ||
707 | /* | |
819a8826 LP |
708 | * We need to set the cpu_logical_map entries before enabling |
709 | * the cpus so that cpu processor description entries (DT cpu nodes | |
710 | * and ACPI MADT entries) can be retrieved by matching the cpu hwid | |
711 | * with entries in cpu_logical_map while initializing the cpus. | |
712 | * If the cpu set-up fails, invalidate the cpu_logical_map entry. | |
4c7aa002 | 713 | */ |
50ee91bd | 714 | for (i = 1; i < nr_cpu_ids; i++) { |
819a8826 LP |
715 | if (cpu_logical_map(i) != INVALID_HWID) { |
716 | if (smp_cpu_setup(i)) | |
eaecca9e | 717 | set_cpu_logical_map(i, INVALID_HWID); |
819a8826 LP |
718 | } |
719 | } | |
08e875c1 CM |
720 | } |
721 | ||
722 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
723 | { | |
de58ed5e | 724 | const struct cpu_operations *ops; |
cd1aebf5 | 725 | int err; |
44dbcc93 | 726 | unsigned int cpu; |
c18df0ad | 727 | unsigned int this_cpu; |
08e875c1 | 728 | |
f6e763b9 MB |
729 | init_cpu_topology(); |
730 | ||
c18df0ad DD |
731 | this_cpu = smp_processor_id(); |
732 | store_cpu_topology(this_cpu); | |
733 | numa_store_cpu_info(this_cpu); | |
97fd6016 | 734 | numa_add_cpu(this_cpu); |
f6e763b9 | 735 | |
e75118a7 SP |
736 | /* |
737 | * If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set | |
738 | * secondary CPUs present. | |
739 | */ | |
740 | if (max_cpus == 0) | |
741 | return; | |
742 | ||
08e875c1 CM |
743 | /* |
744 | * Initialise the present map (which describes the set of CPUs | |
745 | * actually populated at the present time) and release the | |
746 | * secondaries from the bootloader. | |
747 | */ | |
748 | for_each_possible_cpu(cpu) { | |
08e875c1 | 749 | |
57c82954 MR |
750 | per_cpu(cpu_number, cpu) = cpu; |
751 | ||
d329de3f MZ |
752 | if (cpu == smp_processor_id()) |
753 | continue; | |
754 | ||
de58ed5e GS |
755 | ops = get_cpu_ops(cpu); |
756 | if (!ops) | |
08e875c1 CM |
757 | continue; |
758 | ||
de58ed5e | 759 | err = ops->cpu_prepare(cpu); |
d329de3f MZ |
760 | if (err) |
761 | continue; | |
08e875c1 CM |
762 | |
763 | set_cpu_present(cpu, true); | |
c18df0ad | 764 | numa_store_cpu_info(cpu); |
08e875c1 | 765 | } |
08e875c1 CM |
766 | } |
767 | ||
45ed695a | 768 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
0edaee42 AK |
769 | [IPI_RESCHEDULE] = "Rescheduling interrupts", |
770 | [IPI_CALL_FUNC] = "Function call interrupts", | |
771 | [IPI_CPU_STOP] = "CPU stop interrupts", | |
772 | [IPI_CPU_CRASH_STOP] = "CPU stop (for crash dump) interrupts", | |
773 | [IPI_TIMER] = "Timer broadcast interrupts", | |
774 | [IPI_IRQ_WORK] = "IRQ work interrupts", | |
08e875c1 CM |
775 | }; |
776 | ||
5cebfd2d | 777 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr); |
45ed695a | 778 | |
a2638815 MZ |
779 | unsigned long irq_err_count; |
780 | ||
781 | int arch_show_interrupts(struct seq_file *p, int prec) | |
08e875c1 CM |
782 | { |
783 | unsigned int cpu, i; | |
784 | ||
785 | for (i = 0; i < NR_IPI; i++) { | |
45ed695a | 786 | seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, |
08e875c1 | 787 | prec >= 4 ? " " : ""); |
67317c26 | 788 | for_each_online_cpu(cpu) |
5089bc51 | 789 | seq_printf(p, "%10u ", irq_desc_kstat_cpu(ipi_desc[i], cpu)); |
08e875c1 CM |
790 | seq_printf(p, " %s\n", ipi_types[i]); |
791 | } | |
08e875c1 | 792 | |
a2638815 MZ |
793 | seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); |
794 | return 0; | |
08e875c1 CM |
795 | } |
796 | ||
45ed695a NP |
797 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
798 | { | |
799 | smp_cross_call(mask, IPI_CALL_FUNC); | |
800 | } | |
801 | ||
802 | void arch_send_call_function_single_ipi(int cpu) | |
803 | { | |
0aaf0dae | 804 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
45ed695a NP |
805 | } |
806 | ||
807 | #ifdef CONFIG_IRQ_WORK | |
808 | void arch_irq_work_raise(void) | |
809 | { | |
5cebfd2d | 810 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); |
45ed695a NP |
811 | } |
812 | #endif | |
813 | ||
5ab6876c | 814 | static void __noreturn local_cpu_stop(void) |
08e875c1 | 815 | { |
d914d4d4 | 816 | set_cpu_online(smp_processor_id(), false); |
08e875c1 | 817 | |
0fbeb318 | 818 | local_daif_mask(); |
f5df2696 | 819 | sdei_mask_local_cpu(); |
dccc9da2 | 820 | cpu_park_loop(); |
08e875c1 | 821 | } |
08e875c1 | 822 | |
d914d4d4 AK |
823 | /* |
824 | * We need to implement panic_smp_self_stop() for parallel panic() calls, so | |
825 | * that cpu_online_mask gets correctly updated and smp_send_stop() can skip | |
826 | * CPUs that have already stopped themselves. | |
827 | */ | |
7412a60d | 828 | void __noreturn panic_smp_self_stop(void) |
d914d4d4 AK |
829 | { |
830 | local_cpu_stop(); | |
08e875c1 CM |
831 | } |
832 | ||
78fd584c AT |
833 | #ifdef CONFIG_KEXEC_CORE |
834 | static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0); | |
835 | #endif | |
836 | ||
5ab6876c | 837 | static void __noreturn ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) |
78fd584c AT |
838 | { |
839 | #ifdef CONFIG_KEXEC_CORE | |
840 | crash_save_cpu(regs, cpu); | |
841 | ||
842 | atomic_dec(&waiting_for_crash_ipi); | |
843 | ||
844 | local_irq_disable(); | |
f5df2696 | 845 | sdei_mask_local_cpu(); |
78fd584c | 846 | |
de58ed5e GS |
847 | if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) |
848 | __cpu_try_die(cpu); | |
78fd584c AT |
849 | |
850 | /* just in case */ | |
851 | cpu_park_loop(); | |
5ab6876c JP |
852 | #else |
853 | BUG(); | |
78fd584c AT |
854 | #endif |
855 | } | |
856 | ||
331a1b3a DA |
857 | static void arm64_backtrace_ipi(cpumask_t *mask) |
858 | { | |
859 | __ipi_send_mask(ipi_desc[IPI_CPU_BACKTRACE], mask); | |
860 | } | |
861 | ||
862 | void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu) | |
863 | { | |
864 | /* | |
865 | * NOTE: though nmi_trigger_cpumask_backtrace() has "nmi_" in the name, | |
866 | * nothing about it truly needs to be implemented using an NMI, it's | |
867 | * just that it's _allowed_ to work with NMIs. If ipi_should_be_nmi() | |
868 | * returned false our backtrace attempt will just use a regular IPI. | |
869 | */ | |
870 | nmi_trigger_cpumask_backtrace(mask, exclude_cpu, arm64_backtrace_ipi); | |
871 | } | |
872 | ||
2f5cd0c7 DA |
873 | #ifdef CONFIG_KGDB |
874 | void kgdb_roundup_cpus(void) | |
875 | { | |
876 | int this_cpu = raw_smp_processor_id(); | |
877 | int cpu; | |
878 | ||
879 | for_each_online_cpu(cpu) { | |
880 | /* No need to roundup ourselves */ | |
881 | if (cpu == this_cpu) | |
882 | continue; | |
883 | ||
884 | __ipi_send_single(ipi_desc[IPI_KGDB_ROUNDUP], cpu); | |
885 | } | |
886 | } | |
887 | #endif | |
888 | ||
08e875c1 CM |
889 | /* |
890 | * Main handler for inter-processor interrupts | |
891 | */ | |
d3afc7f1 | 892 | static void do_handle_IPI(int ipinr) |
08e875c1 CM |
893 | { |
894 | unsigned int cpu = smp_processor_id(); | |
08e875c1 | 895 | |
a2638815 | 896 | if ((unsigned)ipinr < NR_IPI) |
4a3182e6 | 897 | trace_ipi_entry(ipi_types[ipinr]); |
08e875c1 CM |
898 | |
899 | switch (ipinr) { | |
900 | case IPI_RESCHEDULE: | |
901 | scheduler_ipi(); | |
902 | break; | |
903 | ||
904 | case IPI_CALL_FUNC: | |
08e875c1 | 905 | generic_smp_call_function_interrupt(); |
08e875c1 CM |
906 | break; |
907 | ||
08e875c1 | 908 | case IPI_CPU_STOP: |
d914d4d4 | 909 | local_cpu_stop(); |
08e875c1 CM |
910 | break; |
911 | ||
78fd584c AT |
912 | case IPI_CPU_CRASH_STOP: |
913 | if (IS_ENABLED(CONFIG_KEXEC_CORE)) { | |
d3afc7f1 | 914 | ipi_cpu_crash_stop(cpu, get_irq_regs()); |
78fd584c AT |
915 | |
916 | unreachable(); | |
917 | } | |
918 | break; | |
919 | ||
1f85008e LP |
920 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
921 | case IPI_TIMER: | |
1f85008e | 922 | tick_receive_broadcast(); |
1f85008e LP |
923 | break; |
924 | #endif | |
925 | ||
eb631bb5 LB |
926 | #ifdef CONFIG_IRQ_WORK |
927 | case IPI_IRQ_WORK: | |
eb631bb5 | 928 | irq_work_run(); |
eb631bb5 LB |
929 | break; |
930 | #endif | |
931 | ||
331a1b3a DA |
932 | case IPI_CPU_BACKTRACE: |
933 | /* | |
934 | * NOTE: in some cases this _won't_ be NMI context. See the | |
935 | * comment in arch_trigger_cpumask_backtrace(). | |
936 | */ | |
937 | nmi_cpu_backtrace(get_irq_regs()); | |
938 | break; | |
939 | ||
2f5cd0c7 DA |
940 | case IPI_KGDB_ROUNDUP: |
941 | kgdb_nmicallback(cpu, get_irq_regs()); | |
942 | break; | |
943 | ||
08e875c1 CM |
944 | default: |
945 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); | |
946 | break; | |
947 | } | |
45ed695a NP |
948 | |
949 | if ((unsigned)ipinr < NR_IPI) | |
4a3182e6 | 950 | trace_ipi_exit(ipi_types[ipinr]); |
d3afc7f1 MZ |
951 | } |
952 | ||
d3afc7f1 MZ |
953 | static irqreturn_t ipi_handler(int irq, void *data) |
954 | { | |
955 | do_handle_IPI(irq - ipi_irq_base); | |
956 | return IRQ_HANDLED; | |
957 | } | |
958 | ||
5cebfd2d | 959 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
d3afc7f1 | 960 | { |
5cebfd2d MZ |
961 | trace_ipi_raise(target, ipi_types[ipinr]); |
962 | __ipi_send_mask(ipi_desc[ipinr], target); | |
d3afc7f1 MZ |
963 | } |
964 | ||
331a1b3a DA |
965 | static bool ipi_should_be_nmi(enum ipi_msg_type ipi) |
966 | { | |
a07a5941 MR |
967 | DECLARE_STATIC_KEY_FALSE(supports_pseudo_nmis); |
968 | ||
969 | if (!system_uses_irq_prio_masking() || | |
970 | !static_branch_likely(&supports_pseudo_nmis)) | |
331a1b3a DA |
971 | return false; |
972 | ||
973 | switch (ipi) { | |
d7402513 DA |
974 | case IPI_CPU_STOP: |
975 | case IPI_CPU_CRASH_STOP: | |
331a1b3a | 976 | case IPI_CPU_BACKTRACE: |
2f5cd0c7 | 977 | case IPI_KGDB_ROUNDUP: |
331a1b3a DA |
978 | return true; |
979 | default: | |
980 | return false; | |
981 | } | |
982 | } | |
983 | ||
d3afc7f1 MZ |
984 | static void ipi_setup(int cpu) |
985 | { | |
986 | int i; | |
987 | ||
5cebfd2d | 988 | if (WARN_ON_ONCE(!ipi_irq_base)) |
d3afc7f1 MZ |
989 | return; |
990 | ||
331a1b3a DA |
991 | for (i = 0; i < nr_ipi; i++) { |
992 | if (ipi_should_be_nmi(i)) { | |
993 | prepare_percpu_nmi(ipi_irq_base + i); | |
994 | enable_percpu_nmi(ipi_irq_base + i, 0); | |
995 | } else { | |
996 | enable_percpu_irq(ipi_irq_base + i, 0); | |
997 | } | |
998 | } | |
d3afc7f1 MZ |
999 | } |
1000 | ||
9d9edb96 | 1001 | #ifdef CONFIG_HOTPLUG_CPU |
d3afc7f1 MZ |
1002 | static void ipi_teardown(int cpu) |
1003 | { | |
1004 | int i; | |
1005 | ||
5cebfd2d | 1006 | if (WARN_ON_ONCE(!ipi_irq_base)) |
d3afc7f1 MZ |
1007 | return; |
1008 | ||
331a1b3a DA |
1009 | for (i = 0; i < nr_ipi; i++) { |
1010 | if (ipi_should_be_nmi(i)) { | |
1011 | disable_percpu_nmi(ipi_irq_base + i); | |
1012 | teardown_percpu_nmi(ipi_irq_base + i); | |
1013 | } else { | |
1014 | disable_percpu_irq(ipi_irq_base + i); | |
1015 | } | |
1016 | } | |
d3afc7f1 | 1017 | } |
9d9edb96 | 1018 | #endif |
d3afc7f1 MZ |
1019 | |
1020 | void __init set_smp_ipi_range(int ipi_base, int n) | |
1021 | { | |
1022 | int i; | |
1023 | ||
331a1b3a DA |
1024 | WARN_ON(n < MAX_IPI); |
1025 | nr_ipi = min(n, MAX_IPI); | |
d3afc7f1 MZ |
1026 | |
1027 | for (i = 0; i < nr_ipi; i++) { | |
1028 | int err; | |
1029 | ||
331a1b3a DA |
1030 | if (ipi_should_be_nmi(i)) { |
1031 | err = request_percpu_nmi(ipi_base + i, ipi_handler, | |
1032 | "IPI", &cpu_number); | |
1033 | WARN(err, "Could not request IPI %d as NMI, err=%d\n", | |
1034 | i, err); | |
1035 | } else { | |
1036 | err = request_percpu_irq(ipi_base + i, ipi_handler, | |
1037 | "IPI", &cpu_number); | |
1038 | WARN(err, "Could not request IPI %d as IRQ, err=%d\n", | |
1039 | i, err); | |
1040 | } | |
d3afc7f1 MZ |
1041 | |
1042 | ipi_desc[i] = irq_to_desc(ipi_base + i); | |
1043 | irq_set_status_flags(ipi_base + i, IRQ_HIDDEN); | |
1044 | } | |
1045 | ||
1046 | ipi_irq_base = ipi_base; | |
d3afc7f1 MZ |
1047 | |
1048 | /* Setup the boot CPU immediately */ | |
1049 | ipi_setup(smp_processor_id()); | |
1050 | } | |
1051 | ||
4c8c3c7f | 1052 | void arch_smp_send_reschedule(int cpu) |
08e875c1 CM |
1053 | { |
1054 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); | |
1055 | } | |
1056 | ||
2b2d0a7a MR |
1057 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
1058 | void arch_send_wakeup_ipi(unsigned int cpu) | |
1059 | { | |
1060 | /* | |
1061 | * We use a scheduler IPI to wake the CPU as this avoids the need for a | |
1062 | * dedicated IPI and we can safely handle spurious scheduler IPIs. | |
1063 | */ | |
1064 | arch_smp_send_reschedule(cpu); | |
1065 | } | |
1066 | #endif | |
1067 | ||
1f85008e LP |
1068 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
1069 | void tick_broadcast(const struct cpumask *mask) | |
1070 | { | |
1071 | smp_cross_call(mask, IPI_TIMER); | |
1072 | } | |
1073 | #endif | |
1074 | ||
d0bab0c3 CM |
1075 | /* |
1076 | * The number of CPUs online, not counting this CPU (which may not be | |
1077 | * fully online and so not counted in num_online_cpus()). | |
1078 | */ | |
1079 | static inline unsigned int num_other_online_cpus(void) | |
1080 | { | |
1081 | unsigned int this_cpu_online = cpu_online(smp_processor_id()); | |
1082 | ||
1083 | return num_online_cpus() - this_cpu_online; | |
1084 | } | |
1085 | ||
08e875c1 CM |
1086 | void smp_send_stop(void) |
1087 | { | |
1088 | unsigned long timeout; | |
1089 | ||
d0bab0c3 | 1090 | if (num_other_online_cpus()) { |
08e875c1 CM |
1091 | cpumask_t mask; |
1092 | ||
1093 | cpumask_copy(&mask, cpu_online_mask); | |
434ed7f4 | 1094 | cpumask_clear_cpu(smp_processor_id(), &mask); |
08e875c1 | 1095 | |
ef284f5c | 1096 | if (system_state <= SYSTEM_RUNNING) |
82611c14 | 1097 | pr_crit("SMP: stopping secondary CPUs\n"); |
08e875c1 CM |
1098 | smp_cross_call(&mask, IPI_CPU_STOP); |
1099 | } | |
1100 | ||
1101 | /* Wait up to one second for other CPUs to stop */ | |
1102 | timeout = USEC_PER_SEC; | |
d0bab0c3 | 1103 | while (num_other_online_cpus() && timeout--) |
08e875c1 CM |
1104 | udelay(1); |
1105 | ||
d0bab0c3 | 1106 | if (num_other_online_cpus()) |
a74ec64a KW |
1107 | pr_warn("SMP: failed to stop secondary CPUs %*pbl\n", |
1108 | cpumask_pr_args(cpu_online_mask)); | |
f5df2696 JM |
1109 | |
1110 | sdei_mask_local_cpu(); | |
08e875c1 CM |
1111 | } |
1112 | ||
78fd584c | 1113 | #ifdef CONFIG_KEXEC_CORE |
a88ce63b | 1114 | void crash_smp_send_stop(void) |
78fd584c | 1115 | { |
a88ce63b | 1116 | static int cpus_stopped; |
78fd584c AT |
1117 | cpumask_t mask; |
1118 | unsigned long timeout; | |
1119 | ||
a88ce63b HR |
1120 | /* |
1121 | * This function can be called twice in panic path, but obviously | |
1122 | * we execute this only once. | |
1123 | */ | |
1124 | if (cpus_stopped) | |
1125 | return; | |
1126 | ||
1127 | cpus_stopped = 1; | |
1128 | ||
f50b7dac CM |
1129 | /* |
1130 | * If this cpu is the only one alive at this point in time, online or | |
1131 | * not, there are no stop messages to be sent around, so just back out. | |
1132 | */ | |
5cd474e5 SP |
1133 | if (num_other_online_cpus() == 0) |
1134 | goto skip_ipi; | |
78fd584c AT |
1135 | |
1136 | cpumask_copy(&mask, cpu_online_mask); | |
1137 | cpumask_clear_cpu(smp_processor_id(), &mask); | |
1138 | ||
f50b7dac | 1139 | atomic_set(&waiting_for_crash_ipi, num_other_online_cpus()); |
78fd584c AT |
1140 | |
1141 | pr_crit("SMP: stopping secondary CPUs\n"); | |
1142 | smp_cross_call(&mask, IPI_CPU_CRASH_STOP); | |
1143 | ||
1144 | /* Wait up to one second for other CPUs to stop */ | |
1145 | timeout = USEC_PER_SEC; | |
1146 | while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--) | |
1147 | udelay(1); | |
1148 | ||
1149 | if (atomic_read(&waiting_for_crash_ipi) > 0) | |
a74ec64a KW |
1150 | pr_warn("SMP: failed to stop secondary CPUs %*pbl\n", |
1151 | cpumask_pr_args(&mask)); | |
f5df2696 | 1152 | |
5cd474e5 | 1153 | skip_ipi: |
f5df2696 | 1154 | sdei_mask_local_cpu(); |
5cd474e5 | 1155 | sdei_handler_abort(); |
78fd584c AT |
1156 | } |
1157 | ||
1158 | bool smp_crash_stop_failed(void) | |
1159 | { | |
1160 | return (atomic_read(&waiting_for_crash_ipi) > 0); | |
1161 | } | |
1162 | #endif | |
1163 | ||
5c492c3f JM |
1164 | static bool have_cpu_die(void) |
1165 | { | |
1166 | #ifdef CONFIG_HOTPLUG_CPU | |
1167 | int any_cpu = raw_smp_processor_id(); | |
de58ed5e | 1168 | const struct cpu_operations *ops = get_cpu_ops(any_cpu); |
5c492c3f | 1169 | |
de58ed5e | 1170 | if (ops && ops->cpu_die) |
5c492c3f JM |
1171 | return true; |
1172 | #endif | |
1173 | return false; | |
1174 | } | |
1175 | ||
1176 | bool cpus_are_stuck_in_kernel(void) | |
1177 | { | |
1178 | bool smp_spin_tables = (num_possible_cpus() > 1 && !have_cpu_die()); | |
1179 | ||
8f4566f1 WD |
1180 | return !!cpus_stuck_in_kernel || smp_spin_tables || |
1181 | is_protected_kvm_enabled(); | |
5c492c3f | 1182 | } |