Commit | Line | Data |
---|---|---|
08e875c1 CM |
1 | /* |
2 | * SMP initialisation and IPI support | |
3 | * Based on arch/arm/kernel/smp.c | |
4 | * | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
0f078336 | 20 | #include <linux/acpi.h> |
08e875c1 CM |
21 | #include <linux/delay.h> |
22 | #include <linux/init.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/profile.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/err.h> | |
31 | #include <linux/cpu.h> | |
32 | #include <linux/smp.h> | |
33 | #include <linux/seq_file.h> | |
34 | #include <linux/irq.h> | |
35 | #include <linux/percpu.h> | |
36 | #include <linux/clockchips.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/of.h> | |
eb631bb5 | 39 | #include <linux/irq_work.h> |
08e875c1 | 40 | |
e039ee4e | 41 | #include <asm/alternative.h> |
08e875c1 CM |
42 | #include <asm/atomic.h> |
43 | #include <asm/cacheflush.h> | |
df857416 | 44 | #include <asm/cpu.h> |
08e875c1 | 45 | #include <asm/cputype.h> |
cd1aebf5 | 46 | #include <asm/cpu_ops.h> |
08e875c1 CM |
47 | #include <asm/mmu_context.h> |
48 | #include <asm/pgtable.h> | |
49 | #include <asm/pgalloc.h> | |
50 | #include <asm/processor.h> | |
4c7aa002 | 51 | #include <asm/smp_plat.h> |
08e875c1 CM |
52 | #include <asm/sections.h> |
53 | #include <asm/tlbflush.h> | |
54 | #include <asm/ptrace.h> | |
377bcff9 | 55 | #include <asm/virt.h> |
08e875c1 | 56 | |
45ed695a NP |
57 | #define CREATE_TRACE_POINTS |
58 | #include <trace/events/ipi.h> | |
59 | ||
08e875c1 CM |
60 | /* |
61 | * as from 2.5, kernels no longer have an init_tasks structure | |
62 | * so we need some other way of telling a new secondary core | |
63 | * where to place its SVC stack | |
64 | */ | |
65 | struct secondary_data secondary_data; | |
08e875c1 CM |
66 | |
67 | enum ipi_msg_type { | |
68 | IPI_RESCHEDULE, | |
69 | IPI_CALL_FUNC, | |
08e875c1 | 70 | IPI_CPU_STOP, |
1f85008e | 71 | IPI_TIMER, |
eb631bb5 | 72 | IPI_IRQ_WORK, |
5e89c55e | 73 | IPI_WAKEUP |
08e875c1 CM |
74 | }; |
75 | ||
08e875c1 CM |
76 | /* |
77 | * Boot a secondary CPU, and assign it the specified idle task. | |
78 | * This also gives us the initial stack to use for this CPU. | |
79 | */ | |
b8c6453a | 80 | static int boot_secondary(unsigned int cpu, struct task_struct *idle) |
08e875c1 | 81 | { |
652af899 MR |
82 | if (cpu_ops[cpu]->cpu_boot) |
83 | return cpu_ops[cpu]->cpu_boot(cpu); | |
08e875c1 | 84 | |
652af899 | 85 | return -EOPNOTSUPP; |
08e875c1 CM |
86 | } |
87 | ||
88 | static DECLARE_COMPLETION(cpu_running); | |
89 | ||
b8c6453a | 90 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
08e875c1 CM |
91 | { |
92 | int ret; | |
93 | ||
94 | /* | |
95 | * We need to tell the secondary core where to find its stack and the | |
96 | * page tables. | |
97 | */ | |
98 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; | |
99 | __flush_dcache_area(&secondary_data, sizeof(secondary_data)); | |
100 | ||
101 | /* | |
102 | * Now bring the CPU into our world. | |
103 | */ | |
104 | ret = boot_secondary(cpu, idle); | |
105 | if (ret == 0) { | |
106 | /* | |
107 | * CPU was successfully started, wait for it to come online or | |
108 | * time out. | |
109 | */ | |
110 | wait_for_completion_timeout(&cpu_running, | |
111 | msecs_to_jiffies(1000)); | |
112 | ||
113 | if (!cpu_online(cpu)) { | |
114 | pr_crit("CPU%u: failed to come online\n", cpu); | |
115 | ret = -EIO; | |
116 | } | |
117 | } else { | |
118 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
119 | } | |
120 | ||
121 | secondary_data.stack = NULL; | |
122 | ||
123 | return ret; | |
124 | } | |
125 | ||
f6e763b9 MB |
126 | static void smp_store_cpu_info(unsigned int cpuid) |
127 | { | |
128 | store_cpu_topology(cpuid); | |
129 | } | |
130 | ||
08e875c1 CM |
131 | /* |
132 | * This is the secondary CPU boot entry. We're using this CPUs | |
133 | * idle thread stack, but a set of temporary page tables. | |
134 | */ | |
b8c6453a | 135 | asmlinkage void secondary_start_kernel(void) |
08e875c1 CM |
136 | { |
137 | struct mm_struct *mm = &init_mm; | |
138 | unsigned int cpu = smp_processor_id(); | |
139 | ||
08e875c1 CM |
140 | /* |
141 | * All kernel threads share the same mm context; grab a | |
142 | * reference and switch to it. | |
143 | */ | |
144 | atomic_inc(&mm->mm_count); | |
145 | current->active_mm = mm; | |
08e875c1 | 146 | |
71586276 | 147 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
71586276 | 148 | |
08e875c1 CM |
149 | /* |
150 | * TTBR0 is only used for the identity mapping at this stage. Make it | |
151 | * point to zero page to avoid speculatively fetching new entries. | |
152 | */ | |
9e8e865b | 153 | cpu_uninstall_idmap(); |
08e875c1 CM |
154 | |
155 | preempt_disable(); | |
156 | trace_hardirqs_off(); | |
157 | ||
dbb4e152 SP |
158 | /* |
159 | * If the system has established the capabilities, make sure | |
160 | * this CPU ticks all of those. If it doesn't, the CPU will | |
161 | * fail to come online. | |
162 | */ | |
163 | verify_local_cpu_capabilities(); | |
164 | ||
652af899 MR |
165 | if (cpu_ops[cpu]->cpu_postboot) |
166 | cpu_ops[cpu]->cpu_postboot(); | |
08e875c1 | 167 | |
df857416 MR |
168 | /* |
169 | * Log the CPU info before it is marked online and might get read. | |
170 | */ | |
171 | cpuinfo_store_cpu(); | |
172 | ||
7ade67b5 MZ |
173 | /* |
174 | * Enable GIC and timers. | |
175 | */ | |
176 | notify_cpu_starting(cpu); | |
177 | ||
f6e763b9 MB |
178 | smp_store_cpu_info(cpu); |
179 | ||
08e875c1 CM |
180 | /* |
181 | * OK, now it's safe to let the boot CPU continue. Wait for | |
182 | * the CPU migration code to notice that the CPU is online | |
183 | * before we continue. | |
184 | */ | |
64f17818 SP |
185 | pr_info("CPU%u: Booted secondary processor [%08x]\n", |
186 | cpu, read_cpuid_id()); | |
08e875c1 | 187 | set_cpu_online(cpu, true); |
b3770b32 | 188 | complete(&cpu_running); |
08e875c1 | 189 | |
d8ed442a | 190 | local_dbg_enable(); |
53ae3acd | 191 | local_irq_enable(); |
b3bf6aa7 | 192 | local_async_enable(); |
53ae3acd | 193 | |
08e875c1 CM |
194 | /* |
195 | * OK, it's off to the idle thread for us | |
196 | */ | |
0087298f | 197 | cpu_startup_entry(CPUHP_ONLINE); |
08e875c1 CM |
198 | } |
199 | ||
9327e2c6 MR |
200 | #ifdef CONFIG_HOTPLUG_CPU |
201 | static int op_cpu_disable(unsigned int cpu) | |
202 | { | |
203 | /* | |
204 | * If we don't have a cpu_die method, abort before we reach the point | |
205 | * of no return. CPU0 may not have an cpu_ops, so test for it. | |
206 | */ | |
207 | if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die) | |
208 | return -EOPNOTSUPP; | |
209 | ||
210 | /* | |
211 | * We may need to abort a hot unplug for some other mechanism-specific | |
212 | * reason. | |
213 | */ | |
214 | if (cpu_ops[cpu]->cpu_disable) | |
215 | return cpu_ops[cpu]->cpu_disable(cpu); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
220 | /* | |
221 | * __cpu_disable runs on the processor to be shutdown. | |
222 | */ | |
223 | int __cpu_disable(void) | |
224 | { | |
225 | unsigned int cpu = smp_processor_id(); | |
226 | int ret; | |
227 | ||
228 | ret = op_cpu_disable(cpu); | |
229 | if (ret) | |
230 | return ret; | |
231 | ||
232 | /* | |
233 | * Take this CPU offline. Once we clear this, we can't return, | |
234 | * and we must not schedule until we're ready to give up the cpu. | |
235 | */ | |
236 | set_cpu_online(cpu, false); | |
237 | ||
238 | /* | |
239 | * OK - migrate IRQs away from this CPU | |
240 | */ | |
217d453d YY |
241 | irq_migrate_all_off_this_cpu(); |
242 | ||
9327e2c6 MR |
243 | return 0; |
244 | } | |
245 | ||
c814ca02 AC |
246 | static int op_cpu_kill(unsigned int cpu) |
247 | { | |
248 | /* | |
249 | * If we have no means of synchronising with the dying CPU, then assume | |
250 | * that it is really dead. We can only wait for an arbitrary length of | |
251 | * time and hope that it's dead, so let's skip the wait and just hope. | |
252 | */ | |
253 | if (!cpu_ops[cpu]->cpu_kill) | |
6b99c68c | 254 | return 0; |
c814ca02 AC |
255 | |
256 | return cpu_ops[cpu]->cpu_kill(cpu); | |
257 | } | |
258 | ||
9327e2c6 MR |
259 | /* |
260 | * called on the thread which is asking for a CPU to be shutdown - | |
261 | * waits until shutdown has completed, or it is timed out. | |
262 | */ | |
263 | void __cpu_die(unsigned int cpu) | |
264 | { | |
6b99c68c MR |
265 | int err; |
266 | ||
05981277 | 267 | if (!cpu_wait_death(cpu, 5)) { |
9327e2c6 MR |
268 | pr_crit("CPU%u: cpu didn't die\n", cpu); |
269 | return; | |
270 | } | |
271 | pr_notice("CPU%u: shutdown\n", cpu); | |
c814ca02 AC |
272 | |
273 | /* | |
274 | * Now that the dying CPU is beyond the point of no return w.r.t. | |
275 | * in-kernel synchronisation, try to get the firwmare to help us to | |
276 | * verify that it has really left the kernel before we consider | |
277 | * clobbering anything it might still be using. | |
278 | */ | |
6b99c68c MR |
279 | err = op_cpu_kill(cpu); |
280 | if (err) | |
281 | pr_warn("CPU%d may not have shut down cleanly: %d\n", | |
282 | cpu, err); | |
9327e2c6 MR |
283 | } |
284 | ||
285 | /* | |
286 | * Called from the idle thread for the CPU which has been shutdown. | |
287 | * | |
288 | * Note that we disable IRQs here, but do not re-enable them | |
289 | * before returning to the caller. This is also the behaviour | |
290 | * of the other hotplug-cpu capable cores, so presumably coming | |
291 | * out of idle fixes this. | |
292 | */ | |
293 | void cpu_die(void) | |
294 | { | |
295 | unsigned int cpu = smp_processor_id(); | |
296 | ||
297 | idle_task_exit(); | |
298 | ||
299 | local_irq_disable(); | |
300 | ||
301 | /* Tell __cpu_die() that this CPU is now safe to dispose of */ | |
05981277 | 302 | (void)cpu_report_death(); |
9327e2c6 MR |
303 | |
304 | /* | |
305 | * Actually shutdown the CPU. This must never fail. The specific hotplug | |
306 | * mechanism must perform all required cache maintenance to ensure that | |
307 | * no dirty lines are lost in the process of shutting down the CPU. | |
308 | */ | |
309 | cpu_ops[cpu]->cpu_die(cpu); | |
310 | ||
311 | BUG(); | |
312 | } | |
313 | #endif | |
314 | ||
377bcff9 JR |
315 | static void __init hyp_mode_check(void) |
316 | { | |
317 | if (is_hyp_mode_available()) | |
318 | pr_info("CPU: All CPU(s) started at EL2\n"); | |
319 | else if (is_hyp_mode_mismatched()) | |
320 | WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC, | |
321 | "CPU: CPUs started in inconsistent modes"); | |
322 | else | |
323 | pr_info("CPU: All CPU(s) started at EL1\n"); | |
324 | } | |
325 | ||
08e875c1 CM |
326 | void __init smp_cpus_done(unsigned int max_cpus) |
327 | { | |
326b16db | 328 | pr_info("SMP: Total of %d processors activated.\n", num_online_cpus()); |
3a75578e | 329 | setup_cpu_features(); |
377bcff9 JR |
330 | hyp_mode_check(); |
331 | apply_alternatives_all(); | |
08e875c1 CM |
332 | } |
333 | ||
334 | void __init smp_prepare_boot_cpu(void) | |
335 | { | |
4b998ff1 | 336 | cpuinfo_store_boot_cpu(); |
71586276 | 337 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
08e875c1 CM |
338 | } |
339 | ||
0f078336 LP |
340 | static u64 __init of_get_cpu_mpidr(struct device_node *dn) |
341 | { | |
342 | const __be32 *cell; | |
343 | u64 hwid; | |
344 | ||
345 | /* | |
346 | * A cpu node with missing "reg" property is | |
347 | * considered invalid to build a cpu_logical_map | |
348 | * entry. | |
349 | */ | |
350 | cell = of_get_property(dn, "reg", NULL); | |
351 | if (!cell) { | |
352 | pr_err("%s: missing reg property\n", dn->full_name); | |
353 | return INVALID_HWID; | |
354 | } | |
355 | ||
356 | hwid = of_read_number(cell, of_n_addr_cells(dn)); | |
357 | /* | |
358 | * Non affinity bits must be set to 0 in the DT | |
359 | */ | |
360 | if (hwid & ~MPIDR_HWID_BITMASK) { | |
361 | pr_err("%s: invalid reg property\n", dn->full_name); | |
362 | return INVALID_HWID; | |
363 | } | |
364 | return hwid; | |
365 | } | |
366 | ||
367 | /* | |
368 | * Duplicate MPIDRs are a recipe for disaster. Scan all initialized | |
369 | * entries and check for duplicates. If any is found just ignore the | |
370 | * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid | |
371 | * matching valid MPIDR values. | |
372 | */ | |
373 | static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid) | |
374 | { | |
375 | unsigned int i; | |
376 | ||
377 | for (i = 1; (i < cpu) && (i < NR_CPUS); i++) | |
378 | if (cpu_logical_map(i) == hwid) | |
379 | return true; | |
380 | return false; | |
381 | } | |
382 | ||
819a8826 LP |
383 | /* |
384 | * Initialize cpu operations for a logical cpu and | |
385 | * set it in the possible mask on success | |
386 | */ | |
387 | static int __init smp_cpu_setup(int cpu) | |
388 | { | |
389 | if (cpu_read_ops(cpu)) | |
390 | return -ENODEV; | |
391 | ||
392 | if (cpu_ops[cpu]->cpu_init(cpu)) | |
393 | return -ENODEV; | |
394 | ||
395 | set_cpu_possible(cpu, true); | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
0f078336 LP |
400 | static bool bootcpu_valid __initdata; |
401 | static unsigned int cpu_count = 1; | |
402 | ||
403 | #ifdef CONFIG_ACPI | |
404 | /* | |
405 | * acpi_map_gic_cpu_interface - parse processor MADT entry | |
406 | * | |
407 | * Carry out sanity checks on MADT processor entry and initialize | |
408 | * cpu_logical_map on success | |
409 | */ | |
410 | static void __init | |
411 | acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) | |
412 | { | |
413 | u64 hwid = processor->arm_mpidr; | |
414 | ||
f9058929 HG |
415 | if (!(processor->flags & ACPI_MADT_ENABLED)) { |
416 | pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); | |
0f078336 LP |
417 | return; |
418 | } | |
419 | ||
f9058929 HG |
420 | if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { |
421 | pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); | |
0f078336 LP |
422 | return; |
423 | } | |
424 | ||
425 | if (is_mpidr_duplicate(cpu_count, hwid)) { | |
426 | pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid); | |
427 | return; | |
428 | } | |
429 | ||
430 | /* Check if GICC structure of boot CPU is available in the MADT */ | |
431 | if (cpu_logical_map(0) == hwid) { | |
432 | if (bootcpu_valid) { | |
433 | pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n", | |
434 | hwid); | |
435 | return; | |
436 | } | |
437 | bootcpu_valid = true; | |
438 | return; | |
439 | } | |
440 | ||
441 | if (cpu_count >= NR_CPUS) | |
442 | return; | |
443 | ||
444 | /* map the logical cpu id to cpu MPIDR */ | |
445 | cpu_logical_map(cpu_count) = hwid; | |
446 | ||
5e89c55e LP |
447 | /* |
448 | * Set-up the ACPI parking protocol cpu entries | |
449 | * while initializing the cpu_logical_map to | |
450 | * avoid parsing MADT entries multiple times for | |
451 | * nothing (ie a valid cpu_logical_map entry should | |
452 | * contain a valid parking protocol data set to | |
453 | * initialize the cpu if the parking protocol is | |
454 | * the only available enable method). | |
455 | */ | |
456 | acpi_set_mailbox_entry(cpu_count, processor); | |
457 | ||
0f078336 LP |
458 | cpu_count++; |
459 | } | |
460 | ||
461 | static int __init | |
462 | acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header, | |
463 | const unsigned long end) | |
464 | { | |
465 | struct acpi_madt_generic_interrupt *processor; | |
466 | ||
467 | processor = (struct acpi_madt_generic_interrupt *)header; | |
99e3e3ae | 468 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
0f078336 LP |
469 | return -EINVAL; |
470 | ||
471 | acpi_table_print_madt_entry(header); | |
472 | ||
473 | acpi_map_gic_cpu_interface(processor); | |
474 | ||
475 | return 0; | |
476 | } | |
477 | #else | |
478 | #define acpi_table_parse_madt(...) do { } while (0) | |
479 | #endif | |
480 | ||
08e875c1 | 481 | /* |
4c7aa002 JM |
482 | * Enumerate the possible CPU set from the device tree and build the |
483 | * cpu logical map array containing MPIDR values related to logical | |
484 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
08e875c1 | 485 | */ |
29b8302b | 486 | static void __init of_parse_and_init_cpus(void) |
08e875c1 | 487 | { |
08e875c1 | 488 | struct device_node *dn = NULL; |
08e875c1 CM |
489 | |
490 | while ((dn = of_find_node_by_type(dn, "cpu"))) { | |
0f078336 | 491 | u64 hwid = of_get_cpu_mpidr(dn); |
4c7aa002 | 492 | |
0f078336 | 493 | if (hwid == INVALID_HWID) |
4c7aa002 | 494 | goto next; |
4c7aa002 | 495 | |
0f078336 LP |
496 | if (is_mpidr_duplicate(cpu_count, hwid)) { |
497 | pr_err("%s: duplicate cpu reg properties in the DT\n", | |
498 | dn->full_name); | |
4c7aa002 JM |
499 | goto next; |
500 | } | |
501 | ||
4c7aa002 JM |
502 | /* |
503 | * The numbering scheme requires that the boot CPU | |
504 | * must be assigned logical id 0. Record it so that | |
505 | * the logical map built from DT is validated and can | |
506 | * be used. | |
507 | */ | |
508 | if (hwid == cpu_logical_map(0)) { | |
509 | if (bootcpu_valid) { | |
510 | pr_err("%s: duplicate boot cpu reg property in DT\n", | |
511 | dn->full_name); | |
512 | goto next; | |
513 | } | |
514 | ||
515 | bootcpu_valid = true; | |
516 | ||
517 | /* | |
518 | * cpu_logical_map has already been | |
519 | * initialized and the boot cpu doesn't need | |
520 | * the enable-method so continue without | |
521 | * incrementing cpu. | |
522 | */ | |
523 | continue; | |
524 | } | |
525 | ||
0f078336 | 526 | if (cpu_count >= NR_CPUS) |
08e875c1 CM |
527 | goto next; |
528 | ||
4c7aa002 | 529 | pr_debug("cpu logical map 0x%llx\n", hwid); |
0f078336 | 530 | cpu_logical_map(cpu_count) = hwid; |
08e875c1 | 531 | next: |
0f078336 | 532 | cpu_count++; |
08e875c1 | 533 | } |
0f078336 LP |
534 | } |
535 | ||
536 | /* | |
537 | * Enumerate the possible CPU set from the device tree or ACPI and build the | |
538 | * cpu logical map array containing MPIDR values related to logical | |
539 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
540 | */ | |
541 | void __init smp_init_cpus(void) | |
542 | { | |
543 | int i; | |
544 | ||
545 | if (acpi_disabled) | |
546 | of_parse_and_init_cpus(); | |
547 | else | |
548 | /* | |
549 | * do a walk of MADT to determine how many CPUs | |
550 | * we have including disabled CPUs, and get information | |
551 | * we need for SMP init | |
552 | */ | |
553 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
554 | acpi_parse_gic_cpu_interface, 0); | |
08e875c1 | 555 | |
0f078336 LP |
556 | if (cpu_count > NR_CPUS) |
557 | pr_warn("no. of cores (%d) greater than configured maximum of %d - clipping\n", | |
558 | cpu_count, NR_CPUS); | |
4c7aa002 JM |
559 | |
560 | if (!bootcpu_valid) { | |
0f078336 | 561 | pr_err("missing boot CPU MPIDR, not enabling secondaries\n"); |
4c7aa002 JM |
562 | return; |
563 | } | |
564 | ||
565 | /* | |
819a8826 LP |
566 | * We need to set the cpu_logical_map entries before enabling |
567 | * the cpus so that cpu processor description entries (DT cpu nodes | |
568 | * and ACPI MADT entries) can be retrieved by matching the cpu hwid | |
569 | * with entries in cpu_logical_map while initializing the cpus. | |
570 | * If the cpu set-up fails, invalidate the cpu_logical_map entry. | |
4c7aa002 | 571 | */ |
819a8826 LP |
572 | for (i = 1; i < NR_CPUS; i++) { |
573 | if (cpu_logical_map(i) != INVALID_HWID) { | |
574 | if (smp_cpu_setup(i)) | |
575 | cpu_logical_map(i) = INVALID_HWID; | |
576 | } | |
577 | } | |
08e875c1 CM |
578 | } |
579 | ||
580 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
581 | { | |
cd1aebf5 MR |
582 | int err; |
583 | unsigned int cpu, ncores = num_possible_cpus(); | |
08e875c1 | 584 | |
f6e763b9 MB |
585 | init_cpu_topology(); |
586 | ||
587 | smp_store_cpu_info(smp_processor_id()); | |
588 | ||
08e875c1 CM |
589 | /* |
590 | * are we trying to boot more cores than exist? | |
591 | */ | |
592 | if (max_cpus > ncores) | |
593 | max_cpus = ncores; | |
594 | ||
d329de3f MZ |
595 | /* Don't bother if we're effectively UP */ |
596 | if (max_cpus <= 1) | |
597 | return; | |
598 | ||
08e875c1 CM |
599 | /* |
600 | * Initialise the present map (which describes the set of CPUs | |
601 | * actually populated at the present time) and release the | |
602 | * secondaries from the bootloader. | |
d329de3f MZ |
603 | * |
604 | * Make sure we online at most (max_cpus - 1) additional CPUs. | |
08e875c1 | 605 | */ |
d329de3f | 606 | max_cpus--; |
08e875c1 CM |
607 | for_each_possible_cpu(cpu) { |
608 | if (max_cpus == 0) | |
609 | break; | |
610 | ||
d329de3f MZ |
611 | if (cpu == smp_processor_id()) |
612 | continue; | |
613 | ||
cd1aebf5 | 614 | if (!cpu_ops[cpu]) |
08e875c1 CM |
615 | continue; |
616 | ||
cd1aebf5 | 617 | err = cpu_ops[cpu]->cpu_prepare(cpu); |
d329de3f MZ |
618 | if (err) |
619 | continue; | |
08e875c1 CM |
620 | |
621 | set_cpu_present(cpu, true); | |
622 | max_cpus--; | |
623 | } | |
08e875c1 CM |
624 | } |
625 | ||
36310736 | 626 | void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
08e875c1 CM |
627 | |
628 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
629 | { | |
45ed695a | 630 | __smp_cross_call = fn; |
08e875c1 CM |
631 | } |
632 | ||
45ed695a NP |
633 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
634 | #define S(x,s) [x] = s | |
08e875c1 CM |
635 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), |
636 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
08e875c1 | 637 | S(IPI_CPU_STOP, "CPU stop interrupts"), |
1f85008e | 638 | S(IPI_TIMER, "Timer broadcast interrupts"), |
eb631bb5 | 639 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
5e89c55e | 640 | S(IPI_WAKEUP, "CPU wake-up interrupts"), |
08e875c1 CM |
641 | }; |
642 | ||
45ed695a NP |
643 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
644 | { | |
645 | trace_ipi_raise(target, ipi_types[ipinr]); | |
646 | __smp_cross_call(target, ipinr); | |
647 | } | |
648 | ||
08e875c1 CM |
649 | void show_ipi_list(struct seq_file *p, int prec) |
650 | { | |
651 | unsigned int cpu, i; | |
652 | ||
653 | for (i = 0; i < NR_IPI; i++) { | |
45ed695a | 654 | seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, |
08e875c1 | 655 | prec >= 4 ? " " : ""); |
67317c26 | 656 | for_each_online_cpu(cpu) |
08e875c1 CM |
657 | seq_printf(p, "%10u ", |
658 | __get_irq_stat(cpu, ipi_irqs[i])); | |
659 | seq_printf(p, " %s\n", ipi_types[i]); | |
660 | } | |
661 | } | |
662 | ||
663 | u64 smp_irq_stat_cpu(unsigned int cpu) | |
664 | { | |
665 | u64 sum = 0; | |
666 | int i; | |
667 | ||
668 | for (i = 0; i < NR_IPI; i++) | |
669 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
670 | ||
671 | return sum; | |
672 | } | |
673 | ||
45ed695a NP |
674 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
675 | { | |
676 | smp_cross_call(mask, IPI_CALL_FUNC); | |
677 | } | |
678 | ||
679 | void arch_send_call_function_single_ipi(int cpu) | |
680 | { | |
0aaf0dae | 681 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
45ed695a NP |
682 | } |
683 | ||
5e89c55e LP |
684 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
685 | void arch_send_wakeup_ipi_mask(const struct cpumask *mask) | |
686 | { | |
687 | smp_cross_call(mask, IPI_WAKEUP); | |
688 | } | |
689 | #endif | |
690 | ||
45ed695a NP |
691 | #ifdef CONFIG_IRQ_WORK |
692 | void arch_irq_work_raise(void) | |
693 | { | |
694 | if (__smp_cross_call) | |
695 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); | |
696 | } | |
697 | #endif | |
698 | ||
08e875c1 CM |
699 | static DEFINE_RAW_SPINLOCK(stop_lock); |
700 | ||
701 | /* | |
702 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
703 | */ | |
704 | static void ipi_cpu_stop(unsigned int cpu) | |
705 | { | |
706 | if (system_state == SYSTEM_BOOTING || | |
707 | system_state == SYSTEM_RUNNING) { | |
708 | raw_spin_lock(&stop_lock); | |
709 | pr_crit("CPU%u: stopping\n", cpu); | |
710 | dump_stack(); | |
711 | raw_spin_unlock(&stop_lock); | |
712 | } | |
713 | ||
714 | set_cpu_online(cpu, false); | |
715 | ||
08e875c1 CM |
716 | local_irq_disable(); |
717 | ||
718 | while (1) | |
719 | cpu_relax(); | |
720 | } | |
721 | ||
722 | /* | |
723 | * Main handler for inter-processor interrupts | |
724 | */ | |
725 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
726 | { | |
727 | unsigned int cpu = smp_processor_id(); | |
728 | struct pt_regs *old_regs = set_irq_regs(regs); | |
729 | ||
45ed695a | 730 | if ((unsigned)ipinr < NR_IPI) { |
be081d9b | 731 | trace_ipi_entry_rcuidle(ipi_types[ipinr]); |
45ed695a NP |
732 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); |
733 | } | |
08e875c1 CM |
734 | |
735 | switch (ipinr) { | |
736 | case IPI_RESCHEDULE: | |
737 | scheduler_ipi(); | |
738 | break; | |
739 | ||
740 | case IPI_CALL_FUNC: | |
741 | irq_enter(); | |
742 | generic_smp_call_function_interrupt(); | |
743 | irq_exit(); | |
744 | break; | |
745 | ||
08e875c1 CM |
746 | case IPI_CPU_STOP: |
747 | irq_enter(); | |
748 | ipi_cpu_stop(cpu); | |
749 | irq_exit(); | |
750 | break; | |
751 | ||
1f85008e LP |
752 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
753 | case IPI_TIMER: | |
754 | irq_enter(); | |
755 | tick_receive_broadcast(); | |
756 | irq_exit(); | |
757 | break; | |
758 | #endif | |
759 | ||
eb631bb5 LB |
760 | #ifdef CONFIG_IRQ_WORK |
761 | case IPI_IRQ_WORK: | |
762 | irq_enter(); | |
763 | irq_work_run(); | |
764 | irq_exit(); | |
765 | break; | |
766 | #endif | |
767 | ||
5e89c55e LP |
768 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
769 | case IPI_WAKEUP: | |
770 | WARN_ONCE(!acpi_parking_protocol_valid(cpu), | |
771 | "CPU%u: Wake-up IPI outside the ACPI parking protocol\n", | |
772 | cpu); | |
773 | break; | |
774 | #endif | |
775 | ||
08e875c1 CM |
776 | default: |
777 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); | |
778 | break; | |
779 | } | |
45ed695a NP |
780 | |
781 | if ((unsigned)ipinr < NR_IPI) | |
be081d9b | 782 | trace_ipi_exit_rcuidle(ipi_types[ipinr]); |
08e875c1 CM |
783 | set_irq_regs(old_regs); |
784 | } | |
785 | ||
786 | void smp_send_reschedule(int cpu) | |
787 | { | |
788 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); | |
789 | } | |
790 | ||
1f85008e LP |
791 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
792 | void tick_broadcast(const struct cpumask *mask) | |
793 | { | |
794 | smp_cross_call(mask, IPI_TIMER); | |
795 | } | |
796 | #endif | |
797 | ||
08e875c1 CM |
798 | void smp_send_stop(void) |
799 | { | |
800 | unsigned long timeout; | |
801 | ||
802 | if (num_online_cpus() > 1) { | |
803 | cpumask_t mask; | |
804 | ||
805 | cpumask_copy(&mask, cpu_online_mask); | |
434ed7f4 | 806 | cpumask_clear_cpu(smp_processor_id(), &mask); |
08e875c1 CM |
807 | |
808 | smp_cross_call(&mask, IPI_CPU_STOP); | |
809 | } | |
810 | ||
811 | /* Wait up to one second for other CPUs to stop */ | |
812 | timeout = USEC_PER_SEC; | |
813 | while (num_online_cpus() > 1 && timeout--) | |
814 | udelay(1); | |
815 | ||
816 | if (num_online_cpus() > 1) | |
817 | pr_warning("SMP: failed to stop secondary CPUs\n"); | |
818 | } | |
819 | ||
820 | /* | |
821 | * not supported here | |
822 | */ | |
823 | int setup_profiling_timer(unsigned int multiplier) | |
824 | { | |
825 | return -EINVAL; | |
826 | } |