Commit | Line | Data |
---|---|---|
08e875c1 CM |
1 | /* |
2 | * SMP initialisation and IPI support | |
3 | * Based on arch/arm/kernel/smp.c | |
4 | * | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/sched.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/cache.h> | |
26 | #include <linux/profile.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/mm.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/smp.h> | |
32 | #include <linux/seq_file.h> | |
33 | #include <linux/irq.h> | |
34 | #include <linux/percpu.h> | |
35 | #include <linux/clockchips.h> | |
36 | #include <linux/completion.h> | |
37 | #include <linux/of.h> | |
eb631bb5 | 38 | #include <linux/irq_work.h> |
08e875c1 CM |
39 | |
40 | #include <asm/atomic.h> | |
41 | #include <asm/cacheflush.h> | |
42 | #include <asm/cputype.h> | |
cd1aebf5 | 43 | #include <asm/cpu_ops.h> |
08e875c1 CM |
44 | #include <asm/mmu_context.h> |
45 | #include <asm/pgtable.h> | |
46 | #include <asm/pgalloc.h> | |
47 | #include <asm/processor.h> | |
4c7aa002 | 48 | #include <asm/smp_plat.h> |
08e875c1 CM |
49 | #include <asm/sections.h> |
50 | #include <asm/tlbflush.h> | |
51 | #include <asm/ptrace.h> | |
08e875c1 CM |
52 | |
53 | /* | |
54 | * as from 2.5, kernels no longer have an init_tasks structure | |
55 | * so we need some other way of telling a new secondary core | |
56 | * where to place its SVC stack | |
57 | */ | |
58 | struct secondary_data secondary_data; | |
08e875c1 CM |
59 | |
60 | enum ipi_msg_type { | |
61 | IPI_RESCHEDULE, | |
62 | IPI_CALL_FUNC, | |
63 | IPI_CALL_FUNC_SINGLE, | |
64 | IPI_CPU_STOP, | |
1f85008e | 65 | IPI_TIMER, |
eb631bb5 | 66 | IPI_IRQ_WORK, |
08e875c1 CM |
67 | }; |
68 | ||
08e875c1 CM |
69 | /* |
70 | * Boot a secondary CPU, and assign it the specified idle task. | |
71 | * This also gives us the initial stack to use for this CPU. | |
72 | */ | |
b8c6453a | 73 | static int boot_secondary(unsigned int cpu, struct task_struct *idle) |
08e875c1 | 74 | { |
652af899 MR |
75 | if (cpu_ops[cpu]->cpu_boot) |
76 | return cpu_ops[cpu]->cpu_boot(cpu); | |
08e875c1 | 77 | |
652af899 | 78 | return -EOPNOTSUPP; |
08e875c1 CM |
79 | } |
80 | ||
81 | static DECLARE_COMPLETION(cpu_running); | |
82 | ||
b8c6453a | 83 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
08e875c1 CM |
84 | { |
85 | int ret; | |
86 | ||
87 | /* | |
88 | * We need to tell the secondary core where to find its stack and the | |
89 | * page tables. | |
90 | */ | |
91 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; | |
92 | __flush_dcache_area(&secondary_data, sizeof(secondary_data)); | |
93 | ||
94 | /* | |
95 | * Now bring the CPU into our world. | |
96 | */ | |
97 | ret = boot_secondary(cpu, idle); | |
98 | if (ret == 0) { | |
99 | /* | |
100 | * CPU was successfully started, wait for it to come online or | |
101 | * time out. | |
102 | */ | |
103 | wait_for_completion_timeout(&cpu_running, | |
104 | msecs_to_jiffies(1000)); | |
105 | ||
106 | if (!cpu_online(cpu)) { | |
107 | pr_crit("CPU%u: failed to come online\n", cpu); | |
108 | ret = -EIO; | |
109 | } | |
110 | } else { | |
111 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
112 | } | |
113 | ||
114 | secondary_data.stack = NULL; | |
115 | ||
116 | return ret; | |
117 | } | |
118 | ||
f6e763b9 MB |
119 | static void smp_store_cpu_info(unsigned int cpuid) |
120 | { | |
121 | store_cpu_topology(cpuid); | |
122 | } | |
123 | ||
08e875c1 CM |
124 | /* |
125 | * This is the secondary CPU boot entry. We're using this CPUs | |
126 | * idle thread stack, but a set of temporary page tables. | |
127 | */ | |
b8c6453a | 128 | asmlinkage void secondary_start_kernel(void) |
08e875c1 CM |
129 | { |
130 | struct mm_struct *mm = &init_mm; | |
131 | unsigned int cpu = smp_processor_id(); | |
132 | ||
08e875c1 CM |
133 | /* |
134 | * All kernel threads share the same mm context; grab a | |
135 | * reference and switch to it. | |
136 | */ | |
137 | atomic_inc(&mm->mm_count); | |
138 | current->active_mm = mm; | |
139 | cpumask_set_cpu(cpu, mm_cpumask(mm)); | |
140 | ||
71586276 WD |
141 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
142 | printk("CPU%u: Booted secondary processor\n", cpu); | |
143 | ||
08e875c1 CM |
144 | /* |
145 | * TTBR0 is only used for the identity mapping at this stage. Make it | |
146 | * point to zero page to avoid speculatively fetching new entries. | |
147 | */ | |
148 | cpu_set_reserved_ttbr0(); | |
149 | flush_tlb_all(); | |
150 | ||
151 | preempt_disable(); | |
152 | trace_hardirqs_off(); | |
153 | ||
652af899 MR |
154 | if (cpu_ops[cpu]->cpu_postboot) |
155 | cpu_ops[cpu]->cpu_postboot(); | |
08e875c1 | 156 | |
7ade67b5 MZ |
157 | /* |
158 | * Enable GIC and timers. | |
159 | */ | |
160 | notify_cpu_starting(cpu); | |
161 | ||
f6e763b9 MB |
162 | smp_store_cpu_info(cpu); |
163 | ||
08e875c1 CM |
164 | /* |
165 | * OK, now it's safe to let the boot CPU continue. Wait for | |
166 | * the CPU migration code to notice that the CPU is online | |
167 | * before we continue. | |
168 | */ | |
169 | set_cpu_online(cpu, true); | |
b3770b32 | 170 | complete(&cpu_running); |
08e875c1 | 171 | |
d8ed442a | 172 | local_dbg_enable(); |
53ae3acd | 173 | local_irq_enable(); |
b3bf6aa7 | 174 | local_async_enable(); |
53ae3acd | 175 | |
08e875c1 CM |
176 | /* |
177 | * OK, it's off to the idle thread for us | |
178 | */ | |
0087298f | 179 | cpu_startup_entry(CPUHP_ONLINE); |
08e875c1 CM |
180 | } |
181 | ||
9327e2c6 MR |
182 | #ifdef CONFIG_HOTPLUG_CPU |
183 | static int op_cpu_disable(unsigned int cpu) | |
184 | { | |
185 | /* | |
186 | * If we don't have a cpu_die method, abort before we reach the point | |
187 | * of no return. CPU0 may not have an cpu_ops, so test for it. | |
188 | */ | |
189 | if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die) | |
190 | return -EOPNOTSUPP; | |
191 | ||
192 | /* | |
193 | * We may need to abort a hot unplug for some other mechanism-specific | |
194 | * reason. | |
195 | */ | |
196 | if (cpu_ops[cpu]->cpu_disable) | |
197 | return cpu_ops[cpu]->cpu_disable(cpu); | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
202 | /* | |
203 | * __cpu_disable runs on the processor to be shutdown. | |
204 | */ | |
205 | int __cpu_disable(void) | |
206 | { | |
207 | unsigned int cpu = smp_processor_id(); | |
208 | int ret; | |
209 | ||
210 | ret = op_cpu_disable(cpu); | |
211 | if (ret) | |
212 | return ret; | |
213 | ||
214 | /* | |
215 | * Take this CPU offline. Once we clear this, we can't return, | |
216 | * and we must not schedule until we're ready to give up the cpu. | |
217 | */ | |
218 | set_cpu_online(cpu, false); | |
219 | ||
220 | /* | |
221 | * OK - migrate IRQs away from this CPU | |
222 | */ | |
223 | migrate_irqs(); | |
224 | ||
225 | /* | |
226 | * Remove this CPU from the vm mask set of all processes. | |
227 | */ | |
228 | clear_tasks_mm_cpumask(cpu); | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
c814ca02 AC |
233 | static int op_cpu_kill(unsigned int cpu) |
234 | { | |
235 | /* | |
236 | * If we have no means of synchronising with the dying CPU, then assume | |
237 | * that it is really dead. We can only wait for an arbitrary length of | |
238 | * time and hope that it's dead, so let's skip the wait and just hope. | |
239 | */ | |
240 | if (!cpu_ops[cpu]->cpu_kill) | |
241 | return 1; | |
242 | ||
243 | return cpu_ops[cpu]->cpu_kill(cpu); | |
244 | } | |
245 | ||
9327e2c6 MR |
246 | static DECLARE_COMPLETION(cpu_died); |
247 | ||
248 | /* | |
249 | * called on the thread which is asking for a CPU to be shutdown - | |
250 | * waits until shutdown has completed, or it is timed out. | |
251 | */ | |
252 | void __cpu_die(unsigned int cpu) | |
253 | { | |
254 | if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) { | |
255 | pr_crit("CPU%u: cpu didn't die\n", cpu); | |
256 | return; | |
257 | } | |
258 | pr_notice("CPU%u: shutdown\n", cpu); | |
c814ca02 AC |
259 | |
260 | /* | |
261 | * Now that the dying CPU is beyond the point of no return w.r.t. | |
262 | * in-kernel synchronisation, try to get the firwmare to help us to | |
263 | * verify that it has really left the kernel before we consider | |
264 | * clobbering anything it might still be using. | |
265 | */ | |
266 | if (!op_cpu_kill(cpu)) | |
267 | pr_warn("CPU%d may not have shut down cleanly\n", cpu); | |
9327e2c6 MR |
268 | } |
269 | ||
270 | /* | |
271 | * Called from the idle thread for the CPU which has been shutdown. | |
272 | * | |
273 | * Note that we disable IRQs here, but do not re-enable them | |
274 | * before returning to the caller. This is also the behaviour | |
275 | * of the other hotplug-cpu capable cores, so presumably coming | |
276 | * out of idle fixes this. | |
277 | */ | |
278 | void cpu_die(void) | |
279 | { | |
280 | unsigned int cpu = smp_processor_id(); | |
281 | ||
282 | idle_task_exit(); | |
283 | ||
284 | local_irq_disable(); | |
285 | ||
286 | /* Tell __cpu_die() that this CPU is now safe to dispose of */ | |
287 | complete(&cpu_died); | |
288 | ||
289 | /* | |
290 | * Actually shutdown the CPU. This must never fail. The specific hotplug | |
291 | * mechanism must perform all required cache maintenance to ensure that | |
292 | * no dirty lines are lost in the process of shutting down the CPU. | |
293 | */ | |
294 | cpu_ops[cpu]->cpu_die(cpu); | |
295 | ||
296 | BUG(); | |
297 | } | |
298 | #endif | |
299 | ||
08e875c1 CM |
300 | void __init smp_cpus_done(unsigned int max_cpus) |
301 | { | |
326b16db | 302 | pr_info("SMP: Total of %d processors activated.\n", num_online_cpus()); |
08e875c1 CM |
303 | } |
304 | ||
305 | void __init smp_prepare_boot_cpu(void) | |
306 | { | |
71586276 | 307 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
08e875c1 CM |
308 | } |
309 | ||
310 | static void (*smp_cross_call)(const struct cpumask *, unsigned int); | |
d329de3f | 311 | |
08e875c1 | 312 | /* |
4c7aa002 JM |
313 | * Enumerate the possible CPU set from the device tree and build the |
314 | * cpu logical map array containing MPIDR values related to logical | |
315 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
08e875c1 CM |
316 | */ |
317 | void __init smp_init_cpus(void) | |
318 | { | |
08e875c1 | 319 | struct device_node *dn = NULL; |
cd1aebf5 | 320 | unsigned int i, cpu = 1; |
4c7aa002 | 321 | bool bootcpu_valid = false; |
08e875c1 CM |
322 | |
323 | while ((dn = of_find_node_by_type(dn, "cpu"))) { | |
72aea393 | 324 | const u32 *cell; |
4c7aa002 JM |
325 | u64 hwid; |
326 | ||
327 | /* | |
328 | * A cpu node with missing "reg" property is | |
329 | * considered invalid to build a cpu_logical_map | |
330 | * entry. | |
331 | */ | |
72aea393 WD |
332 | cell = of_get_property(dn, "reg", NULL); |
333 | if (!cell) { | |
4c7aa002 JM |
334 | pr_err("%s: missing reg property\n", dn->full_name); |
335 | goto next; | |
336 | } | |
72aea393 | 337 | hwid = of_read_number(cell, of_n_addr_cells(dn)); |
4c7aa002 JM |
338 | |
339 | /* | |
340 | * Non affinity bits must be set to 0 in the DT | |
341 | */ | |
342 | if (hwid & ~MPIDR_HWID_BITMASK) { | |
343 | pr_err("%s: invalid reg property\n", dn->full_name); | |
344 | goto next; | |
345 | } | |
346 | ||
347 | /* | |
348 | * Duplicate MPIDRs are a recipe for disaster. Scan | |
349 | * all initialized entries and check for | |
350 | * duplicates. If any is found just ignore the cpu. | |
351 | * cpu_logical_map was initialized to INVALID_HWID to | |
352 | * avoid matching valid MPIDR values. | |
353 | */ | |
354 | for (i = 1; (i < cpu) && (i < NR_CPUS); i++) { | |
355 | if (cpu_logical_map(i) == hwid) { | |
356 | pr_err("%s: duplicate cpu reg properties in the DT\n", | |
357 | dn->full_name); | |
358 | goto next; | |
359 | } | |
360 | } | |
361 | ||
362 | /* | |
363 | * The numbering scheme requires that the boot CPU | |
364 | * must be assigned logical id 0. Record it so that | |
365 | * the logical map built from DT is validated and can | |
366 | * be used. | |
367 | */ | |
368 | if (hwid == cpu_logical_map(0)) { | |
369 | if (bootcpu_valid) { | |
370 | pr_err("%s: duplicate boot cpu reg property in DT\n", | |
371 | dn->full_name); | |
372 | goto next; | |
373 | } | |
374 | ||
375 | bootcpu_valid = true; | |
376 | ||
377 | /* | |
378 | * cpu_logical_map has already been | |
379 | * initialized and the boot cpu doesn't need | |
380 | * the enable-method so continue without | |
381 | * incrementing cpu. | |
382 | */ | |
383 | continue; | |
384 | } | |
385 | ||
08e875c1 CM |
386 | if (cpu >= NR_CPUS) |
387 | goto next; | |
388 | ||
e8765b26 | 389 | if (cpu_read_ops(dn, cpu) != 0) |
08e875c1 | 390 | goto next; |
08e875c1 | 391 | |
cd1aebf5 | 392 | if (cpu_ops[cpu]->cpu_init(dn, cpu)) |
d329de3f MZ |
393 | goto next; |
394 | ||
4c7aa002 JM |
395 | pr_debug("cpu logical map 0x%llx\n", hwid); |
396 | cpu_logical_map(cpu) = hwid; | |
08e875c1 CM |
397 | next: |
398 | cpu++; | |
399 | } | |
400 | ||
401 | /* sanity check */ | |
402 | if (cpu > NR_CPUS) | |
403 | pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n", | |
404 | cpu, NR_CPUS); | |
4c7aa002 JM |
405 | |
406 | if (!bootcpu_valid) { | |
407 | pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n"); | |
408 | return; | |
409 | } | |
410 | ||
411 | /* | |
412 | * All the cpus that made it to the cpu_logical_map have been | |
413 | * validated so set them as possible cpus. | |
414 | */ | |
415 | for (i = 0; i < NR_CPUS; i++) | |
416 | if (cpu_logical_map(i) != INVALID_HWID) | |
417 | set_cpu_possible(i, true); | |
08e875c1 CM |
418 | } |
419 | ||
420 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
421 | { | |
cd1aebf5 MR |
422 | int err; |
423 | unsigned int cpu, ncores = num_possible_cpus(); | |
08e875c1 | 424 | |
f6e763b9 MB |
425 | init_cpu_topology(); |
426 | ||
427 | smp_store_cpu_info(smp_processor_id()); | |
428 | ||
08e875c1 CM |
429 | /* |
430 | * are we trying to boot more cores than exist? | |
431 | */ | |
432 | if (max_cpus > ncores) | |
433 | max_cpus = ncores; | |
434 | ||
d329de3f MZ |
435 | /* Don't bother if we're effectively UP */ |
436 | if (max_cpus <= 1) | |
437 | return; | |
438 | ||
08e875c1 CM |
439 | /* |
440 | * Initialise the present map (which describes the set of CPUs | |
441 | * actually populated at the present time) and release the | |
442 | * secondaries from the bootloader. | |
d329de3f MZ |
443 | * |
444 | * Make sure we online at most (max_cpus - 1) additional CPUs. | |
08e875c1 | 445 | */ |
d329de3f | 446 | max_cpus--; |
08e875c1 CM |
447 | for_each_possible_cpu(cpu) { |
448 | if (max_cpus == 0) | |
449 | break; | |
450 | ||
d329de3f MZ |
451 | if (cpu == smp_processor_id()) |
452 | continue; | |
453 | ||
cd1aebf5 | 454 | if (!cpu_ops[cpu]) |
08e875c1 CM |
455 | continue; |
456 | ||
cd1aebf5 | 457 | err = cpu_ops[cpu]->cpu_prepare(cpu); |
d329de3f MZ |
458 | if (err) |
459 | continue; | |
08e875c1 CM |
460 | |
461 | set_cpu_present(cpu, true); | |
462 | max_cpus--; | |
463 | } | |
08e875c1 CM |
464 | } |
465 | ||
466 | ||
467 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
468 | { | |
469 | smp_cross_call = fn; | |
470 | } | |
471 | ||
472 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) | |
473 | { | |
474 | smp_cross_call(mask, IPI_CALL_FUNC); | |
475 | } | |
476 | ||
477 | void arch_send_call_function_single_ipi(int cpu) | |
478 | { | |
479 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); | |
480 | } | |
481 | ||
eb631bb5 LB |
482 | #ifdef CONFIG_IRQ_WORK |
483 | void arch_irq_work_raise(void) | |
484 | { | |
485 | if (smp_cross_call) | |
486 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); | |
487 | } | |
488 | #endif | |
489 | ||
08e875c1 CM |
490 | static const char *ipi_types[NR_IPI] = { |
491 | #define S(x,s) [x - IPI_RESCHEDULE] = s | |
492 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), | |
493 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
494 | S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"), | |
495 | S(IPI_CPU_STOP, "CPU stop interrupts"), | |
1f85008e | 496 | S(IPI_TIMER, "Timer broadcast interrupts"), |
eb631bb5 | 497 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
08e875c1 CM |
498 | }; |
499 | ||
500 | void show_ipi_list(struct seq_file *p, int prec) | |
501 | { | |
502 | unsigned int cpu, i; | |
503 | ||
504 | for (i = 0; i < NR_IPI; i++) { | |
505 | seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i + IPI_RESCHEDULE, | |
506 | prec >= 4 ? " " : ""); | |
67317c26 | 507 | for_each_online_cpu(cpu) |
08e875c1 CM |
508 | seq_printf(p, "%10u ", |
509 | __get_irq_stat(cpu, ipi_irqs[i])); | |
510 | seq_printf(p, " %s\n", ipi_types[i]); | |
511 | } | |
512 | } | |
513 | ||
514 | u64 smp_irq_stat_cpu(unsigned int cpu) | |
515 | { | |
516 | u64 sum = 0; | |
517 | int i; | |
518 | ||
519 | for (i = 0; i < NR_IPI; i++) | |
520 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
521 | ||
522 | return sum; | |
523 | } | |
524 | ||
525 | static DEFINE_RAW_SPINLOCK(stop_lock); | |
526 | ||
527 | /* | |
528 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
529 | */ | |
530 | static void ipi_cpu_stop(unsigned int cpu) | |
531 | { | |
532 | if (system_state == SYSTEM_BOOTING || | |
533 | system_state == SYSTEM_RUNNING) { | |
534 | raw_spin_lock(&stop_lock); | |
535 | pr_crit("CPU%u: stopping\n", cpu); | |
536 | dump_stack(); | |
537 | raw_spin_unlock(&stop_lock); | |
538 | } | |
539 | ||
540 | set_cpu_online(cpu, false); | |
541 | ||
08e875c1 CM |
542 | local_irq_disable(); |
543 | ||
544 | while (1) | |
545 | cpu_relax(); | |
546 | } | |
547 | ||
548 | /* | |
549 | * Main handler for inter-processor interrupts | |
550 | */ | |
551 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
552 | { | |
553 | unsigned int cpu = smp_processor_id(); | |
554 | struct pt_regs *old_regs = set_irq_regs(regs); | |
555 | ||
556 | if (ipinr >= IPI_RESCHEDULE && ipinr < IPI_RESCHEDULE + NR_IPI) | |
557 | __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_RESCHEDULE]); | |
558 | ||
559 | switch (ipinr) { | |
560 | case IPI_RESCHEDULE: | |
561 | scheduler_ipi(); | |
562 | break; | |
563 | ||
564 | case IPI_CALL_FUNC: | |
565 | irq_enter(); | |
566 | generic_smp_call_function_interrupt(); | |
567 | irq_exit(); | |
568 | break; | |
569 | ||
570 | case IPI_CALL_FUNC_SINGLE: | |
571 | irq_enter(); | |
572 | generic_smp_call_function_single_interrupt(); | |
573 | irq_exit(); | |
574 | break; | |
575 | ||
576 | case IPI_CPU_STOP: | |
577 | irq_enter(); | |
578 | ipi_cpu_stop(cpu); | |
579 | irq_exit(); | |
580 | break; | |
581 | ||
1f85008e LP |
582 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
583 | case IPI_TIMER: | |
584 | irq_enter(); | |
585 | tick_receive_broadcast(); | |
586 | irq_exit(); | |
587 | break; | |
588 | #endif | |
589 | ||
eb631bb5 LB |
590 | #ifdef CONFIG_IRQ_WORK |
591 | case IPI_IRQ_WORK: | |
592 | irq_enter(); | |
593 | irq_work_run(); | |
594 | irq_exit(); | |
595 | break; | |
596 | #endif | |
597 | ||
08e875c1 CM |
598 | default: |
599 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); | |
600 | break; | |
601 | } | |
602 | set_irq_regs(old_regs); | |
603 | } | |
604 | ||
605 | void smp_send_reschedule(int cpu) | |
606 | { | |
607 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); | |
608 | } | |
609 | ||
1f85008e LP |
610 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
611 | void tick_broadcast(const struct cpumask *mask) | |
612 | { | |
613 | smp_cross_call(mask, IPI_TIMER); | |
614 | } | |
615 | #endif | |
616 | ||
08e875c1 CM |
617 | void smp_send_stop(void) |
618 | { | |
619 | unsigned long timeout; | |
620 | ||
621 | if (num_online_cpus() > 1) { | |
622 | cpumask_t mask; | |
623 | ||
624 | cpumask_copy(&mask, cpu_online_mask); | |
625 | cpu_clear(smp_processor_id(), mask); | |
626 | ||
627 | smp_cross_call(&mask, IPI_CPU_STOP); | |
628 | } | |
629 | ||
630 | /* Wait up to one second for other CPUs to stop */ | |
631 | timeout = USEC_PER_SEC; | |
632 | while (num_online_cpus() > 1 && timeout--) | |
633 | udelay(1); | |
634 | ||
635 | if (num_online_cpus() > 1) | |
636 | pr_warning("SMP: failed to stop secondary CPUs\n"); | |
637 | } | |
638 | ||
639 | /* | |
640 | * not supported here | |
641 | */ | |
642 | int setup_profiling_timer(unsigned int multiplier) | |
643 | { | |
644 | return -EINVAL; | |
645 | } |