Commit | Line | Data |
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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
e790f1de | 2 | /* |
e790f1de WD |
3 | * |
4 | * Copyright (C) 2013 ARM Limited | |
5 | * | |
6 | * Author: Will Deacon <will.deacon@arm.com> | |
7 | */ | |
8 | ||
9 | #define pr_fmt(fmt) "psci: " fmt | |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/of.h> | |
00ef54bb | 13 | #include <linux/smp.h> |
c814ca02 | 14 | #include <linux/delay.h> |
bff60792 | 15 | #include <linux/psci.h> |
2077be67 | 16 | #include <linux/mm.h> |
bff60792 | 17 | |
e71246a2 | 18 | #include <uapi/linux/psci.h> |
e790f1de | 19 | |
cd1aebf5 | 20 | #include <asm/cpu_ops.h> |
e790f1de | 21 | #include <asm/errno.h> |
00ef54bb | 22 | #include <asm/smp_plat.h> |
18910ab0 | 23 | |
819a8826 | 24 | static int __init cpu_psci_cpu_init(unsigned int cpu) |
00ef54bb MR |
25 | { |
26 | return 0; | |
27 | } | |
28 | ||
cd1aebf5 | 29 | static int __init cpu_psci_cpu_prepare(unsigned int cpu) |
00ef54bb | 30 | { |
00ef54bb MR |
31 | if (!psci_ops.cpu_on) { |
32 | pr_err("no cpu_on method, not booting CPU%d\n", cpu); | |
33 | return -ENODEV; | |
34 | } | |
35 | ||
00ef54bb MR |
36 | return 0; |
37 | } | |
38 | ||
652af899 MR |
39 | static int cpu_psci_cpu_boot(unsigned int cpu) |
40 | { | |
2077be67 | 41 | int err = psci_ops.cpu_on(cpu_logical_map(cpu), __pa_symbol(secondary_entry)); |
652af899 | 42 | if (err) |
288ac26c | 43 | pr_err("failed to boot CPU%d (%d)\n", cpu, err); |
652af899 MR |
44 | |
45 | return err; | |
46 | } | |
47 | ||
831ccf79 | 48 | #ifdef CONFIG_HOTPLUG_CPU |
d55c5f28 SH |
49 | static bool cpu_psci_cpu_can_disable(unsigned int cpu) |
50 | { | |
51 | return !psci_tos_resident_on(cpu); | |
52 | } | |
53 | ||
831ccf79 MR |
54 | static int cpu_psci_cpu_disable(unsigned int cpu) |
55 | { | |
56 | /* Fail early if we don't have CPU_OFF support */ | |
57 | if (!psci_ops.cpu_off) | |
58 | return -EOPNOTSUPP; | |
ff3010e6 MR |
59 | |
60 | /* Trusted OS will deny CPU_OFF */ | |
61 | if (psci_tos_resident_on(cpu)) | |
62 | return -EPERM; | |
63 | ||
831ccf79 MR |
64 | return 0; |
65 | } | |
66 | ||
67 | static void cpu_psci_cpu_die(unsigned int cpu) | |
68 | { | |
69 | int ret; | |
70 | /* | |
71 | * There are no known implementations of PSCI actually using the | |
72 | * power state field, pass a sensible default for now. | |
73 | */ | |
c8cc4273 MR |
74 | u32 state = PSCI_POWER_STATE_TYPE_POWER_DOWN << |
75 | PSCI_0_2_POWER_STATE_TYPE_SHIFT; | |
831ccf79 MR |
76 | |
77 | ret = psci_ops.cpu_off(state); | |
78 | ||
288ac26c | 79 | pr_crit("unable to power off CPU%u (%d)\n", cpu, ret); |
831ccf79 | 80 | } |
c814ca02 AC |
81 | |
82 | static int cpu_psci_cpu_kill(unsigned int cpu) | |
83 | { | |
84 | int err, i; | |
85 | ||
86 | if (!psci_ops.affinity_info) | |
6b99c68c | 87 | return 0; |
c814ca02 AC |
88 | /* |
89 | * cpu_kill could race with cpu_die and we can | |
90 | * potentially end up declaring this cpu undead | |
91 | * while it is dying. So, try again a few times. | |
92 | */ | |
93 | ||
94 | for (i = 0; i < 10; i++) { | |
95 | err = psci_ops.affinity_info(cpu_logical_map(cpu), 0); | |
96 | if (err == PSCI_0_2_AFFINITY_LEVEL_OFF) { | |
97 | pr_info("CPU%d killed.\n", cpu); | |
6b99c68c | 98 | return 0; |
c814ca02 AC |
99 | } |
100 | ||
101 | msleep(10); | |
102 | pr_info("Retrying again to check for CPU kill\n"); | |
103 | } | |
104 | ||
105 | pr_warn("CPU%d may not have shut down cleanly (AFFINITY_INFO reports %d)\n", | |
106 | cpu, err); | |
6b99c68c | 107 | return -ETIMEDOUT; |
c814ca02 | 108 | } |
831ccf79 MR |
109 | #endif |
110 | ||
cd1aebf5 | 111 | const struct cpu_operations cpu_psci_ops = { |
00ef54bb | 112 | .name = "psci", |
cd1aebf5 MR |
113 | .cpu_init = cpu_psci_cpu_init, |
114 | .cpu_prepare = cpu_psci_cpu_prepare, | |
652af899 | 115 | .cpu_boot = cpu_psci_cpu_boot, |
831ccf79 | 116 | #ifdef CONFIG_HOTPLUG_CPU |
d55c5f28 | 117 | .cpu_can_disable = cpu_psci_cpu_can_disable, |
831ccf79 MR |
118 | .cpu_disable = cpu_psci_cpu_disable, |
119 | .cpu_die = cpu_psci_cpu_die, | |
c814ca02 | 120 | .cpu_kill = cpu_psci_cpu_kill, |
831ccf79 | 121 | #endif |
00ef54bb MR |
122 | }; |
123 |