[linux-2.6-block.git] / arch / arm64 / kernel / process.c

/*
 * Based on arch/arm/kernel/process.c
 *
 * Original Copyright (C) 1995  Linus Torvalds
 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <stdarg.h>

#include <linux/compat.h>
#include <linux/efi.h>
#include <linux/export.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/user.h>
#include <linux/delay.h>
#include <linux/reboot.h>
#include <linux/interrupt.h>
#include <linux/kallsyms.h>
#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/elfcore.h>
#include <linux/pm.h>
#include <linux/tick.h>
#include <linux/utsname.h>
#include <linux/uaccess.h>
#include <linux/random.h>
#include <linux/hw_breakpoint.h>
#include <linux/personality.h>
#include <linux/notifier.h>
#include <trace/events/power.h>

#include <asm/alternative.h>
#include <asm/compat.h>
#include <asm/cacheflush.h>
#include <asm/exec.h>
#include <asm/fpsimd.h>
#include <asm/mmu_context.h>
#include <asm/processor.h>
#include <asm/stacktrace.h>

#ifdef CONFIG_CC_STACKPROTECTOR
#include <linux/stackprotector.h>
unsigned long __stack_chk_guard __read_mostly;
EXPORT_SYMBOL(__stack_chk_guard);
#endif

/*
 * Function pointers to optional machine specific functions
 */
void (*pm_power_off)(void);
EXPORT_SYMBOL_GPL(pm_power_off);

void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);

/*
 * This is our default idle handler.
 */
void arch_cpu_idle(void)
{
	/*
	 * This should do all the clock switching and wait for interrupt
	 * tricks
	 */
	trace_cpu_idle_rcuidle(1, smp_processor_id());
	cpu_do_idle();
	local_irq_enable();
	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
}

#ifdef CONFIG_HOTPLUG_CPU
void arch_cpu_idle_dead(void)
{
       cpu_die();
}
#endif

/*
 * Called by kexec, immediately prior to machine_kexec().
 *
 * This must completely disable all secondary CPUs; simply causing those CPUs
 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
 * kexec'd kernel to use any and all RAM as it sees fit, without having to
 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
 * functionality embodied in disable_nonboot_cpus() to achieve this.
 */
void machine_shutdown(void)
{
	disable_nonboot_cpus();
}

/*
 * Halting simply requires that the secondary CPUs stop performing any
 * activity (executing tasks, handling interrupts). smp_send_stop()
 * achieves this.
 */
void machine_halt(void)
{
	local_irq_disable();
	smp_send_stop();
	while (1);
}

/*
 * Power-off simply requires that the secondary CPUs stop performing any
 * activity (executing tasks, handling interrupts). smp_send_stop()
 * achieves this. When the system power is turned off, it will take all CPUs
 * with it.
 */
void machine_power_off(void)
{
	local_irq_disable();
	smp_send_stop();
	if (pm_power_off)
		pm_power_off();
}

/*
 * Restart requires that the secondary CPUs stop performing any activity
 * while the primary CPU resets the system. Systems with multiple CPUs must
 * provide a HW restart implementation, to ensure that all CPUs reset at once.
 * This is required so that any code running after reset on the primary CPU
 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
 * executing pre-reset code, and using RAM that the primary CPU's code wishes
 * to use. Implementing such co-ordination would be essentially impossible.
 */
void machine_restart(char *cmd)
{
	/* Disable interrupts first */
	local_irq_disable();
	smp_send_stop();

	/*
	 * UpdateCapsule() depends on the system being reset via
	 * ResetSystem().
	 */
	if (efi_enabled(EFI_RUNTIME_SERVICES))
		efi_reboot(reboot_mode, NULL);

	/* Now call the architecture specific reboot code. */
	if (arm_pm_restart)
		arm_pm_restart(reboot_mode, cmd);
	else
		do_kernel_restart(cmd);

	/*
	 * Whoops - the architecture was unable to reboot.
	 */
	printk("Reboot failed -- System halted\n");
	while (1);
}

void __show_regs(struct pt_regs *regs)
{
	int i, top_reg;
	u64 lr, sp;

	if (compat_user_mode(regs)) {
		lr = regs->compat_lr;
		sp = regs->compat_sp;
		top_reg = 12;
	} else {
		lr = regs->regs[30];
		sp = regs->sp;
		top_reg = 29;
	}

	show_regs_print_info(KERN_DEFAULT);
	print_symbol("PC is at %s\n", instruction_pointer(regs));
	print_symbol("LR is at %s\n", lr);
	printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
	       regs->pc, lr, regs->pstate);
	printk("sp : %016llx\n", sp);

	i = top_reg;

	while (i >= 0) {
		printk("x%-2d: %016llx ", i, regs->regs[i]);
		i--;

		if (i % 2 == 0) {
			pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
			i--;
		}

		pr_cont("\n");
	}
	printk("\n");
}

void show_regs(struct pt_regs * regs)
{
	printk("\n");
	__show_regs(regs);
}

static void tls_thread_flush(void)
{
	write_sysreg(0, tpidr_el0);

	if (is_compat_task()) {
		current->thread.tp_value = 0;

		/*
		 * We need to ensure ordering between the shadow state and the
		 * hardware state, so that we don't corrupt the hardware state
		 * with a stale shadow state during context switch.
		 */
		barrier();
		write_sysreg(0, tpidrro_el0);
	}
}

void flush_thread(void)
{
	fpsimd_flush_thread();
	tls_thread_flush();
	flush_ptrace_hw_breakpoint(current);
}

void release_thread(struct task_struct *dead_task)
{
}

int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
{
	if (current->mm)
		fpsimd_preserve_current_state();
	*dst = *src;
	return 0;
}

asmlinkage void ret_from_fork(void) asm("ret_from_fork");

int copy_thread(unsigned long clone_flags, unsigned long stack_start,
		unsigned long stk_sz, struct task_struct *p)
{
	struct pt_regs *childregs = task_pt_regs(p);

	memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));

	if (likely(!(p->flags & PF_KTHREAD))) {
		*childregs = *current_pt_regs();
		childregs->regs[0] = 0;

		/*
		 * Read the current TLS pointer from tpidr_el0 as it may be
		 * out-of-sync with the saved value.
		 */
		*task_user_tls(p) = read_sysreg(tpidr_el0);

		if (stack_start) {
			if (is_compat_thread(task_thread_info(p)))
				childregs->compat_sp = stack_start;
			else
				childregs->sp = stack_start;
		}

		/*
		 * If a TLS pointer was passed to clone (4th argument), use it
		 * for the new thread.
		 */
		if (clone_flags & CLONE_SETTLS)
			p->thread.tp_value = childregs->regs[3];
	} else {
		memset(childregs, 0, sizeof(struct pt_regs));
		childregs->pstate = PSR_MODE_EL1h;
		if (IS_ENABLED(CONFIG_ARM64_UAO) &&
		    cpus_have_cap(ARM64_HAS_UAO))
			childregs->pstate |= PSR_UAO_BIT;
		p->thread.cpu_context.x19 = stack_start;
		p->thread.cpu_context.x20 = stk_sz;
	}
	p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
	p->thread.cpu_context.sp = (unsigned long)childregs;

	ptrace_hw_copy_thread(p);

	return 0;
}

static void tls_thread_switch(struct task_struct *next)
{
	unsigned long tpidr, tpidrro;

	tpidr = read_sysreg(tpidr_el0);
	*task_user_tls(current) = tpidr;

	tpidr = *task_user_tls(next);
	tpidrro = is_compat_thread(task_thread_info(next)) ?
		  next->thread.tp_value : 0;

	write_sysreg(tpidr, tpidr_el0);
	write_sysreg(tpidrro, tpidrro_el0);
}

/* Restore the UAO state depending on next's addr_limit */
void uao_thread_switch(struct task_struct *next)
{
	if (IS_ENABLED(CONFIG_ARM64_UAO)) {
		if (task_thread_info(next)->addr_limit == KERNEL_DS)
			asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
		else
			asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
	}
}

/*
 * Thread switching.
 */
struct task_struct *__switch_to(struct task_struct *prev,
				struct task_struct *next)
{
	struct task_struct *last;

	fpsimd_thread_switch(next);
	tls_thread_switch(next);
	hw_breakpoint_thread_switch(next);
	contextidr_thread_switch(next);
	uao_thread_switch(next);

	/*
	 * Complete any pending TLB or cache maintenance on this CPU in case
	 * the thread migrates to a different CPU.
	 */
	dsb(ish);

	/* the actual thread switch */
	last = cpu_switch_to(prev, next);

	return last;
}

unsigned long get_wchan(struct task_struct *p)
{
	struct stackframe frame;
	unsigned long stack_page, ret = 0;
	int count = 0;
	if (!p || p == current || p->state == TASK_RUNNING)
		return 0;

	stack_page = (unsigned long)try_get_task_stack(p);
	if (!stack_page)
		return 0;

	frame.fp = thread_saved_fp(p);
	frame.sp = thread_saved_sp(p);
	frame.pc = thread_saved_pc(p);
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
	frame.graph = p->curr_ret_stack;
#endif
	do {
		if (frame.sp < stack_page ||
		    frame.sp >= stack_page + THREAD_SIZE ||
		    unwind_frame(p, &frame))
			goto out;
		if (!in_sched_functions(frame.pc)) {
			ret = frame.pc;
			goto out;
		}
	} while (count ++ < 16);

out:
	put_task_stack(p);
	return ret;
}

unsigned long arch_align_stack(unsigned long sp)
{
	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
		sp -= get_random_int() & ~PAGE_MASK;
	return sp & ~0xf;
}

unsigned long arch_randomize_brk(struct mm_struct *mm)
{
	if (is_compat_task())
		return randomize_page(mm->brk, 0x02000000);
	else
		return randomize_page(mm->brk, 0x40000000);
}
Commit	Line	Data
b3901d54 CM	1	/*
	2	* Based on arch/arm/kernel/process.c
	3	*
	4	* Original Copyright (C) 1995 Linus Torvalds
	5	* Copyright (C) 1996-2000 Russell King - Converted to ARM.
	6	* Copyright (C) 2012 ARM Ltd.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <stdarg.h>
	22
fd92d4a5	23	#include <linux/compat.h>
60c0d45a	24	#include <linux/efi.h>
b3901d54 CM	25	#include <linux/export.h>
	26	#include <linux/sched.h>
	27	#include <linux/kernel.h>
	28	#include <linux/mm.h>
	29	#include <linux/stddef.h>
	30	#include <linux/unistd.h>
	31	#include <linux/user.h>
	32	#include <linux/delay.h>
	33	#include <linux/reboot.h>
	34	#include <linux/interrupt.h>
	35	#include <linux/kallsyms.h>
	36	#include <linux/init.h>
	37	#include <linux/cpu.h>
	38	#include <linux/elfcore.h>
	39	#include <linux/pm.h>
	40	#include <linux/tick.h>
	41	#include <linux/utsname.h>
	42	#include <linux/uaccess.h>
	43	#include <linux/random.h>
	44	#include <linux/hw_breakpoint.h>
	45	#include <linux/personality.h>
	46	#include <linux/notifier.h>
096b3224	47	#include <trace/events/power.h>
b3901d54	48
57f4959b	49	#include <asm/alternative.h>
b3901d54 CM	50	#include <asm/compat.h>
b3901d54 CM	51	#include <asm/cacheflush.h>
d0854412	52	#include <asm/exec.h>
ec45d1cf WD	53	#include <asm/fpsimd.h>
ec45d1cf WD	54	#include <asm/mmu_context.h>
b3901d54 CM	55	#include <asm/processor.h>
b3901d54 CM	56	#include <asm/stacktrace.h>
b3901d54	57
c0c264ae LA	58	#ifdef CONFIG_CC_STACKPROTECTOR
	59	#include <linux/stackprotector.h>
	60	unsigned long __stack_chk_guard __read_mostly;
	61	EXPORT_SYMBOL(__stack_chk_guard);
	62	#endif
	63
b3901d54 CM	64	/*
	65	* Function pointers to optional machine specific functions
	66	*/
	67	void (*pm_power_off)(void);
	68	EXPORT_SYMBOL_GPL(pm_power_off);
	69
b0946fc8	70	void (arm_pm_restart)(enum reboot_mode reboot_mode, const char cmd);
b3901d54	71
b3901d54 CM	72	/*
	73	* This is our default idle handler.
	74	*/
0087298f	75	void arch_cpu_idle(void)
b3901d54 CM	76	{
	77	/*
	78	* This should do all the clock switching and wait for interrupt
	79	* tricks
	80	*/
096b3224	81	trace_cpu_idle_rcuidle(1, smp_processor_id());
6990566b NP	82	cpu_do_idle();
6990566b NP	83	local_irq_enable();
096b3224	84	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
b3901d54 CM	85	}
b3901d54 CM	86
9327e2c6 MR	87	#ifdef CONFIG_HOTPLUG_CPU
	88	void arch_cpu_idle_dead(void)
	89	{
	90	cpu_die();
	91	}
	92	#endif
	93
90f51a09 AK	94	/*
	95	* Called by kexec, immediately prior to machine_kexec().
	96	*
	97	* This must completely disable all secondary CPUs; simply causing those CPUs
	98	* to execute e.g. a RAM-based pin loop is not sufficient. This allows the
	99	* kexec'd kernel to use any and all RAM as it sees fit, without having to
	100	* avoid any code or data used by any SW CPU pin loop. The CPU hotplug
	101	* functionality embodied in disable_nonboot_cpus() to achieve this.
	102	*/
b3901d54 CM	103	void machine_shutdown(void)
b3901d54 CM	104	{
90f51a09	105	disable_nonboot_cpus();
b3901d54 CM	106	}
b3901d54 CM	107
90f51a09 AK	108	/*
	109	* Halting simply requires that the secondary CPUs stop performing any
	110	* activity (executing tasks, handling interrupts). smp_send_stop()
	111	* achieves this.
	112	*/
b3901d54 CM	113	void machine_halt(void)
b3901d54 CM	114	{
b9acc49e	115	local_irq_disable();
90f51a09	116	smp_send_stop();
b3901d54 CM	117	while (1);
	118	}
	119
90f51a09 AK	120	/*
	121	* Power-off simply requires that the secondary CPUs stop performing any
	122	* activity (executing tasks, handling interrupts). smp_send_stop()
	123	* achieves this. When the system power is turned off, it will take all CPUs
	124	* with it.
	125	*/
b3901d54 CM	126	void machine_power_off(void)
b3901d54 CM	127	{
b9acc49e	128	local_irq_disable();
90f51a09	129	smp_send_stop();
b3901d54 CM	130	if (pm_power_off)
	131	pm_power_off();
	132	}
	133
90f51a09 AK	134	/*
90f51a09 AK	135	* Restart requires that the secondary CPUs stop performing any activity
68234df4	136	* while the primary CPU resets the system. Systems with multiple CPUs must
90f51a09 AK	137	* provide a HW restart implementation, to ensure that all CPUs reset at once.
	138	* This is required so that any code running after reset on the primary CPU
	139	* doesn't have to co-ordinate with other CPUs to ensure they aren't still
	140	* executing pre-reset code, and using RAM that the primary CPU's code wishes
	141	* to use. Implementing such co-ordination would be essentially impossible.
	142	*/
b3901d54 CM	143	void machine_restart(char *cmd)
b3901d54 CM	144	{
b3901d54 CM	145	/* Disable interrupts first */
b3901d54 CM	146	local_irq_disable();
b9acc49e	147	smp_send_stop();
b3901d54	148
60c0d45a AB	149	/*
	150	* UpdateCapsule() depends on the system being reset via
	151	* ResetSystem().
	152	*/
	153	if (efi_enabled(EFI_RUNTIME_SERVICES))
	154	efi_reboot(reboot_mode, NULL);
	155
b3901d54	156	/* Now call the architecture specific reboot code. */
aa1e8ec1	157	if (arm_pm_restart)
ff701306	158	arm_pm_restart(reboot_mode, cmd);
1c7ffc32 GR	159	else
1c7ffc32 GR	160	do_kernel_restart(cmd);
b3901d54 CM	161
	162	/*
	163	* Whoops - the architecture was unable to reboot.
	164	*/
	165	printk("Reboot failed -- System halted\n");
	166	while (1);
	167	}
	168
	169	void __show_regs(struct pt_regs *regs)
	170	{
6ca68e80 CM	171	int i, top_reg;
	172	u64 lr, sp;
	173
	174	if (compat_user_mode(regs)) {
	175	lr = regs->compat_lr;
	176	sp = regs->compat_sp;
	177	top_reg = 12;
	178	} else {
	179	lr = regs->regs[30];
	180	sp = regs->sp;
	181	top_reg = 29;
	182	}
b3901d54	183
a43cb95d	184	show_regs_print_info(KERN_DEFAULT);
b3901d54	185	print_symbol("PC is at %s\n", instruction_pointer(regs));
6ca68e80	186	print_symbol("LR is at %s\n", lr);
b3901d54	187	printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
6ca68e80 CM	188	regs->pc, lr, regs->pstate);
6ca68e80 CM	189	printk("sp : %016llx\n", sp);
db4b0710 MR	190
	191	i = top_reg;
	192
	193	while (i >= 0) {
b3901d54	194	printk("x%-2d: %016llx ", i, regs->regs[i]);
db4b0710 MR	195	i--;
	196
	197	if (i % 2 == 0) {
	198	pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
	199	i--;
	200	}
	201
	202	pr_cont("\n");
b3901d54 CM	203	}
	204	printk("\n");
	205	}
	206
	207	void show_regs(struct pt_regs * regs)
	208	{
	209	printk("\n");
b3901d54 CM	210	__show_regs(regs);
	211	}
	212
eb35bdd7 WD	213	static void tls_thread_flush(void)
eb35bdd7 WD	214	{
adf75899	215	write_sysreg(0, tpidr_el0);
eb35bdd7 WD	216
	217	if (is_compat_task()) {
	218	current->thread.tp_value = 0;
	219
	220	/*
	221	* We need to ensure ordering between the shadow state and the
	222	* hardware state, so that we don't corrupt the hardware state
	223	* with a stale shadow state during context switch.
	224	*/
	225	barrier();
adf75899	226	write_sysreg(0, tpidrro_el0);
eb35bdd7 WD	227	}
	228	}
	229
b3901d54 CM	230	void flush_thread(void)
	231	{
	232	fpsimd_flush_thread();
eb35bdd7	233	tls_thread_flush();
b3901d54 CM	234	flush_ptrace_hw_breakpoint(current);
	235	}
	236
	237	void release_thread(struct task_struct *dead_task)
	238	{
	239	}
	240
	241	int arch_dup_task_struct(struct task_struct dst, struct task_struct src)
	242	{
6eb6c801 JL	243	if (current->mm)
6eb6c801 JL	244	fpsimd_preserve_current_state();
b3901d54 CM	245	dst = src;
	246	return 0;
	247	}
	248
	249	asmlinkage void ret_from_fork(void) asm("ret_from_fork");
	250
	251	int copy_thread(unsigned long clone_flags, unsigned long stack_start,
afa86fc4	252	unsigned long stk_sz, struct task_struct *p)
b3901d54 CM	253	{
b3901d54 CM	254	struct pt_regs *childregs = task_pt_regs(p);
b3901d54	255
c34501d2	256	memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
b3901d54	257
9ac08002 AV	258	if (likely(!(p->flags & PF_KTHREAD))) {
9ac08002 AV	259	childregs = current_pt_regs();
c34501d2	260	childregs->regs[0] = 0;
d00a3810 WD	261
	262	/*
	263	* Read the current TLS pointer from tpidr_el0 as it may be
	264	* out-of-sync with the saved value.
	265	*/
adf75899	266	*task_user_tls(p) = read_sysreg(tpidr_el0);
d00a3810 WD	267
	268	if (stack_start) {
	269	if (is_compat_thread(task_thread_info(p)))
e0fd18ce	270	childregs->compat_sp = stack_start;
d00a3810	271	else
e0fd18ce	272	childregs->sp = stack_start;
c34501d2	273	}
d00a3810	274
b3901d54	275	/*
c34501d2 CM	276	* If a TLS pointer was passed to clone (4th argument), use it
c34501d2 CM	277	* for the new thread.
b3901d54	278	*/
c34501d2	279	if (clone_flags & CLONE_SETTLS)
d00a3810	280	p->thread.tp_value = childregs->regs[3];
c34501d2 CM	281	} else {
	282	memset(childregs, 0, sizeof(struct pt_regs));
	283	childregs->pstate = PSR_MODE_EL1h;
57f4959b JM	284	if (IS_ENABLED(CONFIG_ARM64_UAO) &&
	285	cpus_have_cap(ARM64_HAS_UAO))
	286	childregs->pstate \|= PSR_UAO_BIT;
c34501d2 CM	287	p->thread.cpu_context.x19 = stack_start;
c34501d2 CM	288	p->thread.cpu_context.x20 = stk_sz;
b3901d54	289	}
b3901d54	290	p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
c34501d2	291	p->thread.cpu_context.sp = (unsigned long)childregs;
b3901d54 CM	292
	293	ptrace_hw_copy_thread(p);
	294
	295	return 0;
	296	}
	297
	298	static void tls_thread_switch(struct task_struct *next)
	299	{
	300	unsigned long tpidr, tpidrro;
	301
adf75899	302	tpidr = read_sysreg(tpidr_el0);
d00a3810	303	*task_user_tls(current) = tpidr;
b3901d54	304
d00a3810 WD	305	tpidr = *task_user_tls(next);
	306	tpidrro = is_compat_thread(task_thread_info(next)) ?
	307	next->thread.tp_value : 0;
b3901d54	308
adf75899 MR	309	write_sysreg(tpidr, tpidr_el0);
adf75899 MR	310	write_sysreg(tpidrro, tpidrro_el0);
b3901d54 CM	311	}
b3901d54 CM	312
57f4959b	313	/* Restore the UAO state depending on next's addr_limit */
d0854412	314	void uao_thread_switch(struct task_struct *next)
57f4959b	315	{
e950631e CM	316	if (IS_ENABLED(CONFIG_ARM64_UAO)) {
	317	if (task_thread_info(next)->addr_limit == KERNEL_DS)
	318	asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
	319	else
	320	asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
	321	}
57f4959b JM	322	}
57f4959b JM	323
b3901d54 CM	324	/*
	325	* Thread switching.
	326	*/
	327	struct task_struct __switch_to(struct task_struct prev,
	328	struct task_struct *next)
	329	{
	330	struct task_struct *last;
	331
	332	fpsimd_thread_switch(next);
	333	tls_thread_switch(next);
	334	hw_breakpoint_thread_switch(next);
3325732f	335	contextidr_thread_switch(next);
57f4959b	336	uao_thread_switch(next);
b3901d54	337
5108c67c CM	338	/*
	339	* Complete any pending TLB or cache maintenance on this CPU in case
	340	* the thread migrates to a different CPU.
	341	*/
98f7685e	342	dsb(ish);
b3901d54 CM	343
	344	/* the actual thread switch */
	345	last = cpu_switch_to(prev, next);
	346
	347	return last;
	348	}
	349
b3901d54 CM	350	unsigned long get_wchan(struct task_struct *p)
	351	{
	352	struct stackframe frame;
9bbd4c56	353	unsigned long stack_page, ret = 0;
b3901d54 CM	354	int count = 0;
	355	if (!p \|\| p == current \|\| p->state == TASK_RUNNING)
	356	return 0;
	357
9bbd4c56 MR	358	stack_page = (unsigned long)try_get_task_stack(p);
	359	if (!stack_page)
	360	return 0;
	361
b3901d54 CM	362	frame.fp = thread_saved_fp(p);
	363	frame.sp = thread_saved_sp(p);
	364	frame.pc = thread_saved_pc(p);
20380bb3 AT	365	#ifdef CONFIG_FUNCTION_GRAPH_TRACER
	366	frame.graph = p->curr_ret_stack;
	367	#endif
b3901d54	368	do {
408c3658 KK	369	if (frame.sp < stack_page \|\|
408c3658 KK	370	frame.sp >= stack_page + THREAD_SIZE \|\|
fe13f95b	371	unwind_frame(p, &frame))
9bbd4c56 MR	372	goto out;
	373	if (!in_sched_functions(frame.pc)) {
	374	ret = frame.pc;
	375	goto out;
	376	}
b3901d54	377	} while (count ++ < 16);
9bbd4c56 MR	378
	379	out:
	380	put_task_stack(p);
	381	return ret;
b3901d54 CM	382	}
	383
	384	unsigned long arch_align_stack(unsigned long sp)
	385	{
	386	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
	387	sp -= get_random_int() & ~PAGE_MASK;
	388	return sp & ~0xf;
	389	}
	390
b3901d54 CM	391	unsigned long arch_randomize_brk(struct mm_struct *mm)
b3901d54 CM	392	{
61462c8a	393	if (is_compat_task())
fa5114c7	394	return randomize_page(mm->brk, 0x02000000);
61462c8a	395	else
fa5114c7	396	return randomize_page(mm->brk, 0x40000000);
b3901d54	397	}