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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux
[linux-2.6-block.git] / arch / arm64 / kernel / perf_event.c
CommitLineData
03089688
WD		 1/*
2 * PMU support
3 *
4 * Copyright (C) 2012 ARM Limited
5 * Author: Will Deacon <will.deacon@arm.com>
6 *
7 * This code is based heavily on the ARMv7 perf event code.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
03089688 21
03089688 22#include <asm/irq_regs.h>
d98ecdac 23#include <asm/virt.h>
03089688 24
6475b2d8
MR		 25#include <linux/of.h>
26#include <linux/perf/arm_pmu.h>
27#include <linux/platform_device.h>
03089688
WD		 28
29/*
30 * ARMv8 PMUv3 Performance Events handling code.
31 * Common event types.
32 */
03089688 33
90381cba
DR		 34/* Required events. */
35#define ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR 0x00
36#define ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL 0x03
37#define ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS 0x04
38#define ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED 0x10
39#define ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES 0x11
40#define ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED 0x12
03089688 41
90381cba
DR		 42/* At least one of the following is required. */
43#define ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED 0x08
44#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x1B
03089688 45
90381cba
DR		 46/* Common architectural events. */
47#define ARMV8_PMUV3_PERFCTR_MEM_READ 0x06
48#define ARMV8_PMUV3_PERFCTR_MEM_WRITE 0x07
49#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x09
50#define ARMV8_PMUV3_PERFCTR_EXC_EXECUTED 0x0A
51#define ARMV8_PMUV3_PERFCTR_CID_WRITE 0x0B
52#define ARMV8_PMUV3_PERFCTR_PC_WRITE 0x0C
53#define ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH 0x0D
54#define ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN 0x0E
55#define ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F
56#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE 0x1C
9e9caa6a
DR		 57#define ARMV8_PMUV3_PERFCTR_CHAIN 0x1E
58#define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x21
90381cba
DR		 59
60/* Common microarchitectural events. */
61#define ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL 0x01
62#define ARMV8_PMUV3_PERFCTR_ITLB_REFILL 0x02
63#define ARMV8_PMUV3_PERFCTR_DTLB_REFILL 0x05
64#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x13
65#define ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS 0x14
66#define ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB 0x15
67#define ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS 0x16
68#define ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL 0x17
69#define ARMV8_PMUV3_PERFCTR_L2_CACHE_WB 0x18
70#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x19
71#define ARMV8_PMUV3_PERFCTR_MEM_ERROR 0x1A
72#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x1D
9e9caa6a
DR		 73#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x1F
74#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x20
75#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x22
76#define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x23
77#define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x24
78#define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x25
79#define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x26
80#define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x27
81#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x28
82#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x29
83#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x2A
84#define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x2B
85#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x2C
86#define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x2D
87#define ARMV8_PMUV3_PERFCTR_L21_TLB_REFILL 0x2E
88#define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x2F
89#define ARMV8_PMUV3_PERFCTR_L21_TLB 0x30
03089688 90
ac82d127 91/* ARMv8 Cortex-A53 specific event types. */
90381cba 92#define ARMV8_A53_PERFCTR_PREFETCH_LINEFILL 0xC2
ac82d127 93
5d7ee877 94/* ARMv8 Cortex-A57 and Cortex-A72 specific event types. */
90381cba
DR		 95#define ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_LD 0x40
96#define ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_ST 0x41
97#define ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_LD 0x42
98#define ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_ST 0x43
99#define ARMV8_A57_PERFCTR_DTLB_REFILL_LD 0x4c
100#define ARMV8_A57_PERFCTR_DTLB_REFILL_ST 0x4d
62a4dda9 101
03089688
WD		 102/* PMUv3 HW events mapping. */
103static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
ae2fb7ec 104 PERF_MAP_ALL_UNSUPPORTED,
f46f979f 105 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
03089688
WD		 106 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
107 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
108 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
03089688 109 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
03089688
WD		 110};
111
ac82d127
MR		 112/* ARM Cortex-A53 HW events mapping. */
113static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = {
114 PERF_MAP_ALL_UNSUPPORTED,
115 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
116 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
117 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
118 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
119 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE,
120 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
121 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
122};
123
5d7ee877 124/* ARM Cortex-A57 and Cortex-A72 events mapping. */
62a4dda9
MR		 125static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = {
126 PERF_MAP_ALL_UNSUPPORTED,
127 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
128 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
129 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
130 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
131 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
132 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
133};
134
03089688
WD		 135static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
136 [PERF_COUNT_HW_CACHE_OP_MAX]
137 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
ae2fb7ec
MR		 138 PERF_CACHE_MAP_ALL_UNSUPPORTED,
139
140 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
141 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
142 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
143 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
144
145 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
146 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
147 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
148 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
03089688
WD		 149};
150
ac82d127
MR		 151static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
152 [PERF_COUNT_HW_CACHE_OP_MAX]
153 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
154 PERF_CACHE_MAP_ALL_UNSUPPORTED,
155
156 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
157 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
158 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
159 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
160 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREFETCH_LINEFILL,
161
162 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS,
163 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL,
164
165 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_ITLB_REFILL,
166
167 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
168 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
169 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
170 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
171};
172
62a4dda9
MR		 173static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
174 [PERF_COUNT_HW_CACHE_OP_MAX]
175 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
176 PERF_CACHE_MAP_ALL_UNSUPPORTED,
177
178 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_LD,
179 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_LD,
180 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_ST,
181 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_ST,
182
183 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS,
184 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL,
185
186 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_A57_PERFCTR_DTLB_REFILL_LD,
187 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_A57_PERFCTR_DTLB_REFILL_ST,
188
189 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_ITLB_REFILL,
190
191 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
192 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
193 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
194 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
195};
196
9e9caa6a
DR		 197#define ARMV8_EVENT_ATTR_RESOLVE(m) #m
198#define ARMV8_EVENT_ATTR(name, config) \
199 PMU_EVENT_ATTR_STRING(name, armv8_event_attr_##name, \
200 "event=" ARMV8_EVENT_ATTR_RESOLVE(config))
201
202ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR);
203ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL);
204ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_ITLB_REFILL);
205ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL);
206ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS);
207ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_DTLB_REFILL);
208ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_MEM_READ);
209ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_MEM_WRITE);
210ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED);
211ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN);
212ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_EXECUTED);
213ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE);
214ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE);
215ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH);
216ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN);
217ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS);
218ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED);
219ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES);
220ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED);
221ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS);
222ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS);
223ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB);
224ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS);
225ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL);
226ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2_CACHE_WB);
227ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS);
228ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEM_ERROR);
229ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC);
230ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE);
231ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES);
232ARMV8_EVENT_ATTR(chain, ARMV8_PMUV3_PERFCTR_CHAIN);
233ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE);
234ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE);
235ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED);
236ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED);
237ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND);
238ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND);
239ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB);
240ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB);
241ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE);
242ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL);
243ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE);
244ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL);
245ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE);
246ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB);
247ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL);
248ARMV8_EVENT_ATTR(l21_tlb_refill, ARMV8_PMUV3_PERFCTR_L21_TLB_REFILL);
249ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB);
250ARMV8_EVENT_ATTR(l21_tlb, ARMV8_PMUV3_PERFCTR_L21_TLB);
251
252static struct attribute *armv8_pmuv3_event_attrs[] = {
253 &armv8_event_attr_sw_incr.attr.attr,
254 &armv8_event_attr_l1i_cache_refill.attr.attr,
255 &armv8_event_attr_l1i_tlb_refill.attr.attr,
256 &armv8_event_attr_l1d_cache_refill.attr.attr,
257 &armv8_event_attr_l1d_cache.attr.attr,
258 &armv8_event_attr_l1d_tlb_refill.attr.attr,
259 &armv8_event_attr_ld_retired.attr.attr,
260 &armv8_event_attr_st_retired.attr.attr,
261 &armv8_event_attr_inst_retired.attr.attr,
262 &armv8_event_attr_exc_taken.attr.attr,
263 &armv8_event_attr_exc_return.attr.attr,
264 &armv8_event_attr_cid_write_retired.attr.attr,
265 &armv8_event_attr_pc_write_retired.attr.attr,
266 &armv8_event_attr_br_immed_retired.attr.attr,
267 &armv8_event_attr_br_return_retired.attr.attr,
268 &armv8_event_attr_unaligned_ldst_retired.attr.attr,
269 &armv8_event_attr_br_mis_pred.attr.attr,
270 &armv8_event_attr_cpu_cycles.attr.attr,
271 &armv8_event_attr_br_pred.attr.attr,
272 &armv8_event_attr_mem_access.attr.attr,
273 &armv8_event_attr_l1i_cache.attr.attr,
274 &armv8_event_attr_l1d_cache_wb.attr.attr,
275 &armv8_event_attr_l2d_cache.attr.attr,
276 &armv8_event_attr_l2d_cache_refill.attr.attr,
277 &armv8_event_attr_l2d_cache_wb.attr.attr,
278 &armv8_event_attr_bus_access.attr.attr,
279 &armv8_event_attr_memory_error.attr.attr,
280 &armv8_event_attr_inst_spec.attr.attr,
281 &armv8_event_attr_ttbr_write_retired.attr.attr,
282 &armv8_event_attr_bus_cycles.attr.attr,
283 &armv8_event_attr_chain.attr.attr,
284 &armv8_event_attr_l1d_cache_allocate.attr.attr,
285 &armv8_event_attr_l2d_cache_allocate.attr.attr,
286 &armv8_event_attr_br_retired.attr.attr,
287 &armv8_event_attr_br_mis_pred_retired.attr.attr,
288 &armv8_event_attr_stall_frontend.attr.attr,
289 &armv8_event_attr_stall_backend.attr.attr,
290 &armv8_event_attr_l1d_tlb.attr.attr,
291 &armv8_event_attr_l1i_tlb.attr.attr,
292 &armv8_event_attr_l2i_cache.attr.attr,
293 &armv8_event_attr_l2i_cache_refill.attr.attr,
294 &armv8_event_attr_l3d_cache_allocate.attr.attr,
295 &armv8_event_attr_l3d_cache_refill.attr.attr,
296 &armv8_event_attr_l3d_cache.attr.attr,
297 &armv8_event_attr_l3d_cache_wb.attr.attr,
298 &armv8_event_attr_l2d_tlb_refill.attr.attr,
299 &armv8_event_attr_l21_tlb_refill.attr.attr,
300 &armv8_event_attr_l2d_tlb.attr.attr,
301 &armv8_event_attr_l21_tlb.attr.attr,
57d74123 302 NULL,
9e9caa6a
DR		 303};
304
305static struct attribute_group armv8_pmuv3_events_attr_group = {
306 .name = "events",
307 .attrs = armv8_pmuv3_event_attrs,
308};
309
57d74123
WD		 310PMU_FORMAT_ATTR(event, "config:0-9");
311
312static struct attribute *armv8_pmuv3_format_attrs[] = {
313 &format_attr_event.attr,
314 NULL,
315};
316
317static struct attribute_group armv8_pmuv3_format_attr_group = {
318 .name = "format",
319 .attrs = armv8_pmuv3_format_attrs,
320};
321
9e9caa6a
DR		 322static const struct attribute_group *armv8_pmuv3_attr_groups[] = {
323 &armv8_pmuv3_events_attr_group,
57d74123
WD		 324 &armv8_pmuv3_format_attr_group,
325 NULL,
9e9caa6a 326};
62a4dda9 327
57d74123 328
03089688
WD		 329/*
330 * Perf Events' indices
331 */
332#define ARMV8_IDX_CYCLE_COUNTER 0
333#define ARMV8_IDX_COUNTER0 1
6475b2d8
MR		 334#define ARMV8_IDX_COUNTER_LAST(cpu_pmu) \
335 (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
03089688
WD		 336
337#define ARMV8_MAX_COUNTERS 32
338#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1)
339
340/*
341 * ARMv8 low level PMU access
342 */
343
344/*
345 * Perf Event to low level counters mapping
346 */
347#define ARMV8_IDX_TO_COUNTER(x) \
348 (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK)
349
350/*
351 * Per-CPU PMCR: config reg
352 */
353#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */
354#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */
355#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */
356#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
357#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */
358#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
359#define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */
360#define ARMV8_PMCR_N_MASK 0x1f
361#define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */
362
363/*
364 * PMOVSR: counters overflow flag status reg
365 */
366#define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */
367#define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK
368
369/*
370 * PMXEVTYPER: Event selection reg
371 */
c019de3d
VK		 372#define ARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */
373#define ARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */
03089688
WD		 374
375/*
376 * Event filters for PMUv3
377 */
378#define ARMV8_EXCLUDE_EL1 (1 << 31)
379#define ARMV8_EXCLUDE_EL0 (1 << 30)
380#define ARMV8_INCLUDE_EL2 (1 << 27)
381
382static inline u32 armv8pmu_pmcr_read(void)
383{
384 u32 val;
385 asm volatile("mrs %0, pmcr_el0" : "=r" (val));
386 return val;
387}
388
389static inline void armv8pmu_pmcr_write(u32 val)
390{
391 val &= ARMV8_PMCR_MASK;
392 isb();
393 asm volatile("msr pmcr_el0, %0" :: "r" (val));
394}
395
396static inline int armv8pmu_has_overflowed(u32 pmovsr)
397{
398 return pmovsr & ARMV8_OVERFLOWED_MASK;
399}
400
6475b2d8 401static inline int armv8pmu_counter_valid(struct arm_pmu *cpu_pmu, int idx)
03089688 402{
6475b2d8
MR		 403 return idx >= ARMV8_IDX_CYCLE_COUNTER &&
404 idx <= ARMV8_IDX_COUNTER_LAST(cpu_pmu);
03089688
WD		 405}
406
407static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
408{
6475b2d8 409 return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
03089688
WD		 410}
411
412static inline int armv8pmu_select_counter(int idx)
413{
6475b2d8 414 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
03089688
WD		 415 asm volatile("msr pmselr_el0, %0" :: "r" (counter));
416 isb();
417
418 return idx;
419}
420
6475b2d8 421static inline u32 armv8pmu_read_counter(struct perf_event *event)
03089688 422{
6475b2d8
MR		 423 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
424 struct hw_perf_event *hwc = &event->hw;
425 int idx = hwc->idx;
03089688
WD		 426 u32 value = 0;
427
6475b2d8 428 if (!armv8pmu_counter_valid(cpu_pmu, idx))
03089688
WD		 429 pr_err("CPU%u reading wrong counter %d\n",
430 smp_processor_id(), idx);
431 else if (idx == ARMV8_IDX_CYCLE_COUNTER)
432 asm volatile("mrs %0, pmccntr_el0" : "=r" (value));
433 else if (armv8pmu_select_counter(idx) == idx)
434 asm volatile("mrs %0, pmxevcntr_el0" : "=r" (value));
435
436 return value;
437}
438
6475b2d8 439static inline void armv8pmu_write_counter(struct perf_event *event, u32 value)
03089688 440{
6475b2d8
MR		 441 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
442 struct hw_perf_event *hwc = &event->hw;
443 int idx = hwc->idx;
444
445 if (!armv8pmu_counter_valid(cpu_pmu, idx))
03089688
WD		 446 pr_err("CPU%u writing wrong counter %d\n",
447 smp_processor_id(), idx);
448 else if (idx == ARMV8_IDX_CYCLE_COUNTER)
449 asm volatile("msr pmccntr_el0, %0" :: "r" (value));
450 else if (armv8pmu_select_counter(idx) == idx)
451 asm volatile("msr pmxevcntr_el0, %0" :: "r" (value));
452}
453
454static inline void armv8pmu_write_evtype(int idx, u32 val)
455{
456 if (armv8pmu_select_counter(idx) == idx) {
457 val &= ARMV8_EVTYPE_MASK;
458 asm volatile("msr pmxevtyper_el0, %0" :: "r" (val));
459 }
460}
461
462static inline int armv8pmu_enable_counter(int idx)
463{
6475b2d8 464 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
03089688
WD		 465 asm volatile("msr pmcntenset_el0, %0" :: "r" (BIT(counter)));
466 return idx;
467}
468
469static inline int armv8pmu_disable_counter(int idx)
470{
6475b2d8 471 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
03089688
WD		 472 asm volatile("msr pmcntenclr_el0, %0" :: "r" (BIT(counter)));
473 return idx;
474}
475
476static inline int armv8pmu_enable_intens(int idx)
477{
6475b2d8 478 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
03089688
WD		 479 asm volatile("msr pmintenset_el1, %0" :: "r" (BIT(counter)));
480 return idx;
481}
482
483static inline int armv8pmu_disable_intens(int idx)
484{
6475b2d8 485 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
03089688
WD		 486 asm volatile("msr pmintenclr_el1, %0" :: "r" (BIT(counter)));
487 isb();
488 /* Clear the overflow flag in case an interrupt is pending. */
489 asm volatile("msr pmovsclr_el0, %0" :: "r" (BIT(counter)));
490 isb();
6475b2d8 491
03089688
WD		 492 return idx;
493}
494
495static inline u32 armv8pmu_getreset_flags(void)
496{
497 u32 value;
498
499 /* Read */
500 asm volatile("mrs %0, pmovsclr_el0" : "=r" (value));
501
502 /* Write to clear flags */
503 value &= ARMV8_OVSR_MASK;
504 asm volatile("msr pmovsclr_el0, %0" :: "r" (value));
505
506 return value;
507}
508
6475b2d8 509static void armv8pmu_enable_event(struct perf_event *event)
03089688
WD		 510{
511 unsigned long flags;
6475b2d8
MR		 512 struct hw_perf_event *hwc = &event->hw;
513 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
514 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
515 int idx = hwc->idx;
03089688
WD		 516
517 /*
518 * Enable counter and interrupt, and set the counter to count
519 * the event that we're interested in.
520 */
521 raw_spin_lock_irqsave(&events->pmu_lock, flags);
522
523 /*
524 * Disable counter
525 */
526 armv8pmu_disable_counter(idx);
527
528 /*
529 * Set event (if destined for PMNx counters).
530 */
531 armv8pmu_write_evtype(idx, hwc->config_base);
532
533 /*
534 * Enable interrupt for this counter
535 */
536 armv8pmu_enable_intens(idx);
537
538 /*
539 * Enable counter
540 */
541 armv8pmu_enable_counter(idx);
542
543 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
544}
545
6475b2d8 546static void armv8pmu_disable_event(struct perf_event *event)
03089688
WD		 547{
548 unsigned long flags;
6475b2d8
MR		 549 struct hw_perf_event *hwc = &event->hw;
550 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
551 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
552 int idx = hwc->idx;
03089688
WD		 553
554 /*
555 * Disable counter and interrupt
556 */
557 raw_spin_lock_irqsave(&events->pmu_lock, flags);
558
559 /*
560 * Disable counter
561 */
562 armv8pmu_disable_counter(idx);
563
564 /*
565 * Disable interrupt for this counter
566 */
567 armv8pmu_disable_intens(idx);
568
569 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
570}
571
572static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
573{
574 u32 pmovsr;
575 struct perf_sample_data data;
6475b2d8
MR		 576 struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
577 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
03089688
WD		 578 struct pt_regs *regs;
579 int idx;
580
581 /*
582 * Get and reset the IRQ flags
583 */
584 pmovsr = armv8pmu_getreset_flags();
585
586 /*
587 * Did an overflow occur?
588 */
589 if (!armv8pmu_has_overflowed(pmovsr))
590 return IRQ_NONE;
591
592 /*
593 * Handle the counter(s) overflow(s)
594 */
595 regs = get_irq_regs();
596
03089688
WD		 597 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
598 struct perf_event *event = cpuc->events[idx];
599 struct hw_perf_event *hwc;
600
601 /* Ignore if we don't have an event. */
602 if (!event)
603 continue;
604
605 /*
606 * We have a single interrupt for all counters. Check that
607 * each counter has overflowed before we process it.
608 */
609 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
610 continue;
611
612 hwc = &event->hw;
6475b2d8 613 armpmu_event_update(event);
03089688 614 perf_sample_data_init(&data, 0, hwc->last_period);
6475b2d8 615 if (!armpmu_event_set_period(event))
03089688
WD		 616 continue;
617
618 if (perf_event_overflow(event, &data, regs))
6475b2d8 619 cpu_pmu->disable(event);
03089688
WD		 620 }
621
622 /*
623 * Handle the pending perf events.
624 *
625 * Note: this call *must* be run with interrupts disabled. For
626 * platforms that can have the PMU interrupts raised as an NMI, this
627 * will not work.
628 */
629 irq_work_run();
630
631 return IRQ_HANDLED;
632}
633
6475b2d8 634static void armv8pmu_start(struct arm_pmu *cpu_pmu)
03089688
WD		 635{
636 unsigned long flags;
6475b2d8 637 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
03089688
WD		 638
639 raw_spin_lock_irqsave(&events->pmu_lock, flags);
640 /* Enable all counters */
641 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMCR_E);
642 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
643}
644
6475b2d8 645static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
03089688
WD		 646{
647 unsigned long flags;
6475b2d8 648 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
03089688
WD		 649
650 raw_spin_lock_irqsave(&events->pmu_lock, flags);
651 /* Disable all counters */
652 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMCR_E);
653 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
654}
655
656static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
6475b2d8 657 struct perf_event *event)
03089688
WD		 658{
659 int idx;
6475b2d8
MR		 660 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
661 struct hw_perf_event *hwc = &event->hw;
662 unsigned long evtype = hwc->config_base & ARMV8_EVTYPE_EVENT;
03089688
WD		 663
664 /* Always place a cycle counter into the cycle counter. */
f46f979f 665 if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) {
03089688
WD		 666 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
667 return -EAGAIN;
668
669 return ARMV8_IDX_CYCLE_COUNTER;
670 }
671
672 /*
673 * For anything other than a cycle counter, try and use
674 * the events counters
675 */
676 for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
677 if (!test_and_set_bit(idx, cpuc->used_mask))
678 return idx;
679 }
680
681 /* The counters are all in use. */
682 return -EAGAIN;
683}
684
685/*
686 * Add an event filter to a given event. This will only work for PMUv2 PMUs.
687 */
688static int armv8pmu_set_event_filter(struct hw_perf_event *event,
689 struct perf_event_attr *attr)
690{
691 unsigned long config_base = 0;
692
693 if (attr->exclude_idle)
694 return -EPERM;
d98ecdac
MZ		 695 if (is_kernel_in_hyp_mode() &&
696 attr->exclude_kernel != attr->exclude_hv)
697 return -EINVAL;
03089688
WD		 698 if (attr->exclude_user)
699 config_base |= ARMV8_EXCLUDE_EL0;
d98ecdac 700 if (!is_kernel_in_hyp_mode() && attr->exclude_kernel)
03089688
WD		 701 config_base |= ARMV8_EXCLUDE_EL1;
702 if (!attr->exclude_hv)
703 config_base |= ARMV8_INCLUDE_EL2;
704
705 /*
706 * Install the filter into config_base as this is used to
707 * construct the event type.
708 */
709 event->config_base = config_base;
710
711 return 0;
712}
713
714static void armv8pmu_reset(void *info)
715{
6475b2d8 716 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
03089688
WD		 717 u32 idx, nb_cnt = cpu_pmu->num_events;
718
719 /* The counter and interrupt enable registers are unknown at reset. */
6475b2d8
MR		 720 for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
721 armv8pmu_disable_counter(idx);
722 armv8pmu_disable_intens(idx);
723 }
03089688
WD		 724
725 /* Initialize & Reset PMNC: C and P bits. */
726 armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C);
03089688
WD		 727}
728
729static int armv8_pmuv3_map_event(struct perf_event *event)
730{
6475b2d8 731 return armpmu_map_event(event, &armv8_pmuv3_perf_map,
c019de3d
VK		 732 &armv8_pmuv3_perf_cache_map,
733 ARMV8_EVTYPE_EVENT);
03089688
WD		 734}
735
ac82d127
MR		 736static int armv8_a53_map_event(struct perf_event *event)
737{
738 return armpmu_map_event(event, &armv8_a53_perf_map,
739 &armv8_a53_perf_cache_map,
740 ARMV8_EVTYPE_EVENT);
741}
742
62a4dda9
MR		 743static int armv8_a57_map_event(struct perf_event *event)
744{
745 return armpmu_map_event(event, &armv8_a57_perf_map,
746 &armv8_a57_perf_cache_map,
747 ARMV8_EVTYPE_EVENT);
748}
749
6475b2d8 750static void armv8pmu_read_num_pmnc_events(void *info)
03089688 751{
6475b2d8 752 int *nb_cnt = info;
03089688
WD		 753
754 /* Read the nb of CNTx counters supported from PMNC */
6475b2d8 755 *nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
03089688 756
6475b2d8
MR		 757 /* Add the CPU cycles counter */
758 *nb_cnt += 1;
03089688
WD		 759}
760
6475b2d8 761static int armv8pmu_probe_num_events(struct arm_pmu *arm_pmu)
03089688 762{
6475b2d8
MR		 763 return smp_call_function_any(&arm_pmu->supported_cpus,
764 armv8pmu_read_num_pmnc_events,
765 &arm_pmu->num_events, 1);
03089688
WD		 766}
767
ac82d127 768static void armv8_pmu_init(struct arm_pmu *cpu_pmu)
03089688 769{
6475b2d8
MR		 770 cpu_pmu->handle_irq = armv8pmu_handle_irq,
771 cpu_pmu->enable = armv8pmu_enable_event,
772 cpu_pmu->disable = armv8pmu_disable_event,
773 cpu_pmu->read_counter = armv8pmu_read_counter,
774 cpu_pmu->write_counter = armv8pmu_write_counter,
775 cpu_pmu->get_event_idx = armv8pmu_get_event_idx,
776 cpu_pmu->start = armv8pmu_start,
777 cpu_pmu->stop = armv8pmu_stop,
778 cpu_pmu->reset = armv8pmu_reset,
779 cpu_pmu->max_period = (1LLU << 32) - 1,
ac82d127
MR		 780 cpu_pmu->set_event_filter = armv8pmu_set_event_filter;
781}
782
783static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
784{
785 armv8_pmu_init(cpu_pmu);
6475b2d8
MR		 786 cpu_pmu->name = "armv8_pmuv3";
787 cpu_pmu->map_event = armv8_pmuv3_map_event;
ac82d127
MR		 788 return armv8pmu_probe_num_events(cpu_pmu);
789}
790
791static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
792{
793 armv8_pmu_init(cpu_pmu);
794 cpu_pmu->name = "armv8_cortex_a53";
795 cpu_pmu->map_event = armv8_a53_map_event;
9e9caa6a 796 cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups;
6475b2d8 797 return armv8pmu_probe_num_events(cpu_pmu);
03089688 798}
03089688 799
62a4dda9
MR		 800static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
801{
802 armv8_pmu_init(cpu_pmu);
803 cpu_pmu->name = "armv8_cortex_a57";
804 cpu_pmu->map_event = armv8_a57_map_event;
9e9caa6a 805 cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups;
62a4dda9
MR		 806 return armv8pmu_probe_num_events(cpu_pmu);
807}
808
5d7ee877
WD		 809static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
810{
811 armv8_pmu_init(cpu_pmu);
812 cpu_pmu->name = "armv8_cortex_a72";
813 cpu_pmu->map_event = armv8_a57_map_event;
814 cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups;
815 return armv8pmu_probe_num_events(cpu_pmu);
816}
817
6475b2d8
MR		 818static const struct of_device_id armv8_pmu_of_device_ids[] = {
819 {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
ac82d127 820 {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
62a4dda9 821 {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
5d7ee877 822 {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
03089688
WD		 823 {},
824};
825
6475b2d8 826static int armv8_pmu_device_probe(struct platform_device *pdev)
03089688 827{
6475b2d8 828 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
03089688
WD		 829}
830
6475b2d8 831static struct platform_driver armv8_pmu_driver = {
03089688 832 .driver = {
6475b2d8
MR		 833 .name = "armv8-pmu",
834 .of_match_table = armv8_pmu_of_device_ids,
03089688 835 },
6475b2d8 836 .probe = armv8_pmu_device_probe,
03089688
WD		 837};
838
6475b2d8 839static int __init register_armv8_pmu_driver(void)
03089688 840{
6475b2d8 841 return platform_driver_register(&armv8_pmu_driver);
03089688 842}
6475b2d8 843device_initcall(register_armv8_pmu_driver);
Linux 6.x block layer and io_uring tree(s)