[linux-2.6-block.git] / arch / arm64 / kernel / module.c

/*
 * AArch64 loadable module support.
 *
 * Copyright (C) 2012 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * Author: Will Deacon <will.deacon@arm.com>
 */

#include <linux/bitops.h>
#include <linux/elf.h>
#include <linux/gfp.h>
#include <linux/kasan.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/moduleloader.h>
#include <linux/vmalloc.h>
#include <asm/alternative.h>
#include <asm/insn.h>
#include <asm/sections.h>

void *module_alloc(unsigned long size)
{
	gfp_t gfp_mask = GFP_KERNEL;
	void *p;

	/* Silence the initial allocation */
	if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS))
		gfp_mask |= __GFP_NOWARN;

	p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
				module_alloc_base + MODULES_VSIZE,
				gfp_mask, PAGE_KERNEL_EXEC, 0,
				NUMA_NO_NODE, __builtin_return_address(0));

	if (!p && IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
	    !IS_ENABLED(CONFIG_KASAN))
		/*
		 * KASAN can only deal with module allocations being served
		 * from the reserved module region, since the remainder of
		 * the vmalloc region is already backed by zero shadow pages,
		 * and punching holes into it is non-trivial. Since the module
		 * region is not randomized when KASAN is enabled, it is even
		 * less likely that the module region gets exhausted, so we
		 * can simply omit this fallback in that case.
		 */
		p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
				module_alloc_base + SZ_4G, GFP_KERNEL,
				PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
				__builtin_return_address(0));

	if (p && (kasan_module_alloc(p, size) < 0)) {
		vfree(p);
		return NULL;
	}

	return p;
}

enum aarch64_reloc_op {
	RELOC_OP_NONE,
	RELOC_OP_ABS,
	RELOC_OP_PREL,
	RELOC_OP_PAGE,
};

static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val)
{
	switch (reloc_op) {
	case RELOC_OP_ABS:
		return val;
	case RELOC_OP_PREL:
		return val - (u64)place;
	case RELOC_OP_PAGE:
		return (val & ~0xfff) - ((u64)place & ~0xfff);
	case RELOC_OP_NONE:
		return 0;
	}

	pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
	return 0;
}

static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
{
	s64 sval = do_reloc(op, place, val);

	switch (len) {
	case 16:
		*(s16 *)place = sval;
		if (sval < S16_MIN || sval > U16_MAX)
			return -ERANGE;
		break;
	case 32:
		*(s32 *)place = sval;
		if (sval < S32_MIN || sval > U32_MAX)
			return -ERANGE;
		break;
	case 64:
		*(s64 *)place = sval;
		break;
	default:
		pr_err("Invalid length (%d) for data relocation\n", len);
		return 0;
	}
	return 0;
}

enum aarch64_insn_movw_imm_type {
	AARCH64_INSN_IMM_MOVNZ,
	AARCH64_INSN_IMM_MOVKZ,
};

static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val,
			   int lsb, enum aarch64_insn_movw_imm_type imm_type)
{
	u64 imm;
	s64 sval;
	u32 insn = le32_to_cpu(*place);

	sval = do_reloc(op, place, val);
	imm = sval >> lsb;

	if (imm_type == AARCH64_INSN_IMM_MOVNZ) {
		/*
		 * For signed MOVW relocations, we have to manipulate the
		 * instruction encoding depending on whether or not the
		 * immediate is less than zero.
		 */
		insn &= ~(3 << 29);
		if (sval >= 0) {
			/* >=0: Set the instruction to MOVZ (opcode 10b). */
			insn |= 2 << 29;
		} else {
			/*
			 * <0: Set the instruction to MOVN (opcode 00b).
			 *     Since we've masked the opcode already, we
			 *     don't need to do anything other than
			 *     inverting the new immediate field.
			 */
			imm = ~imm;
		}
	}

	/* Update the instruction with the new encoding. */
	insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
	*place = cpu_to_le32(insn);

	if (imm > U16_MAX)
		return -ERANGE;

	return 0;
}

static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val,
			  int lsb, int len, enum aarch64_insn_imm_type imm_type)
{
	u64 imm, imm_mask;
	s64 sval;
	u32 insn = le32_to_cpu(*place);

	/* Calculate the relocation value. */
	sval = do_reloc(op, place, val);
	sval >>= lsb;

	/* Extract the value bits and shift them to bit 0. */
	imm_mask = (BIT(lsb + len) - 1) >> lsb;
	imm = sval & imm_mask;

	/* Update the instruction's immediate field. */
	insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
	*place = cpu_to_le32(insn);

	/*
	 * Extract the upper value bits (including the sign bit) and
	 * shift them to bit 0.
	 */
	sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);

	/*
	 * Overflow has occurred if the upper bits are not all equal to
	 * the sign bit of the value.
	 */
	if ((u64)(sval + 1) >= 2)
		return -ERANGE;

	return 0;
}

static int reloc_insn_adrp(struct module *mod, __le32 *place, u64 val)
{
	u32 insn;

	if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) ||
	    !cpus_have_const_cap(ARM64_WORKAROUND_843419) ||
	    ((u64)place & 0xfff) < 0xff8)
		return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
				      AARCH64_INSN_IMM_ADR);

	/* patch ADRP to ADR if it is in range */
	if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21,
			    AARCH64_INSN_IMM_ADR)) {
		insn = le32_to_cpu(*place);
		insn &= ~BIT(31);
	} else {
		/* out of range for ADR -> emit a veneer */
		val = module_emit_veneer_for_adrp(mod, place, val & ~0xfff);
		if (!val)
			return -ENOEXEC;
		insn = aarch64_insn_gen_branch_imm((u64)place, val,
						   AARCH64_INSN_BRANCH_NOLINK);
	}

	*place = cpu_to_le32(insn);
	return 0;
}

int apply_relocate_add(Elf64_Shdr *sechdrs,
		       const char *strtab,
		       unsigned int symindex,
		       unsigned int relsec,
		       struct module *me)
{
	unsigned int i;
	int ovf;
	bool overflow_check;
	Elf64_Sym *sym;
	void *loc;
	u64 val;
	Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr;

	for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
		/* loc corresponds to P in the AArch64 ELF document. */
		loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
			+ rel[i].r_offset;

		/* sym is the ELF symbol we're referring to. */
		sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
			+ ELF64_R_SYM(rel[i].r_info);

		/* val corresponds to (S + A) in the AArch64 ELF document. */
		val = sym->st_value + rel[i].r_addend;

		/* Check for overflow by default. */
		overflow_check = true;

		/* Perform the static relocation. */
		switch (ELF64_R_TYPE(rel[i].r_info)) {
		/* Null relocations. */
		case R_ARM_NONE:
		case R_AARCH64_NONE:
			ovf = 0;
			break;

		/* Data relocations. */
		case R_AARCH64_ABS64:
			overflow_check = false;
			ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
			break;
		case R_AARCH64_ABS32:
			ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
			break;
		case R_AARCH64_ABS16:
			ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
			break;
		case R_AARCH64_PREL64:
			overflow_check = false;
			ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
			break;
		case R_AARCH64_PREL32:
			ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
			break;
		case R_AARCH64_PREL16:
			ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
			break;

		/* MOVW instruction relocations. */
		case R_AARCH64_MOVW_UABS_G0_NC:
			overflow_check = false;
		case R_AARCH64_MOVW_UABS_G0:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_UABS_G1_NC:
			overflow_check = false;
		case R_AARCH64_MOVW_UABS_G1:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_UABS_G2_NC:
			overflow_check = false;
		case R_AARCH64_MOVW_UABS_G2:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_UABS_G3:
			/* We're using the top bits so we can't overflow. */
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_SABS_G0:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_SABS_G1:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_SABS_G2:
			ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_PREL_G0_NC:
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_PREL_G0:
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_PREL_G1_NC:
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_PREL_G1:
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_PREL_G2_NC:
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
					      AARCH64_INSN_IMM_MOVKZ);
			break;
		case R_AARCH64_MOVW_PREL_G2:
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
					      AARCH64_INSN_IMM_MOVNZ);
			break;
		case R_AARCH64_MOVW_PREL_G3:
			/* We're using the top bits so we can't overflow. */
			overflow_check = false;
			ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
					      AARCH64_INSN_IMM_MOVNZ);
			break;

		/* Immediate instruction relocations. */
		case R_AARCH64_LD_PREL_LO19:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
					     AARCH64_INSN_IMM_19);
			break;
		case R_AARCH64_ADR_PREL_LO21:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
					     AARCH64_INSN_IMM_ADR);
			break;
		case R_AARCH64_ADR_PREL_PG_HI21_NC:
			overflow_check = false;
		case R_AARCH64_ADR_PREL_PG_HI21:
			ovf = reloc_insn_adrp(me, loc, val);
			if (ovf && ovf != -ERANGE)
				return ovf;
			break;
		case R_AARCH64_ADD_ABS_LO12_NC:
		case R_AARCH64_LDST8_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_LDST16_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_LDST32_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_LDST64_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_LDST128_ABS_LO12_NC:
			overflow_check = false;
			ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
					     AARCH64_INSN_IMM_12);
			break;
		case R_AARCH64_TSTBR14:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
					     AARCH64_INSN_IMM_14);
			break;
		case R_AARCH64_CONDBR19:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
					     AARCH64_INSN_IMM_19);
			break;
		case R_AARCH64_JUMP26:
		case R_AARCH64_CALL26:
			ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
					     AARCH64_INSN_IMM_26);

			if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
			    ovf == -ERANGE) {
				val = module_emit_plt_entry(me, loc, &rel[i], sym);
				if (!val)
					return -ENOEXEC;
				ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2,
						     26, AARCH64_INSN_IMM_26);
			}
			break;

		default:
			pr_err("module %s: unsupported RELA relocation: %llu\n",
			       me->name, ELF64_R_TYPE(rel[i].r_info));
			return -ENOEXEC;
		}

		if (overflow_check && ovf == -ERANGE)
			goto overflow;

	}

	return 0;

overflow:
	pr_err("module %s: overflow in relocation type %d val %Lx\n",
	       me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
	return -ENOEXEC;
}

int module_finalize(const Elf_Ehdr *hdr,
		    const Elf_Shdr *sechdrs,
		    struct module *me)
{
	const Elf_Shdr *s, *se;
	const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;

	for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
		if (strcmp(".altinstructions", secstrs + s->sh_name) == 0) {
			apply_alternatives((void *)s->sh_addr, s->sh_size);
		}
#ifdef CONFIG_ARM64_MODULE_PLTS
		if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) &&
		    !strcmp(".text.ftrace_trampoline", secstrs + s->sh_name))
			me->arch.ftrace_trampoline = (void *)s->sh_addr;
#endif
	}

	return 0;
}
Commit	Line	Data
257cb251 WD	1	/*
	2	* AArch64 loadable module support.
	3	*
	4	* Copyright (C) 2012 ARM Limited
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*
	18	* Author: Will Deacon <will.deacon@arm.com>
	19	*/
	20
	21	#include <linux/bitops.h>
	22	#include <linux/elf.h>
	23	#include <linux/gfp.h>
39d114dd	24	#include <linux/kasan.h>
257cb251 WD	25	#include <linux/kernel.h>
	26	#include <linux/mm.h>
	27	#include <linux/moduleloader.h>
	28	#include <linux/vmalloc.h>
2c2b282d	29	#include <asm/alternative.h>
c84fced8	30	#include <asm/insn.h>
932ded4b	31	#include <asm/sections.h>
c84fced8	32
257cb251 WD	33	void *module_alloc(unsigned long size)
257cb251 WD	34	{
0c2cf6d9	35	gfp_t gfp_mask = GFP_KERNEL;
39d114dd AR	36	void *p;
39d114dd AR	37
0c2cf6d9 FF	38	/* Silence the initial allocation */
	39	if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS))
	40	gfp_mask \|= __GFP_NOWARN;
	41
f80fb3a3 AB	42	p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
f80fb3a3 AB	43	module_alloc_base + MODULES_VSIZE,
0c2cf6d9	44	gfp_mask, PAGE_KERNEL_EXEC, 0,
39d114dd AR	45	NUMA_NO_NODE, __builtin_return_address(0));
39d114dd AR	46
fd045f6c AB	47	if (!p && IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
	48	!IS_ENABLED(CONFIG_KASAN))
	49	/*
	50	* KASAN can only deal with module allocations being served
	51	* from the reserved module region, since the remainder of
	52	* the vmalloc region is already backed by zero shadow pages,
	53	* and punching holes into it is non-trivial. Since the module
	54	* region is not randomized when KASAN is enabled, it is even
	55	* less likely that the module region gets exhausted, so we
	56	* can simply omit this fallback in that case.
	57	*/
f2b9ba87 AB	58	p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
	59	module_alloc_base + SZ_4G, GFP_KERNEL,
	60	PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
	61	__builtin_return_address(0));
fd045f6c	62
39d114dd AR	63	if (p && (kasan_module_alloc(p, size) < 0)) {
	64	vfree(p);
	65	return NULL;
	66	}
	67
	68	return p;
257cb251 WD	69	}
	70
	71	enum aarch64_reloc_op {
	72	RELOC_OP_NONE,
	73	RELOC_OP_ABS,
	74	RELOC_OP_PREL,
	75	RELOC_OP_PAGE,
	76	};
	77
02129ae5	78	static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val)
257cb251 WD	79	{
	80	switch (reloc_op) {
	81	case RELOC_OP_ABS:
	82	return val;
	83	case RELOC_OP_PREL:
	84	return val - (u64)place;
	85	case RELOC_OP_PAGE:
	86	return (val & ~0xfff) - ((u64)place & ~0xfff);
	87	case RELOC_OP_NONE:
	88	return 0;
	89	}
	90
	91	pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
	92	return 0;
	93	}
	94
	95	static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
	96	{
257cb251 WD	97	s64 sval = do_reloc(op, place, val);
	98
	99	switch (len) {
	100	case 16:
	101	(s16 )place = sval;
f9308969 AB	102	if (sval < S16_MIN \|\| sval > U16_MAX)
f9308969 AB	103	return -ERANGE;
257cb251 WD	104	break;
	105	case 32:
	106	(s32 )place = sval;
f9308969 AB	107	if (sval < S32_MIN \|\| sval > U32_MAX)
f9308969 AB	108	return -ERANGE;
257cb251 WD	109	break;
	110	case 64:
	111	(s64 )place = sval;
	112	break;
	113	default:
	114	pr_err("Invalid length (%d) for data relocation\n", len);
	115	return 0;
	116	}
257cb251 WD	117	return 0;
	118	}
	119
b24a5575 AB	120	enum aarch64_insn_movw_imm_type {
	121	AARCH64_INSN_IMM_MOVNZ,
	122	AARCH64_INSN_IMM_MOVKZ,
	123	};
	124
02129ae5	125	static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val,
b24a5575	126	int lsb, enum aarch64_insn_movw_imm_type imm_type)
257cb251	127	{
b24a5575	128	u64 imm;
c84fced8	129	s64 sval;
02129ae5	130	u32 insn = le32_to_cpu(*place);
257cb251	131
c84fced8	132	sval = do_reloc(op, place, val);
b24a5575	133	imm = sval >> lsb;
122e2fa0	134
c84fced8	135	if (imm_type == AARCH64_INSN_IMM_MOVNZ) {
257cb251 WD	136	/*
	137	* For signed MOVW relocations, we have to manipulate the
	138	* instruction encoding depending on whether or not the
	139	* immediate is less than zero.
	140	*/
	141	insn &= ~(3 << 29);
b24a5575	142	if (sval >= 0) {
257cb251 WD	143	/* >=0: Set the instruction to MOVZ (opcode 10b). */
	144	insn \|= 2 << 29;
	145	} else {
	146	/*
	147	* <0: Set the instruction to MOVN (opcode 00b).
	148	* Since we've masked the opcode already, we
	149	* don't need to do anything other than
	150	* inverting the new immediate field.
	151	*/
	152	imm = ~imm;
	153	}
257cb251 WD	154	}
257cb251 WD	155
257cb251	156	/* Update the instruction with the new encoding. */
b24a5575	157	insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
02129ae5	158	*place = cpu_to_le32(insn);
257cb251	159
b24a5575	160	if (imm > U16_MAX)
257cb251 WD	161	return -ERANGE;
	162
	163	return 0;
	164	}
	165
02129ae5	166	static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val,
c84fced8	167	int lsb, int len, enum aarch64_insn_imm_type imm_type)
257cb251 WD	168	{
	169	u64 imm, imm_mask;
	170	s64 sval;
02129ae5	171	u32 insn = le32_to_cpu(*place);
257cb251 WD	172
	173	/* Calculate the relocation value. */
	174	sval = do_reloc(op, place, val);
	175	sval >>= lsb;
	176
	177	/* Extract the value bits and shift them to bit 0. */
	178	imm_mask = (BIT(lsb + len) - 1) >> lsb;
	179	imm = sval & imm_mask;
	180
	181	/* Update the instruction's immediate field. */
c84fced8	182	insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
02129ae5	183	*place = cpu_to_le32(insn);
257cb251 WD	184
	185	/*
	186	* Extract the upper value bits (including the sign bit) and
	187	* shift them to bit 0.
	188	*/
	189	sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
	190
	191	/*
	192	* Overflow has occurred if the upper bits are not all equal to
	193	* the sign bit of the value.
	194	*/
	195	if ((u64)(sval + 1) >= 2)
	196	return -ERANGE;
	197
	198	return 0;
	199	}
	200
a257e025 AB	201	static int reloc_insn_adrp(struct module mod, __le32 place, u64 val)
	202	{
	203	u32 insn;
	204
	205	if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) \|\|
ca79acca	206	!cpus_have_const_cap(ARM64_WORKAROUND_843419) \|\|
a257e025 AB	207	((u64)place & 0xfff) < 0xff8)
	208	return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
	209	AARCH64_INSN_IMM_ADR);
	210
	211	/* patch ADRP to ADR if it is in range */
	212	if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21,
	213	AARCH64_INSN_IMM_ADR)) {
	214	insn = le32_to_cpu(*place);
	215	insn &= ~BIT(31);
	216	} else {
	217	/* out of range for ADR -> emit a veneer */
ed231ae3	218	val = module_emit_veneer_for_adrp(mod, place, val & ~0xfff);
a257e025 AB	219	if (!val)
	220	return -ENOEXEC;
	221	insn = aarch64_insn_gen_branch_imm((u64)place, val,
	222	AARCH64_INSN_BRANCH_NOLINK);
	223	}
	224
	225	*place = cpu_to_le32(insn);
	226	return 0;
	227	}
	228
257cb251 WD	229	int apply_relocate_add(Elf64_Shdr *sechdrs,
	230	const char *strtab,
	231	unsigned int symindex,
	232	unsigned int relsec,
	233	struct module *me)
	234	{
	235	unsigned int i;
	236	int ovf;
	237	bool overflow_check;
	238	Elf64_Sym *sym;
	239	void *loc;
	240	u64 val;
	241	Elf64_Rela rel = (void )sechdrs[relsec].sh_addr;
	242
	243	for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
	244	/* loc corresponds to P in the AArch64 ELF document. */
	245	loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
	246	+ rel[i].r_offset;
	247
	248	/* sym is the ELF symbol we're referring to. */
	249	sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
	250	+ ELF64_R_SYM(rel[i].r_info);
	251
	252	/* val corresponds to (S + A) in the AArch64 ELF document. */
	253	val = sym->st_value + rel[i].r_addend;
	254
	255	/* Check for overflow by default. */
	256	overflow_check = true;
	257
	258	/* Perform the static relocation. */
	259	switch (ELF64_R_TYPE(rel[i].r_info)) {
	260	/* Null relocations. */
	261	case R_ARM_NONE:
	262	case R_AARCH64_NONE:
	263	ovf = 0;
	264	break;
	265
	266	/* Data relocations. */
	267	case R_AARCH64_ABS64:
	268	overflow_check = false;
	269	ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
	270	break;
	271	case R_AARCH64_ABS32:
	272	ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
	273	break;
	274	case R_AARCH64_ABS16:
	275	ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
	276	break;
	277	case R_AARCH64_PREL64:
	278	overflow_check = false;
	279	ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
	280	break;
	281	case R_AARCH64_PREL32:
	282	ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
	283	break;
	284	case R_AARCH64_PREL16:
	285	ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
	286	break;
	287
	288	/* MOVW instruction relocations. */
	289	case R_AARCH64_MOVW_UABS_G0_NC:
	290	overflow_check = false;
	291	case R_AARCH64_MOVW_UABS_G0:
	292	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
b24a5575	293	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	294	break;
	295	case R_AARCH64_MOVW_UABS_G1_NC:
	296	overflow_check = false;
	297	case R_AARCH64_MOVW_UABS_G1:
	298	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
b24a5575	299	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	300	break;
	301	case R_AARCH64_MOVW_UABS_G2_NC:
	302	overflow_check = false;
	303	case R_AARCH64_MOVW_UABS_G2:
	304	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
b24a5575	305	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	306	break;
	307	case R_AARCH64_MOVW_UABS_G3:
	308	/* We're using the top bits so we can't overflow. */
	309	overflow_check = false;
	310	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
b24a5575	311	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	312	break;
	313	case R_AARCH64_MOVW_SABS_G0:
	314	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
c84fced8	315	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	316	break;
	317	case R_AARCH64_MOVW_SABS_G1:
	318	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
c84fced8	319	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	320	break;
	321	case R_AARCH64_MOVW_SABS_G2:
	322	ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
c84fced8	323	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	324	break;
	325	case R_AARCH64_MOVW_PREL_G0_NC:
	326	overflow_check = false;
	327	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
b24a5575	328	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	329	break;
	330	case R_AARCH64_MOVW_PREL_G0:
	331	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
c84fced8	332	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	333	break;
	334	case R_AARCH64_MOVW_PREL_G1_NC:
	335	overflow_check = false;
	336	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
b24a5575	337	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	338	break;
	339	case R_AARCH64_MOVW_PREL_G1:
	340	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
c84fced8	341	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	342	break;
	343	case R_AARCH64_MOVW_PREL_G2_NC:
	344	overflow_check = false;
	345	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
b24a5575	346	AARCH64_INSN_IMM_MOVKZ);
257cb251 WD	347	break;
	348	case R_AARCH64_MOVW_PREL_G2:
	349	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
c84fced8	350	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	351	break;
	352	case R_AARCH64_MOVW_PREL_G3:
	353	/* We're using the top bits so we can't overflow. */
	354	overflow_check = false;
	355	ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
c84fced8	356	AARCH64_INSN_IMM_MOVNZ);
257cb251 WD	357	break;
	358
	359	/* Immediate instruction relocations. */
	360	case R_AARCH64_LD_PREL_LO19:
	361	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
c84fced8	362	AARCH64_INSN_IMM_19);
257cb251 WD	363	break;
	364	case R_AARCH64_ADR_PREL_LO21:
	365	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
c84fced8	366	AARCH64_INSN_IMM_ADR);
257cb251 WD	367	break;
	368	case R_AARCH64_ADR_PREL_PG_HI21_NC:
	369	overflow_check = false;
	370	case R_AARCH64_ADR_PREL_PG_HI21:
a257e025 AB	371	ovf = reloc_insn_adrp(me, loc, val);
	372	if (ovf && ovf != -ERANGE)
	373	return ovf;
257cb251 WD	374	break;
	375	case R_AARCH64_ADD_ABS_LO12_NC:
	376	case R_AARCH64_LDST8_ABS_LO12_NC:
	377	overflow_check = false;
	378	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
c84fced8	379	AARCH64_INSN_IMM_12);
257cb251 WD	380	break;
	381	case R_AARCH64_LDST16_ABS_LO12_NC:
	382	overflow_check = false;
	383	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
c84fced8	384	AARCH64_INSN_IMM_12);
257cb251 WD	385	break;
	386	case R_AARCH64_LDST32_ABS_LO12_NC:
	387	overflow_check = false;
	388	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
c84fced8	389	AARCH64_INSN_IMM_12);
257cb251 WD	390	break;
	391	case R_AARCH64_LDST64_ABS_LO12_NC:
	392	overflow_check = false;
	393	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
c84fced8	394	AARCH64_INSN_IMM_12);
257cb251 WD	395	break;
	396	case R_AARCH64_LDST128_ABS_LO12_NC:
	397	overflow_check = false;
	398	ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
c84fced8	399	AARCH64_INSN_IMM_12);
257cb251 WD	400	break;
	401	case R_AARCH64_TSTBR14:
	402	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
c84fced8	403	AARCH64_INSN_IMM_14);
257cb251 WD	404	break;
	405	case R_AARCH64_CONDBR19:
	406	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
c84fced8	407	AARCH64_INSN_IMM_19);
257cb251 WD	408	break;
	409	case R_AARCH64_JUMP26:
	410	case R_AARCH64_CALL26:
	411	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
c84fced8	412	AARCH64_INSN_IMM_26);
fd045f6c AB	413
	414	if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
	415	ovf == -ERANGE) {
24af6c4e	416	val = module_emit_plt_entry(me, loc, &rel[i], sym);
5e8307b9 AB	417	if (!val)
5e8307b9 AB	418	return -ENOEXEC;
fd045f6c AB	419	ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2,
	420	26, AARCH64_INSN_IMM_26);
	421	}
257cb251 WD	422	break;
	423
	424	default:
	425	pr_err("module %s: unsupported RELA relocation: %llu\n",
	426	me->name, ELF64_R_TYPE(rel[i].r_info));
	427	return -ENOEXEC;
	428	}
	429
	430	if (overflow_check && ovf == -ERANGE)
	431	goto overflow;
	432
	433	}
	434
	435	return 0;
	436
	437	overflow:
	438	pr_err("module %s: overflow in relocation type %d val %Lx\n",
	439	me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
	440	return -ENOEXEC;
	441	}
932ded4b AP	442
	443	int module_finalize(const Elf_Ehdr *hdr,
	444	const Elf_Shdr *sechdrs,
	445	struct module *me)
	446	{
	447	const Elf_Shdr s, se;
	448	const char secstrs = (void )hdr + sechdrs[hdr->e_shstrndx].sh_offset;
	449
	450	for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
	451	if (strcmp(".altinstructions", secstrs + s->sh_name) == 0) {
	452	apply_alternatives((void *)s->sh_addr, s->sh_size);
932ded4b	453	}
e71a4e1b AB	454	#ifdef CONFIG_ARM64_MODULE_PLTS
	455	if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) &&
	456	!strcmp(".text.ftrace_trampoline", secstrs + s->sh_name))
	457	me->arch.ftrace_trampoline = (void *)s->sh_addr;
	458	#endif
932ded4b AP	459	}
	460
	461	return 0;
	462	}