Commit | Line | Data |
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9703d9d7 CM |
1 | /* |
2 | * Low-level CPU initialisation | |
3 | * Based on arch/arm/kernel/head.S | |
4 | * | |
5 | * Copyright (C) 1994-2002 Russell King | |
6 | * Copyright (C) 2003-2012 ARM Ltd. | |
7 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
8 | * Will Deacon <will.deacon@arm.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <linux/linkage.h> | |
24 | #include <linux/init.h> | |
021f6537 | 25 | #include <linux/irqchip/arm-gic-v3.h> |
9703d9d7 CM |
26 | |
27 | #include <asm/assembler.h> | |
08cdac61 | 28 | #include <asm/boot.h> |
9703d9d7 CM |
29 | #include <asm/ptrace.h> |
30 | #include <asm/asm-offsets.h> | |
c218bca7 | 31 | #include <asm/cache.h> |
0359b0e2 | 32 | #include <asm/cputype.h> |
1e48ef7f | 33 | #include <asm/elf.h> |
87d1587b | 34 | #include <asm/kernel-pgtable.h> |
1f364c8c | 35 | #include <asm/kvm_arm.h> |
9703d9d7 | 36 | #include <asm/memory.h> |
9703d9d7 CM |
37 | #include <asm/pgtable-hwdef.h> |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/page.h> | |
bb905274 | 40 | #include <asm/smp.h> |
4bf8b96e SP |
41 | #include <asm/sysreg.h> |
42 | #include <asm/thread_info.h> | |
f35a9205 | 43 | #include <asm/virt.h> |
9703d9d7 | 44 | |
b5f4a214 AB |
45 | #include "efi-header.S" |
46 | ||
6f4d57fa | 47 | #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET) |
9703d9d7 | 48 | |
4190312b AB |
49 | #if (TEXT_OFFSET & 0xfff) != 0 |
50 | #error TEXT_OFFSET must be at least 4KB aligned | |
51 | #elif (PAGE_OFFSET & 0x1fffff) != 0 | |
da57a369 | 52 | #error PAGE_OFFSET must be at least 2MB aligned |
4190312b | 53 | #elif TEXT_OFFSET > 0x1fffff |
da57a369 | 54 | #error TEXT_OFFSET must be less than 2MB |
9703d9d7 CM |
55 | #endif |
56 | ||
9703d9d7 CM |
57 | /* |
58 | * Kernel startup entry point. | |
59 | * --------------------------- | |
60 | * | |
61 | * The requirements are: | |
62 | * MMU = off, D-cache = off, I-cache = on or off, | |
63 | * x0 = physical address to the FDT blob. | |
64 | * | |
65 | * This code is mostly position independent so you call this at | |
66 | * __pa(PAGE_OFFSET + TEXT_OFFSET). | |
67 | * | |
68 | * Note that the callee-saved registers are used for storing variables | |
69 | * that are useful before the MMU is enabled. The allocations are described | |
70 | * in the entry routines. | |
71 | */ | |
72 | __HEAD | |
2bf31a4a | 73 | _head: |
9703d9d7 CM |
74 | /* |
75 | * DO NOT MODIFY. Image header expected by Linux boot-loaders. | |
76 | */ | |
3c7f2550 | 77 | #ifdef CONFIG_EFI |
3c7f2550 MS |
78 | /* |
79 | * This add instruction has no meaningful effect except that | |
80 | * its opcode forms the magic "MZ" signature required by UEFI. | |
81 | */ | |
82 | add x13, x18, #0x16 | |
83 | b stext | |
84 | #else | |
9703d9d7 CM |
85 | b stext // branch to kernel start, magic |
86 | .long 0 // reserved | |
3c7f2550 | 87 | #endif |
6ad1fe5d AB |
88 | le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian |
89 | le64sym _kernel_size_le // Effective size of kernel image, little-endian | |
90 | le64sym _kernel_flags_le // Informative flags, little-endian | |
4370eec0 RF |
91 | .quad 0 // reserved |
92 | .quad 0 // reserved | |
93 | .quad 0 // reserved | |
99922257 | 94 | .ascii "ARM\x64" // Magic number |
3c7f2550 | 95 | #ifdef CONFIG_EFI |
2bf31a4a | 96 | .long pe_header - _head // Offset to the PE header. |
3c7f2550 | 97 | |
3c7f2550 | 98 | pe_header: |
b5f4a214 | 99 | __EFI_PE_HEADER |
99922257 AB |
100 | #else |
101 | .long 0 // reserved | |
3c7f2550 | 102 | #endif |
9703d9d7 | 103 | |
546c8c44 AB |
104 | __INIT |
105 | ||
a9be2ee0 AB |
106 | /* |
107 | * The following callee saved general purpose registers are used on the | |
108 | * primary lowlevel boot path: | |
109 | * | |
110 | * Register Scope Purpose | |
111 | * x21 stext() .. start_kernel() FDT pointer passed at boot in x0 | |
112 | * x23 stext() .. start_kernel() physical misalignment/KASLR offset | |
113 | * x28 __create_page_tables() callee preserved temp register | |
114 | * x19/x20 __primary_switch() callee preserved temp registers | |
115 | */ | |
9703d9d7 | 116 | ENTRY(stext) |
da9c177d | 117 | bl preserve_boot_args |
23c8a500 | 118 | bl el2_setup // Drop to EL1, w0=cpu_boot_mode |
b929fe32 AB |
119 | adrp x23, __PHYS_OFFSET |
120 | and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 | |
828e9834 | 121 | bl set_cpu_boot_mode_flag |
aea73abb | 122 | bl __create_page_tables |
9703d9d7 | 123 | /* |
a591ede4 MZ |
124 | * The following calls CPU setup code, see arch/arm64/mm/proc.S for |
125 | * details. | |
9703d9d7 CM |
126 | * On return, the CPU will be ready for the MMU to be turned on and |
127 | * the TCR will have been set. | |
128 | */ | |
0cd3defe | 129 | bl __cpu_setup // initialise processor |
3c5e9f23 | 130 | b __primary_switch |
9703d9d7 CM |
131 | ENDPROC(stext) |
132 | ||
da9c177d AB |
133 | /* |
134 | * Preserve the arguments passed by the bootloader in x0 .. x3 | |
135 | */ | |
136 | preserve_boot_args: | |
137 | mov x21, x0 // x21=FDT | |
138 | ||
139 | adr_l x0, boot_args // record the contents of | |
140 | stp x21, x1, [x0] // x0 .. x3 at kernel entry | |
141 | stp x2, x3, [x0, #16] | |
142 | ||
143 | dmb sy // needed before dc ivac with | |
144 | // MMU off | |
145 | ||
d46befef RM |
146 | mov x1, #0x20 // 4 x 8 bytes |
147 | b __inval_dcache_area // tail call | |
da9c177d AB |
148 | ENDPROC(preserve_boot_args) |
149 | ||
034edabe LA |
150 | /* |
151 | * Macro to create a table entry to the next page. | |
152 | * | |
153 | * tbl: page table address | |
154 | * virt: virtual address | |
155 | * shift: #imm page table shift | |
156 | * ptrs: #imm pointers per table page | |
157 | * | |
158 | * Preserves: virt | |
159 | * Corrupts: tmp1, tmp2 | |
160 | * Returns: tbl -> next level table page address | |
161 | */ | |
162 | .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 | |
163 | lsr \tmp1, \virt, #\shift | |
164 | and \tmp1, \tmp1, #\ptrs - 1 // table index | |
165 | add \tmp2, \tbl, #PAGE_SIZE | |
166 | orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type | |
167 | str \tmp2, [\tbl, \tmp1, lsl #3] | |
168 | add \tbl, \tbl, #PAGE_SIZE // next level table page | |
169 | .endm | |
170 | ||
171 | /* | |
172 | * Macro to populate the PGD (and possibily PUD) for the corresponding | |
173 | * block entry in the next level (tbl) for the given virtual address. | |
174 | * | |
175 | * Preserves: tbl, next, virt | |
176 | * Corrupts: tmp1, tmp2 | |
177 | */ | |
178 | .macro create_pgd_entry, tbl, virt, tmp1, tmp2 | |
179 | create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2 | |
6a3fd402 SP |
180 | #if SWAPPER_PGTABLE_LEVELS > 3 |
181 | create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2 | |
182 | #endif | |
183 | #if SWAPPER_PGTABLE_LEVELS > 2 | |
87d1587b | 184 | create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2 |
034edabe LA |
185 | #endif |
186 | .endm | |
187 | ||
188 | /* | |
189 | * Macro to populate block entries in the page table for the start..end | |
190 | * virtual range (inclusive). | |
191 | * | |
192 | * Preserves: tbl, flags | |
193 | * Corrupts: phys, start, end, pstate | |
194 | */ | |
195 | .macro create_block_map, tbl, flags, phys, start, end | |
87d1587b SP |
196 | lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT |
197 | lsr \start, \start, #SWAPPER_BLOCK_SHIFT | |
034edabe | 198 | and \start, \start, #PTRS_PER_PTE - 1 // table index |
87d1587b SP |
199 | orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry |
200 | lsr \end, \end, #SWAPPER_BLOCK_SHIFT | |
034edabe LA |
201 | and \end, \end, #PTRS_PER_PTE - 1 // table end index |
202 | 9999: str \phys, [\tbl, \start, lsl #3] // store the entry | |
203 | add \start, \start, #1 // next entry | |
87d1587b | 204 | add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block |
034edabe LA |
205 | cmp \start, \end |
206 | b.ls 9999b | |
207 | .endm | |
208 | ||
209 | /* | |
210 | * Setup the initial page tables. We only setup the barest amount which is | |
211 | * required to get the kernel running. The following sections are required: | |
212 | * - identity mapping to enable the MMU (low address, TTBR0) | |
213 | * - first few MB of the kernel linear mapping to jump to once the MMU has | |
61bd93ce | 214 | * been enabled |
034edabe LA |
215 | */ |
216 | __create_page_tables: | |
f80fb3a3 | 217 | mov x28, lr |
034edabe LA |
218 | |
219 | /* | |
220 | * Invalidate the idmap and swapper page tables to avoid potential | |
221 | * dirty cache lines being evicted. | |
222 | */ | |
aea73abb | 223 | adrp x0, idmap_pg_dir |
d46befef RM |
224 | ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) |
225 | bl __inval_dcache_area | |
034edabe LA |
226 | |
227 | /* | |
228 | * Clear the idmap and swapper page tables. | |
229 | */ | |
aea73abb | 230 | adrp x0, idmap_pg_dir |
d46befef | 231 | ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) |
034edabe LA |
232 | 1: stp xzr, xzr, [x0], #16 |
233 | stp xzr, xzr, [x0], #16 | |
234 | stp xzr, xzr, [x0], #16 | |
235 | stp xzr, xzr, [x0], #16 | |
d46befef RM |
236 | subs x1, x1, #64 |
237 | b.ne 1b | |
034edabe | 238 | |
b03cc885 | 239 | mov x7, SWAPPER_MM_MMUFLAGS |
034edabe LA |
240 | |
241 | /* | |
242 | * Create the identity mapping. | |
243 | */ | |
aea73abb | 244 | adrp x0, idmap_pg_dir |
5dfe9d7d | 245 | adrp x3, __idmap_text_start // __pa(__idmap_text_start) |
dd006da2 AB |
246 | |
247 | #ifndef CONFIG_ARM64_VA_BITS_48 | |
248 | #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) | |
249 | #define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT)) | |
250 | ||
251 | /* | |
252 | * If VA_BITS < 48, it may be too small to allow for an ID mapping to be | |
253 | * created that covers system RAM if that is located sufficiently high | |
254 | * in the physical address space. So for the ID map, use an extended | |
255 | * virtual range in that case, by configuring an additional translation | |
256 | * level. | |
257 | * First, we have to verify our assumption that the current value of | |
258 | * VA_BITS was chosen such that all translation levels are fully | |
259 | * utilised, and that lowering T0SZ will always result in an additional | |
260 | * translation level to be configured. | |
261 | */ | |
262 | #if VA_BITS != EXTRA_SHIFT | |
263 | #error "Mismatch between VA_BITS and page size/number of translation levels" | |
264 | #endif | |
265 | ||
266 | /* | |
267 | * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the | |
5dfe9d7d | 268 | * entire ID map region can be mapped. As T0SZ == (64 - #bits used), |
dd006da2 | 269 | * this number conveniently equals the number of leading zeroes in |
5dfe9d7d | 270 | * the physical address of __idmap_text_end. |
dd006da2 | 271 | */ |
5dfe9d7d | 272 | adrp x5, __idmap_text_end |
dd006da2 AB |
273 | clz x5, x5 |
274 | cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? | |
275 | b.ge 1f // .. then skip additional level | |
276 | ||
0c20856c MR |
277 | adr_l x6, idmap_t0sz |
278 | str x5, [x6] | |
279 | dmb sy | |
280 | dc ivac, x6 // Invalidate potentially stale cache line | |
dd006da2 AB |
281 | |
282 | create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6 | |
283 | 1: | |
284 | #endif | |
285 | ||
034edabe | 286 | create_pgd_entry x0, x3, x5, x6 |
5dfe9d7d AB |
287 | mov x5, x3 // __pa(__idmap_text_start) |
288 | adr_l x6, __idmap_text_end // __pa(__idmap_text_end) | |
034edabe LA |
289 | create_block_map x0, x7, x3, x5, x6 |
290 | ||
291 | /* | |
292 | * Map the kernel image (starting with PHYS_OFFSET). | |
293 | */ | |
aea73abb | 294 | adrp x0, swapper_pg_dir |
18b9c0d6 | 295 | mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text) |
f80fb3a3 | 296 | add x5, x5, x23 // add KASLR displacement |
034edabe | 297 | create_pgd_entry x0, x5, x3, x6 |
18b9c0d6 AB |
298 | adrp x6, _end // runtime __pa(_end) |
299 | adrp x3, _text // runtime __pa(_text) | |
300 | sub x6, x6, x3 // _end - _text | |
301 | add x6, x6, x5 // runtime __va(_end) | |
034edabe LA |
302 | create_block_map x0, x7, x3, x5, x6 |
303 | ||
034edabe LA |
304 | /* |
305 | * Since the page tables have been populated with non-cacheable | |
306 | * accesses (MMU disabled), invalidate the idmap and swapper page | |
307 | * tables again to remove any speculatively loaded cache lines. | |
308 | */ | |
aea73abb | 309 | adrp x0, idmap_pg_dir |
d46befef | 310 | ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) |
91d57155 | 311 | dmb sy |
d46befef | 312 | bl __inval_dcache_area |
034edabe | 313 | |
f80fb3a3 | 314 | ret x28 |
034edabe LA |
315 | ENDPROC(__create_page_tables) |
316 | .ltorg | |
317 | ||
034edabe | 318 | /* |
a871d354 | 319 | * The following fragment of code is executed with the MMU enabled. |
b929fe32 AB |
320 | * |
321 | * x0 = __PHYS_OFFSET | |
034edabe | 322 | */ |
0cd3defe | 323 | __primary_switched: |
60699ba1 AB |
324 | adrp x4, init_thread_union |
325 | add sp, x4, #THREAD_SIZE | |
c02433dd MR |
326 | adr_l x5, init_task |
327 | msr sp_el0, x5 // Save thread_info | |
60699ba1 | 328 | |
2bf31a4a AB |
329 | adr_l x8, vectors // load VBAR_EL1 with virtual |
330 | msr vbar_el1, x8 // vector table address | |
331 | isb | |
332 | ||
60699ba1 AB |
333 | stp xzr, x30, [sp, #-16]! |
334 | mov x29, sp | |
335 | ||
b929fe32 AB |
336 | str_l x21, __fdt_pointer, x5 // Save FDT pointer |
337 | ||
338 | ldr_l x4, kimage_vaddr // Save the offset between | |
339 | sub x4, x4, x0 // the kernel virtual and | |
340 | str_l x4, kimage_voffset, x5 // physical mappings | |
341 | ||
2a803c4d MR |
342 | // Clear BSS |
343 | adr_l x0, __bss_start | |
344 | mov x1, xzr | |
345 | adr_l x2, __bss_stop | |
346 | sub x2, x2, x0 | |
347 | bl __pi_memset | |
5227cfa7 | 348 | dsb ishst // Make zero page visible to PTW |
2a803c4d | 349 | |
39d114dd AR |
350 | #ifdef CONFIG_KASAN |
351 | bl kasan_early_init | |
f80fb3a3 AB |
352 | #endif |
353 | #ifdef CONFIG_RANDOMIZE_BASE | |
08cdac61 AB |
354 | tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? |
355 | b.ne 0f | |
f80fb3a3 AB |
356 | mov x0, x21 // pass FDT address in x0 |
357 | bl kaslr_early_init // parse FDT for KASLR options | |
358 | cbz x0, 0f // KASLR disabled? just proceed | |
08cdac61 | 359 | orr x23, x23, x0 // record KASLR offset |
60699ba1 AB |
360 | ldp x29, x30, [sp], #16 // we must enable KASLR, return |
361 | ret // to __primary_switch() | |
f80fb3a3 | 362 | 0: |
39d114dd | 363 | #endif |
73267498 AB |
364 | add sp, sp, #16 |
365 | mov x29, #0 | |
366 | mov x30, #0 | |
034edabe | 367 | b start_kernel |
0cd3defe | 368 | ENDPROC(__primary_switched) |
034edabe LA |
369 | |
370 | /* | |
371 | * end early head section, begin head code that is also used for | |
372 | * hotplug and needs to have the same protections as the text region | |
373 | */ | |
b6113038 | 374 | .section ".idmap.text","ax" |
f80fb3a3 AB |
375 | |
376 | ENTRY(kimage_vaddr) | |
377 | .quad _text - TEXT_OFFSET | |
378 | ||
9703d9d7 CM |
379 | /* |
380 | * If we're fortunate enough to boot at EL2, ensure that the world is | |
381 | * sane before dropping to EL1. | |
828e9834 | 382 | * |
510224c2 | 383 | * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if |
828e9834 | 384 | * booted in EL1 or EL2 respectively. |
9703d9d7 CM |
385 | */ |
386 | ENTRY(el2_setup) | |
5371513f | 387 | msr SPsel, #1 // We want to use SP_EL{1,2} |
9703d9d7 | 388 | mrs x0, CurrentEL |
974c8e45 | 389 | cmp x0, #CurrentEL_EL2 |
3ad47d05 MR |
390 | b.eq 1f |
391 | mrs x0, sctlr_el1 | |
9cf71728 ML |
392 | CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1 |
393 | CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 | |
394 | msr sctlr_el1, x0 | |
23c8a500 | 395 | mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 |
9cf71728 | 396 | isb |
9703d9d7 CM |
397 | ret |
398 | ||
3ad47d05 MR |
399 | 1: mrs x0, sctlr_el2 |
400 | CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2 | |
401 | CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2 | |
402 | msr sctlr_el2, x0 | |
403 | ||
1f364c8c MZ |
404 | #ifdef CONFIG_ARM64_VHE |
405 | /* | |
406 | * Check for VHE being present. For the rest of the EL2 setup, | |
407 | * x2 being non-zero indicates that we do have VHE, and that the | |
408 | * kernel is intended to run at EL2. | |
409 | */ | |
410 | mrs x2, id_aa64mmfr1_el1 | |
411 | ubfx x2, x2, #8, #4 | |
412 | #else | |
413 | mov x2, xzr | |
414 | #endif | |
415 | ||
9703d9d7 | 416 | /* Hyp configuration. */ |
1f364c8c MZ |
417 | mov x0, #HCR_RW // 64-bit EL1 |
418 | cbz x2, set_hcr | |
419 | orr x0, x0, #HCR_TGE // Enable Host Extensions | |
420 | orr x0, x0, #HCR_E2H | |
421 | set_hcr: | |
9703d9d7 | 422 | msr hcr_el2, x0 |
1f364c8c | 423 | isb |
9703d9d7 | 424 | |
1650ac49 J |
425 | /* |
426 | * Allow Non-secure EL1 and EL0 to access physical timer and counter. | |
427 | * This is not necessary for VHE, since the host kernel runs in EL2, | |
428 | * and EL0 accesses are configured in the later stage of boot process. | |
429 | * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout | |
430 | * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined | |
431 | * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1 | |
432 | * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in | |
433 | * EL2. | |
434 | */ | |
435 | cbnz x2, 1f | |
9703d9d7 CM |
436 | mrs x0, cnthctl_el2 |
437 | orr x0, x0, #3 // Enable EL1 physical timers | |
438 | msr cnthctl_el2, x0 | |
1650ac49 | 439 | 1: |
1f75ff0a | 440 | msr cntvoff_el2, xzr // Clear virtual offset |
9703d9d7 | 441 | |
021f6537 MZ |
442 | #ifdef CONFIG_ARM_GIC_V3 |
443 | /* GICv3 system register access */ | |
444 | mrs x0, id_aa64pfr0_el1 | |
445 | ubfx x0, x0, #24, #4 | |
446 | cmp x0, #1 | |
447 | b.ne 3f | |
448 | ||
0e9884fe | 449 | mrs_s x0, SYS_ICC_SRE_EL2 |
021f6537 MZ |
450 | orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 |
451 | orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 | |
0e9884fe | 452 | msr_s SYS_ICC_SRE_EL2, x0 |
021f6537 | 453 | isb // Make sure SRE is now set |
0e9884fe | 454 | mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, |
d271976d | 455 | tbz x0, #0, 3f // and check that it sticks |
0e9884fe | 456 | msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults |
021f6537 MZ |
457 | |
458 | 3: | |
459 | #endif | |
460 | ||
9703d9d7 CM |
461 | /* Populate ID registers. */ |
462 | mrs x0, midr_el1 | |
463 | mrs x1, mpidr_el1 | |
464 | msr vpidr_el2, x0 | |
465 | msr vmpidr_el2, x1 | |
466 | ||
9703d9d7 CM |
467 | #ifdef CONFIG_COMPAT |
468 | msr hstr_el2, xzr // Disable CP15 traps to EL2 | |
469 | #endif | |
470 | ||
d10bcd47 | 471 | /* EL2 debug */ |
2bf47e19 WD |
472 | mrs x1, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer |
473 | sbfx x0, x1, #8, #4 | |
f436b2ac LP |
474 | cmp x0, #1 |
475 | b.lt 4f // Skip if no PMU present | |
d10bcd47 WD |
476 | mrs x0, pmcr_el0 // Disable debug access traps |
477 | ubfx x0, x0, #11, #5 // to EL2 and allow access to | |
f436b2ac | 478 | 4: |
2bf47e19 WD |
479 | csel x3, xzr, x0, lt // all PMU counters from EL1 |
480 | ||
481 | /* Statistical profiling */ | |
482 | ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer | |
483 | cbz x0, 6f // Skip if SPE not present | |
484 | cbnz x2, 5f // VHE? | |
485 | mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) | |
486 | orr x3, x3, x1 // If we don't have VHE, then | |
487 | b 6f // use EL1&0 translation. | |
488 | 5: // For VHE, use EL2 translation | |
489 | orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1 | |
490 | 6: | |
491 | msr mdcr_el2, x3 // Configure debug traps | |
d10bcd47 | 492 | |
7dbfbe5b MZ |
493 | /* Stage-2 translation */ |
494 | msr vttbr_el2, xzr | |
495 | ||
1f364c8c MZ |
496 | cbz x2, install_el2_stub |
497 | ||
23c8a500 | 498 | mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 |
1f364c8c MZ |
499 | isb |
500 | ret | |
501 | ||
502 | install_el2_stub: | |
d61c97a7 MR |
503 | /* |
504 | * When VHE is not in use, early init of EL2 and EL1 needs to be | |
505 | * done here. | |
506 | * When VHE _is_ in use, EL1 will not be used in the host and | |
507 | * requires no configuration, and all non-hyp-specific EL2 setup | |
508 | * will be done via the _EL1 system register aliases in __cpu_setup. | |
509 | */ | |
510 | /* sctlr_el1 */ | |
511 | mov x0, #0x0800 // Set/clear RES{1,0} bits | |
512 | CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems | |
513 | CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems | |
514 | msr sctlr_el1, x0 | |
515 | ||
516 | /* Coprocessor traps. */ | |
517 | mov x0, #0x33ff | |
518 | msr cptr_el2, x0 // Disable copro. traps to EL2 | |
519 | ||
712c6ff4 | 520 | /* Hypervisor stub */ |
9bb00360 | 521 | adr_l x0, __hyp_stub_vectors |
712c6ff4 MZ |
522 | msr vbar_el2, x0 |
523 | ||
9703d9d7 CM |
524 | /* spsr */ |
525 | mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ | |
526 | PSR_MODE_EL1h) | |
527 | msr spsr_el2, x0 | |
528 | msr elr_el2, lr | |
23c8a500 | 529 | mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 |
9703d9d7 CM |
530 | eret |
531 | ENDPROC(el2_setup) | |
532 | ||
828e9834 ML |
533 | /* |
534 | * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed | |
510224c2 | 535 | * in w0. See arch/arm64/include/asm/virt.h for more info. |
828e9834 | 536 | */ |
190c056f | 537 | set_cpu_boot_mode_flag: |
6f4d57fa | 538 | adr_l x1, __boot_cpu_mode |
23c8a500 | 539 | cmp w0, #BOOT_CPU_MODE_EL2 |
828e9834 ML |
540 | b.ne 1f |
541 | add x1, x1, #4 | |
23c8a500 | 542 | 1: str w0, [x1] // This CPU has booted in EL1 |
d0488597 WD |
543 | dmb sy |
544 | dc ivac, x1 // Invalidate potentially stale cache line | |
828e9834 ML |
545 | ret |
546 | ENDPROC(set_cpu_boot_mode_flag) | |
547 | ||
b6113038 JM |
548 | /* |
549 | * These values are written with the MMU off, but read with the MMU on. | |
550 | * Writers will invalidate the corresponding address, discarding up to a | |
551 | * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures | |
552 | * sufficient alignment that the CWG doesn't overlap another section. | |
553 | */ | |
554 | .pushsection ".mmuoff.data.write", "aw" | |
f35a9205 MZ |
555 | /* |
556 | * We need to find out the CPU boot mode long after boot, so we need to | |
557 | * store it in a writable variable. | |
558 | * | |
559 | * This is not in .bss, because we set it sufficiently early that the boot-time | |
560 | * zeroing of .bss would clobber it. | |
561 | */ | |
947bb758 | 562 | ENTRY(__boot_cpu_mode) |
f35a9205 | 563 | .long BOOT_CPU_MODE_EL2 |
424a3838 | 564 | .long BOOT_CPU_MODE_EL1 |
b6113038 JM |
565 | /* |
566 | * The booting CPU updates the failed status @__early_cpu_boot_status, | |
567 | * with MMU turned off. | |
568 | */ | |
569 | ENTRY(__early_cpu_boot_status) | |
570 | .long 0 | |
571 | ||
f35a9205 MZ |
572 | .popsection |
573 | ||
9703d9d7 CM |
574 | /* |
575 | * This provides a "holding pen" for platforms to hold all secondary | |
576 | * cores are held until we're ready for them to initialise. | |
577 | */ | |
578 | ENTRY(secondary_holding_pen) | |
23c8a500 | 579 | bl el2_setup // Drop to EL1, w0=cpu_boot_mode |
828e9834 | 580 | bl set_cpu_boot_mode_flag |
9703d9d7 | 581 | mrs x0, mpidr_el1 |
b03cc885 | 582 | mov_q x1, MPIDR_HWID_BITMASK |
0359b0e2 | 583 | and x0, x0, x1 |
b1c98297 | 584 | adr_l x3, secondary_holding_pen_release |
9703d9d7 CM |
585 | pen: ldr x4, [x3] |
586 | cmp x4, x0 | |
587 | b.eq secondary_startup | |
588 | wfe | |
589 | b pen | |
590 | ENDPROC(secondary_holding_pen) | |
652af899 MR |
591 | |
592 | /* | |
593 | * Secondary entry point that jumps straight into the kernel. Only to | |
594 | * be used where CPUs are brought online dynamically by the kernel. | |
595 | */ | |
596 | ENTRY(secondary_entry) | |
652af899 | 597 | bl el2_setup // Drop to EL1 |
85cc00ea | 598 | bl set_cpu_boot_mode_flag |
652af899 MR |
599 | b secondary_startup |
600 | ENDPROC(secondary_entry) | |
9703d9d7 | 601 | |
190c056f | 602 | secondary_startup: |
9703d9d7 CM |
603 | /* |
604 | * Common entry point for secondary CPUs. | |
605 | */ | |
a591ede4 | 606 | bl __cpu_setup // initialise processor |
9dcf7914 AB |
607 | bl __enable_mmu |
608 | ldr x8, =__secondary_switched | |
609 | br x8 | |
9703d9d7 CM |
610 | ENDPROC(secondary_startup) |
611 | ||
190c056f | 612 | __secondary_switched: |
2bf31a4a AB |
613 | adr_l x5, vectors |
614 | msr vbar_el1, x5 | |
615 | isb | |
616 | ||
bb905274 | 617 | adr_l x0, secondary_data |
c02433dd MR |
618 | ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack |
619 | mov sp, x1 | |
620 | ldr x2, [x0, #CPU_BOOT_TASK] | |
621 | msr sp_el0, x2 | |
9703d9d7 | 622 | mov x29, #0 |
73267498 | 623 | mov x30, #0 |
9703d9d7 CM |
624 | b secondary_start_kernel |
625 | ENDPROC(__secondary_switched) | |
9703d9d7 | 626 | |
bb905274 SP |
627 | /* |
628 | * The booting CPU updates the failed status @__early_cpu_boot_status, | |
629 | * with MMU turned off. | |
630 | * | |
631 | * update_early_cpu_boot_status tmp, status | |
632 | * - Corrupts tmp1, tmp2 | |
633 | * - Writes 'status' to __early_cpu_boot_status and makes sure | |
634 | * it is committed to memory. | |
635 | */ | |
636 | ||
637 | .macro update_early_cpu_boot_status status, tmp1, tmp2 | |
638 | mov \tmp2, #\status | |
adb49070 AB |
639 | adr_l \tmp1, __early_cpu_boot_status |
640 | str \tmp2, [\tmp1] | |
bb905274 SP |
641 | dmb sy |
642 | dc ivac, \tmp1 // Invalidate potentially stale cache line | |
643 | .endm | |
644 | ||
9703d9d7 | 645 | /* |
8b0a9575 | 646 | * Enable the MMU. |
9703d9d7 | 647 | * |
8b0a9575 | 648 | * x0 = SCTLR_EL1 value for turning on the MMU. |
8b0a9575 | 649 | * |
9dcf7914 AB |
650 | * Returns to the caller via x30/lr. This requires the caller to be covered |
651 | * by the .idmap.text section. | |
4bf8b96e SP |
652 | * |
653 | * Checks if the selected granule size is supported by the CPU. | |
654 | * If it isn't, park the CPU | |
9703d9d7 | 655 | */ |
cabe1c81 | 656 | ENTRY(__enable_mmu) |
4bf8b96e SP |
657 | mrs x1, ID_AA64MMFR0_EL1 |
658 | ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4 | |
659 | cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED | |
660 | b.ne __no_granule_support | |
bb905274 | 661 | update_early_cpu_boot_status 0, x1, x2 |
aea73abb AB |
662 | adrp x1, idmap_pg_dir |
663 | adrp x2, swapper_pg_dir | |
664 | msr ttbr0_el1, x1 // load TTBR0 | |
665 | msr ttbr1_el1, x2 // load TTBR1 | |
9703d9d7 | 666 | isb |
9703d9d7 CM |
667 | msr sctlr_el1, x0 |
668 | isb | |
8ec41987 WD |
669 | /* |
670 | * Invalidate the local I-cache so that any instructions fetched | |
671 | * speculatively from the PoC are discarded, since they may have | |
672 | * been dynamically patched at the PoU. | |
673 | */ | |
674 | ic iallu | |
675 | dsb nsh | |
676 | isb | |
9dcf7914 | 677 | ret |
8b0a9575 | 678 | ENDPROC(__enable_mmu) |
4bf8b96e SP |
679 | |
680 | __no_granule_support: | |
bb905274 SP |
681 | /* Indicate that this CPU can't boot and is stuck in the kernel */ |
682 | update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2 | |
683 | 1: | |
4bf8b96e | 684 | wfe |
bb905274 | 685 | wfi |
3c5e9f23 | 686 | b 1b |
4bf8b96e | 687 | ENDPROC(__no_granule_support) |
e5ebeec8 | 688 | |
0cd3defe | 689 | #ifdef CONFIG_RELOCATABLE |
3c5e9f23 | 690 | __relocate_kernel: |
0cd3defe AB |
691 | /* |
692 | * Iterate over each entry in the relocation table, and apply the | |
693 | * relocations in place. | |
694 | */ | |
0cd3defe AB |
695 | ldr w9, =__rela_offset // offset to reloc table |
696 | ldr w10, =__rela_size // size of reloc table | |
697 | ||
b03cc885 | 698 | mov_q x11, KIMAGE_VADDR // default virtual offset |
0cd3defe | 699 | add x11, x11, x23 // actual virtual offset |
0cd3defe AB |
700 | add x9, x9, x11 // __va(.rela) |
701 | add x10, x9, x10 // __va(.rela) + sizeof(.rela) | |
702 | ||
703 | 0: cmp x9, x10 | |
08cc55b2 | 704 | b.hs 1f |
0cd3defe AB |
705 | ldp x11, x12, [x9], #24 |
706 | ldr x13, [x9, #-8] | |
707 | cmp w12, #R_AARCH64_RELATIVE | |
08cc55b2 | 708 | b.ne 0b |
0cd3defe AB |
709 | add x13, x13, x23 // relocate |
710 | str x13, [x11, x23] | |
711 | b 0b | |
3c5e9f23 AB |
712 | 1: ret |
713 | ENDPROC(__relocate_kernel) | |
714 | #endif | |
0cd3defe | 715 | |
3c5e9f23 AB |
716 | __primary_switch: |
717 | #ifdef CONFIG_RANDOMIZE_BASE | |
718 | mov x19, x0 // preserve new SCTLR_EL1 value | |
719 | mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value | |
720 | #endif | |
721 | ||
9dcf7914 | 722 | bl __enable_mmu |
3c5e9f23 AB |
723 | #ifdef CONFIG_RELOCATABLE |
724 | bl __relocate_kernel | |
725 | #ifdef CONFIG_RANDOMIZE_BASE | |
726 | ldr x8, =__primary_switched | |
b929fe32 | 727 | adrp x0, __PHYS_OFFSET |
3c5e9f23 AB |
728 | blr x8 |
729 | ||
730 | /* | |
731 | * If we return here, we have a KASLR displacement in x23 which we need | |
732 | * to take into account by discarding the current kernel mapping and | |
733 | * creating a new one. | |
734 | */ | |
735 | msr sctlr_el1, x20 // disable the MMU | |
736 | isb | |
737 | bl __create_page_tables // recreate kernel mapping | |
738 | ||
739 | tlbi vmalle1 // Remove any stale TLB entries | |
740 | dsb nsh | |
741 | ||
742 | msr sctlr_el1, x19 // re-enable the MMU | |
743 | isb | |
744 | ic iallu // flush instructions fetched | |
745 | dsb nsh // via old mapping | |
746 | isb | |
747 | ||
748 | bl __relocate_kernel | |
749 | #endif | |
0cd3defe AB |
750 | #endif |
751 | ldr x8, =__primary_switched | |
b929fe32 | 752 | adrp x0, __PHYS_OFFSET |
0cd3defe AB |
753 | br x8 |
754 | ENDPROC(__primary_switch) |