Commit | Line | Data |
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9703d9d7 CM |
1 | /* |
2 | * Low-level CPU initialisation | |
3 | * Based on arch/arm/kernel/head.S | |
4 | * | |
5 | * Copyright (C) 1994-2002 Russell King | |
6 | * Copyright (C) 2003-2012 ARM Ltd. | |
7 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
8 | * Will Deacon <will.deacon@arm.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <linux/linkage.h> | |
24 | #include <linux/init.h> | |
021f6537 | 25 | #include <linux/irqchip/arm-gic-v3.h> |
9703d9d7 CM |
26 | |
27 | #include <asm/assembler.h> | |
28 | #include <asm/ptrace.h> | |
29 | #include <asm/asm-offsets.h> | |
c218bca7 | 30 | #include <asm/cache.h> |
0359b0e2 | 31 | #include <asm/cputype.h> |
1e48ef7f | 32 | #include <asm/elf.h> |
87d1587b | 33 | #include <asm/kernel-pgtable.h> |
1f364c8c | 34 | #include <asm/kvm_arm.h> |
9703d9d7 | 35 | #include <asm/memory.h> |
9703d9d7 CM |
36 | #include <asm/pgtable-hwdef.h> |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/page.h> | |
bb905274 | 39 | #include <asm/smp.h> |
4bf8b96e SP |
40 | #include <asm/sysreg.h> |
41 | #include <asm/thread_info.h> | |
f35a9205 | 42 | #include <asm/virt.h> |
9703d9d7 | 43 | |
6f4d57fa | 44 | #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET) |
9703d9d7 | 45 | |
4190312b AB |
46 | #if (TEXT_OFFSET & 0xfff) != 0 |
47 | #error TEXT_OFFSET must be at least 4KB aligned | |
48 | #elif (PAGE_OFFSET & 0x1fffff) != 0 | |
da57a369 | 49 | #error PAGE_OFFSET must be at least 2MB aligned |
4190312b | 50 | #elif TEXT_OFFSET > 0x1fffff |
da57a369 | 51 | #error TEXT_OFFSET must be less than 2MB |
9703d9d7 CM |
52 | #endif |
53 | ||
6f4d57fa | 54 | #define KERNEL_START _text |
9703d9d7 CM |
55 | #define KERNEL_END _end |
56 | ||
9703d9d7 CM |
57 | /* |
58 | * Kernel startup entry point. | |
59 | * --------------------------- | |
60 | * | |
61 | * The requirements are: | |
62 | * MMU = off, D-cache = off, I-cache = on or off, | |
63 | * x0 = physical address to the FDT blob. | |
64 | * | |
65 | * This code is mostly position independent so you call this at | |
66 | * __pa(PAGE_OFFSET + TEXT_OFFSET). | |
67 | * | |
68 | * Note that the callee-saved registers are used for storing variables | |
69 | * that are useful before the MMU is enabled. The allocations are described | |
70 | * in the entry routines. | |
71 | */ | |
72 | __HEAD | |
2bf31a4a | 73 | _head: |
9703d9d7 CM |
74 | /* |
75 | * DO NOT MODIFY. Image header expected by Linux boot-loaders. | |
76 | */ | |
3c7f2550 | 77 | #ifdef CONFIG_EFI |
3c7f2550 MS |
78 | /* |
79 | * This add instruction has no meaningful effect except that | |
80 | * its opcode forms the magic "MZ" signature required by UEFI. | |
81 | */ | |
82 | add x13, x18, #0x16 | |
83 | b stext | |
84 | #else | |
9703d9d7 CM |
85 | b stext // branch to kernel start, magic |
86 | .long 0 // reserved | |
3c7f2550 | 87 | #endif |
6ad1fe5d AB |
88 | le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian |
89 | le64sym _kernel_size_le // Effective size of kernel image, little-endian | |
90 | le64sym _kernel_flags_le // Informative flags, little-endian | |
4370eec0 RF |
91 | .quad 0 // reserved |
92 | .quad 0 // reserved | |
93 | .quad 0 // reserved | |
94 | .byte 0x41 // Magic number, "ARM\x64" | |
95 | .byte 0x52 | |
96 | .byte 0x4d | |
97 | .byte 0x64 | |
3c7f2550 | 98 | #ifdef CONFIG_EFI |
2bf31a4a | 99 | .long pe_header - _head // Offset to the PE header. |
3c7f2550 | 100 | #else |
4370eec0 | 101 | .word 0 // reserved |
3c7f2550 MS |
102 | #endif |
103 | ||
104 | #ifdef CONFIG_EFI | |
105 | .align 3 | |
106 | pe_header: | |
107 | .ascii "PE" | |
108 | .short 0 | |
109 | coff_header: | |
110 | .short 0xaa64 // AArch64 | |
111 | .short 2 // nr_sections | |
112 | .long 0 // TimeDateStamp | |
113 | .long 0 // PointerToSymbolTable | |
114 | .long 1 // NumberOfSymbols | |
115 | .short section_table - optional_header // SizeOfOptionalHeader | |
116 | .short 0x206 // Characteristics. | |
117 | // IMAGE_FILE_DEBUG_STRIPPED | | |
118 | // IMAGE_FILE_EXECUTABLE_IMAGE | | |
119 | // IMAGE_FILE_LINE_NUMS_STRIPPED | |
120 | optional_header: | |
121 | .short 0x20b // PE32+ format | |
122 | .byte 0x02 // MajorLinkerVersion | |
123 | .byte 0x14 // MinorLinkerVersion | |
546c8c44 | 124 | .long _end - efi_header_end // SizeOfCode |
3c7f2550 MS |
125 | .long 0 // SizeOfInitializedData |
126 | .long 0 // SizeOfUninitializedData | |
2bf31a4a | 127 | .long __efistub_entry - _head // AddressOfEntryPoint |
546c8c44 | 128 | .long efi_header_end - _head // BaseOfCode |
3c7f2550 MS |
129 | |
130 | extra_header_fields: | |
131 | .quad 0 // ImageBase | |
ea6bc80d | 132 | .long 0x1000 // SectionAlignment |
a352ea3e | 133 | .long PECOFF_FILE_ALIGNMENT // FileAlignment |
3c7f2550 MS |
134 | .short 0 // MajorOperatingSystemVersion |
135 | .short 0 // MinorOperatingSystemVersion | |
136 | .short 0 // MajorImageVersion | |
137 | .short 0 // MinorImageVersion | |
138 | .short 0 // MajorSubsystemVersion | |
139 | .short 0 // MinorSubsystemVersion | |
140 | .long 0 // Win32VersionValue | |
141 | ||
2bf31a4a | 142 | .long _end - _head // SizeOfImage |
3c7f2550 MS |
143 | |
144 | // Everything before the kernel image is considered part of the header | |
546c8c44 | 145 | .long efi_header_end - _head // SizeOfHeaders |
3c7f2550 MS |
146 | .long 0 // CheckSum |
147 | .short 0xa // Subsystem (EFI application) | |
148 | .short 0 // DllCharacteristics | |
149 | .quad 0 // SizeOfStackReserve | |
150 | .quad 0 // SizeOfStackCommit | |
151 | .quad 0 // SizeOfHeapReserve | |
152 | .quad 0 // SizeOfHeapCommit | |
153 | .long 0 // LoaderFlags | |
154 | .long 0x6 // NumberOfRvaAndSizes | |
155 | ||
156 | .quad 0 // ExportTable | |
157 | .quad 0 // ImportTable | |
158 | .quad 0 // ResourceTable | |
159 | .quad 0 // ExceptionTable | |
160 | .quad 0 // CertificationTable | |
161 | .quad 0 // BaseRelocationTable | |
162 | ||
163 | // Section table | |
164 | section_table: | |
165 | ||
166 | /* | |
167 | * The EFI application loader requires a relocation section | |
168 | * because EFI applications must be relocatable. This is a | |
169 | * dummy section as far as we are concerned. | |
170 | */ | |
171 | .ascii ".reloc" | |
172 | .byte 0 | |
173 | .byte 0 // end of 0 padding of section name | |
174 | .long 0 | |
175 | .long 0 | |
176 | .long 0 // SizeOfRawData | |
177 | .long 0 // PointerToRawData | |
178 | .long 0 // PointerToRelocations | |
179 | .long 0 // PointerToLineNumbers | |
180 | .short 0 // NumberOfRelocations | |
181 | .short 0 // NumberOfLineNumbers | |
182 | .long 0x42100040 // Characteristics (section flags) | |
183 | ||
184 | ||
185 | .ascii ".text" | |
186 | .byte 0 | |
187 | .byte 0 | |
188 | .byte 0 // end of 0 padding of section name | |
546c8c44 AB |
189 | .long _end - efi_header_end // VirtualSize |
190 | .long efi_header_end - _head // VirtualAddress | |
191 | .long _edata - efi_header_end // SizeOfRawData | |
192 | .long efi_header_end - _head // PointerToRawData | |
3c7f2550 MS |
193 | |
194 | .long 0 // PointerToRelocations (0 for executables) | |
195 | .long 0 // PointerToLineNumbers (0 for executables) | |
196 | .short 0 // NumberOfRelocations (0 for executables) | |
197 | .short 0 // NumberOfLineNumbers (0 for executables) | |
198 | .long 0xe0500020 // Characteristics (section flags) | |
ea6bc80d AB |
199 | |
200 | /* | |
546c8c44 | 201 | * EFI will load .text onwards at the 4k section alignment |
ea6bc80d AB |
202 | * described in the PE/COFF header. To ensure that instruction |
203 | * sequences using an adrp and a :lo12: immediate will function | |
546c8c44 | 204 | * correctly at this alignment, we must ensure that .text is |
ea6bc80d AB |
205 | * placed at a 4k boundary in the Image to begin with. |
206 | */ | |
207 | .align 12 | |
546c8c44 | 208 | efi_header_end: |
3c7f2550 | 209 | #endif |
9703d9d7 | 210 | |
546c8c44 AB |
211 | __INIT |
212 | ||
9703d9d7 | 213 | ENTRY(stext) |
da9c177d | 214 | bl preserve_boot_args |
828e9834 | 215 | bl el2_setup // Drop to EL1, w20=cpu_boot_mode |
f80fb3a3 | 216 | mov x23, xzr // KASLR offset, defaults to 0 |
6f4d57fa | 217 | adrp x24, __PHYS_OFFSET |
828e9834 | 218 | bl set_cpu_boot_mode_flag |
9703d9d7 CM |
219 | bl __create_page_tables // x25=TTBR0, x26=TTBR1 |
220 | /* | |
a591ede4 MZ |
221 | * The following calls CPU setup code, see arch/arm64/mm/proc.S for |
222 | * details. | |
9703d9d7 CM |
223 | * On return, the CPU will be ready for the MMU to be turned on and |
224 | * the TCR will have been set. | |
225 | */ | |
0cd3defe AB |
226 | bl __cpu_setup // initialise processor |
227 | adr_l x27, __primary_switch // address to jump to after | |
228 | // MMU has been enabled | |
229 | b __enable_mmu | |
9703d9d7 CM |
230 | ENDPROC(stext) |
231 | ||
da9c177d AB |
232 | /* |
233 | * Preserve the arguments passed by the bootloader in x0 .. x3 | |
234 | */ | |
235 | preserve_boot_args: | |
236 | mov x21, x0 // x21=FDT | |
237 | ||
238 | adr_l x0, boot_args // record the contents of | |
239 | stp x21, x1, [x0] // x0 .. x3 at kernel entry | |
240 | stp x2, x3, [x0, #16] | |
241 | ||
242 | dmb sy // needed before dc ivac with | |
243 | // MMU off | |
244 | ||
245 | add x1, x0, #0x20 // 4 x 8 bytes | |
246 | b __inval_cache_range // tail call | |
247 | ENDPROC(preserve_boot_args) | |
248 | ||
034edabe LA |
249 | /* |
250 | * Macro to create a table entry to the next page. | |
251 | * | |
252 | * tbl: page table address | |
253 | * virt: virtual address | |
254 | * shift: #imm page table shift | |
255 | * ptrs: #imm pointers per table page | |
256 | * | |
257 | * Preserves: virt | |
258 | * Corrupts: tmp1, tmp2 | |
259 | * Returns: tbl -> next level table page address | |
260 | */ | |
261 | .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 | |
262 | lsr \tmp1, \virt, #\shift | |
263 | and \tmp1, \tmp1, #\ptrs - 1 // table index | |
264 | add \tmp2, \tbl, #PAGE_SIZE | |
265 | orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type | |
266 | str \tmp2, [\tbl, \tmp1, lsl #3] | |
267 | add \tbl, \tbl, #PAGE_SIZE // next level table page | |
268 | .endm | |
269 | ||
270 | /* | |
271 | * Macro to populate the PGD (and possibily PUD) for the corresponding | |
272 | * block entry in the next level (tbl) for the given virtual address. | |
273 | * | |
274 | * Preserves: tbl, next, virt | |
275 | * Corrupts: tmp1, tmp2 | |
276 | */ | |
277 | .macro create_pgd_entry, tbl, virt, tmp1, tmp2 | |
278 | create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2 | |
6a3fd402 SP |
279 | #if SWAPPER_PGTABLE_LEVELS > 3 |
280 | create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2 | |
281 | #endif | |
282 | #if SWAPPER_PGTABLE_LEVELS > 2 | |
87d1587b | 283 | create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2 |
034edabe LA |
284 | #endif |
285 | .endm | |
286 | ||
287 | /* | |
288 | * Macro to populate block entries in the page table for the start..end | |
289 | * virtual range (inclusive). | |
290 | * | |
291 | * Preserves: tbl, flags | |
292 | * Corrupts: phys, start, end, pstate | |
293 | */ | |
294 | .macro create_block_map, tbl, flags, phys, start, end | |
87d1587b SP |
295 | lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT |
296 | lsr \start, \start, #SWAPPER_BLOCK_SHIFT | |
034edabe | 297 | and \start, \start, #PTRS_PER_PTE - 1 // table index |
87d1587b SP |
298 | orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry |
299 | lsr \end, \end, #SWAPPER_BLOCK_SHIFT | |
034edabe LA |
300 | and \end, \end, #PTRS_PER_PTE - 1 // table end index |
301 | 9999: str \phys, [\tbl, \start, lsl #3] // store the entry | |
302 | add \start, \start, #1 // next entry | |
87d1587b | 303 | add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block |
034edabe LA |
304 | cmp \start, \end |
305 | b.ls 9999b | |
306 | .endm | |
307 | ||
308 | /* | |
309 | * Setup the initial page tables. We only setup the barest amount which is | |
310 | * required to get the kernel running. The following sections are required: | |
311 | * - identity mapping to enable the MMU (low address, TTBR0) | |
312 | * - first few MB of the kernel linear mapping to jump to once the MMU has | |
61bd93ce | 313 | * been enabled |
034edabe LA |
314 | */ |
315 | __create_page_tables: | |
6f4d57fa AB |
316 | adrp x25, idmap_pg_dir |
317 | adrp x26, swapper_pg_dir | |
f80fb3a3 | 318 | mov x28, lr |
034edabe LA |
319 | |
320 | /* | |
321 | * Invalidate the idmap and swapper page tables to avoid potential | |
322 | * dirty cache lines being evicted. | |
323 | */ | |
324 | mov x0, x25 | |
325 | add x1, x26, #SWAPPER_DIR_SIZE | |
326 | bl __inval_cache_range | |
327 | ||
328 | /* | |
329 | * Clear the idmap and swapper page tables. | |
330 | */ | |
331 | mov x0, x25 | |
332 | add x6, x26, #SWAPPER_DIR_SIZE | |
333 | 1: stp xzr, xzr, [x0], #16 | |
334 | stp xzr, xzr, [x0], #16 | |
335 | stp xzr, xzr, [x0], #16 | |
336 | stp xzr, xzr, [x0], #16 | |
337 | cmp x0, x6 | |
338 | b.lo 1b | |
339 | ||
b03cc885 | 340 | mov x7, SWAPPER_MM_MMUFLAGS |
034edabe LA |
341 | |
342 | /* | |
343 | * Create the identity mapping. | |
344 | */ | |
345 | mov x0, x25 // idmap_pg_dir | |
5dfe9d7d | 346 | adrp x3, __idmap_text_start // __pa(__idmap_text_start) |
dd006da2 AB |
347 | |
348 | #ifndef CONFIG_ARM64_VA_BITS_48 | |
349 | #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) | |
350 | #define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT)) | |
351 | ||
352 | /* | |
353 | * If VA_BITS < 48, it may be too small to allow for an ID mapping to be | |
354 | * created that covers system RAM if that is located sufficiently high | |
355 | * in the physical address space. So for the ID map, use an extended | |
356 | * virtual range in that case, by configuring an additional translation | |
357 | * level. | |
358 | * First, we have to verify our assumption that the current value of | |
359 | * VA_BITS was chosen such that all translation levels are fully | |
360 | * utilised, and that lowering T0SZ will always result in an additional | |
361 | * translation level to be configured. | |
362 | */ | |
363 | #if VA_BITS != EXTRA_SHIFT | |
364 | #error "Mismatch between VA_BITS and page size/number of translation levels" | |
365 | #endif | |
366 | ||
367 | /* | |
368 | * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the | |
5dfe9d7d | 369 | * entire ID map region can be mapped. As T0SZ == (64 - #bits used), |
dd006da2 | 370 | * this number conveniently equals the number of leading zeroes in |
5dfe9d7d | 371 | * the physical address of __idmap_text_end. |
dd006da2 | 372 | */ |
5dfe9d7d | 373 | adrp x5, __idmap_text_end |
dd006da2 AB |
374 | clz x5, x5 |
375 | cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? | |
376 | b.ge 1f // .. then skip additional level | |
377 | ||
0c20856c MR |
378 | adr_l x6, idmap_t0sz |
379 | str x5, [x6] | |
380 | dmb sy | |
381 | dc ivac, x6 // Invalidate potentially stale cache line | |
dd006da2 AB |
382 | |
383 | create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6 | |
384 | 1: | |
385 | #endif | |
386 | ||
034edabe | 387 | create_pgd_entry x0, x3, x5, x6 |
5dfe9d7d AB |
388 | mov x5, x3 // __pa(__idmap_text_start) |
389 | adr_l x6, __idmap_text_end // __pa(__idmap_text_end) | |
034edabe LA |
390 | create_block_map x0, x7, x3, x5, x6 |
391 | ||
392 | /* | |
393 | * Map the kernel image (starting with PHYS_OFFSET). | |
394 | */ | |
395 | mov x0, x26 // swapper_pg_dir | |
18b9c0d6 | 396 | mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text) |
f80fb3a3 | 397 | add x5, x5, x23 // add KASLR displacement |
034edabe | 398 | create_pgd_entry x0, x5, x3, x6 |
18b9c0d6 AB |
399 | adrp x6, _end // runtime __pa(_end) |
400 | adrp x3, _text // runtime __pa(_text) | |
401 | sub x6, x6, x3 // _end - _text | |
402 | add x6, x6, x5 // runtime __va(_end) | |
034edabe LA |
403 | create_block_map x0, x7, x3, x5, x6 |
404 | ||
034edabe LA |
405 | /* |
406 | * Since the page tables have been populated with non-cacheable | |
407 | * accesses (MMU disabled), invalidate the idmap and swapper page | |
408 | * tables again to remove any speculatively loaded cache lines. | |
409 | */ | |
410 | mov x0, x25 | |
411 | add x1, x26, #SWAPPER_DIR_SIZE | |
91d57155 | 412 | dmb sy |
034edabe LA |
413 | bl __inval_cache_range |
414 | ||
f80fb3a3 | 415 | ret x28 |
034edabe LA |
416 | ENDPROC(__create_page_tables) |
417 | .ltorg | |
418 | ||
034edabe | 419 | /* |
a871d354 | 420 | * The following fragment of code is executed with the MMU enabled. |
034edabe | 421 | */ |
a871d354 | 422 | .set initial_sp, init_thread_union + THREAD_START_SP |
0cd3defe | 423 | __primary_switched: |
f80fb3a3 | 424 | mov x28, lr // preserve LR |
2bf31a4a AB |
425 | adr_l x8, vectors // load VBAR_EL1 with virtual |
426 | msr vbar_el1, x8 // vector table address | |
427 | isb | |
428 | ||
2a803c4d MR |
429 | // Clear BSS |
430 | adr_l x0, __bss_start | |
431 | mov x1, xzr | |
432 | adr_l x2, __bss_stop | |
433 | sub x2, x2, x0 | |
434 | bl __pi_memset | |
5227cfa7 | 435 | dsb ishst // Make zero page visible to PTW |
2a803c4d | 436 | |
a871d354 | 437 | adr_l sp, initial_sp, x4 |
6cdf9c7c JL |
438 | mov x4, sp |
439 | and x4, x4, #~(THREAD_SIZE - 1) | |
440 | msr sp_el0, x4 // Save thread_info | |
a871d354 | 441 | str_l x21, __fdt_pointer, x5 // Save FDT pointer |
a7f8de16 | 442 | |
f80fb3a3 | 443 | ldr_l x4, kimage_vaddr // Save the offset between |
a7f8de16 AB |
444 | sub x4, x4, x24 // the kernel virtual and |
445 | str_l x4, kimage_voffset, x5 // physical mappings | |
446 | ||
034edabe | 447 | mov x29, #0 |
39d114dd AR |
448 | #ifdef CONFIG_KASAN |
449 | bl kasan_early_init | |
f80fb3a3 AB |
450 | #endif |
451 | #ifdef CONFIG_RANDOMIZE_BASE | |
452 | cbnz x23, 0f // already running randomized? | |
453 | mov x0, x21 // pass FDT address in x0 | |
454 | bl kaslr_early_init // parse FDT for KASLR options | |
455 | cbz x0, 0f // KASLR disabled? just proceed | |
456 | mov x23, x0 // record KASLR offset | |
457 | ret x28 // we must enable KASLR, return | |
458 | // to __enable_mmu() | |
459 | 0: | |
39d114dd | 460 | #endif |
034edabe | 461 | b start_kernel |
0cd3defe | 462 | ENDPROC(__primary_switched) |
034edabe LA |
463 | |
464 | /* | |
465 | * end early head section, begin head code that is also used for | |
466 | * hotplug and needs to have the same protections as the text region | |
467 | */ | |
468 | .section ".text","ax" | |
f80fb3a3 AB |
469 | |
470 | ENTRY(kimage_vaddr) | |
471 | .quad _text - TEXT_OFFSET | |
472 | ||
9703d9d7 CM |
473 | /* |
474 | * If we're fortunate enough to boot at EL2, ensure that the world is | |
475 | * sane before dropping to EL1. | |
828e9834 ML |
476 | * |
477 | * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if | |
478 | * booted in EL1 or EL2 respectively. | |
9703d9d7 CM |
479 | */ |
480 | ENTRY(el2_setup) | |
481 | mrs x0, CurrentEL | |
974c8e45 | 482 | cmp x0, #CurrentEL_EL2 |
9cf71728 ML |
483 | b.ne 1f |
484 | mrs x0, sctlr_el2 | |
485 | CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2 | |
486 | CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2 | |
487 | msr sctlr_el2, x0 | |
488 | b 2f | |
489 | 1: mrs x0, sctlr_el1 | |
490 | CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1 | |
491 | CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 | |
492 | msr sctlr_el1, x0 | |
828e9834 | 493 | mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 |
9cf71728 | 494 | isb |
9703d9d7 CM |
495 | ret |
496 | ||
1f364c8c MZ |
497 | 2: |
498 | #ifdef CONFIG_ARM64_VHE | |
499 | /* | |
500 | * Check for VHE being present. For the rest of the EL2 setup, | |
501 | * x2 being non-zero indicates that we do have VHE, and that the | |
502 | * kernel is intended to run at EL2. | |
503 | */ | |
504 | mrs x2, id_aa64mmfr1_el1 | |
505 | ubfx x2, x2, #8, #4 | |
506 | #else | |
507 | mov x2, xzr | |
508 | #endif | |
509 | ||
9703d9d7 | 510 | /* Hyp configuration. */ |
1f364c8c MZ |
511 | mov x0, #HCR_RW // 64-bit EL1 |
512 | cbz x2, set_hcr | |
513 | orr x0, x0, #HCR_TGE // Enable Host Extensions | |
514 | orr x0, x0, #HCR_E2H | |
515 | set_hcr: | |
9703d9d7 | 516 | msr hcr_el2, x0 |
1f364c8c | 517 | isb |
9703d9d7 CM |
518 | |
519 | /* Generic timers. */ | |
520 | mrs x0, cnthctl_el2 | |
521 | orr x0, x0, #3 // Enable EL1 physical timers | |
522 | msr cnthctl_el2, x0 | |
1f75ff0a | 523 | msr cntvoff_el2, xzr // Clear virtual offset |
9703d9d7 | 524 | |
021f6537 MZ |
525 | #ifdef CONFIG_ARM_GIC_V3 |
526 | /* GICv3 system register access */ | |
527 | mrs x0, id_aa64pfr0_el1 | |
528 | ubfx x0, x0, #24, #4 | |
529 | cmp x0, #1 | |
530 | b.ne 3f | |
531 | ||
72c58395 | 532 | mrs_s x0, ICC_SRE_EL2 |
021f6537 MZ |
533 | orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 |
534 | orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 | |
72c58395 | 535 | msr_s ICC_SRE_EL2, x0 |
021f6537 | 536 | isb // Make sure SRE is now set |
d271976d MZ |
537 | mrs_s x0, ICC_SRE_EL2 // Read SRE back, |
538 | tbz x0, #0, 3f // and check that it sticks | |
72c58395 | 539 | msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults |
021f6537 MZ |
540 | |
541 | 3: | |
542 | #endif | |
543 | ||
9703d9d7 CM |
544 | /* Populate ID registers. */ |
545 | mrs x0, midr_el1 | |
546 | mrs x1, mpidr_el1 | |
547 | msr vpidr_el2, x0 | |
548 | msr vmpidr_el2, x1 | |
549 | ||
550 | /* sctlr_el1 */ | |
551 | mov x0, #0x0800 // Set/clear RES{1,0} bits | |
9cf71728 ML |
552 | CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems |
553 | CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems | |
9703d9d7 CM |
554 | msr sctlr_el1, x0 |
555 | ||
556 | /* Coprocessor traps. */ | |
557 | mov x0, #0x33ff | |
558 | msr cptr_el2, x0 // Disable copro. traps to EL2 | |
559 | ||
560 | #ifdef CONFIG_COMPAT | |
561 | msr hstr_el2, xzr // Disable CP15 traps to EL2 | |
562 | #endif | |
563 | ||
d10bcd47 | 564 | /* EL2 debug */ |
f436b2ac LP |
565 | mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer |
566 | sbfx x0, x0, #8, #4 | |
567 | cmp x0, #1 | |
568 | b.lt 4f // Skip if no PMU present | |
d10bcd47 WD |
569 | mrs x0, pmcr_el0 // Disable debug access traps |
570 | ubfx x0, x0, #11, #5 // to EL2 and allow access to | |
571 | msr mdcr_el2, x0 // all PMU counters from EL1 | |
f436b2ac | 572 | 4: |
d10bcd47 | 573 | |
7dbfbe5b MZ |
574 | /* Stage-2 translation */ |
575 | msr vttbr_el2, xzr | |
576 | ||
1f364c8c MZ |
577 | cbz x2, install_el2_stub |
578 | ||
579 | mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 | |
580 | isb | |
581 | ret | |
582 | ||
583 | install_el2_stub: | |
712c6ff4 | 584 | /* Hypervisor stub */ |
ac2dec5f LA |
585 | adrp x0, __hyp_stub_vectors |
586 | add x0, x0, #:lo12:__hyp_stub_vectors | |
712c6ff4 MZ |
587 | msr vbar_el2, x0 |
588 | ||
9703d9d7 CM |
589 | /* spsr */ |
590 | mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ | |
591 | PSR_MODE_EL1h) | |
592 | msr spsr_el2, x0 | |
593 | msr elr_el2, lr | |
828e9834 | 594 | mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 |
9703d9d7 CM |
595 | eret |
596 | ENDPROC(el2_setup) | |
597 | ||
828e9834 ML |
598 | /* |
599 | * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed | |
600 | * in x20. See arch/arm64/include/asm/virt.h for more info. | |
601 | */ | |
190c056f | 602 | set_cpu_boot_mode_flag: |
6f4d57fa | 603 | adr_l x1, __boot_cpu_mode |
828e9834 ML |
604 | cmp w20, #BOOT_CPU_MODE_EL2 |
605 | b.ne 1f | |
606 | add x1, x1, #4 | |
d0488597 WD |
607 | 1: str w20, [x1] // This CPU has booted in EL1 |
608 | dmb sy | |
609 | dc ivac, x1 // Invalidate potentially stale cache line | |
828e9834 ML |
610 | ret |
611 | ENDPROC(set_cpu_boot_mode_flag) | |
612 | ||
f35a9205 MZ |
613 | /* |
614 | * We need to find out the CPU boot mode long after boot, so we need to | |
615 | * store it in a writable variable. | |
616 | * | |
617 | * This is not in .bss, because we set it sufficiently early that the boot-time | |
618 | * zeroing of .bss would clobber it. | |
619 | */ | |
c218bca7 | 620 | .pushsection .data..cacheline_aligned |
c218bca7 | 621 | .align L1_CACHE_SHIFT |
947bb758 | 622 | ENTRY(__boot_cpu_mode) |
f35a9205 | 623 | .long BOOT_CPU_MODE_EL2 |
424a3838 | 624 | .long BOOT_CPU_MODE_EL1 |
f35a9205 MZ |
625 | .popsection |
626 | ||
9703d9d7 CM |
627 | /* |
628 | * This provides a "holding pen" for platforms to hold all secondary | |
629 | * cores are held until we're ready for them to initialise. | |
630 | */ | |
631 | ENTRY(secondary_holding_pen) | |
828e9834 | 632 | bl el2_setup // Drop to EL1, w20=cpu_boot_mode |
828e9834 | 633 | bl set_cpu_boot_mode_flag |
9703d9d7 | 634 | mrs x0, mpidr_el1 |
b03cc885 | 635 | mov_q x1, MPIDR_HWID_BITMASK |
0359b0e2 | 636 | and x0, x0, x1 |
b1c98297 | 637 | adr_l x3, secondary_holding_pen_release |
9703d9d7 CM |
638 | pen: ldr x4, [x3] |
639 | cmp x4, x0 | |
640 | b.eq secondary_startup | |
641 | wfe | |
642 | b pen | |
643 | ENDPROC(secondary_holding_pen) | |
652af899 MR |
644 | |
645 | /* | |
646 | * Secondary entry point that jumps straight into the kernel. Only to | |
647 | * be used where CPUs are brought online dynamically by the kernel. | |
648 | */ | |
649 | ENTRY(secondary_entry) | |
652af899 | 650 | bl el2_setup // Drop to EL1 |
85cc00ea | 651 | bl set_cpu_boot_mode_flag |
652af899 MR |
652 | b secondary_startup |
653 | ENDPROC(secondary_entry) | |
9703d9d7 | 654 | |
190c056f | 655 | secondary_startup: |
9703d9d7 CM |
656 | /* |
657 | * Common entry point for secondary CPUs. | |
658 | */ | |
6f4d57fa AB |
659 | adrp x25, idmap_pg_dir |
660 | adrp x26, swapper_pg_dir | |
a591ede4 | 661 | bl __cpu_setup // initialise processor |
9703d9d7 | 662 | |
e5ebeec8 | 663 | adr_l x27, __secondary_switch // address to jump to after enabling the MMU |
9703d9d7 CM |
664 | b __enable_mmu |
665 | ENDPROC(secondary_startup) | |
666 | ||
190c056f | 667 | __secondary_switched: |
2bf31a4a AB |
668 | adr_l x5, vectors |
669 | msr vbar_el1, x5 | |
670 | isb | |
671 | ||
bb905274 SP |
672 | adr_l x0, secondary_data |
673 | ldr x0, [x0, #CPU_BOOT_STACK] // get secondary_data.stack | |
9703d9d7 | 674 | mov sp, x0 |
6cdf9c7c JL |
675 | and x0, x0, #~(THREAD_SIZE - 1) |
676 | msr sp_el0, x0 // save thread_info | |
9703d9d7 CM |
677 | mov x29, #0 |
678 | b secondary_start_kernel | |
679 | ENDPROC(__secondary_switched) | |
9703d9d7 | 680 | |
bb905274 SP |
681 | /* |
682 | * The booting CPU updates the failed status @__early_cpu_boot_status, | |
683 | * with MMU turned off. | |
684 | * | |
685 | * update_early_cpu_boot_status tmp, status | |
686 | * - Corrupts tmp1, tmp2 | |
687 | * - Writes 'status' to __early_cpu_boot_status and makes sure | |
688 | * it is committed to memory. | |
689 | */ | |
690 | ||
691 | .macro update_early_cpu_boot_status status, tmp1, tmp2 | |
692 | mov \tmp2, #\status | |
693 | str_l \tmp2, __early_cpu_boot_status, \tmp1 | |
694 | dmb sy | |
695 | dc ivac, \tmp1 // Invalidate potentially stale cache line | |
696 | .endm | |
697 | ||
698 | .pushsection .data..cacheline_aligned | |
699 | .align L1_CACHE_SHIFT | |
700 | ENTRY(__early_cpu_boot_status) | |
701 | .long 0 | |
702 | .popsection | |
703 | ||
9703d9d7 | 704 | /* |
8b0a9575 | 705 | * Enable the MMU. |
9703d9d7 | 706 | * |
8b0a9575 AB |
707 | * x0 = SCTLR_EL1 value for turning on the MMU. |
708 | * x27 = *virtual* address to jump to upon completion | |
709 | * | |
4bf8b96e SP |
710 | * Other registers depend on the function called upon completion. |
711 | * | |
712 | * Checks if the selected granule size is supported by the CPU. | |
713 | * If it isn't, park the CPU | |
9703d9d7 | 714 | */ |
5dfe9d7d | 715 | .section ".idmap.text", "ax" |
9703d9d7 | 716 | __enable_mmu: |
d5e57437 | 717 | mrs x22, sctlr_el1 // preserve old SCTLR_EL1 value |
4bf8b96e SP |
718 | mrs x1, ID_AA64MMFR0_EL1 |
719 | ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4 | |
720 | cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED | |
721 | b.ne __no_granule_support | |
bb905274 | 722 | update_early_cpu_boot_status 0, x1, x2 |
9703d9d7 CM |
723 | msr ttbr0_el1, x25 // load TTBR0 |
724 | msr ttbr1_el1, x26 // load TTBR1 | |
725 | isb | |
9703d9d7 CM |
726 | msr sctlr_el1, x0 |
727 | isb | |
8ec41987 WD |
728 | /* |
729 | * Invalidate the local I-cache so that any instructions fetched | |
730 | * speculatively from the PoC are discarded, since they may have | |
731 | * been dynamically patched at the PoU. | |
732 | */ | |
733 | ic iallu | |
734 | dsb nsh | |
735 | isb | |
f80fb3a3 AB |
736 | #ifdef CONFIG_RANDOMIZE_BASE |
737 | mov x19, x0 // preserve new SCTLR_EL1 value | |
738 | blr x27 | |
739 | ||
740 | /* | |
741 | * If we return here, we have a KASLR displacement in x23 which we need | |
742 | * to take into account by discarding the current kernel mapping and | |
743 | * creating a new one. | |
744 | */ | |
d5e57437 | 745 | msr sctlr_el1, x22 // disable the MMU |
f80fb3a3 AB |
746 | isb |
747 | bl __create_page_tables // recreate kernel mapping | |
748 | ||
749 | msr sctlr_el1, x19 // re-enable the MMU | |
750 | isb | |
b90b4a60 MR |
751 | ic iallu // flush instructions fetched |
752 | dsb nsh // via old mapping | |
753 | isb | |
f80fb3a3 | 754 | #endif |
9703d9d7 | 755 | br x27 |
8b0a9575 | 756 | ENDPROC(__enable_mmu) |
4bf8b96e SP |
757 | |
758 | __no_granule_support: | |
bb905274 SP |
759 | /* Indicate that this CPU can't boot and is stuck in the kernel */ |
760 | update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2 | |
761 | 1: | |
4bf8b96e | 762 | wfe |
bb905274 SP |
763 | wfi |
764 | b 1b | |
4bf8b96e | 765 | ENDPROC(__no_granule_support) |
e5ebeec8 | 766 | |
0cd3defe AB |
767 | __primary_switch: |
768 | #ifdef CONFIG_RELOCATABLE | |
769 | /* | |
770 | * Iterate over each entry in the relocation table, and apply the | |
771 | * relocations in place. | |
772 | */ | |
773 | ldr w8, =__dynsym_offset // offset to symbol table | |
774 | ldr w9, =__rela_offset // offset to reloc table | |
775 | ldr w10, =__rela_size // size of reloc table | |
776 | ||
b03cc885 | 777 | mov_q x11, KIMAGE_VADDR // default virtual offset |
0cd3defe AB |
778 | add x11, x11, x23 // actual virtual offset |
779 | add x8, x8, x11 // __va(.dynsym) | |
780 | add x9, x9, x11 // __va(.rela) | |
781 | add x10, x9, x10 // __va(.rela) + sizeof(.rela) | |
782 | ||
783 | 0: cmp x9, x10 | |
784 | b.hs 2f | |
785 | ldp x11, x12, [x9], #24 | |
786 | ldr x13, [x9, #-8] | |
787 | cmp w12, #R_AARCH64_RELATIVE | |
788 | b.ne 1f | |
789 | add x13, x13, x23 // relocate | |
790 | str x13, [x11, x23] | |
791 | b 0b | |
792 | ||
793 | 1: cmp w12, #R_AARCH64_ABS64 | |
794 | b.ne 0b | |
795 | add x12, x12, x12, lsl #1 // symtab offset: 24x top word | |
796 | add x12, x8, x12, lsr #(32 - 3) // ... shifted into bottom word | |
797 | ldrsh w14, [x12, #6] // Elf64_Sym::st_shndx | |
798 | ldr x15, [x12, #8] // Elf64_Sym::st_value | |
799 | cmp w14, #-0xf // SHN_ABS (0xfff1) ? | |
800 | add x14, x15, x23 // relocate | |
801 | csel x15, x14, x15, ne | |
802 | add x15, x13, x15 | |
803 | str x15, [x11, x23] | |
804 | b 0b | |
805 | ||
806 | 2: | |
807 | #endif | |
808 | ldr x8, =__primary_switched | |
809 | br x8 | |
810 | ENDPROC(__primary_switch) | |
811 | ||
e5ebeec8 AB |
812 | __secondary_switch: |
813 | ldr x8, =__secondary_switched | |
814 | br x8 | |
815 | ENDPROC(__secondary_switch) |