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53631b54 CM |
1 | /* |
2 | * FP/SIMD context switching and fault handling | |
3 | * | |
4 | * Copyright (C) 2012 ARM Ltd. | |
5 | * Author: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
7582e220 | 20 | #include <linux/bitmap.h> |
cb84d11e | 21 | #include <linux/bottom_half.h> |
bc0ee476 | 22 | #include <linux/bug.h> |
7582e220 | 23 | #include <linux/cache.h> |
bc0ee476 | 24 | #include <linux/compat.h> |
32365e64 | 25 | #include <linux/cpu.h> |
fb1ab1ab | 26 | #include <linux/cpu_pm.h> |
53631b54 | 27 | #include <linux/kernel.h> |
94ef7ecb | 28 | #include <linux/linkage.h> |
bc0ee476 | 29 | #include <linux/irqflags.h> |
53631b54 | 30 | #include <linux/init.h> |
cb84d11e | 31 | #include <linux/percpu.h> |
4328825d | 32 | #include <linux/preempt.h> |
7582e220 | 33 | #include <linux/prctl.h> |
bc0ee476 | 34 | #include <linux/ptrace.h> |
3f07c014 | 35 | #include <linux/sched/signal.h> |
bc0ee476 | 36 | #include <linux/sched/task_stack.h> |
53631b54 | 37 | #include <linux/signal.h> |
bc0ee476 | 38 | #include <linux/slab.h> |
53631b54 CM |
39 | |
40 | #include <asm/fpsimd.h> | |
41 | #include <asm/cputype.h> | |
4328825d | 42 | #include <asm/simd.h> |
bc0ee476 DM |
43 | #include <asm/sigcontext.h> |
44 | #include <asm/sysreg.h> | |
45 | #include <asm/traps.h> | |
53631b54 CM |
46 | |
47 | #define FPEXC_IOF (1 << 0) | |
48 | #define FPEXC_DZF (1 << 1) | |
49 | #define FPEXC_OFF (1 << 2) | |
50 | #define FPEXC_UFF (1 << 3) | |
51 | #define FPEXC_IXF (1 << 4) | |
52 | #define FPEXC_IDF (1 << 7) | |
53 | ||
005f78cd | 54 | /* |
bc0ee476 DM |
55 | * (Note: in this discussion, statements about FPSIMD apply equally to SVE.) |
56 | * | |
005f78cd AB |
57 | * In order to reduce the number of times the FPSIMD state is needlessly saved |
58 | * and restored, we need to keep track of two things: | |
59 | * (a) for each task, we need to remember which CPU was the last one to have | |
60 | * the task's FPSIMD state loaded into its FPSIMD registers; | |
61 | * (b) for each CPU, we need to remember which task's userland FPSIMD state has | |
62 | * been loaded into its FPSIMD registers most recently, or whether it has | |
63 | * been used to perform kernel mode NEON in the meantime. | |
64 | * | |
65 | * For (a), we add a 'cpu' field to struct fpsimd_state, which gets updated to | |
ef769e32 | 66 | * the id of the current CPU every time the state is loaded onto a CPU. For (b), |
005f78cd AB |
67 | * we add the per-cpu variable 'fpsimd_last_state' (below), which contains the |
68 | * address of the userland FPSIMD state of the task that was loaded onto the CPU | |
69 | * the most recently, or NULL if kernel mode NEON has been performed after that. | |
70 | * | |
71 | * With this in place, we no longer have to restore the next FPSIMD state right | |
72 | * when switching between tasks. Instead, we can defer this check to userland | |
73 | * resume, at which time we verify whether the CPU's fpsimd_last_state and the | |
74 | * task's fpsimd_state.cpu are still mutually in sync. If this is the case, we | |
75 | * can omit the FPSIMD restore. | |
76 | * | |
77 | * As an optimization, we use the thread_info flag TIF_FOREIGN_FPSTATE to | |
78 | * indicate whether or not the userland FPSIMD state of the current task is | |
79 | * present in the registers. The flag is set unless the FPSIMD registers of this | |
80 | * CPU currently contain the most recent userland FPSIMD state of the current | |
81 | * task. | |
82 | * | |
cb84d11e DM |
83 | * In order to allow softirq handlers to use FPSIMD, kernel_neon_begin() may |
84 | * save the task's FPSIMD context back to task_struct from softirq context. | |
85 | * To prevent this from racing with the manipulation of the task's FPSIMD state | |
86 | * from task context and thereby corrupting the state, it is necessary to | |
87 | * protect any manipulation of a task's fpsimd_state or TIF_FOREIGN_FPSTATE | |
88 | * flag with local_bh_disable() unless softirqs are already masked. | |
89 | * | |
005f78cd AB |
90 | * For a certain task, the sequence may look something like this: |
91 | * - the task gets scheduled in; if both the task's fpsimd_state.cpu field | |
92 | * contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu | |
93 | * variable points to the task's fpsimd_state, the TIF_FOREIGN_FPSTATE flag is | |
94 | * cleared, otherwise it is set; | |
95 | * | |
96 | * - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's | |
97 | * userland FPSIMD state is copied from memory to the registers, the task's | |
98 | * fpsimd_state.cpu field is set to the id of the current CPU, the current | |
99 | * CPU's fpsimd_last_state pointer is set to this task's fpsimd_state and the | |
100 | * TIF_FOREIGN_FPSTATE flag is cleared; | |
101 | * | |
102 | * - the task executes an ordinary syscall; upon return to userland, the | |
103 | * TIF_FOREIGN_FPSTATE flag will still be cleared, so no FPSIMD state is | |
104 | * restored; | |
105 | * | |
106 | * - the task executes a syscall which executes some NEON instructions; this is | |
107 | * preceded by a call to kernel_neon_begin(), which copies the task's FPSIMD | |
108 | * register contents to memory, clears the fpsimd_last_state per-cpu variable | |
109 | * and sets the TIF_FOREIGN_FPSTATE flag; | |
110 | * | |
111 | * - the task gets preempted after kernel_neon_end() is called; as we have not | |
112 | * returned from the 2nd syscall yet, TIF_FOREIGN_FPSTATE is still set so | |
113 | * whatever is in the FPSIMD registers is not saved to memory, but discarded. | |
114 | */ | |
115 | static DEFINE_PER_CPU(struct fpsimd_state *, fpsimd_last_state); | |
116 | ||
79ab047c | 117 | /* Default VL for tasks that don't set it explicitly: */ |
2e0f2478 | 118 | static int sve_default_vl = -1; |
79ab047c | 119 | |
7582e220 DM |
120 | #ifdef CONFIG_ARM64_SVE |
121 | ||
122 | /* Maximum supported vector length across all CPUs (initially poisoned) */ | |
123 | int __ro_after_init sve_max_vl = -1; | |
124 | /* Set of available vector lengths, as vq_to_bit(vq): */ | |
2e0f2478 | 125 | static __ro_after_init DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX); |
fdfa976c | 126 | static void __percpu *efi_sve_state; |
7582e220 DM |
127 | |
128 | #else /* ! CONFIG_ARM64_SVE */ | |
129 | ||
130 | /* Dummy declaration for code that will be optimised out: */ | |
2e0f2478 | 131 | extern __ro_after_init DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX); |
fdfa976c | 132 | extern void __percpu *efi_sve_state; |
7582e220 DM |
133 | |
134 | #endif /* ! CONFIG_ARM64_SVE */ | |
135 | ||
bc0ee476 DM |
136 | /* |
137 | * Call __sve_free() directly only if you know task can't be scheduled | |
138 | * or preempted. | |
139 | */ | |
140 | static void __sve_free(struct task_struct *task) | |
141 | { | |
142 | kfree(task->thread.sve_state); | |
143 | task->thread.sve_state = NULL; | |
144 | } | |
145 | ||
146 | static void sve_free(struct task_struct *task) | |
147 | { | |
148 | WARN_ON(test_tsk_thread_flag(task, TIF_SVE)); | |
149 | ||
150 | __sve_free(task); | |
151 | } | |
152 | ||
153 | ||
154 | /* Offset of FFR in the SVE register dump */ | |
155 | static size_t sve_ffr_offset(int vl) | |
156 | { | |
157 | return SVE_SIG_FFR_OFFSET(sve_vq_from_vl(vl)) - SVE_SIG_REGS_OFFSET; | |
158 | } | |
159 | ||
160 | static void *sve_pffr(struct task_struct *task) | |
161 | { | |
162 | return (char *)task->thread.sve_state + | |
163 | sve_ffr_offset(task->thread.sve_vl); | |
164 | } | |
165 | ||
166 | static void change_cpacr(u64 val, u64 mask) | |
167 | { | |
168 | u64 cpacr = read_sysreg(CPACR_EL1); | |
169 | u64 new = (cpacr & ~mask) | val; | |
170 | ||
171 | if (new != cpacr) | |
172 | write_sysreg(new, CPACR_EL1); | |
173 | } | |
174 | ||
175 | static void sve_user_disable(void) | |
176 | { | |
177 | change_cpacr(0, CPACR_EL1_ZEN_EL0EN); | |
178 | } | |
179 | ||
180 | static void sve_user_enable(void) | |
181 | { | |
182 | change_cpacr(CPACR_EL1_ZEN_EL0EN, CPACR_EL1_ZEN_EL0EN); | |
183 | } | |
184 | ||
185 | /* | |
186 | * TIF_SVE controls whether a task can use SVE without trapping while | |
187 | * in userspace, and also the way a task's FPSIMD/SVE state is stored | |
188 | * in thread_struct. | |
189 | * | |
190 | * The kernel uses this flag to track whether a user task is actively | |
191 | * using SVE, and therefore whether full SVE register state needs to | |
192 | * be tracked. If not, the cheaper FPSIMD context handling code can | |
193 | * be used instead of the more costly SVE equivalents. | |
194 | * | |
195 | * * TIF_SVE set: | |
196 | * | |
197 | * The task can execute SVE instructions while in userspace without | |
198 | * trapping to the kernel. | |
199 | * | |
200 | * When stored, Z0-Z31 (incorporating Vn in bits[127:0] or the | |
201 | * corresponding Zn), P0-P15 and FFR are encoded in in | |
202 | * task->thread.sve_state, formatted appropriately for vector | |
203 | * length task->thread.sve_vl. | |
204 | * | |
205 | * task->thread.sve_state must point to a valid buffer at least | |
206 | * sve_state_size(task) bytes in size. | |
207 | * | |
208 | * During any syscall, the kernel may optionally clear TIF_SVE and | |
209 | * discard the vector state except for the FPSIMD subset. | |
210 | * | |
211 | * * TIF_SVE clear: | |
212 | * | |
213 | * An attempt by the user task to execute an SVE instruction causes | |
214 | * do_sve_acc() to be called, which does some preparation and then | |
215 | * sets TIF_SVE. | |
216 | * | |
217 | * When stored, FPSIMD registers V0-V31 are encoded in | |
218 | * task->fpsimd_state; bits [max : 128] for each of Z0-Z31 are | |
219 | * logically zero but not stored anywhere; P0-P15 and FFR are not | |
220 | * stored and have unspecified values from userspace's point of | |
221 | * view. For hygiene purposes, the kernel zeroes them on next use, | |
222 | * but userspace is discouraged from relying on this. | |
223 | * | |
224 | * task->thread.sve_state does not need to be non-NULL, valid or any | |
225 | * particular size: it must not be dereferenced. | |
226 | * | |
227 | * * FPSR and FPCR are always stored in task->fpsimd_state irrespctive of | |
228 | * whether TIF_SVE is clear or set, since these are not vector length | |
229 | * dependent. | |
230 | */ | |
231 | ||
232 | /* | |
233 | * Update current's FPSIMD/SVE registers from thread_struct. | |
234 | * | |
235 | * This function should be called only when the FPSIMD/SVE state in | |
236 | * thread_struct is known to be up to date, when preparing to enter | |
237 | * userspace. | |
238 | * | |
239 | * Softirqs (and preemption) must be disabled. | |
240 | */ | |
241 | static void task_fpsimd_load(void) | |
242 | { | |
243 | WARN_ON(!in_softirq() && !irqs_disabled()); | |
244 | ||
245 | if (system_supports_sve() && test_thread_flag(TIF_SVE)) | |
246 | sve_load_state(sve_pffr(current), | |
247 | ¤t->thread.fpsimd_state.fpsr, | |
248 | sve_vq_from_vl(current->thread.sve_vl) - 1); | |
249 | else | |
250 | fpsimd_load_state(¤t->thread.fpsimd_state); | |
251 | ||
252 | if (system_supports_sve()) { | |
253 | /* Toggle SVE trapping for userspace if needed */ | |
254 | if (test_thread_flag(TIF_SVE)) | |
255 | sve_user_enable(); | |
256 | else | |
257 | sve_user_disable(); | |
258 | ||
259 | /* Serialised by exception return to user */ | |
260 | } | |
261 | } | |
262 | ||
263 | /* | |
264 | * Ensure current's FPSIMD/SVE storage in thread_struct is up to date | |
265 | * with respect to the CPU registers. | |
266 | * | |
267 | * Softirqs (and preemption) must be disabled. | |
268 | */ | |
269 | static void task_fpsimd_save(void) | |
270 | { | |
271 | WARN_ON(!in_softirq() && !irqs_disabled()); | |
272 | ||
273 | if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) { | |
274 | if (system_supports_sve() && test_thread_flag(TIF_SVE)) { | |
275 | if (WARN_ON(sve_get_vl() != current->thread.sve_vl)) { | |
276 | /* | |
277 | * Can't save the user regs, so current would | |
278 | * re-enter user with corrupt state. | |
279 | * There's no way to recover, so kill it: | |
280 | */ | |
281 | force_signal_inject( | |
282 | SIGKILL, 0, current_pt_regs(), 0); | |
283 | return; | |
284 | } | |
285 | ||
286 | sve_save_state(sve_pffr(current), | |
287 | ¤t->thread.fpsimd_state.fpsr); | |
288 | } else | |
289 | fpsimd_save_state(¤t->thread.fpsimd_state); | |
290 | } | |
291 | } | |
292 | ||
7582e220 DM |
293 | /* |
294 | * Helpers to translate bit indices in sve_vq_map to VQ values (and | |
295 | * vice versa). This allows find_next_bit() to be used to find the | |
296 | * _maximum_ VQ not exceeding a certain value. | |
297 | */ | |
298 | ||
299 | static unsigned int vq_to_bit(unsigned int vq) | |
300 | { | |
301 | return SVE_VQ_MAX - vq; | |
302 | } | |
303 | ||
304 | static unsigned int bit_to_vq(unsigned int bit) | |
305 | { | |
306 | if (WARN_ON(bit >= SVE_VQ_MAX)) | |
307 | bit = SVE_VQ_MAX - 1; | |
308 | ||
309 | return SVE_VQ_MAX - bit; | |
310 | } | |
311 | ||
312 | /* | |
313 | * All vector length selection from userspace comes through here. | |
314 | * We're on a slow path, so some sanity-checks are included. | |
315 | * If things go wrong there's a bug somewhere, but try to fall back to a | |
316 | * safe choice. | |
317 | */ | |
318 | static unsigned int find_supported_vector_length(unsigned int vl) | |
319 | { | |
320 | int bit; | |
321 | int max_vl = sve_max_vl; | |
322 | ||
323 | if (WARN_ON(!sve_vl_valid(vl))) | |
324 | vl = SVE_VL_MIN; | |
325 | ||
326 | if (WARN_ON(!sve_vl_valid(max_vl))) | |
327 | max_vl = SVE_VL_MIN; | |
328 | ||
329 | if (vl > max_vl) | |
330 | vl = max_vl; | |
331 | ||
332 | bit = find_next_bit(sve_vq_map, SVE_VQ_MAX, | |
333 | vq_to_bit(sve_vq_from_vl(vl))); | |
334 | return sve_vl_from_vq(bit_to_vq(bit)); | |
335 | } | |
336 | ||
bc0ee476 DM |
337 | #define ZREG(sve_state, vq, n) ((char *)(sve_state) + \ |
338 | (SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET)) | |
339 | ||
340 | /* | |
341 | * Transfer the FPSIMD state in task->thread.fpsimd_state to | |
342 | * task->thread.sve_state. | |
343 | * | |
344 | * Task can be a non-runnable task, or current. In the latter case, | |
345 | * softirqs (and preemption) must be disabled. | |
346 | * task->thread.sve_state must point to at least sve_state_size(task) | |
347 | * bytes of allocated kernel memory. | |
348 | * task->thread.fpsimd_state must be up to date before calling this function. | |
349 | */ | |
350 | static void fpsimd_to_sve(struct task_struct *task) | |
351 | { | |
352 | unsigned int vq; | |
353 | void *sst = task->thread.sve_state; | |
354 | struct fpsimd_state const *fst = &task->thread.fpsimd_state; | |
355 | unsigned int i; | |
356 | ||
357 | if (!system_supports_sve()) | |
358 | return; | |
359 | ||
360 | vq = sve_vq_from_vl(task->thread.sve_vl); | |
361 | for (i = 0; i < 32; ++i) | |
362 | memcpy(ZREG(sst, vq, i), &fst->vregs[i], | |
363 | sizeof(fst->vregs[i])); | |
364 | } | |
365 | ||
8cd969d2 DM |
366 | /* |
367 | * Transfer the SVE state in task->thread.sve_state to | |
368 | * task->thread.fpsimd_state. | |
369 | * | |
370 | * Task can be a non-runnable task, or current. In the latter case, | |
371 | * softirqs (and preemption) must be disabled. | |
372 | * task->thread.sve_state must point to at least sve_state_size(task) | |
373 | * bytes of allocated kernel memory. | |
374 | * task->thread.sve_state must be up to date before calling this function. | |
375 | */ | |
376 | static void sve_to_fpsimd(struct task_struct *task) | |
377 | { | |
378 | unsigned int vq; | |
379 | void const *sst = task->thread.sve_state; | |
380 | struct fpsimd_state *fst = &task->thread.fpsimd_state; | |
381 | unsigned int i; | |
382 | ||
383 | if (!system_supports_sve()) | |
384 | return; | |
385 | ||
386 | vq = sve_vq_from_vl(task->thread.sve_vl); | |
387 | for (i = 0; i < 32; ++i) | |
388 | memcpy(&fst->vregs[i], ZREG(sst, vq, i), | |
389 | sizeof(fst->vregs[i])); | |
390 | } | |
391 | ||
bc0ee476 DM |
392 | #ifdef CONFIG_ARM64_SVE |
393 | ||
394 | /* | |
395 | * Return how many bytes of memory are required to store the full SVE | |
396 | * state for task, given task's currently configured vector length. | |
397 | */ | |
398 | size_t sve_state_size(struct task_struct const *task) | |
399 | { | |
400 | return SVE_SIG_REGS_SIZE(sve_vq_from_vl(task->thread.sve_vl)); | |
401 | } | |
402 | ||
403 | /* | |
404 | * Ensure that task->thread.sve_state is allocated and sufficiently large. | |
405 | * | |
406 | * This function should be used only in preparation for replacing | |
407 | * task->thread.sve_state with new data. The memory is always zeroed | |
408 | * here to prevent stale data from showing through: this is done in | |
409 | * the interest of testability and predictability: except in the | |
410 | * do_sve_acc() case, there is no ABI requirement to hide stale data | |
411 | * written previously be task. | |
412 | */ | |
413 | void sve_alloc(struct task_struct *task) | |
414 | { | |
415 | if (task->thread.sve_state) { | |
416 | memset(task->thread.sve_state, 0, sve_state_size(current)); | |
417 | return; | |
418 | } | |
419 | ||
420 | /* This is a small allocation (maximum ~8KB) and Should Not Fail. */ | |
421 | task->thread.sve_state = | |
422 | kzalloc(sve_state_size(task), GFP_KERNEL); | |
423 | ||
424 | /* | |
425 | * If future SVE revisions can have larger vectors though, | |
426 | * this may cease to be true: | |
427 | */ | |
428 | BUG_ON(!task->thread.sve_state); | |
429 | } | |
430 | ||
43d4da2c DM |
431 | |
432 | /* | |
433 | * Ensure that task->thread.sve_state is up to date with respect to | |
434 | * the user task, irrespective of when SVE is in use or not. | |
435 | * | |
436 | * This should only be called by ptrace. task must be non-runnable. | |
437 | * task->thread.sve_state must point to at least sve_state_size(task) | |
438 | * bytes of allocated kernel memory. | |
439 | */ | |
440 | void fpsimd_sync_to_sve(struct task_struct *task) | |
441 | { | |
442 | if (!test_tsk_thread_flag(task, TIF_SVE)) | |
443 | fpsimd_to_sve(task); | |
444 | } | |
445 | ||
446 | /* | |
447 | * Ensure that task->thread.fpsimd_state is up to date with respect to | |
448 | * the user task, irrespective of whether SVE is in use or not. | |
449 | * | |
450 | * This should only be called by ptrace. task must be non-runnable. | |
451 | * task->thread.sve_state must point to at least sve_state_size(task) | |
452 | * bytes of allocated kernel memory. | |
453 | */ | |
454 | void sve_sync_to_fpsimd(struct task_struct *task) | |
455 | { | |
456 | if (test_tsk_thread_flag(task, TIF_SVE)) | |
457 | sve_to_fpsimd(task); | |
458 | } | |
459 | ||
460 | /* | |
461 | * Ensure that task->thread.sve_state is up to date with respect to | |
462 | * the task->thread.fpsimd_state. | |
463 | * | |
464 | * This should only be called by ptrace to merge new FPSIMD register | |
465 | * values into a task for which SVE is currently active. | |
466 | * task must be non-runnable. | |
467 | * task->thread.sve_state must point to at least sve_state_size(task) | |
468 | * bytes of allocated kernel memory. | |
469 | * task->thread.fpsimd_state must already have been initialised with | |
470 | * the new FPSIMD register values to be merged in. | |
471 | */ | |
472 | void sve_sync_from_fpsimd_zeropad(struct task_struct *task) | |
473 | { | |
474 | unsigned int vq; | |
475 | void *sst = task->thread.sve_state; | |
476 | struct fpsimd_state const *fst = &task->thread.fpsimd_state; | |
477 | unsigned int i; | |
478 | ||
479 | if (!test_tsk_thread_flag(task, TIF_SVE)) | |
480 | return; | |
481 | ||
482 | vq = sve_vq_from_vl(task->thread.sve_vl); | |
483 | ||
484 | memset(sst, 0, SVE_SIG_REGS_SIZE(vq)); | |
485 | ||
486 | for (i = 0; i < 32; ++i) | |
487 | memcpy(ZREG(sst, vq, i), &fst->vregs[i], | |
488 | sizeof(fst->vregs[i])); | |
489 | } | |
490 | ||
7582e220 DM |
491 | int sve_set_vector_length(struct task_struct *task, |
492 | unsigned long vl, unsigned long flags) | |
493 | { | |
494 | if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT | | |
495 | PR_SVE_SET_VL_ONEXEC)) | |
496 | return -EINVAL; | |
497 | ||
498 | if (!sve_vl_valid(vl)) | |
499 | return -EINVAL; | |
500 | ||
501 | /* | |
502 | * Clamp to the maximum vector length that VL-agnostic SVE code can | |
503 | * work with. A flag may be assigned in the future to allow setting | |
504 | * of larger vector lengths without confusing older software. | |
505 | */ | |
506 | if (vl > SVE_VL_ARCH_MAX) | |
507 | vl = SVE_VL_ARCH_MAX; | |
508 | ||
509 | vl = find_supported_vector_length(vl); | |
510 | ||
511 | if (flags & (PR_SVE_VL_INHERIT | | |
512 | PR_SVE_SET_VL_ONEXEC)) | |
513 | task->thread.sve_vl_onexec = vl; | |
514 | else | |
515 | /* Reset VL to system default on next exec: */ | |
516 | task->thread.sve_vl_onexec = 0; | |
517 | ||
518 | /* Only actually set the VL if not deferred: */ | |
519 | if (flags & PR_SVE_SET_VL_ONEXEC) | |
520 | goto out; | |
521 | ||
522 | if (vl == task->thread.sve_vl) | |
523 | goto out; | |
524 | ||
525 | /* | |
526 | * To ensure the FPSIMD bits of the SVE vector registers are preserved, | |
527 | * write any live register state back to task_struct, and convert to a | |
528 | * non-SVE thread. | |
529 | */ | |
530 | if (task == current) { | |
531 | local_bh_disable(); | |
532 | ||
533 | task_fpsimd_save(); | |
534 | set_thread_flag(TIF_FOREIGN_FPSTATE); | |
535 | } | |
536 | ||
537 | fpsimd_flush_task_state(task); | |
538 | if (test_and_clear_tsk_thread_flag(task, TIF_SVE)) | |
539 | sve_to_fpsimd(task); | |
540 | ||
541 | if (task == current) | |
542 | local_bh_enable(); | |
543 | ||
544 | /* | |
545 | * Force reallocation of task SVE state to the correct size | |
546 | * on next use: | |
547 | */ | |
548 | sve_free(task); | |
549 | ||
550 | task->thread.sve_vl = vl; | |
551 | ||
552 | out: | |
553 | if (flags & PR_SVE_VL_INHERIT) | |
554 | set_tsk_thread_flag(task, TIF_SVE_VL_INHERIT); | |
555 | else | |
556 | clear_tsk_thread_flag(task, TIF_SVE_VL_INHERIT); | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
2e0f2478 DM |
561 | /* |
562 | * Bitmap for temporary storage of the per-CPU set of supported vector lengths | |
563 | * during secondary boot. | |
564 | */ | |
565 | static DECLARE_BITMAP(sve_secondary_vq_map, SVE_VQ_MAX); | |
566 | ||
567 | static void sve_probe_vqs(DECLARE_BITMAP(map, SVE_VQ_MAX)) | |
568 | { | |
569 | unsigned int vq, vl; | |
570 | unsigned long zcr; | |
571 | ||
572 | bitmap_zero(map, SVE_VQ_MAX); | |
573 | ||
574 | zcr = ZCR_ELx_LEN_MASK; | |
575 | zcr = read_sysreg_s(SYS_ZCR_EL1) & ~zcr; | |
576 | ||
577 | for (vq = SVE_VQ_MAX; vq >= SVE_VQ_MIN; --vq) { | |
578 | write_sysreg_s(zcr | (vq - 1), SYS_ZCR_EL1); /* self-syncing */ | |
579 | vl = sve_get_vl(); | |
580 | vq = sve_vq_from_vl(vl); /* skip intervening lengths */ | |
581 | set_bit(vq_to_bit(vq), map); | |
582 | } | |
583 | } | |
584 | ||
585 | void __init sve_init_vq_map(void) | |
586 | { | |
587 | sve_probe_vqs(sve_vq_map); | |
588 | } | |
589 | ||
590 | /* | |
591 | * If we haven't committed to the set of supported VQs yet, filter out | |
592 | * those not supported by the current CPU. | |
593 | */ | |
594 | void sve_update_vq_map(void) | |
595 | { | |
596 | sve_probe_vqs(sve_secondary_vq_map); | |
597 | bitmap_and(sve_vq_map, sve_vq_map, sve_secondary_vq_map, SVE_VQ_MAX); | |
598 | } | |
599 | ||
600 | /* Check whether the current CPU supports all VQs in the committed set */ | |
601 | int sve_verify_vq_map(void) | |
602 | { | |
603 | int ret = 0; | |
604 | ||
605 | sve_probe_vqs(sve_secondary_vq_map); | |
606 | bitmap_andnot(sve_secondary_vq_map, sve_vq_map, sve_secondary_vq_map, | |
607 | SVE_VQ_MAX); | |
608 | if (!bitmap_empty(sve_secondary_vq_map, SVE_VQ_MAX)) { | |
609 | pr_warn("SVE: cpu%d: Required vector length(s) missing\n", | |
610 | smp_processor_id()); | |
611 | ret = -EINVAL; | |
612 | } | |
613 | ||
614 | return ret; | |
615 | } | |
616 | ||
fdfa976c DM |
617 | static void __init sve_efi_setup(void) |
618 | { | |
619 | if (!IS_ENABLED(CONFIG_EFI)) | |
620 | return; | |
621 | ||
622 | /* | |
623 | * alloc_percpu() warns and prints a backtrace if this goes wrong. | |
624 | * This is evidence of a crippled system and we are returning void, | |
625 | * so no attempt is made to handle this situation here. | |
626 | */ | |
627 | if (!sve_vl_valid(sve_max_vl)) | |
628 | goto fail; | |
629 | ||
630 | efi_sve_state = __alloc_percpu( | |
631 | SVE_SIG_REGS_SIZE(sve_vq_from_vl(sve_max_vl)), SVE_VQ_BYTES); | |
632 | if (!efi_sve_state) | |
633 | goto fail; | |
634 | ||
635 | return; | |
636 | ||
637 | fail: | |
638 | panic("Cannot allocate percpu memory for EFI SVE save/restore"); | |
639 | } | |
640 | ||
2e0f2478 DM |
641 | /* |
642 | * Enable SVE for EL1. | |
643 | * Intended for use by the cpufeatures code during CPU boot. | |
644 | */ | |
645 | int sve_kernel_enable(void *__always_unused p) | |
646 | { | |
647 | write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1); | |
648 | isb(); | |
649 | ||
650 | return 0; | |
651 | } | |
652 | ||
653 | void __init sve_setup(void) | |
654 | { | |
655 | u64 zcr; | |
656 | ||
657 | if (!system_supports_sve()) | |
658 | return; | |
659 | ||
660 | /* | |
661 | * The SVE architecture mandates support for 128-bit vectors, | |
662 | * so sve_vq_map must have at least SVE_VQ_MIN set. | |
663 | * If something went wrong, at least try to patch it up: | |
664 | */ | |
665 | if (WARN_ON(!test_bit(vq_to_bit(SVE_VQ_MIN), sve_vq_map))) | |
666 | set_bit(vq_to_bit(SVE_VQ_MIN), sve_vq_map); | |
667 | ||
668 | zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); | |
669 | sve_max_vl = sve_vl_from_vq((zcr & ZCR_ELx_LEN_MASK) + 1); | |
670 | ||
671 | /* | |
672 | * Sanity-check that the max VL we determined through CPU features | |
673 | * corresponds properly to sve_vq_map. If not, do our best: | |
674 | */ | |
675 | if (WARN_ON(sve_max_vl != find_supported_vector_length(sve_max_vl))) | |
676 | sve_max_vl = find_supported_vector_length(sve_max_vl); | |
677 | ||
678 | /* | |
679 | * For the default VL, pick the maximum supported value <= 64. | |
680 | * VL == 64 is guaranteed not to grow the signal frame. | |
681 | */ | |
682 | sve_default_vl = find_supported_vector_length(64); | |
683 | ||
684 | pr_info("SVE: maximum available vector length %u bytes per vector\n", | |
685 | sve_max_vl); | |
686 | pr_info("SVE: default vector length %u bytes per vector\n", | |
687 | sve_default_vl); | |
fdfa976c DM |
688 | |
689 | sve_efi_setup(); | |
2e0f2478 DM |
690 | } |
691 | ||
bc0ee476 DM |
692 | /* |
693 | * Called from the put_task_struct() path, which cannot get here | |
694 | * unless dead_task is really dead and not schedulable. | |
695 | */ | |
696 | void fpsimd_release_task(struct task_struct *dead_task) | |
697 | { | |
698 | __sve_free(dead_task); | |
699 | } | |
700 | ||
701 | #endif /* CONFIG_ARM64_SVE */ | |
702 | ||
703 | /* | |
704 | * Trapped SVE access | |
705 | * | |
706 | * Storage is allocated for the full SVE state, the current FPSIMD | |
707 | * register contents are migrated across, and TIF_SVE is set so that | |
708 | * the SVE access trap will be disabled the next time this task | |
709 | * reaches ret_to_user. | |
710 | * | |
711 | * TIF_SVE should be clear on entry: otherwise, task_fpsimd_load() | |
712 | * would have disabled the SVE access trap for userspace during | |
713 | * ret_to_user, making an SVE access trap impossible in that case. | |
714 | */ | |
715 | asmlinkage void do_sve_acc(unsigned int esr, struct pt_regs *regs) | |
716 | { | |
717 | /* Even if we chose not to use SVE, the hardware could still trap: */ | |
718 | if (unlikely(!system_supports_sve()) || WARN_ON(is_compat_task())) { | |
719 | force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0); | |
720 | return; | |
721 | } | |
722 | ||
723 | sve_alloc(current); | |
724 | ||
725 | local_bh_disable(); | |
726 | ||
727 | task_fpsimd_save(); | |
728 | fpsimd_to_sve(current); | |
729 | ||
730 | /* Force ret_to_user to reload the registers: */ | |
731 | fpsimd_flush_task_state(current); | |
732 | set_thread_flag(TIF_FOREIGN_FPSTATE); | |
733 | ||
734 | if (test_and_set_thread_flag(TIF_SVE)) | |
735 | WARN_ON(1); /* SVE access shouldn't have trapped */ | |
736 | ||
737 | local_bh_enable(); | |
738 | } | |
739 | ||
53631b54 CM |
740 | /* |
741 | * Trapped FP/ASIMD access. | |
742 | */ | |
94ef7ecb | 743 | asmlinkage void do_fpsimd_acc(unsigned int esr, struct pt_regs *regs) |
53631b54 CM |
744 | { |
745 | /* TODO: implement lazy context saving/restoring */ | |
746 | WARN_ON(1); | |
747 | } | |
748 | ||
749 | /* | |
750 | * Raise a SIGFPE for the current process. | |
751 | */ | |
94ef7ecb | 752 | asmlinkage void do_fpsimd_exc(unsigned int esr, struct pt_regs *regs) |
53631b54 CM |
753 | { |
754 | siginfo_t info; | |
755 | unsigned int si_code = 0; | |
756 | ||
757 | if (esr & FPEXC_IOF) | |
758 | si_code = FPE_FLTINV; | |
759 | else if (esr & FPEXC_DZF) | |
760 | si_code = FPE_FLTDIV; | |
761 | else if (esr & FPEXC_OFF) | |
762 | si_code = FPE_FLTOVF; | |
763 | else if (esr & FPEXC_UFF) | |
764 | si_code = FPE_FLTUND; | |
765 | else if (esr & FPEXC_IXF) | |
766 | si_code = FPE_FLTRES; | |
767 | ||
768 | memset(&info, 0, sizeof(info)); | |
769 | info.si_signo = SIGFPE; | |
770 | info.si_code = si_code; | |
771 | info.si_addr = (void __user *)instruction_pointer(regs); | |
772 | ||
773 | send_sig_info(SIGFPE, &info, current); | |
774 | } | |
775 | ||
776 | void fpsimd_thread_switch(struct task_struct *next) | |
777 | { | |
82e0191a SP |
778 | if (!system_supports_fpsimd()) |
779 | return; | |
005f78cd AB |
780 | /* |
781 | * Save the current FPSIMD state to memory, but only if whatever is in | |
782 | * the registers is in fact the most recent userland FPSIMD state of | |
783 | * 'current'. | |
784 | */ | |
bc0ee476 DM |
785 | if (current->mm) |
786 | task_fpsimd_save(); | |
005f78cd AB |
787 | |
788 | if (next->mm) { | |
789 | /* | |
790 | * If we are switching to a task whose most recent userland | |
791 | * FPSIMD state is already in the registers of *this* cpu, | |
792 | * we can skip loading the state from memory. Otherwise, set | |
793 | * the TIF_FOREIGN_FPSTATE flag so the state will be loaded | |
794 | * upon the next return to userland. | |
795 | */ | |
796 | struct fpsimd_state *st = &next->thread.fpsimd_state; | |
797 | ||
798 | if (__this_cpu_read(fpsimd_last_state) == st | |
799 | && st->cpu == smp_processor_id()) | |
9cf5b54f | 800 | clear_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE); |
005f78cd | 801 | else |
9cf5b54f | 802 | set_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE); |
005f78cd | 803 | } |
53631b54 CM |
804 | } |
805 | ||
806 | void fpsimd_flush_thread(void) | |
807 | { | |
7582e220 | 808 | int vl, supported_vl; |
bc0ee476 | 809 | |
82e0191a SP |
810 | if (!system_supports_fpsimd()) |
811 | return; | |
cb84d11e DM |
812 | |
813 | local_bh_disable(); | |
814 | ||
53631b54 | 815 | memset(¤t->thread.fpsimd_state, 0, sizeof(struct fpsimd_state)); |
674c242c | 816 | fpsimd_flush_task_state(current); |
bc0ee476 DM |
817 | |
818 | if (system_supports_sve()) { | |
819 | clear_thread_flag(TIF_SVE); | |
820 | sve_free(current); | |
821 | ||
822 | /* | |
823 | * Reset the task vector length as required. | |
824 | * This is where we ensure that all user tasks have a valid | |
825 | * vector length configured: no kernel task can become a user | |
826 | * task without an exec and hence a call to this function. | |
2e0f2478 DM |
827 | * By the time the first call to this function is made, all |
828 | * early hardware probing is complete, so sve_default_vl | |
829 | * should be valid. | |
bc0ee476 DM |
830 | * If a bug causes this to go wrong, we make some noise and |
831 | * try to fudge thread.sve_vl to a safe value here. | |
832 | */ | |
79ab047c DM |
833 | vl = current->thread.sve_vl_onexec ? |
834 | current->thread.sve_vl_onexec : sve_default_vl; | |
bc0ee476 DM |
835 | |
836 | if (WARN_ON(!sve_vl_valid(vl))) | |
837 | vl = SVE_VL_MIN; | |
838 | ||
7582e220 DM |
839 | supported_vl = find_supported_vector_length(vl); |
840 | if (WARN_ON(supported_vl != vl)) | |
841 | vl = supported_vl; | |
842 | ||
bc0ee476 | 843 | current->thread.sve_vl = vl; |
79ab047c DM |
844 | |
845 | /* | |
846 | * If the task is not set to inherit, ensure that the vector | |
847 | * length will be reset by a subsequent exec: | |
848 | */ | |
849 | if (!test_thread_flag(TIF_SVE_VL_INHERIT)) | |
850 | current->thread.sve_vl_onexec = 0; | |
bc0ee476 DM |
851 | } |
852 | ||
005f78cd | 853 | set_thread_flag(TIF_FOREIGN_FPSTATE); |
cb84d11e DM |
854 | |
855 | local_bh_enable(); | |
53631b54 CM |
856 | } |
857 | ||
c51f9269 | 858 | /* |
005f78cd AB |
859 | * Save the userland FPSIMD state of 'current' to memory, but only if the state |
860 | * currently held in the registers does in fact belong to 'current' | |
c51f9269 AB |
861 | */ |
862 | void fpsimd_preserve_current_state(void) | |
863 | { | |
82e0191a SP |
864 | if (!system_supports_fpsimd()) |
865 | return; | |
cb84d11e DM |
866 | |
867 | local_bh_disable(); | |
8cd969d2 | 868 | task_fpsimd_save(); |
cb84d11e | 869 | local_bh_enable(); |
c51f9269 AB |
870 | } |
871 | ||
8cd969d2 DM |
872 | /* |
873 | * Like fpsimd_preserve_current_state(), but ensure that | |
874 | * current->thread.fpsimd_state is updated so that it can be copied to | |
875 | * the signal frame. | |
876 | */ | |
877 | void fpsimd_signal_preserve_current_state(void) | |
878 | { | |
879 | fpsimd_preserve_current_state(); | |
880 | if (system_supports_sve() && test_thread_flag(TIF_SVE)) | |
881 | sve_to_fpsimd(current); | |
882 | } | |
883 | ||
c51f9269 | 884 | /* |
005f78cd AB |
885 | * Load the userland FPSIMD state of 'current' from memory, but only if the |
886 | * FPSIMD state already held in the registers is /not/ the most recent FPSIMD | |
887 | * state of 'current' | |
888 | */ | |
889 | void fpsimd_restore_current_state(void) | |
890 | { | |
82e0191a SP |
891 | if (!system_supports_fpsimd()) |
892 | return; | |
cb84d11e DM |
893 | |
894 | local_bh_disable(); | |
895 | ||
005f78cd AB |
896 | if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) { |
897 | struct fpsimd_state *st = ¤t->thread.fpsimd_state; | |
898 | ||
bc0ee476 | 899 | task_fpsimd_load(); |
50464185 | 900 | __this_cpu_write(fpsimd_last_state, st); |
005f78cd AB |
901 | st->cpu = smp_processor_id(); |
902 | } | |
cb84d11e DM |
903 | |
904 | local_bh_enable(); | |
005f78cd AB |
905 | } |
906 | ||
907 | /* | |
908 | * Load an updated userland FPSIMD state for 'current' from memory and set the | |
909 | * flag that indicates that the FPSIMD register contents are the most recent | |
910 | * FPSIMD state of 'current' | |
c51f9269 AB |
911 | */ |
912 | void fpsimd_update_current_state(struct fpsimd_state *state) | |
913 | { | |
82e0191a SP |
914 | if (!system_supports_fpsimd()) |
915 | return; | |
cb84d11e DM |
916 | |
917 | local_bh_disable(); | |
918 | ||
8cd969d2 DM |
919 | if (system_supports_sve() && test_thread_flag(TIF_SVE)) { |
920 | current->thread.fpsimd_state = *state; | |
921 | fpsimd_to_sve(current); | |
922 | } | |
923 | task_fpsimd_load(); | |
924 | ||
005f78cd AB |
925 | if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) { |
926 | struct fpsimd_state *st = ¤t->thread.fpsimd_state; | |
927 | ||
50464185 | 928 | __this_cpu_write(fpsimd_last_state, st); |
005f78cd AB |
929 | st->cpu = smp_processor_id(); |
930 | } | |
cb84d11e DM |
931 | |
932 | local_bh_enable(); | |
c51f9269 AB |
933 | } |
934 | ||
005f78cd AB |
935 | /* |
936 | * Invalidate live CPU copies of task t's FPSIMD state | |
937 | */ | |
938 | void fpsimd_flush_task_state(struct task_struct *t) | |
939 | { | |
940 | t->thread.fpsimd_state.cpu = NR_CPUS; | |
941 | } | |
942 | ||
4cfb3613 AB |
943 | #ifdef CONFIG_KERNEL_MODE_NEON |
944 | ||
cb84d11e | 945 | DEFINE_PER_CPU(bool, kernel_neon_busy); |
11cefd5a | 946 | EXPORT_PER_CPU_SYMBOL(kernel_neon_busy); |
190f1ca8 | 947 | |
4cfb3613 AB |
948 | /* |
949 | * Kernel-side NEON support functions | |
950 | */ | |
cb84d11e DM |
951 | |
952 | /* | |
953 | * kernel_neon_begin(): obtain the CPU FPSIMD registers for use by the calling | |
954 | * context | |
955 | * | |
956 | * Must not be called unless may_use_simd() returns true. | |
957 | * Task context in the FPSIMD registers is saved back to memory as necessary. | |
958 | * | |
959 | * A matching call to kernel_neon_end() must be made before returning from the | |
960 | * calling context. | |
961 | * | |
962 | * The caller may freely use the FPSIMD registers until kernel_neon_end() is | |
963 | * called. | |
964 | */ | |
965 | void kernel_neon_begin(void) | |
4cfb3613 | 966 | { |
82e0191a SP |
967 | if (WARN_ON(!system_supports_fpsimd())) |
968 | return; | |
4cfb3613 | 969 | |
cb84d11e DM |
970 | BUG_ON(!may_use_simd()); |
971 | ||
972 | local_bh_disable(); | |
973 | ||
974 | __this_cpu_write(kernel_neon_busy, true); | |
975 | ||
976 | /* Save unsaved task fpsimd state, if any: */ | |
1bd3f936 DM |
977 | if (current->mm) { |
978 | task_fpsimd_save(); | |
979 | set_thread_flag(TIF_FOREIGN_FPSTATE); | |
980 | } | |
cb84d11e DM |
981 | |
982 | /* Invalidate any task state remaining in the fpsimd regs: */ | |
983 | __this_cpu_write(fpsimd_last_state, NULL); | |
984 | ||
985 | preempt_disable(); | |
986 | ||
987 | local_bh_enable(); | |
4cfb3613 | 988 | } |
cb84d11e | 989 | EXPORT_SYMBOL(kernel_neon_begin); |
4cfb3613 | 990 | |
cb84d11e DM |
991 | /* |
992 | * kernel_neon_end(): give the CPU FPSIMD registers back to the current task | |
993 | * | |
994 | * Must be called from a context in which kernel_neon_begin() was previously | |
995 | * called, with no call to kernel_neon_end() in the meantime. | |
996 | * | |
997 | * The caller must not use the FPSIMD registers after this function is called, | |
998 | * unless kernel_neon_begin() is called again in the meantime. | |
999 | */ | |
4cfb3613 AB |
1000 | void kernel_neon_end(void) |
1001 | { | |
cb84d11e DM |
1002 | bool busy; |
1003 | ||
82e0191a SP |
1004 | if (!system_supports_fpsimd()) |
1005 | return; | |
cb84d11e DM |
1006 | |
1007 | busy = __this_cpu_xchg(kernel_neon_busy, false); | |
1008 | WARN_ON(!busy); /* No matching kernel_neon_begin()? */ | |
1009 | ||
1010 | preempt_enable(); | |
4cfb3613 AB |
1011 | } |
1012 | EXPORT_SYMBOL(kernel_neon_end); | |
1013 | ||
e580b8bc DM |
1014 | #ifdef CONFIG_EFI |
1015 | ||
3b66023d DM |
1016 | static DEFINE_PER_CPU(struct fpsimd_state, efi_fpsimd_state); |
1017 | static DEFINE_PER_CPU(bool, efi_fpsimd_state_used); | |
fdfa976c | 1018 | static DEFINE_PER_CPU(bool, efi_sve_state_used); |
4328825d DM |
1019 | |
1020 | /* | |
1021 | * EFI runtime services support functions | |
1022 | * | |
1023 | * The ABI for EFI runtime services allows EFI to use FPSIMD during the call. | |
1024 | * This means that for EFI (and only for EFI), we have to assume that FPSIMD | |
1025 | * is always used rather than being an optional accelerator. | |
1026 | * | |
1027 | * These functions provide the necessary support for ensuring FPSIMD | |
1028 | * save/restore in the contexts from which EFI is used. | |
1029 | * | |
1030 | * Do not use them for any other purpose -- if tempted to do so, you are | |
1031 | * either doing something wrong or you need to propose some refactoring. | |
1032 | */ | |
1033 | ||
1034 | /* | |
1035 | * __efi_fpsimd_begin(): prepare FPSIMD for making an EFI runtime services call | |
1036 | */ | |
1037 | void __efi_fpsimd_begin(void) | |
1038 | { | |
1039 | if (!system_supports_fpsimd()) | |
1040 | return; | |
1041 | ||
1042 | WARN_ON(preemptible()); | |
1043 | ||
fdfa976c | 1044 | if (may_use_simd()) { |
4328825d | 1045 | kernel_neon_begin(); |
fdfa976c DM |
1046 | } else { |
1047 | /* | |
1048 | * If !efi_sve_state, SVE can't be in use yet and doesn't need | |
1049 | * preserving: | |
1050 | */ | |
1051 | if (system_supports_sve() && likely(efi_sve_state)) { | |
1052 | char *sve_state = this_cpu_ptr(efi_sve_state); | |
1053 | ||
1054 | __this_cpu_write(efi_sve_state_used, true); | |
1055 | ||
1056 | sve_save_state(sve_state + sve_ffr_offset(sve_max_vl), | |
1057 | &this_cpu_ptr(&efi_fpsimd_state)->fpsr); | |
1058 | } else { | |
1059 | fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state)); | |
1060 | } | |
1061 | ||
4328825d DM |
1062 | __this_cpu_write(efi_fpsimd_state_used, true); |
1063 | } | |
1064 | } | |
1065 | ||
1066 | /* | |
1067 | * __efi_fpsimd_end(): clean up FPSIMD after an EFI runtime services call | |
1068 | */ | |
1069 | void __efi_fpsimd_end(void) | |
1070 | { | |
1071 | if (!system_supports_fpsimd()) | |
1072 | return; | |
1073 | ||
fdfa976c | 1074 | if (!__this_cpu_xchg(efi_fpsimd_state_used, false)) { |
4328825d | 1075 | kernel_neon_end(); |
fdfa976c DM |
1076 | } else { |
1077 | if (system_supports_sve() && | |
1078 | likely(__this_cpu_read(efi_sve_state_used))) { | |
1079 | char const *sve_state = this_cpu_ptr(efi_sve_state); | |
1080 | ||
1081 | sve_load_state(sve_state + sve_ffr_offset(sve_max_vl), | |
1082 | &this_cpu_ptr(&efi_fpsimd_state)->fpsr, | |
1083 | sve_vq_from_vl(sve_get_vl()) - 1); | |
1084 | ||
1085 | __this_cpu_write(efi_sve_state_used, false); | |
1086 | } else { | |
1087 | fpsimd_load_state(this_cpu_ptr(&efi_fpsimd_state)); | |
1088 | } | |
1089 | } | |
4328825d DM |
1090 | } |
1091 | ||
e580b8bc DM |
1092 | #endif /* CONFIG_EFI */ |
1093 | ||
4cfb3613 AB |
1094 | #endif /* CONFIG_KERNEL_MODE_NEON */ |
1095 | ||
fb1ab1ab LP |
1096 | #ifdef CONFIG_CPU_PM |
1097 | static int fpsimd_cpu_pm_notifier(struct notifier_block *self, | |
1098 | unsigned long cmd, void *v) | |
1099 | { | |
1100 | switch (cmd) { | |
1101 | case CPU_PM_ENTER: | |
bc0ee476 DM |
1102 | if (current->mm) |
1103 | task_fpsimd_save(); | |
7c68a9cc | 1104 | this_cpu_write(fpsimd_last_state, NULL); |
fb1ab1ab LP |
1105 | break; |
1106 | case CPU_PM_EXIT: | |
1107 | if (current->mm) | |
005f78cd | 1108 | set_thread_flag(TIF_FOREIGN_FPSTATE); |
fb1ab1ab LP |
1109 | break; |
1110 | case CPU_PM_ENTER_FAILED: | |
1111 | default: | |
1112 | return NOTIFY_DONE; | |
1113 | } | |
1114 | return NOTIFY_OK; | |
1115 | } | |
1116 | ||
1117 | static struct notifier_block fpsimd_cpu_pm_notifier_block = { | |
1118 | .notifier_call = fpsimd_cpu_pm_notifier, | |
1119 | }; | |
1120 | ||
a7c61a34 | 1121 | static void __init fpsimd_pm_init(void) |
fb1ab1ab LP |
1122 | { |
1123 | cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block); | |
1124 | } | |
1125 | ||
1126 | #else | |
1127 | static inline void fpsimd_pm_init(void) { } | |
1128 | #endif /* CONFIG_CPU_PM */ | |
1129 | ||
32365e64 | 1130 | #ifdef CONFIG_HOTPLUG_CPU |
c23a7266 | 1131 | static int fpsimd_cpu_dead(unsigned int cpu) |
32365e64 | 1132 | { |
c23a7266 SAS |
1133 | per_cpu(fpsimd_last_state, cpu) = NULL; |
1134 | return 0; | |
32365e64 JL |
1135 | } |
1136 | ||
32365e64 JL |
1137 | static inline void fpsimd_hotplug_init(void) |
1138 | { | |
c23a7266 SAS |
1139 | cpuhp_setup_state_nocalls(CPUHP_ARM64_FPSIMD_DEAD, "arm64/fpsimd:dead", |
1140 | NULL, fpsimd_cpu_dead); | |
32365e64 JL |
1141 | } |
1142 | ||
1143 | #else | |
1144 | static inline void fpsimd_hotplug_init(void) { } | |
1145 | #endif | |
1146 | ||
53631b54 CM |
1147 | /* |
1148 | * FP/SIMD support code initialisation. | |
1149 | */ | |
1150 | static int __init fpsimd_init(void) | |
1151 | { | |
fe80f9f2 SP |
1152 | if (elf_hwcap & HWCAP_FP) { |
1153 | fpsimd_pm_init(); | |
1154 | fpsimd_hotplug_init(); | |
1155 | } else { | |
53631b54 | 1156 | pr_notice("Floating-point is not implemented\n"); |
53631b54 | 1157 | } |
53631b54 | 1158 | |
fe80f9f2 | 1159 | if (!(elf_hwcap & HWCAP_ASIMD)) |
53631b54 | 1160 | pr_notice("Advanced SIMD is not implemented\n"); |
fb1ab1ab | 1161 | |
53631b54 CM |
1162 | return 0; |
1163 | } | |
1164 | late_initcall(fpsimd_init); |