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53631b54 CM |
1 | /* |
2 | * FP/SIMD context switching and fault handling | |
3 | * | |
4 | * Copyright (C) 2012 ARM Ltd. | |
5 | * Author: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
7582e220 | 20 | #include <linux/bitmap.h> |
cb84d11e | 21 | #include <linux/bottom_half.h> |
bc0ee476 | 22 | #include <linux/bug.h> |
7582e220 | 23 | #include <linux/cache.h> |
bc0ee476 | 24 | #include <linux/compat.h> |
32365e64 | 25 | #include <linux/cpu.h> |
fb1ab1ab | 26 | #include <linux/cpu_pm.h> |
53631b54 | 27 | #include <linux/kernel.h> |
94ef7ecb | 28 | #include <linux/linkage.h> |
bc0ee476 | 29 | #include <linux/irqflags.h> |
53631b54 | 30 | #include <linux/init.h> |
cb84d11e | 31 | #include <linux/percpu.h> |
2d2123bc | 32 | #include <linux/prctl.h> |
4328825d | 33 | #include <linux/preempt.h> |
bc0ee476 | 34 | #include <linux/ptrace.h> |
3f07c014 | 35 | #include <linux/sched/signal.h> |
bc0ee476 | 36 | #include <linux/sched/task_stack.h> |
53631b54 | 37 | #include <linux/signal.h> |
bc0ee476 | 38 | #include <linux/slab.h> |
31dc52b3 | 39 | #include <linux/stddef.h> |
4ffa09a9 | 40 | #include <linux/sysctl.h> |
53631b54 | 41 | |
af4a81b9 | 42 | #include <asm/esr.h> |
53631b54 | 43 | #include <asm/fpsimd.h> |
c0cda3b8 | 44 | #include <asm/cpufeature.h> |
53631b54 | 45 | #include <asm/cputype.h> |
2cf97d46 | 46 | #include <asm/processor.h> |
4328825d | 47 | #include <asm/simd.h> |
bc0ee476 DM |
48 | #include <asm/sigcontext.h> |
49 | #include <asm/sysreg.h> | |
50 | #include <asm/traps.h> | |
53631b54 CM |
51 | |
52 | #define FPEXC_IOF (1 << 0) | |
53 | #define FPEXC_DZF (1 << 1) | |
54 | #define FPEXC_OFF (1 << 2) | |
55 | #define FPEXC_UFF (1 << 3) | |
56 | #define FPEXC_IXF (1 << 4) | |
57 | #define FPEXC_IDF (1 << 7) | |
58 | ||
005f78cd | 59 | /* |
bc0ee476 DM |
60 | * (Note: in this discussion, statements about FPSIMD apply equally to SVE.) |
61 | * | |
005f78cd AB |
62 | * In order to reduce the number of times the FPSIMD state is needlessly saved |
63 | * and restored, we need to keep track of two things: | |
64 | * (a) for each task, we need to remember which CPU was the last one to have | |
65 | * the task's FPSIMD state loaded into its FPSIMD registers; | |
66 | * (b) for each CPU, we need to remember which task's userland FPSIMD state has | |
67 | * been loaded into its FPSIMD registers most recently, or whether it has | |
68 | * been used to perform kernel mode NEON in the meantime. | |
69 | * | |
20b85472 | 70 | * For (a), we add a fpsimd_cpu field to thread_struct, which gets updated to |
ef769e32 | 71 | * the id of the current CPU every time the state is loaded onto a CPU. For (b), |
005f78cd AB |
72 | * we add the per-cpu variable 'fpsimd_last_state' (below), which contains the |
73 | * address of the userland FPSIMD state of the task that was loaded onto the CPU | |
74 | * the most recently, or NULL if kernel mode NEON has been performed after that. | |
75 | * | |
76 | * With this in place, we no longer have to restore the next FPSIMD state right | |
77 | * when switching between tasks. Instead, we can defer this check to userland | |
78 | * resume, at which time we verify whether the CPU's fpsimd_last_state and the | |
20b85472 | 79 | * task's fpsimd_cpu are still mutually in sync. If this is the case, we |
005f78cd AB |
80 | * can omit the FPSIMD restore. |
81 | * | |
82 | * As an optimization, we use the thread_info flag TIF_FOREIGN_FPSTATE to | |
83 | * indicate whether or not the userland FPSIMD state of the current task is | |
84 | * present in the registers. The flag is set unless the FPSIMD registers of this | |
85 | * CPU currently contain the most recent userland FPSIMD state of the current | |
86 | * task. | |
87 | * | |
cb84d11e DM |
88 | * In order to allow softirq handlers to use FPSIMD, kernel_neon_begin() may |
89 | * save the task's FPSIMD context back to task_struct from softirq context. | |
90 | * To prevent this from racing with the manipulation of the task's FPSIMD state | |
91 | * from task context and thereby corrupting the state, it is necessary to | |
92 | * protect any manipulation of a task's fpsimd_state or TIF_FOREIGN_FPSTATE | |
93 | * flag with local_bh_disable() unless softirqs are already masked. | |
94 | * | |
005f78cd | 95 | * For a certain task, the sequence may look something like this: |
20b85472 | 96 | * - the task gets scheduled in; if both the task's fpsimd_cpu field |
005f78cd AB |
97 | * contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu |
98 | * variable points to the task's fpsimd_state, the TIF_FOREIGN_FPSTATE flag is | |
99 | * cleared, otherwise it is set; | |
100 | * | |
101 | * - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's | |
102 | * userland FPSIMD state is copied from memory to the registers, the task's | |
20b85472 | 103 | * fpsimd_cpu field is set to the id of the current CPU, the current |
005f78cd AB |
104 | * CPU's fpsimd_last_state pointer is set to this task's fpsimd_state and the |
105 | * TIF_FOREIGN_FPSTATE flag is cleared; | |
106 | * | |
107 | * - the task executes an ordinary syscall; upon return to userland, the | |
108 | * TIF_FOREIGN_FPSTATE flag will still be cleared, so no FPSIMD state is | |
109 | * restored; | |
110 | * | |
111 | * - the task executes a syscall which executes some NEON instructions; this is | |
112 | * preceded by a call to kernel_neon_begin(), which copies the task's FPSIMD | |
113 | * register contents to memory, clears the fpsimd_last_state per-cpu variable | |
114 | * and sets the TIF_FOREIGN_FPSTATE flag; | |
115 | * | |
116 | * - the task gets preempted after kernel_neon_end() is called; as we have not | |
117 | * returned from the 2nd syscall yet, TIF_FOREIGN_FPSTATE is still set so | |
118 | * whatever is in the FPSIMD registers is not saved to memory, but discarded. | |
119 | */ | |
cb968afc | 120 | struct fpsimd_last_state_struct { |
20b85472 | 121 | struct user_fpsimd_state *st; |
cb968afc DM |
122 | }; |
123 | ||
124 | static DEFINE_PER_CPU(struct fpsimd_last_state_struct, fpsimd_last_state); | |
005f78cd | 125 | |
79ab047c | 126 | /* Default VL for tasks that don't set it explicitly: */ |
2e0f2478 | 127 | static int sve_default_vl = -1; |
79ab047c | 128 | |
7582e220 DM |
129 | #ifdef CONFIG_ARM64_SVE |
130 | ||
131 | /* Maximum supported vector length across all CPUs (initially poisoned) */ | |
87c021a8 | 132 | int __ro_after_init sve_max_vl = SVE_VL_MIN; |
7582e220 | 133 | /* Set of available vector lengths, as vq_to_bit(vq): */ |
2e0f2478 | 134 | static __ro_after_init DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX); |
fdfa976c | 135 | static void __percpu *efi_sve_state; |
7582e220 DM |
136 | |
137 | #else /* ! CONFIG_ARM64_SVE */ | |
138 | ||
139 | /* Dummy declaration for code that will be optimised out: */ | |
2e0f2478 | 140 | extern __ro_after_init DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX); |
fdfa976c | 141 | extern void __percpu *efi_sve_state; |
7582e220 DM |
142 | |
143 | #endif /* ! CONFIG_ARM64_SVE */ | |
144 | ||
bc0ee476 DM |
145 | /* |
146 | * Call __sve_free() directly only if you know task can't be scheduled | |
147 | * or preempted. | |
148 | */ | |
149 | static void __sve_free(struct task_struct *task) | |
150 | { | |
151 | kfree(task->thread.sve_state); | |
152 | task->thread.sve_state = NULL; | |
153 | } | |
154 | ||
155 | static void sve_free(struct task_struct *task) | |
156 | { | |
157 | WARN_ON(test_tsk_thread_flag(task, TIF_SVE)); | |
158 | ||
159 | __sve_free(task); | |
160 | } | |
161 | ||
bc0ee476 DM |
162 | /* |
163 | * TIF_SVE controls whether a task can use SVE without trapping while | |
164 | * in userspace, and also the way a task's FPSIMD/SVE state is stored | |
165 | * in thread_struct. | |
166 | * | |
167 | * The kernel uses this flag to track whether a user task is actively | |
168 | * using SVE, and therefore whether full SVE register state needs to | |
169 | * be tracked. If not, the cheaper FPSIMD context handling code can | |
170 | * be used instead of the more costly SVE equivalents. | |
171 | * | |
172 | * * TIF_SVE set: | |
173 | * | |
174 | * The task can execute SVE instructions while in userspace without | |
175 | * trapping to the kernel. | |
176 | * | |
177 | * When stored, Z0-Z31 (incorporating Vn in bits[127:0] or the | |
178 | * corresponding Zn), P0-P15 and FFR are encoded in in | |
179 | * task->thread.sve_state, formatted appropriately for vector | |
180 | * length task->thread.sve_vl. | |
181 | * | |
182 | * task->thread.sve_state must point to a valid buffer at least | |
183 | * sve_state_size(task) bytes in size. | |
184 | * | |
185 | * During any syscall, the kernel may optionally clear TIF_SVE and | |
186 | * discard the vector state except for the FPSIMD subset. | |
187 | * | |
188 | * * TIF_SVE clear: | |
189 | * | |
190 | * An attempt by the user task to execute an SVE instruction causes | |
191 | * do_sve_acc() to be called, which does some preparation and then | |
192 | * sets TIF_SVE. | |
193 | * | |
194 | * When stored, FPSIMD registers V0-V31 are encoded in | |
65896545 | 195 | * task->thread.uw.fpsimd_state; bits [max : 128] for each of Z0-Z31 are |
bc0ee476 DM |
196 | * logically zero but not stored anywhere; P0-P15 and FFR are not |
197 | * stored and have unspecified values from userspace's point of | |
198 | * view. For hygiene purposes, the kernel zeroes them on next use, | |
199 | * but userspace is discouraged from relying on this. | |
200 | * | |
201 | * task->thread.sve_state does not need to be non-NULL, valid or any | |
202 | * particular size: it must not be dereferenced. | |
203 | * | |
65896545 DM |
204 | * * FPSR and FPCR are always stored in task->thread.uw.fpsimd_state |
205 | * irrespective of whether TIF_SVE is clear or set, since these are | |
206 | * not vector length dependent. | |
bc0ee476 DM |
207 | */ |
208 | ||
209 | /* | |
210 | * Update current's FPSIMD/SVE registers from thread_struct. | |
211 | * | |
212 | * This function should be called only when the FPSIMD/SVE state in | |
213 | * thread_struct is known to be up to date, when preparing to enter | |
214 | * userspace. | |
215 | * | |
216 | * Softirqs (and preemption) must be disabled. | |
217 | */ | |
218 | static void task_fpsimd_load(void) | |
219 | { | |
220 | WARN_ON(!in_softirq() && !irqs_disabled()); | |
221 | ||
222 | if (system_supports_sve() && test_thread_flag(TIF_SVE)) | |
2cf97d46 | 223 | sve_load_state(sve_pffr(¤t->thread), |
65896545 | 224 | ¤t->thread.uw.fpsimd_state.fpsr, |
bc0ee476 DM |
225 | sve_vq_from_vl(current->thread.sve_vl) - 1); |
226 | else | |
65896545 | 227 | fpsimd_load_state(¤t->thread.uw.fpsimd_state); |
bc0ee476 DM |
228 | } |
229 | ||
230 | /* | |
d1797615 DM |
231 | * Ensure FPSIMD/SVE storage in memory for the loaded context is up to |
232 | * date with respect to the CPU registers. | |
bc0ee476 DM |
233 | * |
234 | * Softirqs (and preemption) must be disabled. | |
235 | */ | |
e6b673b7 | 236 | void fpsimd_save(void) |
bc0ee476 | 237 | { |
d1797615 | 238 | struct user_fpsimd_state *st = __this_cpu_read(fpsimd_last_state.st); |
e6b673b7 | 239 | /* set by fpsimd_bind_task_to_cpu() or fpsimd_bind_state_to_cpu() */ |
d1797615 | 240 | |
bc0ee476 DM |
241 | WARN_ON(!in_softirq() && !irqs_disabled()); |
242 | ||
243 | if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) { | |
244 | if (system_supports_sve() && test_thread_flag(TIF_SVE)) { | |
245 | if (WARN_ON(sve_get_vl() != current->thread.sve_vl)) { | |
246 | /* | |
247 | * Can't save the user regs, so current would | |
248 | * re-enter user with corrupt state. | |
249 | * There's no way to recover, so kill it: | |
250 | */ | |
af40ff68 | 251 | force_signal_inject(SIGKILL, SI_KERNEL, 0); |
bc0ee476 DM |
252 | return; |
253 | } | |
254 | ||
2cf97d46 | 255 | sve_save_state(sve_pffr(¤t->thread), &st->fpsr); |
bc0ee476 | 256 | } else |
d1797615 | 257 | fpsimd_save_state(st); |
bc0ee476 DM |
258 | } |
259 | } | |
260 | ||
7582e220 DM |
261 | /* |
262 | * Helpers to translate bit indices in sve_vq_map to VQ values (and | |
263 | * vice versa). This allows find_next_bit() to be used to find the | |
264 | * _maximum_ VQ not exceeding a certain value. | |
265 | */ | |
266 | ||
267 | static unsigned int vq_to_bit(unsigned int vq) | |
268 | { | |
269 | return SVE_VQ_MAX - vq; | |
270 | } | |
271 | ||
272 | static unsigned int bit_to_vq(unsigned int bit) | |
273 | { | |
274 | if (WARN_ON(bit >= SVE_VQ_MAX)) | |
275 | bit = SVE_VQ_MAX - 1; | |
276 | ||
277 | return SVE_VQ_MAX - bit; | |
278 | } | |
279 | ||
280 | /* | |
281 | * All vector length selection from userspace comes through here. | |
282 | * We're on a slow path, so some sanity-checks are included. | |
283 | * If things go wrong there's a bug somewhere, but try to fall back to a | |
284 | * safe choice. | |
285 | */ | |
286 | static unsigned int find_supported_vector_length(unsigned int vl) | |
287 | { | |
288 | int bit; | |
289 | int max_vl = sve_max_vl; | |
290 | ||
291 | if (WARN_ON(!sve_vl_valid(vl))) | |
292 | vl = SVE_VL_MIN; | |
293 | ||
294 | if (WARN_ON(!sve_vl_valid(max_vl))) | |
295 | max_vl = SVE_VL_MIN; | |
296 | ||
297 | if (vl > max_vl) | |
298 | vl = max_vl; | |
299 | ||
300 | bit = find_next_bit(sve_vq_map, SVE_VQ_MAX, | |
301 | vq_to_bit(sve_vq_from_vl(vl))); | |
302 | return sve_vl_from_vq(bit_to_vq(bit)); | |
303 | } | |
304 | ||
4ffa09a9 DM |
305 | #ifdef CONFIG_SYSCTL |
306 | ||
307 | static int sve_proc_do_default_vl(struct ctl_table *table, int write, | |
308 | void __user *buffer, size_t *lenp, | |
309 | loff_t *ppos) | |
310 | { | |
311 | int ret; | |
312 | int vl = sve_default_vl; | |
313 | struct ctl_table tmp_table = { | |
314 | .data = &vl, | |
315 | .maxlen = sizeof(vl), | |
316 | }; | |
317 | ||
318 | ret = proc_dointvec(&tmp_table, write, buffer, lenp, ppos); | |
319 | if (ret || !write) | |
320 | return ret; | |
321 | ||
322 | /* Writing -1 has the special meaning "set to max": */ | |
87c021a8 DM |
323 | if (vl == -1) |
324 | vl = sve_max_vl; | |
4ffa09a9 DM |
325 | |
326 | if (!sve_vl_valid(vl)) | |
327 | return -EINVAL; | |
328 | ||
87c021a8 | 329 | sve_default_vl = find_supported_vector_length(vl); |
4ffa09a9 DM |
330 | return 0; |
331 | } | |
332 | ||
333 | static struct ctl_table sve_default_vl_table[] = { | |
334 | { | |
335 | .procname = "sve_default_vector_length", | |
336 | .mode = 0644, | |
337 | .proc_handler = sve_proc_do_default_vl, | |
338 | }, | |
339 | { } | |
340 | }; | |
341 | ||
342 | static int __init sve_sysctl_init(void) | |
343 | { | |
344 | if (system_supports_sve()) | |
345 | if (!register_sysctl("abi", sve_default_vl_table)) | |
346 | return -EINVAL; | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
351 | #else /* ! CONFIG_SYSCTL */ | |
352 | static int __init sve_sysctl_init(void) { return 0; } | |
353 | #endif /* ! CONFIG_SYSCTL */ | |
354 | ||
bc0ee476 DM |
355 | #define ZREG(sve_state, vq, n) ((char *)(sve_state) + \ |
356 | (SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET)) | |
357 | ||
358 | /* | |
65896545 | 359 | * Transfer the FPSIMD state in task->thread.uw.fpsimd_state to |
bc0ee476 DM |
360 | * task->thread.sve_state. |
361 | * | |
362 | * Task can be a non-runnable task, or current. In the latter case, | |
363 | * softirqs (and preemption) must be disabled. | |
364 | * task->thread.sve_state must point to at least sve_state_size(task) | |
365 | * bytes of allocated kernel memory. | |
65896545 DM |
366 | * task->thread.uw.fpsimd_state must be up to date before calling this |
367 | * function. | |
bc0ee476 DM |
368 | */ |
369 | static void fpsimd_to_sve(struct task_struct *task) | |
370 | { | |
371 | unsigned int vq; | |
372 | void *sst = task->thread.sve_state; | |
65896545 | 373 | struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; |
bc0ee476 DM |
374 | unsigned int i; |
375 | ||
376 | if (!system_supports_sve()) | |
377 | return; | |
378 | ||
379 | vq = sve_vq_from_vl(task->thread.sve_vl); | |
380 | for (i = 0; i < 32; ++i) | |
381 | memcpy(ZREG(sst, vq, i), &fst->vregs[i], | |
382 | sizeof(fst->vregs[i])); | |
383 | } | |
384 | ||
8cd969d2 DM |
385 | /* |
386 | * Transfer the SVE state in task->thread.sve_state to | |
65896545 | 387 | * task->thread.uw.fpsimd_state. |
8cd969d2 DM |
388 | * |
389 | * Task can be a non-runnable task, or current. In the latter case, | |
390 | * softirqs (and preemption) must be disabled. | |
391 | * task->thread.sve_state must point to at least sve_state_size(task) | |
392 | * bytes of allocated kernel memory. | |
393 | * task->thread.sve_state must be up to date before calling this function. | |
394 | */ | |
395 | static void sve_to_fpsimd(struct task_struct *task) | |
396 | { | |
397 | unsigned int vq; | |
398 | void const *sst = task->thread.sve_state; | |
65896545 | 399 | struct user_fpsimd_state *fst = &task->thread.uw.fpsimd_state; |
8cd969d2 DM |
400 | unsigned int i; |
401 | ||
402 | if (!system_supports_sve()) | |
403 | return; | |
404 | ||
405 | vq = sve_vq_from_vl(task->thread.sve_vl); | |
406 | for (i = 0; i < 32; ++i) | |
407 | memcpy(&fst->vregs[i], ZREG(sst, vq, i), | |
408 | sizeof(fst->vregs[i])); | |
409 | } | |
410 | ||
bc0ee476 DM |
411 | #ifdef CONFIG_ARM64_SVE |
412 | ||
413 | /* | |
414 | * Return how many bytes of memory are required to store the full SVE | |
415 | * state for task, given task's currently configured vector length. | |
416 | */ | |
417 | size_t sve_state_size(struct task_struct const *task) | |
418 | { | |
419 | return SVE_SIG_REGS_SIZE(sve_vq_from_vl(task->thread.sve_vl)); | |
420 | } | |
421 | ||
422 | /* | |
423 | * Ensure that task->thread.sve_state is allocated and sufficiently large. | |
424 | * | |
425 | * This function should be used only in preparation for replacing | |
426 | * task->thread.sve_state with new data. The memory is always zeroed | |
427 | * here to prevent stale data from showing through: this is done in | |
428 | * the interest of testability and predictability: except in the | |
429 | * do_sve_acc() case, there is no ABI requirement to hide stale data | |
430 | * written previously be task. | |
431 | */ | |
432 | void sve_alloc(struct task_struct *task) | |
433 | { | |
434 | if (task->thread.sve_state) { | |
435 | memset(task->thread.sve_state, 0, sve_state_size(current)); | |
436 | return; | |
437 | } | |
438 | ||
439 | /* This is a small allocation (maximum ~8KB) and Should Not Fail. */ | |
440 | task->thread.sve_state = | |
441 | kzalloc(sve_state_size(task), GFP_KERNEL); | |
442 | ||
443 | /* | |
444 | * If future SVE revisions can have larger vectors though, | |
445 | * this may cease to be true: | |
446 | */ | |
447 | BUG_ON(!task->thread.sve_state); | |
448 | } | |
449 | ||
43d4da2c DM |
450 | |
451 | /* | |
452 | * Ensure that task->thread.sve_state is up to date with respect to | |
453 | * the user task, irrespective of when SVE is in use or not. | |
454 | * | |
455 | * This should only be called by ptrace. task must be non-runnable. | |
456 | * task->thread.sve_state must point to at least sve_state_size(task) | |
457 | * bytes of allocated kernel memory. | |
458 | */ | |
459 | void fpsimd_sync_to_sve(struct task_struct *task) | |
460 | { | |
461 | if (!test_tsk_thread_flag(task, TIF_SVE)) | |
462 | fpsimd_to_sve(task); | |
463 | } | |
464 | ||
465 | /* | |
65896545 | 466 | * Ensure that task->thread.uw.fpsimd_state is up to date with respect to |
43d4da2c DM |
467 | * the user task, irrespective of whether SVE is in use or not. |
468 | * | |
469 | * This should only be called by ptrace. task must be non-runnable. | |
470 | * task->thread.sve_state must point to at least sve_state_size(task) | |
471 | * bytes of allocated kernel memory. | |
472 | */ | |
473 | void sve_sync_to_fpsimd(struct task_struct *task) | |
474 | { | |
475 | if (test_tsk_thread_flag(task, TIF_SVE)) | |
476 | sve_to_fpsimd(task); | |
477 | } | |
478 | ||
479 | /* | |
480 | * Ensure that task->thread.sve_state is up to date with respect to | |
65896545 | 481 | * the task->thread.uw.fpsimd_state. |
43d4da2c DM |
482 | * |
483 | * This should only be called by ptrace to merge new FPSIMD register | |
484 | * values into a task for which SVE is currently active. | |
485 | * task must be non-runnable. | |
486 | * task->thread.sve_state must point to at least sve_state_size(task) | |
487 | * bytes of allocated kernel memory. | |
65896545 | 488 | * task->thread.uw.fpsimd_state must already have been initialised with |
43d4da2c DM |
489 | * the new FPSIMD register values to be merged in. |
490 | */ | |
491 | void sve_sync_from_fpsimd_zeropad(struct task_struct *task) | |
492 | { | |
493 | unsigned int vq; | |
494 | void *sst = task->thread.sve_state; | |
65896545 | 495 | struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; |
43d4da2c DM |
496 | unsigned int i; |
497 | ||
498 | if (!test_tsk_thread_flag(task, TIF_SVE)) | |
499 | return; | |
500 | ||
501 | vq = sve_vq_from_vl(task->thread.sve_vl); | |
502 | ||
503 | memset(sst, 0, SVE_SIG_REGS_SIZE(vq)); | |
504 | ||
505 | for (i = 0; i < 32; ++i) | |
506 | memcpy(ZREG(sst, vq, i), &fst->vregs[i], | |
507 | sizeof(fst->vregs[i])); | |
508 | } | |
509 | ||
7582e220 DM |
510 | int sve_set_vector_length(struct task_struct *task, |
511 | unsigned long vl, unsigned long flags) | |
512 | { | |
513 | if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT | | |
514 | PR_SVE_SET_VL_ONEXEC)) | |
515 | return -EINVAL; | |
516 | ||
517 | if (!sve_vl_valid(vl)) | |
518 | return -EINVAL; | |
519 | ||
520 | /* | |
521 | * Clamp to the maximum vector length that VL-agnostic SVE code can | |
522 | * work with. A flag may be assigned in the future to allow setting | |
523 | * of larger vector lengths without confusing older software. | |
524 | */ | |
525 | if (vl > SVE_VL_ARCH_MAX) | |
526 | vl = SVE_VL_ARCH_MAX; | |
527 | ||
528 | vl = find_supported_vector_length(vl); | |
529 | ||
530 | if (flags & (PR_SVE_VL_INHERIT | | |
531 | PR_SVE_SET_VL_ONEXEC)) | |
532 | task->thread.sve_vl_onexec = vl; | |
533 | else | |
534 | /* Reset VL to system default on next exec: */ | |
535 | task->thread.sve_vl_onexec = 0; | |
536 | ||
537 | /* Only actually set the VL if not deferred: */ | |
538 | if (flags & PR_SVE_SET_VL_ONEXEC) | |
539 | goto out; | |
540 | ||
541 | if (vl == task->thread.sve_vl) | |
542 | goto out; | |
543 | ||
544 | /* | |
545 | * To ensure the FPSIMD bits of the SVE vector registers are preserved, | |
546 | * write any live register state back to task_struct, and convert to a | |
547 | * non-SVE thread. | |
548 | */ | |
549 | if (task == current) { | |
550 | local_bh_disable(); | |
551 | ||
d1797615 | 552 | fpsimd_save(); |
7582e220 DM |
553 | set_thread_flag(TIF_FOREIGN_FPSTATE); |
554 | } | |
555 | ||
556 | fpsimd_flush_task_state(task); | |
557 | if (test_and_clear_tsk_thread_flag(task, TIF_SVE)) | |
558 | sve_to_fpsimd(task); | |
559 | ||
560 | if (task == current) | |
561 | local_bh_enable(); | |
562 | ||
563 | /* | |
564 | * Force reallocation of task SVE state to the correct size | |
565 | * on next use: | |
566 | */ | |
567 | sve_free(task); | |
568 | ||
569 | task->thread.sve_vl = vl; | |
570 | ||
571 | out: | |
09d1223a DM |
572 | update_tsk_thread_flag(task, TIF_SVE_VL_INHERIT, |
573 | flags & PR_SVE_VL_INHERIT); | |
7582e220 DM |
574 | |
575 | return 0; | |
576 | } | |
577 | ||
2d2123bc DM |
578 | /* |
579 | * Encode the current vector length and flags for return. | |
580 | * This is only required for prctl(): ptrace has separate fields | |
581 | * | |
582 | * flags are as for sve_set_vector_length(). | |
583 | */ | |
584 | static int sve_prctl_status(unsigned long flags) | |
585 | { | |
586 | int ret; | |
587 | ||
588 | if (flags & PR_SVE_SET_VL_ONEXEC) | |
589 | ret = current->thread.sve_vl_onexec; | |
590 | else | |
591 | ret = current->thread.sve_vl; | |
592 | ||
593 | if (test_thread_flag(TIF_SVE_VL_INHERIT)) | |
594 | ret |= PR_SVE_VL_INHERIT; | |
595 | ||
596 | return ret; | |
597 | } | |
598 | ||
599 | /* PR_SVE_SET_VL */ | |
600 | int sve_set_current_vl(unsigned long arg) | |
601 | { | |
602 | unsigned long vl, flags; | |
603 | int ret; | |
604 | ||
605 | vl = arg & PR_SVE_VL_LEN_MASK; | |
606 | flags = arg & ~vl; | |
607 | ||
608 | if (!system_supports_sve()) | |
609 | return -EINVAL; | |
610 | ||
611 | ret = sve_set_vector_length(current, vl, flags); | |
612 | if (ret) | |
613 | return ret; | |
614 | ||
615 | return sve_prctl_status(flags); | |
616 | } | |
617 | ||
618 | /* PR_SVE_GET_VL */ | |
619 | int sve_get_current_vl(void) | |
620 | { | |
621 | if (!system_supports_sve()) | |
622 | return -EINVAL; | |
623 | ||
624 | return sve_prctl_status(0); | |
625 | } | |
626 | ||
2e0f2478 DM |
627 | /* |
628 | * Bitmap for temporary storage of the per-CPU set of supported vector lengths | |
629 | * during secondary boot. | |
630 | */ | |
631 | static DECLARE_BITMAP(sve_secondary_vq_map, SVE_VQ_MAX); | |
632 | ||
633 | static void sve_probe_vqs(DECLARE_BITMAP(map, SVE_VQ_MAX)) | |
634 | { | |
635 | unsigned int vq, vl; | |
636 | unsigned long zcr; | |
637 | ||
638 | bitmap_zero(map, SVE_VQ_MAX); | |
639 | ||
640 | zcr = ZCR_ELx_LEN_MASK; | |
641 | zcr = read_sysreg_s(SYS_ZCR_EL1) & ~zcr; | |
642 | ||
643 | for (vq = SVE_VQ_MAX; vq >= SVE_VQ_MIN; --vq) { | |
644 | write_sysreg_s(zcr | (vq - 1), SYS_ZCR_EL1); /* self-syncing */ | |
645 | vl = sve_get_vl(); | |
646 | vq = sve_vq_from_vl(vl); /* skip intervening lengths */ | |
647 | set_bit(vq_to_bit(vq), map); | |
648 | } | |
649 | } | |
650 | ||
651 | void __init sve_init_vq_map(void) | |
652 | { | |
653 | sve_probe_vqs(sve_vq_map); | |
654 | } | |
655 | ||
656 | /* | |
657 | * If we haven't committed to the set of supported VQs yet, filter out | |
658 | * those not supported by the current CPU. | |
659 | */ | |
660 | void sve_update_vq_map(void) | |
661 | { | |
662 | sve_probe_vqs(sve_secondary_vq_map); | |
663 | bitmap_and(sve_vq_map, sve_vq_map, sve_secondary_vq_map, SVE_VQ_MAX); | |
664 | } | |
665 | ||
666 | /* Check whether the current CPU supports all VQs in the committed set */ | |
667 | int sve_verify_vq_map(void) | |
668 | { | |
669 | int ret = 0; | |
670 | ||
671 | sve_probe_vqs(sve_secondary_vq_map); | |
672 | bitmap_andnot(sve_secondary_vq_map, sve_vq_map, sve_secondary_vq_map, | |
673 | SVE_VQ_MAX); | |
674 | if (!bitmap_empty(sve_secondary_vq_map, SVE_VQ_MAX)) { | |
675 | pr_warn("SVE: cpu%d: Required vector length(s) missing\n", | |
676 | smp_processor_id()); | |
677 | ret = -EINVAL; | |
678 | } | |
679 | ||
680 | return ret; | |
681 | } | |
682 | ||
fdfa976c DM |
683 | static void __init sve_efi_setup(void) |
684 | { | |
685 | if (!IS_ENABLED(CONFIG_EFI)) | |
686 | return; | |
687 | ||
688 | /* | |
689 | * alloc_percpu() warns and prints a backtrace if this goes wrong. | |
690 | * This is evidence of a crippled system and we are returning void, | |
691 | * so no attempt is made to handle this situation here. | |
692 | */ | |
693 | if (!sve_vl_valid(sve_max_vl)) | |
694 | goto fail; | |
695 | ||
696 | efi_sve_state = __alloc_percpu( | |
697 | SVE_SIG_REGS_SIZE(sve_vq_from_vl(sve_max_vl)), SVE_VQ_BYTES); | |
698 | if (!efi_sve_state) | |
699 | goto fail; | |
700 | ||
701 | return; | |
702 | ||
703 | fail: | |
704 | panic("Cannot allocate percpu memory for EFI SVE save/restore"); | |
705 | } | |
706 | ||
2e0f2478 DM |
707 | /* |
708 | * Enable SVE for EL1. | |
709 | * Intended for use by the cpufeatures code during CPU boot. | |
710 | */ | |
c0cda3b8 | 711 | void sve_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) |
2e0f2478 DM |
712 | { |
713 | write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1); | |
714 | isb(); | |
2e0f2478 DM |
715 | } |
716 | ||
31dc52b3 DM |
717 | /* |
718 | * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE | |
719 | * vector length. | |
720 | * | |
721 | * Use only if SVE is present. | |
722 | * This function clobbers the SVE vector length. | |
723 | */ | |
724 | u64 read_zcr_features(void) | |
725 | { | |
726 | u64 zcr; | |
727 | unsigned int vq_max; | |
728 | ||
729 | /* | |
730 | * Set the maximum possible VL, and write zeroes to all other | |
731 | * bits to see if they stick. | |
732 | */ | |
733 | sve_kernel_enable(NULL); | |
734 | write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); | |
735 | ||
736 | zcr = read_sysreg_s(SYS_ZCR_EL1); | |
737 | zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* find sticky 1s outside LEN field */ | |
738 | vq_max = sve_vq_from_vl(sve_get_vl()); | |
739 | zcr |= vq_max - 1; /* set LEN field to maximum effective value */ | |
740 | ||
741 | return zcr; | |
742 | } | |
743 | ||
2e0f2478 DM |
744 | void __init sve_setup(void) |
745 | { | |
746 | u64 zcr; | |
747 | ||
748 | if (!system_supports_sve()) | |
749 | return; | |
750 | ||
751 | /* | |
752 | * The SVE architecture mandates support for 128-bit vectors, | |
753 | * so sve_vq_map must have at least SVE_VQ_MIN set. | |
754 | * If something went wrong, at least try to patch it up: | |
755 | */ | |
756 | if (WARN_ON(!test_bit(vq_to_bit(SVE_VQ_MIN), sve_vq_map))) | |
757 | set_bit(vq_to_bit(SVE_VQ_MIN), sve_vq_map); | |
758 | ||
759 | zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); | |
760 | sve_max_vl = sve_vl_from_vq((zcr & ZCR_ELx_LEN_MASK) + 1); | |
761 | ||
762 | /* | |
763 | * Sanity-check that the max VL we determined through CPU features | |
764 | * corresponds properly to sve_vq_map. If not, do our best: | |
765 | */ | |
766 | if (WARN_ON(sve_max_vl != find_supported_vector_length(sve_max_vl))) | |
767 | sve_max_vl = find_supported_vector_length(sve_max_vl); | |
768 | ||
769 | /* | |
770 | * For the default VL, pick the maximum supported value <= 64. | |
771 | * VL == 64 is guaranteed not to grow the signal frame. | |
772 | */ | |
773 | sve_default_vl = find_supported_vector_length(64); | |
774 | ||
775 | pr_info("SVE: maximum available vector length %u bytes per vector\n", | |
776 | sve_max_vl); | |
777 | pr_info("SVE: default vector length %u bytes per vector\n", | |
778 | sve_default_vl); | |
fdfa976c DM |
779 | |
780 | sve_efi_setup(); | |
2e0f2478 DM |
781 | } |
782 | ||
bc0ee476 DM |
783 | /* |
784 | * Called from the put_task_struct() path, which cannot get here | |
785 | * unless dead_task is really dead and not schedulable. | |
786 | */ | |
787 | void fpsimd_release_task(struct task_struct *dead_task) | |
788 | { | |
789 | __sve_free(dead_task); | |
790 | } | |
791 | ||
792 | #endif /* CONFIG_ARM64_SVE */ | |
793 | ||
794 | /* | |
795 | * Trapped SVE access | |
796 | * | |
797 | * Storage is allocated for the full SVE state, the current FPSIMD | |
798 | * register contents are migrated across, and TIF_SVE is set so that | |
799 | * the SVE access trap will be disabled the next time this task | |
800 | * reaches ret_to_user. | |
801 | * | |
802 | * TIF_SVE should be clear on entry: otherwise, task_fpsimd_load() | |
803 | * would have disabled the SVE access trap for userspace during | |
804 | * ret_to_user, making an SVE access trap impossible in that case. | |
805 | */ | |
806 | asmlinkage void do_sve_acc(unsigned int esr, struct pt_regs *regs) | |
807 | { | |
808 | /* Even if we chose not to use SVE, the hardware could still trap: */ | |
809 | if (unlikely(!system_supports_sve()) || WARN_ON(is_compat_task())) { | |
2c9120f3 | 810 | force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); |
bc0ee476 DM |
811 | return; |
812 | } | |
813 | ||
814 | sve_alloc(current); | |
815 | ||
816 | local_bh_disable(); | |
817 | ||
d1797615 | 818 | fpsimd_save(); |
bc0ee476 DM |
819 | fpsimd_to_sve(current); |
820 | ||
821 | /* Force ret_to_user to reload the registers: */ | |
822 | fpsimd_flush_task_state(current); | |
823 | set_thread_flag(TIF_FOREIGN_FPSTATE); | |
824 | ||
825 | if (test_and_set_thread_flag(TIF_SVE)) | |
826 | WARN_ON(1); /* SVE access shouldn't have trapped */ | |
827 | ||
828 | local_bh_enable(); | |
829 | } | |
830 | ||
53631b54 CM |
831 | /* |
832 | * Trapped FP/ASIMD access. | |
833 | */ | |
94ef7ecb | 834 | asmlinkage void do_fpsimd_acc(unsigned int esr, struct pt_regs *regs) |
53631b54 CM |
835 | { |
836 | /* TODO: implement lazy context saving/restoring */ | |
837 | WARN_ON(1); | |
838 | } | |
839 | ||
840 | /* | |
841 | * Raise a SIGFPE for the current process. | |
842 | */ | |
94ef7ecb | 843 | asmlinkage void do_fpsimd_exc(unsigned int esr, struct pt_regs *regs) |
53631b54 | 844 | { |
af4a81b9 DM |
845 | unsigned int si_code = FPE_FLTUNK; |
846 | ||
847 | if (esr & ESR_ELx_FP_EXC_TFV) { | |
848 | if (esr & FPEXC_IOF) | |
849 | si_code = FPE_FLTINV; | |
850 | else if (esr & FPEXC_DZF) | |
851 | si_code = FPE_FLTDIV; | |
852 | else if (esr & FPEXC_OFF) | |
853 | si_code = FPE_FLTOVF; | |
854 | else if (esr & FPEXC_UFF) | |
855 | si_code = FPE_FLTUND; | |
856 | else if (esr & FPEXC_IXF) | |
857 | si_code = FPE_FLTRES; | |
858 | } | |
53631b54 | 859 | |
c8526809 EB |
860 | send_sig_fault(SIGFPE, si_code, |
861 | (void __user *)instruction_pointer(regs), | |
862 | current); | |
53631b54 CM |
863 | } |
864 | ||
865 | void fpsimd_thread_switch(struct task_struct *next) | |
866 | { | |
df3fb968 DM |
867 | bool wrong_task, wrong_cpu; |
868 | ||
82e0191a SP |
869 | if (!system_supports_fpsimd()) |
870 | return; | |
df3fb968 DM |
871 | |
872 | /* Save unsaved fpsimd state, if any: */ | |
873 | fpsimd_save(); | |
874 | ||
005f78cd | 875 | /* |
df3fb968 DM |
876 | * Fix up TIF_FOREIGN_FPSTATE to correctly describe next's |
877 | * state. For kernel threads, FPSIMD registers are never loaded | |
878 | * and wrong_task and wrong_cpu will always be true. | |
005f78cd | 879 | */ |
df3fb968 | 880 | wrong_task = __this_cpu_read(fpsimd_last_state.st) != |
09d1223a | 881 | &next->thread.uw.fpsimd_state; |
df3fb968 | 882 | wrong_cpu = next->thread.fpsimd_cpu != smp_processor_id(); |
005f78cd | 883 | |
df3fb968 DM |
884 | update_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE, |
885 | wrong_task || wrong_cpu); | |
53631b54 CM |
886 | } |
887 | ||
888 | void fpsimd_flush_thread(void) | |
889 | { | |
7582e220 | 890 | int vl, supported_vl; |
bc0ee476 | 891 | |
82e0191a SP |
892 | if (!system_supports_fpsimd()) |
893 | return; | |
cb84d11e DM |
894 | |
895 | local_bh_disable(); | |
896 | ||
65896545 DM |
897 | memset(¤t->thread.uw.fpsimd_state, 0, |
898 | sizeof(current->thread.uw.fpsimd_state)); | |
674c242c | 899 | fpsimd_flush_task_state(current); |
bc0ee476 DM |
900 | |
901 | if (system_supports_sve()) { | |
902 | clear_thread_flag(TIF_SVE); | |
903 | sve_free(current); | |
904 | ||
905 | /* | |
906 | * Reset the task vector length as required. | |
907 | * This is where we ensure that all user tasks have a valid | |
908 | * vector length configured: no kernel task can become a user | |
909 | * task without an exec and hence a call to this function. | |
2e0f2478 DM |
910 | * By the time the first call to this function is made, all |
911 | * early hardware probing is complete, so sve_default_vl | |
912 | * should be valid. | |
bc0ee476 DM |
913 | * If a bug causes this to go wrong, we make some noise and |
914 | * try to fudge thread.sve_vl to a safe value here. | |
915 | */ | |
79ab047c DM |
916 | vl = current->thread.sve_vl_onexec ? |
917 | current->thread.sve_vl_onexec : sve_default_vl; | |
bc0ee476 DM |
918 | |
919 | if (WARN_ON(!sve_vl_valid(vl))) | |
920 | vl = SVE_VL_MIN; | |
921 | ||
7582e220 DM |
922 | supported_vl = find_supported_vector_length(vl); |
923 | if (WARN_ON(supported_vl != vl)) | |
924 | vl = supported_vl; | |
925 | ||
bc0ee476 | 926 | current->thread.sve_vl = vl; |
79ab047c DM |
927 | |
928 | /* | |
929 | * If the task is not set to inherit, ensure that the vector | |
930 | * length will be reset by a subsequent exec: | |
931 | */ | |
932 | if (!test_thread_flag(TIF_SVE_VL_INHERIT)) | |
933 | current->thread.sve_vl_onexec = 0; | |
bc0ee476 DM |
934 | } |
935 | ||
005f78cd | 936 | set_thread_flag(TIF_FOREIGN_FPSTATE); |
cb84d11e DM |
937 | |
938 | local_bh_enable(); | |
53631b54 CM |
939 | } |
940 | ||
c51f9269 | 941 | /* |
005f78cd AB |
942 | * Save the userland FPSIMD state of 'current' to memory, but only if the state |
943 | * currently held in the registers does in fact belong to 'current' | |
c51f9269 AB |
944 | */ |
945 | void fpsimd_preserve_current_state(void) | |
946 | { | |
82e0191a SP |
947 | if (!system_supports_fpsimd()) |
948 | return; | |
cb84d11e DM |
949 | |
950 | local_bh_disable(); | |
d1797615 | 951 | fpsimd_save(); |
cb84d11e | 952 | local_bh_enable(); |
c51f9269 AB |
953 | } |
954 | ||
8cd969d2 DM |
955 | /* |
956 | * Like fpsimd_preserve_current_state(), but ensure that | |
65896545 | 957 | * current->thread.uw.fpsimd_state is updated so that it can be copied to |
8cd969d2 DM |
958 | * the signal frame. |
959 | */ | |
960 | void fpsimd_signal_preserve_current_state(void) | |
961 | { | |
962 | fpsimd_preserve_current_state(); | |
963 | if (system_supports_sve() && test_thread_flag(TIF_SVE)) | |
964 | sve_to_fpsimd(current); | |
965 | } | |
966 | ||
8884b7bd DM |
967 | /* |
968 | * Associate current's FPSIMD context with this cpu | |
969 | * Preemption must be disabled when calling this function. | |
970 | */ | |
e6b673b7 | 971 | void fpsimd_bind_task_to_cpu(void) |
8884b7bd | 972 | { |
cb968afc DM |
973 | struct fpsimd_last_state_struct *last = |
974 | this_cpu_ptr(&fpsimd_last_state); | |
8884b7bd | 975 | |
65896545 | 976 | last->st = ¤t->thread.uw.fpsimd_state; |
20b85472 | 977 | current->thread.fpsimd_cpu = smp_processor_id(); |
0cff8e77 DM |
978 | |
979 | if (system_supports_sve()) { | |
980 | /* Toggle SVE trapping for userspace if needed */ | |
981 | if (test_thread_flag(TIF_SVE)) | |
982 | sve_user_enable(); | |
983 | else | |
984 | sve_user_disable(); | |
985 | ||
986 | /* Serialised by exception return to user */ | |
987 | } | |
8884b7bd DM |
988 | } |
989 | ||
e6b673b7 DM |
990 | void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st) |
991 | { | |
992 | struct fpsimd_last_state_struct *last = | |
993 | this_cpu_ptr(&fpsimd_last_state); | |
994 | ||
995 | WARN_ON(!in_softirq() && !irqs_disabled()); | |
996 | ||
997 | last->st = st; | |
8884b7bd DM |
998 | } |
999 | ||
c51f9269 | 1000 | /* |
005f78cd AB |
1001 | * Load the userland FPSIMD state of 'current' from memory, but only if the |
1002 | * FPSIMD state already held in the registers is /not/ the most recent FPSIMD | |
1003 | * state of 'current' | |
1004 | */ | |
1005 | void fpsimd_restore_current_state(void) | |
1006 | { | |
82e0191a SP |
1007 | if (!system_supports_fpsimd()) |
1008 | return; | |
cb84d11e DM |
1009 | |
1010 | local_bh_disable(); | |
1011 | ||
005f78cd | 1012 | if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) { |
bc0ee476 | 1013 | task_fpsimd_load(); |
0cff8e77 | 1014 | fpsimd_bind_task_to_cpu(); |
005f78cd | 1015 | } |
cb84d11e DM |
1016 | |
1017 | local_bh_enable(); | |
005f78cd AB |
1018 | } |
1019 | ||
1020 | /* | |
1021 | * Load an updated userland FPSIMD state for 'current' from memory and set the | |
1022 | * flag that indicates that the FPSIMD register contents are the most recent | |
1023 | * FPSIMD state of 'current' | |
c51f9269 | 1024 | */ |
0abdeff5 | 1025 | void fpsimd_update_current_state(struct user_fpsimd_state const *state) |
c51f9269 | 1026 | { |
82e0191a SP |
1027 | if (!system_supports_fpsimd()) |
1028 | return; | |
cb84d11e DM |
1029 | |
1030 | local_bh_disable(); | |
1031 | ||
65896545 | 1032 | current->thread.uw.fpsimd_state = *state; |
9de52a75 | 1033 | if (system_supports_sve() && test_thread_flag(TIF_SVE)) |
8cd969d2 | 1034 | fpsimd_to_sve(current); |
9de52a75 | 1035 | |
8cd969d2 | 1036 | task_fpsimd_load(); |
0cff8e77 | 1037 | fpsimd_bind_task_to_cpu(); |
8cd969d2 | 1038 | |
0cff8e77 | 1039 | clear_thread_flag(TIF_FOREIGN_FPSTATE); |
cb84d11e DM |
1040 | |
1041 | local_bh_enable(); | |
c51f9269 AB |
1042 | } |
1043 | ||
005f78cd AB |
1044 | /* |
1045 | * Invalidate live CPU copies of task t's FPSIMD state | |
1046 | */ | |
1047 | void fpsimd_flush_task_state(struct task_struct *t) | |
1048 | { | |
20b85472 | 1049 | t->thread.fpsimd_cpu = NR_CPUS; |
005f78cd AB |
1050 | } |
1051 | ||
e6b673b7 | 1052 | void fpsimd_flush_cpu_state(void) |
17eed27b | 1053 | { |
cb968afc | 1054 | __this_cpu_write(fpsimd_last_state.st, NULL); |
d8ad71fa | 1055 | set_thread_flag(TIF_FOREIGN_FPSTATE); |
17eed27b DM |
1056 | } |
1057 | ||
4cfb3613 AB |
1058 | #ifdef CONFIG_KERNEL_MODE_NEON |
1059 | ||
cb84d11e | 1060 | DEFINE_PER_CPU(bool, kernel_neon_busy); |
11cefd5a | 1061 | EXPORT_PER_CPU_SYMBOL(kernel_neon_busy); |
190f1ca8 | 1062 | |
4cfb3613 AB |
1063 | /* |
1064 | * Kernel-side NEON support functions | |
1065 | */ | |
cb84d11e DM |
1066 | |
1067 | /* | |
1068 | * kernel_neon_begin(): obtain the CPU FPSIMD registers for use by the calling | |
1069 | * context | |
1070 | * | |
1071 | * Must not be called unless may_use_simd() returns true. | |
1072 | * Task context in the FPSIMD registers is saved back to memory as necessary. | |
1073 | * | |
1074 | * A matching call to kernel_neon_end() must be made before returning from the | |
1075 | * calling context. | |
1076 | * | |
1077 | * The caller may freely use the FPSIMD registers until kernel_neon_end() is | |
1078 | * called. | |
1079 | */ | |
1080 | void kernel_neon_begin(void) | |
4cfb3613 | 1081 | { |
82e0191a SP |
1082 | if (WARN_ON(!system_supports_fpsimd())) |
1083 | return; | |
4cfb3613 | 1084 | |
cb84d11e DM |
1085 | BUG_ON(!may_use_simd()); |
1086 | ||
1087 | local_bh_disable(); | |
1088 | ||
1089 | __this_cpu_write(kernel_neon_busy, true); | |
1090 | ||
df3fb968 DM |
1091 | /* Save unsaved fpsimd state, if any: */ |
1092 | fpsimd_save(); | |
cb84d11e DM |
1093 | |
1094 | /* Invalidate any task state remaining in the fpsimd regs: */ | |
17eed27b | 1095 | fpsimd_flush_cpu_state(); |
cb84d11e DM |
1096 | |
1097 | preempt_disable(); | |
1098 | ||
1099 | local_bh_enable(); | |
4cfb3613 | 1100 | } |
cb84d11e | 1101 | EXPORT_SYMBOL(kernel_neon_begin); |
4cfb3613 | 1102 | |
cb84d11e DM |
1103 | /* |
1104 | * kernel_neon_end(): give the CPU FPSIMD registers back to the current task | |
1105 | * | |
1106 | * Must be called from a context in which kernel_neon_begin() was previously | |
1107 | * called, with no call to kernel_neon_end() in the meantime. | |
1108 | * | |
1109 | * The caller must not use the FPSIMD registers after this function is called, | |
1110 | * unless kernel_neon_begin() is called again in the meantime. | |
1111 | */ | |
4cfb3613 AB |
1112 | void kernel_neon_end(void) |
1113 | { | |
cb84d11e DM |
1114 | bool busy; |
1115 | ||
82e0191a SP |
1116 | if (!system_supports_fpsimd()) |
1117 | return; | |
cb84d11e DM |
1118 | |
1119 | busy = __this_cpu_xchg(kernel_neon_busy, false); | |
1120 | WARN_ON(!busy); /* No matching kernel_neon_begin()? */ | |
1121 | ||
1122 | preempt_enable(); | |
4cfb3613 AB |
1123 | } |
1124 | EXPORT_SYMBOL(kernel_neon_end); | |
1125 | ||
e580b8bc DM |
1126 | #ifdef CONFIG_EFI |
1127 | ||
20b85472 | 1128 | static DEFINE_PER_CPU(struct user_fpsimd_state, efi_fpsimd_state); |
3b66023d | 1129 | static DEFINE_PER_CPU(bool, efi_fpsimd_state_used); |
fdfa976c | 1130 | static DEFINE_PER_CPU(bool, efi_sve_state_used); |
4328825d DM |
1131 | |
1132 | /* | |
1133 | * EFI runtime services support functions | |
1134 | * | |
1135 | * The ABI for EFI runtime services allows EFI to use FPSIMD during the call. | |
1136 | * This means that for EFI (and only for EFI), we have to assume that FPSIMD | |
1137 | * is always used rather than being an optional accelerator. | |
1138 | * | |
1139 | * These functions provide the necessary support for ensuring FPSIMD | |
1140 | * save/restore in the contexts from which EFI is used. | |
1141 | * | |
1142 | * Do not use them for any other purpose -- if tempted to do so, you are | |
1143 | * either doing something wrong or you need to propose some refactoring. | |
1144 | */ | |
1145 | ||
1146 | /* | |
1147 | * __efi_fpsimd_begin(): prepare FPSIMD for making an EFI runtime services call | |
1148 | */ | |
1149 | void __efi_fpsimd_begin(void) | |
1150 | { | |
1151 | if (!system_supports_fpsimd()) | |
1152 | return; | |
1153 | ||
1154 | WARN_ON(preemptible()); | |
1155 | ||
fdfa976c | 1156 | if (may_use_simd()) { |
4328825d | 1157 | kernel_neon_begin(); |
fdfa976c DM |
1158 | } else { |
1159 | /* | |
1160 | * If !efi_sve_state, SVE can't be in use yet and doesn't need | |
1161 | * preserving: | |
1162 | */ | |
1163 | if (system_supports_sve() && likely(efi_sve_state)) { | |
1164 | char *sve_state = this_cpu_ptr(efi_sve_state); | |
1165 | ||
1166 | __this_cpu_write(efi_sve_state_used, true); | |
1167 | ||
1168 | sve_save_state(sve_state + sve_ffr_offset(sve_max_vl), | |
1169 | &this_cpu_ptr(&efi_fpsimd_state)->fpsr); | |
1170 | } else { | |
1171 | fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state)); | |
1172 | } | |
1173 | ||
4328825d DM |
1174 | __this_cpu_write(efi_fpsimd_state_used, true); |
1175 | } | |
1176 | } | |
1177 | ||
1178 | /* | |
1179 | * __efi_fpsimd_end(): clean up FPSIMD after an EFI runtime services call | |
1180 | */ | |
1181 | void __efi_fpsimd_end(void) | |
1182 | { | |
1183 | if (!system_supports_fpsimd()) | |
1184 | return; | |
1185 | ||
fdfa976c | 1186 | if (!__this_cpu_xchg(efi_fpsimd_state_used, false)) { |
4328825d | 1187 | kernel_neon_end(); |
fdfa976c DM |
1188 | } else { |
1189 | if (system_supports_sve() && | |
1190 | likely(__this_cpu_read(efi_sve_state_used))) { | |
1191 | char const *sve_state = this_cpu_ptr(efi_sve_state); | |
1192 | ||
1193 | sve_load_state(sve_state + sve_ffr_offset(sve_max_vl), | |
1194 | &this_cpu_ptr(&efi_fpsimd_state)->fpsr, | |
1195 | sve_vq_from_vl(sve_get_vl()) - 1); | |
1196 | ||
1197 | __this_cpu_write(efi_sve_state_used, false); | |
1198 | } else { | |
1199 | fpsimd_load_state(this_cpu_ptr(&efi_fpsimd_state)); | |
1200 | } | |
1201 | } | |
4328825d DM |
1202 | } |
1203 | ||
e580b8bc DM |
1204 | #endif /* CONFIG_EFI */ |
1205 | ||
4cfb3613 AB |
1206 | #endif /* CONFIG_KERNEL_MODE_NEON */ |
1207 | ||
fb1ab1ab LP |
1208 | #ifdef CONFIG_CPU_PM |
1209 | static int fpsimd_cpu_pm_notifier(struct notifier_block *self, | |
1210 | unsigned long cmd, void *v) | |
1211 | { | |
1212 | switch (cmd) { | |
1213 | case CPU_PM_ENTER: | |
df3fb968 | 1214 | fpsimd_save(); |
17eed27b | 1215 | fpsimd_flush_cpu_state(); |
fb1ab1ab LP |
1216 | break; |
1217 | case CPU_PM_EXIT: | |
fb1ab1ab LP |
1218 | break; |
1219 | case CPU_PM_ENTER_FAILED: | |
1220 | default: | |
1221 | return NOTIFY_DONE; | |
1222 | } | |
1223 | return NOTIFY_OK; | |
1224 | } | |
1225 | ||
1226 | static struct notifier_block fpsimd_cpu_pm_notifier_block = { | |
1227 | .notifier_call = fpsimd_cpu_pm_notifier, | |
1228 | }; | |
1229 | ||
a7c61a34 | 1230 | static void __init fpsimd_pm_init(void) |
fb1ab1ab LP |
1231 | { |
1232 | cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block); | |
1233 | } | |
1234 | ||
1235 | #else | |
1236 | static inline void fpsimd_pm_init(void) { } | |
1237 | #endif /* CONFIG_CPU_PM */ | |
1238 | ||
32365e64 | 1239 | #ifdef CONFIG_HOTPLUG_CPU |
c23a7266 | 1240 | static int fpsimd_cpu_dead(unsigned int cpu) |
32365e64 | 1241 | { |
cb968afc | 1242 | per_cpu(fpsimd_last_state.st, cpu) = NULL; |
c23a7266 | 1243 | return 0; |
32365e64 JL |
1244 | } |
1245 | ||
32365e64 JL |
1246 | static inline void fpsimd_hotplug_init(void) |
1247 | { | |
c23a7266 SAS |
1248 | cpuhp_setup_state_nocalls(CPUHP_ARM64_FPSIMD_DEAD, "arm64/fpsimd:dead", |
1249 | NULL, fpsimd_cpu_dead); | |
32365e64 JL |
1250 | } |
1251 | ||
1252 | #else | |
1253 | static inline void fpsimd_hotplug_init(void) { } | |
1254 | #endif | |
1255 | ||
53631b54 CM |
1256 | /* |
1257 | * FP/SIMD support code initialisation. | |
1258 | */ | |
1259 | static int __init fpsimd_init(void) | |
1260 | { | |
aaba098f | 1261 | if (cpu_have_named_feature(FP)) { |
fe80f9f2 SP |
1262 | fpsimd_pm_init(); |
1263 | fpsimd_hotplug_init(); | |
1264 | } else { | |
53631b54 | 1265 | pr_notice("Floating-point is not implemented\n"); |
53631b54 | 1266 | } |
53631b54 | 1267 | |
aaba098f | 1268 | if (!cpu_have_named_feature(ASIMD)) |
53631b54 | 1269 | pr_notice("Advanced SIMD is not implemented\n"); |
fb1ab1ab | 1270 | |
4ffa09a9 | 1271 | return sve_sysctl_init(); |
53631b54 | 1272 | } |
ae2e972d | 1273 | core_initcall(fpsimd_init); |