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60ffc30d CM |
1 | /* |
2 | * Low-level exception handling code | |
3 | * | |
4 | * Copyright (C) 2012 ARM Ltd. | |
5 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * Will Deacon <will.deacon@arm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/linkage.h> | |
23 | ||
8d883b23 | 24 | #include <asm/alternative.h> |
60ffc30d CM |
25 | #include <asm/assembler.h> |
26 | #include <asm/asm-offsets.h> | |
905e8c5d | 27 | #include <asm/cpufeature.h> |
60ffc30d | 28 | #include <asm/errno.h> |
5c1ce6f7 | 29 | #include <asm/esr.h> |
8e23dacd | 30 | #include <asm/irq.h> |
e19a6ee2 | 31 | #include <asm/memory.h> |
60ffc30d CM |
32 | #include <asm/thread_info.h> |
33 | #include <asm/unistd.h> | |
34 | ||
6c81fe79 LB |
35 | /* |
36 | * Context tracking subsystem. Used to instrument transitions | |
37 | * between user and kernel mode. | |
38 | */ | |
39 | .macro ct_user_exit, syscall = 0 | |
40 | #ifdef CONFIG_CONTEXT_TRACKING | |
41 | bl context_tracking_user_exit | |
42 | .if \syscall == 1 | |
43 | /* | |
44 | * Save/restore needed during syscalls. Restore syscall arguments from | |
45 | * the values already saved on stack during kernel_entry. | |
46 | */ | |
47 | ldp x0, x1, [sp] | |
48 | ldp x2, x3, [sp, #S_X2] | |
49 | ldp x4, x5, [sp, #S_X4] | |
50 | ldp x6, x7, [sp, #S_X6] | |
51 | .endif | |
52 | #endif | |
53 | .endm | |
54 | ||
55 | .macro ct_user_enter | |
56 | #ifdef CONFIG_CONTEXT_TRACKING | |
57 | bl context_tracking_user_enter | |
58 | #endif | |
59 | .endm | |
60 | ||
60ffc30d CM |
61 | /* |
62 | * Bad Abort numbers | |
63 | *----------------- | |
64 | */ | |
65 | #define BAD_SYNC 0 | |
66 | #define BAD_IRQ 1 | |
67 | #define BAD_FIQ 2 | |
68 | #define BAD_ERROR 3 | |
69 | ||
70 | .macro kernel_entry, el, regsize = 64 | |
63648dd2 | 71 | sub sp, sp, #S_FRAME_SIZE |
60ffc30d CM |
72 | .if \regsize == 32 |
73 | mov w0, w0 // zero upper 32 bits of x0 | |
74 | .endif | |
63648dd2 WD |
75 | stp x0, x1, [sp, #16 * 0] |
76 | stp x2, x3, [sp, #16 * 1] | |
77 | stp x4, x5, [sp, #16 * 2] | |
78 | stp x6, x7, [sp, #16 * 3] | |
79 | stp x8, x9, [sp, #16 * 4] | |
80 | stp x10, x11, [sp, #16 * 5] | |
81 | stp x12, x13, [sp, #16 * 6] | |
82 | stp x14, x15, [sp, #16 * 7] | |
83 | stp x16, x17, [sp, #16 * 8] | |
84 | stp x18, x19, [sp, #16 * 9] | |
85 | stp x20, x21, [sp, #16 * 10] | |
86 | stp x22, x23, [sp, #16 * 11] | |
87 | stp x24, x25, [sp, #16 * 12] | |
88 | stp x26, x27, [sp, #16 * 13] | |
89 | stp x28, x29, [sp, #16 * 14] | |
90 | ||
60ffc30d CM |
91 | .if \el == 0 |
92 | mrs x21, sp_el0 | |
6cdf9c7c JL |
93 | mov tsk, sp |
94 | and tsk, tsk, #~(THREAD_SIZE - 1) // Ensure MDSCR_EL1.SS is clear, | |
2a283070 WD |
95 | ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug |
96 | disable_step_tsk x19, x20 // exceptions when scheduling. | |
49003a8d JM |
97 | |
98 | mov x29, xzr // fp pointed to user-space | |
60ffc30d CM |
99 | .else |
100 | add x21, sp, #S_FRAME_SIZE | |
e19a6ee2 JM |
101 | get_thread_info tsk |
102 | /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */ | |
103 | ldr x20, [tsk, #TI_ADDR_LIMIT] | |
104 | str x20, [sp, #S_ORIG_ADDR_LIMIT] | |
105 | mov x20, #TASK_SIZE_64 | |
106 | str x20, [tsk, #TI_ADDR_LIMIT] | |
107 | ALTERNATIVE(nop, SET_PSTATE_UAO(0), ARM64_HAS_UAO, CONFIG_ARM64_UAO) | |
108 | .endif /* \el == 0 */ | |
60ffc30d CM |
109 | mrs x22, elr_el1 |
110 | mrs x23, spsr_el1 | |
111 | stp lr, x21, [sp, #S_LR] | |
112 | stp x22, x23, [sp, #S_PC] | |
113 | ||
114 | /* | |
115 | * Set syscallno to -1 by default (overridden later if real syscall). | |
116 | */ | |
117 | .if \el == 0 | |
118 | mvn x21, xzr | |
119 | str x21, [sp, #S_SYSCALLNO] | |
120 | .endif | |
121 | ||
6cdf9c7c JL |
122 | /* |
123 | * Set sp_el0 to current thread_info. | |
124 | */ | |
125 | .if \el == 0 | |
126 | msr sp_el0, tsk | |
127 | .endif | |
128 | ||
60ffc30d CM |
129 | /* |
130 | * Registers that may be useful after this macro is invoked: | |
131 | * | |
132 | * x21 - aborted SP | |
133 | * x22 - aborted PC | |
134 | * x23 - aborted PSTATE | |
135 | */ | |
136 | .endm | |
137 | ||
412fcb6c | 138 | .macro kernel_exit, el |
e19a6ee2 JM |
139 | .if \el != 0 |
140 | /* Restore the task's original addr_limit. */ | |
141 | ldr x20, [sp, #S_ORIG_ADDR_LIMIT] | |
142 | str x20, [tsk, #TI_ADDR_LIMIT] | |
143 | ||
144 | /* No need to restore UAO, it will be restored from SPSR_EL1 */ | |
145 | .endif | |
146 | ||
60ffc30d CM |
147 | ldp x21, x22, [sp, #S_PC] // load ELR, SPSR |
148 | .if \el == 0 | |
6c81fe79 | 149 | ct_user_enter |
60ffc30d | 150 | ldr x23, [sp, #S_SP] // load return stack pointer |
63648dd2 | 151 | msr sp_el0, x23 |
905e8c5d | 152 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
e28cabf1 DT |
153 | alternative_if_not ARM64_WORKAROUND_845719 |
154 | nop | |
155 | nop | |
905e8c5d | 156 | #ifdef CONFIG_PID_IN_CONTEXTIDR |
e28cabf1 DT |
157 | nop |
158 | #endif | |
159 | alternative_else | |
160 | tbz x22, #4, 1f | |
161 | #ifdef CONFIG_PID_IN_CONTEXTIDR | |
162 | mrs x29, contextidr_el1 | |
163 | msr contextidr_el1, x29 | |
905e8c5d | 164 | #else |
e28cabf1 | 165 | msr contextidr_el1, xzr |
905e8c5d | 166 | #endif |
e28cabf1 DT |
167 | 1: |
168 | alternative_endif | |
905e8c5d | 169 | #endif |
60ffc30d | 170 | .endif |
63648dd2 WD |
171 | msr elr_el1, x21 // set up the return data |
172 | msr spsr_el1, x22 | |
63648dd2 | 173 | ldp x0, x1, [sp, #16 * 0] |
63648dd2 WD |
174 | ldp x2, x3, [sp, #16 * 1] |
175 | ldp x4, x5, [sp, #16 * 2] | |
176 | ldp x6, x7, [sp, #16 * 3] | |
177 | ldp x8, x9, [sp, #16 * 4] | |
178 | ldp x10, x11, [sp, #16 * 5] | |
179 | ldp x12, x13, [sp, #16 * 6] | |
180 | ldp x14, x15, [sp, #16 * 7] | |
181 | ldp x16, x17, [sp, #16 * 8] | |
182 | ldp x18, x19, [sp, #16 * 9] | |
183 | ldp x20, x21, [sp, #16 * 10] | |
184 | ldp x22, x23, [sp, #16 * 11] | |
185 | ldp x24, x25, [sp, #16 * 12] | |
186 | ldp x26, x27, [sp, #16 * 13] | |
187 | ldp x28, x29, [sp, #16 * 14] | |
188 | ldr lr, [sp, #S_LR] | |
189 | add sp, sp, #S_FRAME_SIZE // restore sp | |
60ffc30d CM |
190 | eret // return to kernel |
191 | .endm | |
192 | ||
193 | .macro get_thread_info, rd | |
6cdf9c7c | 194 | mrs \rd, sp_el0 |
60ffc30d CM |
195 | .endm |
196 | ||
971c67ce | 197 | .macro irq_stack_entry |
8e23dacd JM |
198 | mov x19, sp // preserve the original sp |
199 | ||
8e23dacd | 200 | /* |
d224a69e JM |
201 | * Compare sp with the current thread_info, if the top |
202 | * ~(THREAD_SIZE - 1) bits match, we are on a task stack, and | |
203 | * should switch to the irq stack. | |
8e23dacd | 204 | */ |
d224a69e JM |
205 | and x25, x19, #~(THREAD_SIZE - 1) |
206 | cmp x25, tsk | |
207 | b.ne 9998f | |
8e23dacd | 208 | |
d224a69e | 209 | this_cpu_ptr irq_stack, x25, x26 |
8e23dacd JM |
210 | mov x26, #IRQ_STACK_START_SP |
211 | add x26, x25, x26 | |
d224a69e JM |
212 | |
213 | /* switch to the irq stack */ | |
8e23dacd JM |
214 | mov sp, x26 |
215 | ||
971c67ce JM |
216 | /* |
217 | * Add a dummy stack frame, this non-standard format is fixed up | |
218 | * by unwind_frame() | |
219 | */ | |
220 | stp x29, x19, [sp, #-16]! | |
8e23dacd | 221 | mov x29, sp |
8e23dacd JM |
222 | |
223 | 9998: | |
224 | .endm | |
225 | ||
226 | /* | |
227 | * x19 should be preserved between irq_stack_entry and | |
228 | * irq_stack_exit. | |
229 | */ | |
230 | .macro irq_stack_exit | |
231 | mov sp, x19 | |
232 | .endm | |
233 | ||
60ffc30d CM |
234 | /* |
235 | * These are the registers used in the syscall handler, and allow us to | |
236 | * have in theory up to 7 arguments to a function - x0 to x6. | |
237 | * | |
238 | * x7 is reserved for the system call number in 32-bit mode. | |
239 | */ | |
240 | sc_nr .req x25 // number of system calls | |
241 | scno .req x26 // syscall number | |
242 | stbl .req x27 // syscall table pointer | |
243 | tsk .req x28 // current thread_info | |
244 | ||
245 | /* | |
246 | * Interrupt handling. | |
247 | */ | |
248 | .macro irq_handler | |
8e23dacd | 249 | ldr_l x1, handle_arch_irq |
60ffc30d | 250 | mov x0, sp |
971c67ce | 251 | irq_stack_entry |
60ffc30d | 252 | blr x1 |
8e23dacd | 253 | irq_stack_exit |
60ffc30d CM |
254 | .endm |
255 | ||
256 | .text | |
257 | ||
258 | /* | |
259 | * Exception vectors. | |
260 | */ | |
60ffc30d CM |
261 | |
262 | .align 11 | |
263 | ENTRY(vectors) | |
264 | ventry el1_sync_invalid // Synchronous EL1t | |
265 | ventry el1_irq_invalid // IRQ EL1t | |
266 | ventry el1_fiq_invalid // FIQ EL1t | |
267 | ventry el1_error_invalid // Error EL1t | |
268 | ||
269 | ventry el1_sync // Synchronous EL1h | |
270 | ventry el1_irq // IRQ EL1h | |
271 | ventry el1_fiq_invalid // FIQ EL1h | |
272 | ventry el1_error_invalid // Error EL1h | |
273 | ||
274 | ventry el0_sync // Synchronous 64-bit EL0 | |
275 | ventry el0_irq // IRQ 64-bit EL0 | |
276 | ventry el0_fiq_invalid // FIQ 64-bit EL0 | |
277 | ventry el0_error_invalid // Error 64-bit EL0 | |
278 | ||
279 | #ifdef CONFIG_COMPAT | |
280 | ventry el0_sync_compat // Synchronous 32-bit EL0 | |
281 | ventry el0_irq_compat // IRQ 32-bit EL0 | |
282 | ventry el0_fiq_invalid_compat // FIQ 32-bit EL0 | |
283 | ventry el0_error_invalid_compat // Error 32-bit EL0 | |
284 | #else | |
285 | ventry el0_sync_invalid // Synchronous 32-bit EL0 | |
286 | ventry el0_irq_invalid // IRQ 32-bit EL0 | |
287 | ventry el0_fiq_invalid // FIQ 32-bit EL0 | |
288 | ventry el0_error_invalid // Error 32-bit EL0 | |
289 | #endif | |
290 | END(vectors) | |
291 | ||
292 | /* | |
293 | * Invalid mode handlers | |
294 | */ | |
295 | .macro inv_entry, el, reason, regsize = 64 | |
b660950c | 296 | kernel_entry \el, \regsize |
60ffc30d CM |
297 | mov x0, sp |
298 | mov x1, #\reason | |
299 | mrs x2, esr_el1 | |
300 | b bad_mode | |
301 | .endm | |
302 | ||
303 | el0_sync_invalid: | |
304 | inv_entry 0, BAD_SYNC | |
305 | ENDPROC(el0_sync_invalid) | |
306 | ||
307 | el0_irq_invalid: | |
308 | inv_entry 0, BAD_IRQ | |
309 | ENDPROC(el0_irq_invalid) | |
310 | ||
311 | el0_fiq_invalid: | |
312 | inv_entry 0, BAD_FIQ | |
313 | ENDPROC(el0_fiq_invalid) | |
314 | ||
315 | el0_error_invalid: | |
316 | inv_entry 0, BAD_ERROR | |
317 | ENDPROC(el0_error_invalid) | |
318 | ||
319 | #ifdef CONFIG_COMPAT | |
320 | el0_fiq_invalid_compat: | |
321 | inv_entry 0, BAD_FIQ, 32 | |
322 | ENDPROC(el0_fiq_invalid_compat) | |
323 | ||
324 | el0_error_invalid_compat: | |
325 | inv_entry 0, BAD_ERROR, 32 | |
326 | ENDPROC(el0_error_invalid_compat) | |
327 | #endif | |
328 | ||
329 | el1_sync_invalid: | |
330 | inv_entry 1, BAD_SYNC | |
331 | ENDPROC(el1_sync_invalid) | |
332 | ||
333 | el1_irq_invalid: | |
334 | inv_entry 1, BAD_IRQ | |
335 | ENDPROC(el1_irq_invalid) | |
336 | ||
337 | el1_fiq_invalid: | |
338 | inv_entry 1, BAD_FIQ | |
339 | ENDPROC(el1_fiq_invalid) | |
340 | ||
341 | el1_error_invalid: | |
342 | inv_entry 1, BAD_ERROR | |
343 | ENDPROC(el1_error_invalid) | |
344 | ||
345 | /* | |
346 | * EL1 mode handlers. | |
347 | */ | |
348 | .align 6 | |
349 | el1_sync: | |
350 | kernel_entry 1 | |
351 | mrs x1, esr_el1 // read the syndrome register | |
aed40e01 MR |
352 | lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class |
353 | cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 | |
60ffc30d | 354 | b.eq el1_da |
aed40e01 | 355 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
60ffc30d | 356 | b.eq el1_undef |
aed40e01 | 357 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 358 | b.eq el1_sp_pc |
aed40e01 | 359 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 360 | b.eq el1_sp_pc |
aed40e01 | 361 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 |
60ffc30d | 362 | b.eq el1_undef |
aed40e01 | 363 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 |
60ffc30d CM |
364 | b.ge el1_dbg |
365 | b el1_inv | |
366 | el1_da: | |
367 | /* | |
368 | * Data abort handling | |
369 | */ | |
370 | mrs x0, far_el1 | |
2a283070 | 371 | enable_dbg |
60ffc30d CM |
372 | // re-enable interrupts if they were enabled in the aborted context |
373 | tbnz x23, #7, 1f // PSR_I_BIT | |
374 | enable_irq | |
375 | 1: | |
376 | mov x2, sp // struct pt_regs | |
377 | bl do_mem_abort | |
378 | ||
379 | // disable interrupts before pulling preserved data off the stack | |
380 | disable_irq | |
381 | kernel_exit 1 | |
382 | el1_sp_pc: | |
383 | /* | |
384 | * Stack or PC alignment exception handling | |
385 | */ | |
386 | mrs x0, far_el1 | |
2a283070 | 387 | enable_dbg |
60ffc30d CM |
388 | mov x2, sp |
389 | b do_sp_pc_abort | |
390 | el1_undef: | |
391 | /* | |
392 | * Undefined instruction | |
393 | */ | |
2a283070 | 394 | enable_dbg |
60ffc30d CM |
395 | mov x0, sp |
396 | b do_undefinstr | |
397 | el1_dbg: | |
398 | /* | |
399 | * Debug exception handling | |
400 | */ | |
aed40e01 | 401 | cmp x24, #ESR_ELx_EC_BRK64 // if BRK64 |
ee6214ce | 402 | cinc x24, x24, eq // set bit '0' |
60ffc30d CM |
403 | tbz x24, #0, el1_inv // EL1 only |
404 | mrs x0, far_el1 | |
405 | mov x2, sp // struct pt_regs | |
406 | bl do_debug_exception | |
60ffc30d CM |
407 | kernel_exit 1 |
408 | el1_inv: | |
409 | // TODO: add support for undefined instructions in kernel mode | |
2a283070 | 410 | enable_dbg |
60ffc30d | 411 | mov x0, sp |
1b42804d | 412 | mov x2, x1 |
60ffc30d | 413 | mov x1, #BAD_SYNC |
60ffc30d CM |
414 | b bad_mode |
415 | ENDPROC(el1_sync) | |
416 | ||
417 | .align 6 | |
418 | el1_irq: | |
419 | kernel_entry 1 | |
2a283070 | 420 | enable_dbg |
60ffc30d CM |
421 | #ifdef CONFIG_TRACE_IRQFLAGS |
422 | bl trace_hardirqs_off | |
423 | #endif | |
64681787 | 424 | |
60ffc30d | 425 | irq_handler |
64681787 | 426 | |
60ffc30d | 427 | #ifdef CONFIG_PREEMPT |
883c0573 | 428 | ldr w24, [tsk, #TI_PREEMPT] // get preempt count |
717321fc | 429 | cbnz w24, 1f // preempt count != 0 |
60ffc30d CM |
430 | ldr x0, [tsk, #TI_FLAGS] // get flags |
431 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? | |
432 | bl el1_preempt | |
433 | 1: | |
434 | #endif | |
435 | #ifdef CONFIG_TRACE_IRQFLAGS | |
436 | bl trace_hardirqs_on | |
437 | #endif | |
438 | kernel_exit 1 | |
439 | ENDPROC(el1_irq) | |
440 | ||
441 | #ifdef CONFIG_PREEMPT | |
442 | el1_preempt: | |
443 | mov x24, lr | |
2a283070 | 444 | 1: bl preempt_schedule_irq // irq en/disable is done inside |
60ffc30d CM |
445 | ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS |
446 | tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? | |
447 | ret x24 | |
448 | #endif | |
449 | ||
450 | /* | |
451 | * EL0 mode handlers. | |
452 | */ | |
453 | .align 6 | |
454 | el0_sync: | |
455 | kernel_entry 0 | |
456 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
457 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
458 | cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state | |
60ffc30d | 459 | b.eq el0_svc |
aed40e01 | 460 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 461 | b.eq el0_da |
aed40e01 | 462 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 463 | b.eq el0_ia |
aed40e01 | 464 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 465 | b.eq el0_fpsimd_acc |
aed40e01 | 466 | cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception |
60ffc30d | 467 | b.eq el0_fpsimd_exc |
aed40e01 | 468 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
60ffc30d | 469 | b.eq el0_undef |
aed40e01 | 470 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 471 | b.eq el0_sp_pc |
aed40e01 | 472 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 473 | b.eq el0_sp_pc |
aed40e01 | 474 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 475 | b.eq el0_undef |
aed40e01 | 476 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
477 | b.ge el0_dbg |
478 | b el0_inv | |
479 | ||
480 | #ifdef CONFIG_COMPAT | |
481 | .align 6 | |
482 | el0_sync_compat: | |
483 | kernel_entry 0, 32 | |
484 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
485 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
486 | cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state | |
60ffc30d | 487 | b.eq el0_svc_compat |
aed40e01 | 488 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 489 | b.eq el0_da |
aed40e01 | 490 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 491 | b.eq el0_ia |
aed40e01 | 492 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 493 | b.eq el0_fpsimd_acc |
aed40e01 | 494 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception |
60ffc30d | 495 | b.eq el0_fpsimd_exc |
77f3228f MS |
496 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
497 | b.eq el0_sp_pc | |
aed40e01 | 498 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 499 | b.eq el0_undef |
aed40e01 | 500 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap |
381cc2b9 | 501 | b.eq el0_undef |
aed40e01 | 502 | cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap |
381cc2b9 | 503 | b.eq el0_undef |
aed40e01 | 504 | cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap |
381cc2b9 | 505 | b.eq el0_undef |
aed40e01 | 506 | cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap |
381cc2b9 | 507 | b.eq el0_undef |
aed40e01 | 508 | cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap |
381cc2b9 | 509 | b.eq el0_undef |
aed40e01 | 510 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
511 | b.ge el0_dbg |
512 | b el0_inv | |
513 | el0_svc_compat: | |
514 | /* | |
515 | * AArch32 syscall handling | |
516 | */ | |
0156411b | 517 | adrp stbl, compat_sys_call_table // load compat syscall table pointer |
60ffc30d CM |
518 | uxtw scno, w7 // syscall number in w7 (r7) |
519 | mov sc_nr, #__NR_compat_syscalls | |
520 | b el0_svc_naked | |
521 | ||
522 | .align 6 | |
523 | el0_irq_compat: | |
524 | kernel_entry 0, 32 | |
525 | b el0_irq_naked | |
526 | #endif | |
527 | ||
528 | el0_da: | |
529 | /* | |
530 | * Data abort handling | |
531 | */ | |
6ab6463a | 532 | mrs x26, far_el1 |
60ffc30d | 533 | // enable interrupts before calling the main handler |
2a283070 | 534 | enable_dbg_and_irq |
6c81fe79 | 535 | ct_user_exit |
6ab6463a | 536 | bic x0, x26, #(0xff << 56) |
60ffc30d CM |
537 | mov x1, x25 |
538 | mov x2, sp | |
d54e81f9 WD |
539 | bl do_mem_abort |
540 | b ret_to_user | |
60ffc30d CM |
541 | el0_ia: |
542 | /* | |
543 | * Instruction abort handling | |
544 | */ | |
6ab6463a | 545 | mrs x26, far_el1 |
60ffc30d | 546 | // enable interrupts before calling the main handler |
2a283070 | 547 | enable_dbg_and_irq |
6c81fe79 | 548 | ct_user_exit |
6ab6463a | 549 | mov x0, x26 |
60ffc30d CM |
550 | orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts |
551 | mov x2, sp | |
d54e81f9 WD |
552 | bl do_mem_abort |
553 | b ret_to_user | |
60ffc30d CM |
554 | el0_fpsimd_acc: |
555 | /* | |
556 | * Floating Point or Advanced SIMD access | |
557 | */ | |
2a283070 | 558 | enable_dbg |
6c81fe79 | 559 | ct_user_exit |
60ffc30d CM |
560 | mov x0, x25 |
561 | mov x1, sp | |
d54e81f9 WD |
562 | bl do_fpsimd_acc |
563 | b ret_to_user | |
60ffc30d CM |
564 | el0_fpsimd_exc: |
565 | /* | |
566 | * Floating Point or Advanced SIMD exception | |
567 | */ | |
2a283070 | 568 | enable_dbg |
6c81fe79 | 569 | ct_user_exit |
60ffc30d CM |
570 | mov x0, x25 |
571 | mov x1, sp | |
d54e81f9 WD |
572 | bl do_fpsimd_exc |
573 | b ret_to_user | |
60ffc30d CM |
574 | el0_sp_pc: |
575 | /* | |
576 | * Stack or PC alignment exception handling | |
577 | */ | |
6ab6463a | 578 | mrs x26, far_el1 |
60ffc30d | 579 | // enable interrupts before calling the main handler |
2a283070 | 580 | enable_dbg_and_irq |
46b0567c | 581 | ct_user_exit |
6ab6463a | 582 | mov x0, x26 |
60ffc30d CM |
583 | mov x1, x25 |
584 | mov x2, sp | |
d54e81f9 WD |
585 | bl do_sp_pc_abort |
586 | b ret_to_user | |
60ffc30d CM |
587 | el0_undef: |
588 | /* | |
589 | * Undefined instruction | |
590 | */ | |
2600e130 | 591 | // enable interrupts before calling the main handler |
2a283070 | 592 | enable_dbg_and_irq |
6c81fe79 | 593 | ct_user_exit |
2a283070 | 594 | mov x0, sp |
d54e81f9 WD |
595 | bl do_undefinstr |
596 | b ret_to_user | |
60ffc30d CM |
597 | el0_dbg: |
598 | /* | |
599 | * Debug exception handling | |
600 | */ | |
601 | tbnz x24, #0, el0_inv // EL0 only | |
602 | mrs x0, far_el1 | |
60ffc30d CM |
603 | mov x1, x25 |
604 | mov x2, sp | |
2a283070 WD |
605 | bl do_debug_exception |
606 | enable_dbg | |
6c81fe79 | 607 | ct_user_exit |
2a283070 | 608 | b ret_to_user |
60ffc30d | 609 | el0_inv: |
2a283070 | 610 | enable_dbg |
6c81fe79 | 611 | ct_user_exit |
60ffc30d CM |
612 | mov x0, sp |
613 | mov x1, #BAD_SYNC | |
1b42804d | 614 | mov x2, x25 |
d54e81f9 WD |
615 | bl bad_mode |
616 | b ret_to_user | |
60ffc30d CM |
617 | ENDPROC(el0_sync) |
618 | ||
619 | .align 6 | |
620 | el0_irq: | |
621 | kernel_entry 0 | |
622 | el0_irq_naked: | |
60ffc30d CM |
623 | enable_dbg |
624 | #ifdef CONFIG_TRACE_IRQFLAGS | |
625 | bl trace_hardirqs_off | |
626 | #endif | |
64681787 | 627 | |
6c81fe79 | 628 | ct_user_exit |
60ffc30d | 629 | irq_handler |
64681787 | 630 | |
60ffc30d CM |
631 | #ifdef CONFIG_TRACE_IRQFLAGS |
632 | bl trace_hardirqs_on | |
633 | #endif | |
634 | b ret_to_user | |
635 | ENDPROC(el0_irq) | |
636 | ||
60ffc30d CM |
637 | /* |
638 | * Register switch for AArch64. The callee-saved registers need to be saved | |
639 | * and restored. On entry: | |
640 | * x0 = previous task_struct (must be preserved across the switch) | |
641 | * x1 = next task_struct | |
642 | * Previous and next are guaranteed not to be the same. | |
643 | * | |
644 | */ | |
645 | ENTRY(cpu_switch_to) | |
c0d3fce5 WD |
646 | mov x10, #THREAD_CPU_CONTEXT |
647 | add x8, x0, x10 | |
60ffc30d CM |
648 | mov x9, sp |
649 | stp x19, x20, [x8], #16 // store callee-saved registers | |
650 | stp x21, x22, [x8], #16 | |
651 | stp x23, x24, [x8], #16 | |
652 | stp x25, x26, [x8], #16 | |
653 | stp x27, x28, [x8], #16 | |
654 | stp x29, x9, [x8], #16 | |
655 | str lr, [x8] | |
c0d3fce5 | 656 | add x8, x1, x10 |
60ffc30d CM |
657 | ldp x19, x20, [x8], #16 // restore callee-saved registers |
658 | ldp x21, x22, [x8], #16 | |
659 | ldp x23, x24, [x8], #16 | |
660 | ldp x25, x26, [x8], #16 | |
661 | ldp x27, x28, [x8], #16 | |
662 | ldp x29, x9, [x8], #16 | |
663 | ldr lr, [x8] | |
664 | mov sp, x9 | |
6cdf9c7c JL |
665 | and x9, x9, #~(THREAD_SIZE - 1) |
666 | msr sp_el0, x9 | |
60ffc30d CM |
667 | ret |
668 | ENDPROC(cpu_switch_to) | |
669 | ||
670 | /* | |
671 | * This is the fast syscall return path. We do as little as possible here, | |
672 | * and this includes saving x0 back into the kernel stack. | |
673 | */ | |
674 | ret_fast_syscall: | |
675 | disable_irq // disable interrupts | |
412fcb6c | 676 | str x0, [sp, #S_X0] // returned x0 |
04d7e098 JS |
677 | ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing |
678 | and x2, x1, #_TIF_SYSCALL_WORK | |
679 | cbnz x2, ret_fast_syscall_trace | |
60ffc30d | 680 | and x2, x1, #_TIF_WORK_MASK |
412fcb6c | 681 | cbnz x2, work_pending |
2a283070 | 682 | enable_step_tsk x1, x2 |
412fcb6c | 683 | kernel_exit 0 |
04d7e098 JS |
684 | ret_fast_syscall_trace: |
685 | enable_irq // enable interrupts | |
412fcb6c | 686 | b __sys_trace_return_skipped // we already saved x0 |
60ffc30d CM |
687 | |
688 | /* | |
689 | * Ok, we need to do extra processing, enter the slow path. | |
690 | */ | |
60ffc30d CM |
691 | work_pending: |
692 | tbnz x1, #TIF_NEED_RESCHED, work_resched | |
005f78cd | 693 | /* TIF_SIGPENDING, TIF_NOTIFY_RESUME or TIF_FOREIGN_FPSTATE case */ |
60ffc30d | 694 | mov x0, sp // 'regs' |
6916fd08 | 695 | enable_irq // enable interrupts for do_notify_resume() |
60ffc30d CM |
696 | bl do_notify_resume |
697 | b ret_to_user | |
698 | work_resched: | |
db3899a6 CM |
699 | #ifdef CONFIG_TRACE_IRQFLAGS |
700 | bl trace_hardirqs_off // the IRQs are off here, inform the tracing code | |
701 | #endif | |
60ffc30d CM |
702 | bl schedule |
703 | ||
704 | /* | |
705 | * "slow" syscall return path. | |
706 | */ | |
59dc67b0 | 707 | ret_to_user: |
60ffc30d CM |
708 | disable_irq // disable interrupts |
709 | ldr x1, [tsk, #TI_FLAGS] | |
710 | and x2, x1, #_TIF_WORK_MASK | |
711 | cbnz x2, work_pending | |
2a283070 | 712 | enable_step_tsk x1, x2 |
412fcb6c | 713 | kernel_exit 0 |
60ffc30d CM |
714 | ENDPROC(ret_to_user) |
715 | ||
716 | /* | |
717 | * This is how we return from a fork. | |
718 | */ | |
719 | ENTRY(ret_from_fork) | |
720 | bl schedule_tail | |
c34501d2 CM |
721 | cbz x19, 1f // not a kernel thread |
722 | mov x0, x20 | |
723 | blr x19 | |
724 | 1: get_thread_info tsk | |
60ffc30d CM |
725 | b ret_to_user |
726 | ENDPROC(ret_from_fork) | |
727 | ||
728 | /* | |
729 | * SVC handler. | |
730 | */ | |
731 | .align 6 | |
732 | el0_svc: | |
733 | adrp stbl, sys_call_table // load syscall table pointer | |
734 | uxtw scno, w8 // syscall number in w8 | |
735 | mov sc_nr, #__NR_syscalls | |
736 | el0_svc_naked: // compat entry point | |
737 | stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number | |
2a283070 | 738 | enable_dbg_and_irq |
6c81fe79 | 739 | ct_user_exit 1 |
60ffc30d | 740 | |
449f81a4 AT |
741 | ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks |
742 | tst x16, #_TIF_SYSCALL_WORK | |
743 | b.ne __sys_trace | |
60ffc30d CM |
744 | cmp scno, sc_nr // check upper syscall limit |
745 | b.hs ni_sys | |
746 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table | |
d54e81f9 WD |
747 | blr x16 // call sys_* routine |
748 | b ret_fast_syscall | |
60ffc30d CM |
749 | ni_sys: |
750 | mov x0, sp | |
d54e81f9 WD |
751 | bl do_ni_syscall |
752 | b ret_fast_syscall | |
60ffc30d CM |
753 | ENDPROC(el0_svc) |
754 | ||
755 | /* | |
756 | * This is the really slow path. We're going to be doing context | |
757 | * switches, and waiting for our parent to respond. | |
758 | */ | |
759 | __sys_trace: | |
1014c81d AT |
760 | mov w0, #-1 // set default errno for |
761 | cmp scno, x0 // user-issued syscall(-1) | |
762 | b.ne 1f | |
763 | mov x0, #-ENOSYS | |
764 | str x0, [sp, #S_X0] | |
765 | 1: mov x0, sp | |
3157858f | 766 | bl syscall_trace_enter |
1014c81d AT |
767 | cmp w0, #-1 // skip the syscall? |
768 | b.eq __sys_trace_return_skipped | |
60ffc30d CM |
769 | uxtw scno, w0 // syscall number (possibly new) |
770 | mov x1, sp // pointer to regs | |
771 | cmp scno, sc_nr // check upper syscall limit | |
d54e81f9 | 772 | b.hs __ni_sys_trace |
60ffc30d CM |
773 | ldp x0, x1, [sp] // restore the syscall args |
774 | ldp x2, x3, [sp, #S_X2] | |
775 | ldp x4, x5, [sp, #S_X4] | |
776 | ldp x6, x7, [sp, #S_X6] | |
777 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table | |
d54e81f9 | 778 | blr x16 // call sys_* routine |
60ffc30d CM |
779 | |
780 | __sys_trace_return: | |
1014c81d AT |
781 | str x0, [sp, #S_X0] // save returned x0 |
782 | __sys_trace_return_skipped: | |
3157858f AT |
783 | mov x0, sp |
784 | bl syscall_trace_exit | |
60ffc30d CM |
785 | b ret_to_user |
786 | ||
d54e81f9 WD |
787 | __ni_sys_trace: |
788 | mov x0, sp | |
789 | bl do_ni_syscall | |
790 | b __sys_trace_return | |
791 | ||
60ffc30d CM |
792 | /* |
793 | * Special system call wrappers. | |
794 | */ | |
60ffc30d CM |
795 | ENTRY(sys_rt_sigreturn_wrapper) |
796 | mov x0, sp | |
797 | b sys_rt_sigreturn | |
798 | ENDPROC(sys_rt_sigreturn_wrapper) |