[linux-2.6-block.git] / arch / arm64 / kernel / debug-monitors.c

/*
 * ARMv8 single-step debug support and mdscr context switching.
 *
 * Copyright (C) 2012 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * Author: Will Deacon <will.deacon@arm.com>
 */

#include <linux/cpu.h>
#include <linux/debugfs.h>
#include <linux/hardirq.h>
#include <linux/init.h>
#include <linux/ptrace.h>
#include <linux/stat.h>
#include <linux/uaccess.h>

#include <asm/debug-monitors.h>
#include <asm/cputype.h>
#include <asm/system_misc.h>

/* Low-level stepping controls. */
#define DBG_MDSCR_SS		(1 << 0)
#define DBG_SPSR_SS		(1 << 21)

/* MDSCR_EL1 enabling bits */
#define DBG_MDSCR_KDE		(1 << 13)
#define DBG_MDSCR_MDE		(1 << 15)
#define DBG_MDSCR_MASK		~(DBG_MDSCR_KDE | DBG_MDSCR_MDE)

/* Determine debug architecture. */
u8 debug_monitors_arch(void)
{
	return read_cpuid(ID_AA64DFR0_EL1) & 0xf;
}

/*
 * MDSCR access routines.
 */
static void mdscr_write(u32 mdscr)
{
	unsigned long flags;
	local_dbg_save(flags);
	asm volatile("msr mdscr_el1, %0" :: "r" (mdscr));
	local_dbg_restore(flags);
}

static u32 mdscr_read(void)
{
	u32 mdscr;
	asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr));
	return mdscr;
}

/*
 * Allow root to disable self-hosted debug from userspace.
 * This is useful if you want to connect an external JTAG debugger.
 */
static u32 debug_enabled = 1;

static int create_debug_debugfs_entry(void)
{
	debugfs_create_bool("debug_enabled", 0644, NULL, &debug_enabled);
	return 0;
}
fs_initcall(create_debug_debugfs_entry);

static int __init early_debug_disable(char *buf)
{
	debug_enabled = 0;
	return 0;
}

early_param("nodebugmon", early_debug_disable);

/*
 * Keep track of debug users on each core.
 * The ref counts are per-cpu so we use a local_t type.
 */
static DEFINE_PER_CPU(int, mde_ref_count);
static DEFINE_PER_CPU(int, kde_ref_count);

void enable_debug_monitors(enum debug_el el)
{
	u32 mdscr, enable = 0;

	WARN_ON(preemptible());

	if (this_cpu_inc_return(mde_ref_count) == 1)
		enable = DBG_MDSCR_MDE;

	if (el == DBG_ACTIVE_EL1 &&
	    this_cpu_inc_return(kde_ref_count) == 1)
		enable |= DBG_MDSCR_KDE;

	if (enable && debug_enabled) {
		mdscr = mdscr_read();
		mdscr |= enable;
		mdscr_write(mdscr);
	}
}

void disable_debug_monitors(enum debug_el el)
{
	u32 mdscr, disable = 0;

	WARN_ON(preemptible());

	if (this_cpu_dec_return(mde_ref_count) == 0)
		disable = ~DBG_MDSCR_MDE;

	if (el == DBG_ACTIVE_EL1 &&
	    this_cpu_dec_return(kde_ref_count) == 0)
		disable &= ~DBG_MDSCR_KDE;

	if (disable) {
		mdscr = mdscr_read();
		mdscr &= disable;
		mdscr_write(mdscr);
	}
}

/*
 * OS lock clearing.
 */
static void clear_os_lock(void *unused)
{
	asm volatile("msr oslar_el1, %0" : : "r" (0));
	isb();
}

static int os_lock_notify(struct notifier_block *self,
				    unsigned long action, void *data)
{
	int cpu = (unsigned long)data;
	if (action == CPU_ONLINE)
		smp_call_function_single(cpu, clear_os_lock, NULL, 1);
	return NOTIFY_OK;
}

static struct notifier_block os_lock_nb = {
	.notifier_call = os_lock_notify,
};

static int debug_monitors_init(void)
{
	/* Clear the OS lock. */
	smp_call_function(clear_os_lock, NULL, 1);
	clear_os_lock(NULL);

	/* Register hotplug handler. */
	register_cpu_notifier(&os_lock_nb);
	return 0;
}
postcore_initcall(debug_monitors_init);

/*
 * Single step API and exception handling.
 */
static void set_regs_spsr_ss(struct pt_regs *regs)
{
	unsigned long spsr;

	spsr = regs->pstate;
	spsr &= ~DBG_SPSR_SS;
	spsr |= DBG_SPSR_SS;
	regs->pstate = spsr;
}

static void clear_regs_spsr_ss(struct pt_regs *regs)
{
	unsigned long spsr;

	spsr = regs->pstate;
	spsr &= ~DBG_SPSR_SS;
	regs->pstate = spsr;
}

static int single_step_handler(unsigned long addr, unsigned int esr,
			       struct pt_regs *regs)
{
	siginfo_t info;

	/*
	 * If we are stepping a pending breakpoint, call the hw_breakpoint
	 * handler first.
	 */
	if (!reinstall_suspended_bps(regs))
		return 0;

	if (user_mode(regs)) {
		info.si_signo = SIGTRAP;
		info.si_errno = 0;
		info.si_code  = TRAP_HWBKPT;
		info.si_addr  = (void __user *)instruction_pointer(regs);
		force_sig_info(SIGTRAP, &info, current);

		/*
		 * ptrace will disable single step unless explicitly
		 * asked to re-enable it. For other clients, it makes
		 * sense to leave it enabled (i.e. rewind the controls
		 * to the active-not-pending state).
		 */
		user_rewind_single_step(current);
	} else {
		/* TODO: route to KGDB */
		pr_warning("Unexpected kernel single-step exception at EL1\n");
		/*
		 * Re-enable stepping since we know that we will be
		 * returning to regs.
		 */
		set_regs_spsr_ss(regs);
	}

	return 0;
}

static int brk_handler(unsigned long addr, unsigned int esr,
		       struct pt_regs *regs)
{
	siginfo_t info;

	if (!user_mode(regs))
		return -EFAULT;

	info = (siginfo_t) {
		.si_signo = SIGTRAP,
		.si_errno = 0,
		.si_code  = TRAP_BRKPT,
		.si_addr  = (void __user *)instruction_pointer(regs),
	};

	force_sig_info(SIGTRAP, &info, current);
	return 0;
}

int aarch32_break_handler(struct pt_regs *regs)
{
	siginfo_t info;
	u32 arm_instr;
	u16 thumb_instr;
	bool bp = false;
	void __user *pc = (void __user *)instruction_pointer(regs);

	if (!compat_user_mode(regs))
		return -EFAULT;

	if (compat_thumb_mode(regs)) {
		/* get 16-bit Thumb instruction */
		get_user(thumb_instr, (u16 __user *)pc);
		thumb_instr = le16_to_cpu(thumb_instr);
		if (thumb_instr == AARCH32_BREAK_THUMB2_LO) {
			/* get second half of 32-bit Thumb-2 instruction */
			get_user(thumb_instr, (u16 __user *)(pc + 2));
			thumb_instr = le16_to_cpu(thumb_instr);
			bp = thumb_instr == AARCH32_BREAK_THUMB2_HI;
		} else {
			bp = thumb_instr == AARCH32_BREAK_THUMB;
		}
	} else {
		/* 32-bit ARM instruction */
		get_user(arm_instr, (u32 __user *)pc);
		arm_instr = le32_to_cpu(arm_instr);
		bp = (arm_instr & ~0xf0000000) == AARCH32_BREAK_ARM;
	}

	if (!bp)
		return -EFAULT;

	info = (siginfo_t) {
		.si_signo = SIGTRAP,
		.si_errno = 0,
		.si_code  = TRAP_BRKPT,
		.si_addr  = pc,
	};

	force_sig_info(SIGTRAP, &info, current);
	return 0;
}

static int __init debug_traps_init(void)
{
	hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP,
			      TRAP_HWBKPT, "single-step handler");
	hook_debug_fault_code(DBG_ESR_EVT_BRK, brk_handler, SIGTRAP,
			      TRAP_BRKPT, "ptrace BRK handler");
	return 0;
}
arch_initcall(debug_traps_init);

/* Re-enable single step for syscall restarting. */
void user_rewind_single_step(struct task_struct *task)
{
	/*
	 * If single step is active for this thread, then set SPSR.SS
	 * to 1 to avoid returning to the active-pending state.
	 */
	if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))
		set_regs_spsr_ss(task_pt_regs(task));
}

void user_fastforward_single_step(struct task_struct *task)
{
	if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))
		clear_regs_spsr_ss(task_pt_regs(task));
}

/* Kernel API */
void kernel_enable_single_step(struct pt_regs *regs)
{
	WARN_ON(!irqs_disabled());
	set_regs_spsr_ss(regs);
	mdscr_write(mdscr_read() | DBG_MDSCR_SS);
	enable_debug_monitors(DBG_ACTIVE_EL1);
}

void kernel_disable_single_step(void)
{
	WARN_ON(!irqs_disabled());
	mdscr_write(mdscr_read() & ~DBG_MDSCR_SS);
	disable_debug_monitors(DBG_ACTIVE_EL1);
}

int kernel_active_single_step(void)
{
	WARN_ON(!irqs_disabled());
	return mdscr_read() & DBG_MDSCR_SS;
}

/* ptrace API */
void user_enable_single_step(struct task_struct *task)
{
	set_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);
	set_regs_spsr_ss(task_pt_regs(task));
}

void user_disable_single_step(struct task_struct *task)
{
	clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);
}
Commit	Line	Data
478fcb2c WD	1	/*
	2	* ARMv8 single-step debug support and mdscr context switching.
	3	*
	4	* Copyright (C) 2012 ARM Limited
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*
	18	* Author: Will Deacon <will.deacon@arm.com>
	19	*/
	20
	21	#include <linux/cpu.h>
	22	#include <linux/debugfs.h>
	23	#include <linux/hardirq.h>
	24	#include <linux/init.h>
	25	#include <linux/ptrace.h>
	26	#include <linux/stat.h>
1442b6ed	27	#include <linux/uaccess.h>
478fcb2c WD	28
478fcb2c WD	29	#include <asm/debug-monitors.h>
478fcb2c WD	30	#include <asm/cputype.h>
	31	#include <asm/system_misc.h>
	32
	33	/* Low-level stepping controls. */
	34	#define DBG_MDSCR_SS (1 << 0)
	35	#define DBG_SPSR_SS (1 << 21)
	36
	37	/* MDSCR_EL1 enabling bits */
	38	#define DBG_MDSCR_KDE (1 << 13)
	39	#define DBG_MDSCR_MDE (1 << 15)
	40	#define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE \| DBG_MDSCR_MDE)
	41
	42	/* Determine debug architecture. */
	43	u8 debug_monitors_arch(void)
	44	{
	45	return read_cpuid(ID_AA64DFR0_EL1) & 0xf;
	46	}
	47
	48	/*
	49	* MDSCR access routines.
	50	*/
	51	static void mdscr_write(u32 mdscr)
	52	{
	53	unsigned long flags;
	54	local_dbg_save(flags);
	55	asm volatile("msr mdscr_el1, %0" :: "r" (mdscr));
	56	local_dbg_restore(flags);
	57	}
	58
	59	static u32 mdscr_read(void)
	60	{
	61	u32 mdscr;
	62	asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr));
	63	return mdscr;
	64	}
	65
	66	/*
	67	* Allow root to disable self-hosted debug from userspace.
	68	* This is useful if you want to connect an external JTAG debugger.
	69	*/
	70	static u32 debug_enabled = 1;
	71
	72	static int create_debug_debugfs_entry(void)
	73	{
	74	debugfs_create_bool("debug_enabled", 0644, NULL, &debug_enabled);
	75	return 0;
	76	}
	77	fs_initcall(create_debug_debugfs_entry);
	78
	79	static int __init early_debug_disable(char *buf)
	80	{
	81	debug_enabled = 0;
	82	return 0;
	83	}
	84
	85	early_param("nodebugmon", early_debug_disable);
	86
	87	/*
	88	* Keep track of debug users on each core.
	89	* The ref counts are per-cpu so we use a local_t type.
	90	*/
1436c1aa CL	91	static DEFINE_PER_CPU(int, mde_ref_count);
1436c1aa CL	92	static DEFINE_PER_CPU(int, kde_ref_count);
478fcb2c WD	93
	94	void enable_debug_monitors(enum debug_el el)
	95	{
	96	u32 mdscr, enable = 0;
	97
	98	WARN_ON(preemptible());
	99
1436c1aa	100	if (this_cpu_inc_return(mde_ref_count) == 1)
478fcb2c WD	101	enable = DBG_MDSCR_MDE;
	102
	103	if (el == DBG_ACTIVE_EL1 &&
1436c1aa	104	this_cpu_inc_return(kde_ref_count) == 1)
478fcb2c WD	105	enable \|= DBG_MDSCR_KDE;
	106
	107	if (enable && debug_enabled) {
	108	mdscr = mdscr_read();
	109	mdscr \|= enable;
	110	mdscr_write(mdscr);
	111	}
	112	}
	113
	114	void disable_debug_monitors(enum debug_el el)
	115	{
	116	u32 mdscr, disable = 0;
	117
	118	WARN_ON(preemptible());
	119
1436c1aa	120	if (this_cpu_dec_return(mde_ref_count) == 0)
478fcb2c WD	121	disable = ~DBG_MDSCR_MDE;
	122
	123	if (el == DBG_ACTIVE_EL1 &&
1436c1aa	124	this_cpu_dec_return(kde_ref_count) == 0)
478fcb2c WD	125	disable &= ~DBG_MDSCR_KDE;
	126
	127	if (disable) {
	128	mdscr = mdscr_read();
	129	mdscr &= disable;
	130	mdscr_write(mdscr);
	131	}
	132	}
	133
	134	/*
	135	* OS lock clearing.
	136	*/
	137	static void clear_os_lock(void *unused)
	138	{
478fcb2c WD	139	asm volatile("msr oslar_el1, %0" : : "r" (0));
	140	isb();
	141	}
	142
b8c6453a	143	static int os_lock_notify(struct notifier_block *self,
478fcb2c WD	144	unsigned long action, void *data)
	145	{
	146	int cpu = (unsigned long)data;
	147	if (action == CPU_ONLINE)
	148	smp_call_function_single(cpu, clear_os_lock, NULL, 1);
	149	return NOTIFY_OK;
	150	}
	151
b8c6453a	152	static struct notifier_block os_lock_nb = {
478fcb2c WD	153	.notifier_call = os_lock_notify,
	154	};
	155
b8c6453a	156	static int debug_monitors_init(void)
478fcb2c WD	157	{
	158	/* Clear the OS lock. */
	159	smp_call_function(clear_os_lock, NULL, 1);
	160	clear_os_lock(NULL);
	161
	162	/* Register hotplug handler. */
	163	register_cpu_notifier(&os_lock_nb);
	164	return 0;
	165	}
	166	postcore_initcall(debug_monitors_init);
	167
	168	/*
	169	* Single step API and exception handling.
	170	*/
	171	static void set_regs_spsr_ss(struct pt_regs *regs)
	172	{
	173	unsigned long spsr;
	174
	175	spsr = regs->pstate;
	176	spsr &= ~DBG_SPSR_SS;
	177	spsr \|= DBG_SPSR_SS;
	178	regs->pstate = spsr;
	179	}
	180
	181	static void clear_regs_spsr_ss(struct pt_regs *regs)
	182	{
	183	unsigned long spsr;
	184
	185	spsr = regs->pstate;
	186	spsr &= ~DBG_SPSR_SS;
	187	regs->pstate = spsr;
	188	}
	189
	190	static int single_step_handler(unsigned long addr, unsigned int esr,
	191	struct pt_regs *regs)
	192	{
	193	siginfo_t info;
	194
	195	/*
	196	* If we are stepping a pending breakpoint, call the hw_breakpoint
	197	* handler first.
	198	*/
	199	if (!reinstall_suspended_bps(regs))
	200	return 0;
	201
	202	if (user_mode(regs)) {
	203	info.si_signo = SIGTRAP;
	204	info.si_errno = 0;
	205	info.si_code = TRAP_HWBKPT;
	206	info.si_addr = (void __user *)instruction_pointer(regs);
	207	force_sig_info(SIGTRAP, &info, current);
	208
	209	/*
	210	* ptrace will disable single step unless explicitly
	211	* asked to re-enable it. For other clients, it makes
	212	* sense to leave it enabled (i.e. rewind the controls
	213	* to the active-not-pending state).
	214	*/
	215	user_rewind_single_step(current);
	216	} else {
	217	/* TODO: route to KGDB */
	218	pr_warning("Unexpected kernel single-step exception at EL1\n");
	219	/*
	220	* Re-enable stepping since we know that we will be
221	* returning to regs.
222	*/
223	set_regs_spsr_ss(regs);
224	}
225
226	return 0;
227	}
228
1442b6ed WD	229	static int brk_handler(unsigned long addr, unsigned int esr,
	230	struct pt_regs *regs)
	231	{
	232	siginfo_t info;
	233
	234	if (!user_mode(regs))
	235	return -EFAULT;
	236
	237	info = (siginfo_t) {
	238	.si_signo = SIGTRAP,
	239	.si_errno = 0,
	240	.si_code = TRAP_BRKPT,
	241	.si_addr = (void __user *)instruction_pointer(regs),
	242	};
	243
	244	force_sig_info(SIGTRAP, &info, current);
	245	return 0;
	246	}
	247
	248	int aarch32_break_handler(struct pt_regs *regs)
	249	{
	250	siginfo_t info;
2dacab73 ML	251	u32 arm_instr;
2dacab73 ML	252	u16 thumb_instr;
1442b6ed WD	253	bool bp = false;
	254	void __user pc = (void __user )instruction_pointer(regs);
	255
	256	if (!compat_user_mode(regs))
	257	return -EFAULT;
	258
	259	if (compat_thumb_mode(regs)) {
	260	/* get 16-bit Thumb instruction */
2dacab73 ML	261	get_user(thumb_instr, (u16 __user *)pc);
	262	thumb_instr = le16_to_cpu(thumb_instr);
	263	if (thumb_instr == AARCH32_BREAK_THUMB2_LO) {
1442b6ed	264	/* get second half of 32-bit Thumb-2 instruction */
2dacab73 ML	265	get_user(thumb_instr, (u16 __user *)(pc + 2));
	266	thumb_instr = le16_to_cpu(thumb_instr);
	267	bp = thumb_instr == AARCH32_BREAK_THUMB2_HI;
1442b6ed	268	} else {
2dacab73	269	bp = thumb_instr == AARCH32_BREAK_THUMB;
1442b6ed WD	270	}
	271	} else {
	272	/* 32-bit ARM instruction */
2dacab73 ML	273	get_user(arm_instr, (u32 __user *)pc);
	274	arm_instr = le32_to_cpu(arm_instr);
	275	bp = (arm_instr & ~0xf0000000) == AARCH32_BREAK_ARM;
1442b6ed WD	276	}
	277
	278	if (!bp)
	279	return -EFAULT;
	280
	281	info = (siginfo_t) {
	282	.si_signo = SIGTRAP,
	283	.si_errno = 0,
	284	.si_code = TRAP_BRKPT,
	285	.si_addr = pc,
	286	};
	287
	288	force_sig_info(SIGTRAP, &info, current);
	289	return 0;
	290	}
	291
	292	static int __init debug_traps_init(void)
478fcb2c WD	293	{
	294	hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP,
	295	TRAP_HWBKPT, "single-step handler");
1442b6ed WD	296	hook_debug_fault_code(DBG_ESR_EVT_BRK, brk_handler, SIGTRAP,
1442b6ed WD	297	TRAP_BRKPT, "ptrace BRK handler");
478fcb2c WD	298	return 0;
478fcb2c WD	299	}
1442b6ed	300	arch_initcall(debug_traps_init);
478fcb2c WD	301
	302	/* Re-enable single step for syscall restarting. */
	303	void user_rewind_single_step(struct task_struct *task)
	304	{
	305	/*
	306	* If single step is active for this thread, then set SPSR.SS
	307	* to 1 to avoid returning to the active-pending state.
	308	*/
	309	if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))
	310	set_regs_spsr_ss(task_pt_regs(task));
	311	}
	312
	313	void user_fastforward_single_step(struct task_struct *task)
	314	{
	315	if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))
	316	clear_regs_spsr_ss(task_pt_regs(task));
	317	}
	318
	319	/* Kernel API */
	320	void kernel_enable_single_step(struct pt_regs *regs)
	321	{
	322	WARN_ON(!irqs_disabled());
	323	set_regs_spsr_ss(regs);
	324	mdscr_write(mdscr_read() \| DBG_MDSCR_SS);
	325	enable_debug_monitors(DBG_ACTIVE_EL1);
	326	}
	327
	328	void kernel_disable_single_step(void)
	329	{
	330	WARN_ON(!irqs_disabled());
	331	mdscr_write(mdscr_read() & ~DBG_MDSCR_SS);
	332	disable_debug_monitors(DBG_ACTIVE_EL1);
	333	}
	334
	335	int kernel_active_single_step(void)
	336	{
	337	WARN_ON(!irqs_disabled());
	338	return mdscr_read() & DBG_MDSCR_SS;
	339	}
	340
	341	/* ptrace API */
	342	void user_enable_single_step(struct task_struct *task)
	343	{
	344	set_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);
	345	set_regs_spsr_ss(task_pt_regs(task));
	346	}
	347
	348	void user_disable_single_step(struct task_struct *task)
	349	{
	350	clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);
	351	}