Commit | Line | Data |
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478fcb2c WD |
1 | /* |
2 | * ARMv8 single-step debug support and mdscr context switching. | |
3 | * | |
4 | * Copyright (C) 2012 ARM Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: Will Deacon <will.deacon@arm.com> | |
19 | */ | |
20 | ||
21 | #include <linux/cpu.h> | |
22 | #include <linux/debugfs.h> | |
23 | #include <linux/hardirq.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/ptrace.h> | |
2dd0e8d2 | 26 | #include <linux/kprobes.h> |
478fcb2c | 27 | #include <linux/stat.h> |
1442b6ed | 28 | #include <linux/uaccess.h> |
478fcb2c | 29 | |
3085bb01 | 30 | #include <asm/cpufeature.h> |
478fcb2c | 31 | #include <asm/cputype.h> |
3085bb01 | 32 | #include <asm/debug-monitors.h> |
478fcb2c WD |
33 | #include <asm/system_misc.h> |
34 | ||
478fcb2c WD |
35 | /* Determine debug architecture. */ |
36 | u8 debug_monitors_arch(void) | |
37 | { | |
28c5dcb2 | 38 | return cpuid_feature_extract_unsigned_field(read_system_reg(SYS_ID_AA64DFR0_EL1), |
3085bb01 | 39 | ID_AA64DFR0_DEBUGVER_SHIFT); |
478fcb2c WD |
40 | } |
41 | ||
42 | /* | |
43 | * MDSCR access routines. | |
44 | */ | |
45 | static void mdscr_write(u32 mdscr) | |
46 | { | |
47 | unsigned long flags; | |
48 | local_dbg_save(flags); | |
49 | asm volatile("msr mdscr_el1, %0" :: "r" (mdscr)); | |
50 | local_dbg_restore(flags); | |
51 | } | |
52 | ||
53 | static u32 mdscr_read(void) | |
54 | { | |
55 | u32 mdscr; | |
56 | asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr)); | |
57 | return mdscr; | |
58 | } | |
59 | ||
60 | /* | |
61 | * Allow root to disable self-hosted debug from userspace. | |
62 | * This is useful if you want to connect an external JTAG debugger. | |
63 | */ | |
621a5f7a | 64 | static bool debug_enabled = true; |
478fcb2c WD |
65 | |
66 | static int create_debug_debugfs_entry(void) | |
67 | { | |
68 | debugfs_create_bool("debug_enabled", 0644, NULL, &debug_enabled); | |
69 | return 0; | |
70 | } | |
71 | fs_initcall(create_debug_debugfs_entry); | |
72 | ||
73 | static int __init early_debug_disable(char *buf) | |
74 | { | |
621a5f7a | 75 | debug_enabled = false; |
478fcb2c WD |
76 | return 0; |
77 | } | |
78 | ||
79 | early_param("nodebugmon", early_debug_disable); | |
80 | ||
81 | /* | |
82 | * Keep track of debug users on each core. | |
83 | * The ref counts are per-cpu so we use a local_t type. | |
84 | */ | |
1436c1aa CL |
85 | static DEFINE_PER_CPU(int, mde_ref_count); |
86 | static DEFINE_PER_CPU(int, kde_ref_count); | |
478fcb2c | 87 | |
6f883d10 | 88 | void enable_debug_monitors(enum dbg_active_el el) |
478fcb2c WD |
89 | { |
90 | u32 mdscr, enable = 0; | |
91 | ||
92 | WARN_ON(preemptible()); | |
93 | ||
1436c1aa | 94 | if (this_cpu_inc_return(mde_ref_count) == 1) |
478fcb2c WD |
95 | enable = DBG_MDSCR_MDE; |
96 | ||
97 | if (el == DBG_ACTIVE_EL1 && | |
1436c1aa | 98 | this_cpu_inc_return(kde_ref_count) == 1) |
478fcb2c WD |
99 | enable |= DBG_MDSCR_KDE; |
100 | ||
101 | if (enable && debug_enabled) { | |
102 | mdscr = mdscr_read(); | |
103 | mdscr |= enable; | |
104 | mdscr_write(mdscr); | |
105 | } | |
106 | } | |
107 | ||
6f883d10 | 108 | void disable_debug_monitors(enum dbg_active_el el) |
478fcb2c WD |
109 | { |
110 | u32 mdscr, disable = 0; | |
111 | ||
112 | WARN_ON(preemptible()); | |
113 | ||
1436c1aa | 114 | if (this_cpu_dec_return(mde_ref_count) == 0) |
478fcb2c WD |
115 | disable = ~DBG_MDSCR_MDE; |
116 | ||
117 | if (el == DBG_ACTIVE_EL1 && | |
1436c1aa | 118 | this_cpu_dec_return(kde_ref_count) == 0) |
478fcb2c WD |
119 | disable &= ~DBG_MDSCR_KDE; |
120 | ||
121 | if (disable) { | |
122 | mdscr = mdscr_read(); | |
123 | mdscr &= disable; | |
124 | mdscr_write(mdscr); | |
125 | } | |
126 | } | |
127 | ||
128 | /* | |
129 | * OS lock clearing. | |
130 | */ | |
131 | static void clear_os_lock(void *unused) | |
132 | { | |
478fcb2c | 133 | asm volatile("msr oslar_el1, %0" : : "r" (0)); |
478fcb2c WD |
134 | } |
135 | ||
b8c6453a | 136 | static int os_lock_notify(struct notifier_block *self, |
478fcb2c WD |
137 | unsigned long action, void *data) |
138 | { | |
e56d82a1 | 139 | if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE) |
499c8150 | 140 | clear_os_lock(NULL); |
478fcb2c WD |
141 | return NOTIFY_OK; |
142 | } | |
143 | ||
b8c6453a | 144 | static struct notifier_block os_lock_nb = { |
478fcb2c WD |
145 | .notifier_call = os_lock_notify, |
146 | }; | |
147 | ||
b8c6453a | 148 | static int debug_monitors_init(void) |
478fcb2c | 149 | { |
4b0b68af SB |
150 | cpu_notifier_register_begin(); |
151 | ||
478fcb2c | 152 | /* Clear the OS lock. */ |
d8ed442a VK |
153 | on_each_cpu(clear_os_lock, NULL, 1); |
154 | isb(); | |
155 | local_dbg_enable(); | |
478fcb2c WD |
156 | |
157 | /* Register hotplug handler. */ | |
4b0b68af SB |
158 | __register_cpu_notifier(&os_lock_nb); |
159 | ||
160 | cpu_notifier_register_done(); | |
478fcb2c WD |
161 | return 0; |
162 | } | |
163 | postcore_initcall(debug_monitors_init); | |
164 | ||
165 | /* | |
166 | * Single step API and exception handling. | |
167 | */ | |
168 | static void set_regs_spsr_ss(struct pt_regs *regs) | |
169 | { | |
170 | unsigned long spsr; | |
171 | ||
172 | spsr = regs->pstate; | |
173 | spsr &= ~DBG_SPSR_SS; | |
174 | spsr |= DBG_SPSR_SS; | |
175 | regs->pstate = spsr; | |
176 | } | |
177 | ||
178 | static void clear_regs_spsr_ss(struct pt_regs *regs) | |
179 | { | |
180 | unsigned long spsr; | |
181 | ||
182 | spsr = regs->pstate; | |
183 | spsr &= ~DBG_SPSR_SS; | |
184 | regs->pstate = spsr; | |
185 | } | |
186 | ||
ee6214ce SP |
187 | /* EL1 Single Step Handler hooks */ |
188 | static LIST_HEAD(step_hook); | |
cf0a2543 | 189 | static DEFINE_SPINLOCK(step_hook_lock); |
ee6214ce SP |
190 | |
191 | void register_step_hook(struct step_hook *hook) | |
192 | { | |
cf0a2543 YS |
193 | spin_lock(&step_hook_lock); |
194 | list_add_rcu(&hook->node, &step_hook); | |
195 | spin_unlock(&step_hook_lock); | |
ee6214ce SP |
196 | } |
197 | ||
198 | void unregister_step_hook(struct step_hook *hook) | |
199 | { | |
cf0a2543 YS |
200 | spin_lock(&step_hook_lock); |
201 | list_del_rcu(&hook->node); | |
202 | spin_unlock(&step_hook_lock); | |
203 | synchronize_rcu(); | |
ee6214ce SP |
204 | } |
205 | ||
206 | /* | |
95485fdc | 207 | * Call registered single step handlers |
ee6214ce SP |
208 | * There is no Syndrome info to check for determining the handler. |
209 | * So we call all the registered handlers, until the right handler is | |
210 | * found which returns zero. | |
211 | */ | |
212 | static int call_step_hook(struct pt_regs *regs, unsigned int esr) | |
213 | { | |
214 | struct step_hook *hook; | |
215 | int retval = DBG_HOOK_ERROR; | |
216 | ||
cf0a2543 | 217 | rcu_read_lock(); |
ee6214ce | 218 | |
cf0a2543 | 219 | list_for_each_entry_rcu(hook, &step_hook, node) { |
ee6214ce SP |
220 | retval = hook->fn(regs, esr); |
221 | if (retval == DBG_HOOK_HANDLED) | |
222 | break; | |
223 | } | |
224 | ||
cf0a2543 | 225 | rcu_read_unlock(); |
ee6214ce SP |
226 | |
227 | return retval; | |
228 | } | |
229 | ||
e04a28d4 WD |
230 | static void send_user_sigtrap(int si_code) |
231 | { | |
232 | struct pt_regs *regs = current_pt_regs(); | |
233 | siginfo_t info = { | |
234 | .si_signo = SIGTRAP, | |
235 | .si_errno = 0, | |
236 | .si_code = si_code, | |
237 | .si_addr = (void __user *)instruction_pointer(regs), | |
238 | }; | |
239 | ||
240 | if (WARN_ON(!user_mode(regs))) | |
241 | return; | |
242 | ||
243 | if (interrupts_enabled(regs)) | |
244 | local_irq_enable(); | |
245 | ||
246 | force_sig_info(SIGTRAP, &info, current); | |
247 | } | |
248 | ||
478fcb2c WD |
249 | static int single_step_handler(unsigned long addr, unsigned int esr, |
250 | struct pt_regs *regs) | |
251 | { | |
478fcb2c WD |
252 | /* |
253 | * If we are stepping a pending breakpoint, call the hw_breakpoint | |
254 | * handler first. | |
255 | */ | |
256 | if (!reinstall_suspended_bps(regs)) | |
257 | return 0; | |
258 | ||
259 | if (user_mode(regs)) { | |
e04a28d4 | 260 | send_user_sigtrap(TRAP_HWBKPT); |
478fcb2c WD |
261 | |
262 | /* | |
263 | * ptrace will disable single step unless explicitly | |
264 | * asked to re-enable it. For other clients, it makes | |
265 | * sense to leave it enabled (i.e. rewind the controls | |
266 | * to the active-not-pending state). | |
267 | */ | |
268 | user_rewind_single_step(current); | |
269 | } else { | |
2dd0e8d2 SP |
270 | #ifdef CONFIG_KPROBES |
271 | if (kprobe_single_step_handler(regs, esr) == DBG_HOOK_HANDLED) | |
272 | return 0; | |
273 | #endif | |
ee6214ce SP |
274 | if (call_step_hook(regs, esr) == DBG_HOOK_HANDLED) |
275 | return 0; | |
276 | ||
478fcb2c WD |
277 | pr_warning("Unexpected kernel single-step exception at EL1\n"); |
278 | /* | |
279 | * Re-enable stepping since we know that we will be | |
280 | * returning to regs. | |
281 | */ | |
282 | set_regs_spsr_ss(regs); | |
283 | } | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
ee6214ce SP |
288 | /* |
289 | * Breakpoint handler is re-entrant as another breakpoint can | |
290 | * hit within breakpoint handler, especically in kprobes. | |
291 | * Use reader/writer locks instead of plain spinlock. | |
292 | */ | |
293 | static LIST_HEAD(break_hook); | |
62c6c61a | 294 | static DEFINE_SPINLOCK(break_hook_lock); |
ee6214ce SP |
295 | |
296 | void register_break_hook(struct break_hook *hook) | |
297 | { | |
62c6c61a YS |
298 | spin_lock(&break_hook_lock); |
299 | list_add_rcu(&hook->node, &break_hook); | |
300 | spin_unlock(&break_hook_lock); | |
ee6214ce SP |
301 | } |
302 | ||
303 | void unregister_break_hook(struct break_hook *hook) | |
304 | { | |
62c6c61a YS |
305 | spin_lock(&break_hook_lock); |
306 | list_del_rcu(&hook->node); | |
307 | spin_unlock(&break_hook_lock); | |
308 | synchronize_rcu(); | |
ee6214ce SP |
309 | } |
310 | ||
311 | static int call_break_hook(struct pt_regs *regs, unsigned int esr) | |
312 | { | |
313 | struct break_hook *hook; | |
314 | int (*fn)(struct pt_regs *regs, unsigned int esr) = NULL; | |
315 | ||
62c6c61a YS |
316 | rcu_read_lock(); |
317 | list_for_each_entry_rcu(hook, &break_hook, node) | |
ee6214ce SP |
318 | if ((esr & hook->esr_mask) == hook->esr_val) |
319 | fn = hook->fn; | |
62c6c61a | 320 | rcu_read_unlock(); |
ee6214ce SP |
321 | |
322 | return fn ? fn(regs, esr) : DBG_HOOK_ERROR; | |
323 | } | |
324 | ||
1442b6ed WD |
325 | static int brk_handler(unsigned long addr, unsigned int esr, |
326 | struct pt_regs *regs) | |
327 | { | |
c878e0cf | 328 | if (user_mode(regs)) { |
e04a28d4 | 329 | send_user_sigtrap(TRAP_BRKPT); |
2dd0e8d2 SP |
330 | } |
331 | #ifdef CONFIG_KPROBES | |
332 | else if ((esr & BRK64_ESR_MASK) == BRK64_ESR_KPROBES) { | |
333 | if (kprobe_breakpoint_handler(regs, esr) != DBG_HOOK_HANDLED) | |
334 | return -EFAULT; | |
335 | } | |
336 | #endif | |
337 | else if (call_break_hook(regs, esr) != DBG_HOOK_HANDLED) { | |
338 | pr_warn("Unexpected kernel BRK exception at EL1\n"); | |
1442b6ed | 339 | return -EFAULT; |
c878e0cf | 340 | } |
1442b6ed | 341 | |
1442b6ed WD |
342 | return 0; |
343 | } | |
344 | ||
345 | int aarch32_break_handler(struct pt_regs *regs) | |
346 | { | |
2dacab73 ML |
347 | u32 arm_instr; |
348 | u16 thumb_instr; | |
1442b6ed WD |
349 | bool bp = false; |
350 | void __user *pc = (void __user *)instruction_pointer(regs); | |
351 | ||
352 | if (!compat_user_mode(regs)) | |
353 | return -EFAULT; | |
354 | ||
355 | if (compat_thumb_mode(regs)) { | |
356 | /* get 16-bit Thumb instruction */ | |
2dacab73 ML |
357 | get_user(thumb_instr, (u16 __user *)pc); |
358 | thumb_instr = le16_to_cpu(thumb_instr); | |
359 | if (thumb_instr == AARCH32_BREAK_THUMB2_LO) { | |
1442b6ed | 360 | /* get second half of 32-bit Thumb-2 instruction */ |
2dacab73 ML |
361 | get_user(thumb_instr, (u16 __user *)(pc + 2)); |
362 | thumb_instr = le16_to_cpu(thumb_instr); | |
363 | bp = thumb_instr == AARCH32_BREAK_THUMB2_HI; | |
1442b6ed | 364 | } else { |
2dacab73 | 365 | bp = thumb_instr == AARCH32_BREAK_THUMB; |
1442b6ed WD |
366 | } |
367 | } else { | |
368 | /* 32-bit ARM instruction */ | |
2dacab73 ML |
369 | get_user(arm_instr, (u32 __user *)pc); |
370 | arm_instr = le32_to_cpu(arm_instr); | |
371 | bp = (arm_instr & ~0xf0000000) == AARCH32_BREAK_ARM; | |
1442b6ed WD |
372 | } |
373 | ||
374 | if (!bp) | |
375 | return -EFAULT; | |
376 | ||
e04a28d4 | 377 | send_user_sigtrap(TRAP_BRKPT); |
1442b6ed WD |
378 | return 0; |
379 | } | |
380 | ||
381 | static int __init debug_traps_init(void) | |
478fcb2c WD |
382 | { |
383 | hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP, | |
384 | TRAP_HWBKPT, "single-step handler"); | |
1442b6ed WD |
385 | hook_debug_fault_code(DBG_ESR_EVT_BRK, brk_handler, SIGTRAP, |
386 | TRAP_BRKPT, "ptrace BRK handler"); | |
478fcb2c WD |
387 | return 0; |
388 | } | |
1442b6ed | 389 | arch_initcall(debug_traps_init); |
478fcb2c WD |
390 | |
391 | /* Re-enable single step for syscall restarting. */ | |
392 | void user_rewind_single_step(struct task_struct *task) | |
393 | { | |
394 | /* | |
395 | * If single step is active for this thread, then set SPSR.SS | |
396 | * to 1 to avoid returning to the active-pending state. | |
397 | */ | |
398 | if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP)) | |
399 | set_regs_spsr_ss(task_pt_regs(task)); | |
400 | } | |
401 | ||
402 | void user_fastforward_single_step(struct task_struct *task) | |
403 | { | |
404 | if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP)) | |
405 | clear_regs_spsr_ss(task_pt_regs(task)); | |
406 | } | |
407 | ||
408 | /* Kernel API */ | |
409 | void kernel_enable_single_step(struct pt_regs *regs) | |
410 | { | |
411 | WARN_ON(!irqs_disabled()); | |
412 | set_regs_spsr_ss(regs); | |
413 | mdscr_write(mdscr_read() | DBG_MDSCR_SS); | |
414 | enable_debug_monitors(DBG_ACTIVE_EL1); | |
415 | } | |
416 | ||
417 | void kernel_disable_single_step(void) | |
418 | { | |
419 | WARN_ON(!irqs_disabled()); | |
420 | mdscr_write(mdscr_read() & ~DBG_MDSCR_SS); | |
421 | disable_debug_monitors(DBG_ACTIVE_EL1); | |
422 | } | |
423 | ||
424 | int kernel_active_single_step(void) | |
425 | { | |
426 | WARN_ON(!irqs_disabled()); | |
427 | return mdscr_read() & DBG_MDSCR_SS; | |
428 | } | |
429 | ||
430 | /* ptrace API */ | |
431 | void user_enable_single_step(struct task_struct *task) | |
432 | { | |
433 | set_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP); | |
434 | set_regs_spsr_ss(task_pt_regs(task)); | |
435 | } | |
436 | ||
437 | void user_disable_single_step(struct task_struct *task) | |
438 | { | |
439 | clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP); | |
440 | } |