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arm64: Use existing defines for mdscr
[linux-2.6-block.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57 21#include <linux/bsearch.h>
2a6dcb2b 22#include <linux/cpumask.h>
3c739b57 23#include <linux/sort.h>
2a6dcb2b 24#include <linux/stop_machine.h>
359b7064 25#include <linux/types.h>
2077be67 26#include <linux/mm.h>
359b7064
MZ		 27#include <asm/cpu.h>
28#include <asm/cpufeature.h>
dbb4e152 29#include <asm/cpu_ops.h>
13f417f3 30#include <asm/mmu_context.h>
338d4f49 31#include <asm/processor.h>
cdcf817b 32#include <asm/sysreg.h>
77c97b4e 33#include <asm/traps.h>
d88701be 34#include <asm/virt.h>
359b7064 35
9cdf8ec4
SP		 36unsigned long elf_hwcap __read_mostly;
37EXPORT_SYMBOL_GPL(elf_hwcap);
38
39#ifdef CONFIG_COMPAT
40#define COMPAT_ELF_HWCAP_DEFAULT \
41 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
42 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
43 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
44 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
45 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
46 COMPAT_HWCAP_LPAE)
47unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
48unsigned int compat_elf_hwcap2 __read_mostly;
49#endif
50
51DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
4b65a5db 52EXPORT_SYMBOL(cpu_hwcaps);
9cdf8ec4 53
8effeaaf
MR		 54static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
55{
56 /* file-wide pr_fmt adds "CPU features: " prefix */
57 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
58 return 0;
59}
60
61static struct notifier_block cpu_hwcaps_notifier = {
62 .notifier_call = dump_cpu_hwcaps
63};
64
65static int __init register_cpu_hwcaps_dumper(void)
66{
67 atomic_notifier_chain_register(&panic_notifier_list,
68 &cpu_hwcaps_notifier);
69 return 0;
70}
71__initcall(register_cpu_hwcaps_dumper);
72
efd9e03f
CM		 73DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
74EXPORT_SYMBOL(cpu_hwcap_keys);
75
fe4fbdbc 76#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 77 { \
4f0a606b 78 .sign = SIGNED, \
fe4fbdbc 79 .visible = VISIBLE, \
3c739b57
SP		 80 .strict = STRICT, \
81 .type = TYPE, \
82 .shift = SHIFT, \
83 .width = WIDTH, \
84 .safe_val = SAFE_VAL, \
85 }
86
0710cfdb 87/* Define a feature with unsigned values */
fe4fbdbc
SP		 88#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
89 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
4f0a606b 90
0710cfdb 91/* Define a feature with a signed value */
fe4fbdbc
SP		 92#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
93 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
0710cfdb 94
3c739b57
SP		 95#define ARM64_FTR_END \
96 { \
97 .width = 0, \
98 }
99
70544196
JM		 100/* meta feature for alternatives */
101static bool __maybe_unused
92406f0c
SP		 102cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
103
70544196 104
4aa8a472
SP		 105/*
106 * NOTE: Any changes to the visibility of features should be kept in
107 * sync with the documentation of the CPU feature register ABI.
108 */
5e49d73c 109static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
5bdecb79
SP		 110 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
111 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
112 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
113 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
114 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
fe4fbdbc
SP		 115 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
116 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
117 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
118 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
119 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
3c739b57
SP		 120 ARM64_FTR_END,
121};
122
c8c3798d 123static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
5bdecb79
SP		 124 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
125 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
c8c3798d
SP		 128 ARM64_FTR_END,
129};
130
5e49d73c 131static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
5bdecb79 132 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
fe4fbdbc
SP		 133 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
134 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57 135 /* Linux doesn't care about the EL3 */
5bdecb79
SP		 136 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
137 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
138 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
139 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
3c739b57
SP		 140 ARM64_FTR_END,
141};
142
5e49d73c 143static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
5bdecb79
SP		 144 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
145 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
146 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
147 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
3c739b57 148 /* Linux shouldn't care about secure memory */
5bdecb79
SP		 149 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
150 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
151 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
3c739b57
SP		 152 /*
153 * Differing PARange is fine as long as all peripherals and memory are mapped
154 * within the minimum PARange of all CPUs
155 */
fe4fbdbc 156 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 157 ARM64_FTR_END,
158};
159
5e49d73c 160static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
fe4fbdbc 161 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
5bdecb79
SP		 162 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
163 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
164 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
165 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
166 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
3c739b57
SP		 167 ARM64_FTR_END,
168};
169
5e49d73c 170static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
5bdecb79
SP		 171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
172 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
173 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
174 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
175 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 176 ARM64_FTR_END,
177};
178
5e49d73c 179static const struct arm64_ftr_bits ftr_ctr[] = {
fe4fbdbc
SP		 180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
182 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
3c739b57
SP		 184 /*
185 * Linux can handle differing I-cache policies. Userspace JITs will
ee7bc638 186 * make use of *minLine.
155433cb 187 * If we have differing I-cache policies, report it as the weakest - VIPT.
3c739b57 188 */
155433cb 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
fe4fbdbc 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
3c739b57
SP		 191 ARM64_FTR_END,
192};
193
675b0563
AB		 194struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
195 .name = "SYS_CTR_EL0",
196 .ftr_bits = ftr_ctr
197};
198
5e49d73c 199static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
5bdecb79
SP		 200 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
201 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
fe4fbdbc 202 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
5bdecb79
SP		 203 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
205 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
206 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
3c739b57
SP		 208 ARM64_FTR_END,
209};
210
5e49d73c 211static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
fe4fbdbc
SP		 212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
213 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
214 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
b20d1ba3
WD		 217 /*
218 * We can instantiate multiple PMU instances with different levels
219 * of support.
fe4fbdbc
SP		 220 */
221 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 224 ARM64_FTR_END,
225};
226
5e49d73c 227static const struct arm64_ftr_bits ftr_mvfr2[] = {
5bdecb79
SP		 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
3c739b57
SP		 230 ARM64_FTR_END,
231};
232
5e49d73c 233static const struct arm64_ftr_bits ftr_dczid[] = {
fe4fbdbc
SP		 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
3c739b57
SP		 236 ARM64_FTR_END,
237};
238
239
5e49d73c 240static const struct arm64_ftr_bits ftr_id_isar5[] = {
5bdecb79
SP		 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
3c739b57
SP		 247 ARM64_FTR_END,
248};
249
5e49d73c 250static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
5bdecb79 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
3c739b57
SP		 252 ARM64_FTR_END,
253};
254
5e49d73c 255static const struct arm64_ftr_bits ftr_id_pfr0[] = {
5bdecb79
SP		 256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
257 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
3c739b57
SP		 260 ARM64_FTR_END,
261};
262
5e49d73c 263static const struct arm64_ftr_bits ftr_id_dfr0[] = {
fe4fbdbc
SP		 264 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
265 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
266 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
270 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
271 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
e5343503
SP		 272 ARM64_FTR_END,
273};
274
3c739b57
SP		 275/*
276 * Common ftr bits for a 32bit register with all hidden, strict
277 * attributes, with 4bit feature fields and a default safe value of
278 * 0. Covers the following 32bit registers:
279 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
280 */
5e49d73c 281static const struct arm64_ftr_bits ftr_generic_32bits[] = {
fe4fbdbc
SP		 282 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
285 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
3c739b57
SP		 290 ARM64_FTR_END,
291};
292
eab43e88
SP		 293/* Table for a single 32bit feature value */
294static const struct arm64_ftr_bits ftr_single32[] = {
fe4fbdbc 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
3c739b57
SP		 296 ARM64_FTR_END,
297};
298
eab43e88 299static const struct arm64_ftr_bits ftr_raz[] = {
3c739b57
SP		 300 ARM64_FTR_END,
301};
302
6f2b7eef
AB		 303#define ARM64_FTR_REG(id, table) { \
304 .sys_id = id, \
305 .reg = &(struct arm64_ftr_reg){ \
3c739b57
SP		 306 .name = #id, \
307 .ftr_bits = &((table)[0]), \
6f2b7eef 308 }}
3c739b57 309
6f2b7eef
AB		 310static const struct __ftr_reg_entry {
311 u32 sys_id;
312 struct arm64_ftr_reg *reg;
313} arm64_ftr_regs[] = {
3c739b57
SP		 314
315 /* Op1 = 0, CRn = 0, CRm = 1 */
316 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
317 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 318 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 319 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
320 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
321 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
322 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
323
324 /* Op1 = 0, CRn = 0, CRm = 2 */
325 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
326 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
327 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
328 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
329 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
330 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
331 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
332
333 /* Op1 = 0, CRn = 0, CRm = 3 */
334 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
335 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
336 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
337
338 /* Op1 = 0, CRn = 0, CRm = 4 */
339 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
eab43e88 340 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz),
3c739b57
SP		 341
342 /* Op1 = 0, CRn = 0, CRm = 5 */
343 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
eab43e88 344 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
3c739b57
SP		 345
346 /* Op1 = 0, CRn = 0, CRm = 6 */
347 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
c8c3798d 348 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
3c739b57
SP		 349
350 /* Op1 = 0, CRn = 0, CRm = 7 */
351 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
352 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 353 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57
SP		 354
355 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 356 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP		 357 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
358
359 /* Op1 = 3, CRn = 14, CRm = 0 */
eab43e88 360 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
3c739b57
SP		 361};
362
363static int search_cmp_ftr_reg(const void *id, const void *regp)
364{
6f2b7eef 365 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP		 366}
367
368/*
369 * get_arm64_ftr_reg - Lookup a feature register entry using its
370 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
371 * ascending order of sys_id , we use binary search to find a matching
372 * entry.
373 *
374 * returns - Upon success, matching ftr_reg entry for id.
375 * - NULL on failure. It is upto the caller to decide
376 * the impact of a failure.
377 */
378static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
379{
6f2b7eef
AB		 380 const struct __ftr_reg_entry *ret;
381
382 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP		 383 arm64_ftr_regs,
384 ARRAY_SIZE(arm64_ftr_regs),
385 sizeof(arm64_ftr_regs[0]),
386 search_cmp_ftr_reg);
6f2b7eef
AB		 387 if (ret)
388 return ret->reg;
389 return NULL;
3c739b57
SP		 390}
391
5e49d73c
AB		 392static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
393 s64 ftr_val)
3c739b57
SP		 394{
395 u64 mask = arm64_ftr_mask(ftrp);
396
397 reg &= ~mask;
398 reg |= (ftr_val << ftrp->shift) & mask;
399 return reg;
400}
401
5e49d73c
AB		 402static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
403 s64 cur)
3c739b57
SP		 404{
405 s64 ret = 0;
406
407 switch (ftrp->type) {
408 case FTR_EXACT:
409 ret = ftrp->safe_val;
410 break;
411 case FTR_LOWER_SAFE:
412 ret = new < cur ? new : cur;
413 break;
414 case FTR_HIGHER_SAFE:
415 ret = new > cur ? new : cur;
416 break;
417 default:
418 BUG();
419 }
420
421 return ret;
422}
423
3c739b57
SP		 424static void __init sort_ftr_regs(void)
425{
6f2b7eef
AB		 426 int i;
427
428 /* Check that the array is sorted so that we can do the binary search */
429 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
430 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP		 431}
432
433/*
434 * Initialise the CPU feature register from Boot CPU values.
435 * Also initiliases the strict_mask for the register.
b389d799
MR		 436 * Any bits that are not covered by an arm64_ftr_bits entry are considered
437 * RES0 for the system-wide value, and must strictly match.
3c739b57
SP		 438 */
439static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
440{
441 u64 val = 0;
442 u64 strict_mask = ~0x0ULL;
fe4fbdbc 443 u64 user_mask = 0;
b389d799
MR		 444 u64 valid_mask = 0;
445
5e49d73c 446 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 447 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
448
449 BUG_ON(!reg);
450
451 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
b389d799 452 u64 ftr_mask = arm64_ftr_mask(ftrp);
3c739b57
SP		 453 s64 ftr_new = arm64_ftr_value(ftrp, new);
454
455 val = arm64_ftr_set_value(ftrp, val, ftr_new);
b389d799
MR		 456
457 valid_mask |= ftr_mask;
3c739b57 458 if (!ftrp->strict)
b389d799 459 strict_mask &= ~ftr_mask;
fe4fbdbc
SP		 460 if (ftrp->visible)
461 user_mask |= ftr_mask;
462 else
463 reg->user_val = arm64_ftr_set_value(ftrp,
464 reg->user_val,
465 ftrp->safe_val);
3c739b57 466 }
b389d799
MR		 467
468 val &= valid_mask;
469
3c739b57
SP		 470 reg->sys_val = val;
471 reg->strict_mask = strict_mask;
fe4fbdbc 472 reg->user_mask = user_mask;
3c739b57
SP		 473}
474
475void __init init_cpu_features(struct cpuinfo_arm64 *info)
476{
477 /* Before we start using the tables, make sure it is sorted */
478 sort_ftr_regs();
479
480 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
481 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
482 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
483 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
484 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
485 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
486 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
487 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
488 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 489 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 490 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
491 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
a6dc3cd7
SP		 492
493 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
494 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
495 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
496 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
497 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
498 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
499 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
500 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
501 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
502 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
503 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
504 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
505 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
506 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
507 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
508 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
509 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
510 }
511
3c739b57
SP		 512}
513
3086d391 514static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 515{
5e49d73c 516 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 517
518 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
519 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
520 s64 ftr_new = arm64_ftr_value(ftrp, new);
521
522 if (ftr_cur == ftr_new)
523 continue;
524 /* Find a safe value */
525 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
526 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
527 }
528
529}
530
3086d391 531static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 532{
3086d391
SP		 533 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
534
535 BUG_ON(!regp);
536 update_cpu_ftr_reg(regp, val);
537 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
538 return 0;
539 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
540 regp->name, boot, cpu, val);
541 return 1;
542}
543
544/*
545 * Update system wide CPU feature registers with the values from a
546 * non-boot CPU. Also performs SANITY checks to make sure that there
547 * aren't any insane variations from that of the boot CPU.
548 */
549void update_cpu_features(int cpu,
550 struct cpuinfo_arm64 *info,
551 struct cpuinfo_arm64 *boot)
552{
553 int taint = 0;
554
555 /*
556 * The kernel can handle differing I-cache policies, but otherwise
557 * caches should look identical. Userspace JITs will make use of
558 * *minLine.
559 */
560 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
561 info->reg_ctr, boot->reg_ctr);
562
563 /*
564 * Userspace may perform DC ZVA instructions. Mismatched block sizes
565 * could result in too much or too little memory being zeroed if a
566 * process is preempted and migrated between CPUs.
567 */
568 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
569 info->reg_dczid, boot->reg_dczid);
570
571 /* If different, timekeeping will be broken (especially with KVM) */
572 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
573 info->reg_cntfrq, boot->reg_cntfrq);
574
575 /*
576 * The kernel uses self-hosted debug features and expects CPUs to
577 * support identical debug features. We presently need CTX_CMPs, WRPs,
578 * and BRPs to be identical.
579 * ID_AA64DFR1 is currently RES0.
580 */
581 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
582 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
583 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
584 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
585 /*
586 * Even in big.LITTLE, processors should be identical instruction-set
587 * wise.
588 */
589 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
590 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
591 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
592 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
593
594 /*
595 * Differing PARange support is fine as long as all peripherals and
596 * memory are mapped within the minimum PARange of all CPUs.
597 * Linux should not care about secure memory.
598 */
599 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
600 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
601 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
602 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 603 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
604 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 605
606 /*
607 * EL3 is not our concern.
608 * ID_AA64PFR1 is currently RES0.
609 */
610 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
611 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
612 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
613 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
614
615 /*
a6dc3cd7
SP		 616 * If we have AArch32, we care about 32-bit features for compat.
617 * If the system doesn't support AArch32, don't update them.
3086d391 618 */
46823dd1 619 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
a6dc3cd7
SP		 620 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
621
622 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
3086d391 623 info->reg_id_dfr0, boot->reg_id_dfr0);
a6dc3cd7 624 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
3086d391 625 info->reg_id_isar0, boot->reg_id_isar0);
a6dc3cd7 626 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
3086d391 627 info->reg_id_isar1, boot->reg_id_isar1);
a6dc3cd7 628 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
3086d391 629 info->reg_id_isar2, boot->reg_id_isar2);
a6dc3cd7 630 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
3086d391 631 info->reg_id_isar3, boot->reg_id_isar3);
a6dc3cd7 632 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
3086d391 633 info->reg_id_isar4, boot->reg_id_isar4);
a6dc3cd7 634 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
3086d391
SP		 635 info->reg_id_isar5, boot->reg_id_isar5);
636
a6dc3cd7
SP		 637 /*
638 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
639 * ACTLR formats could differ across CPUs and therefore would have to
640 * be trapped for virtualization anyway.
641 */
642 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
3086d391 643 info->reg_id_mmfr0, boot->reg_id_mmfr0);
a6dc3cd7 644 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
3086d391 645 info->reg_id_mmfr1, boot->reg_id_mmfr1);
a6dc3cd7 646 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
3086d391 647 info->reg_id_mmfr2, boot->reg_id_mmfr2);
a6dc3cd7 648 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
3086d391 649 info->reg_id_mmfr3, boot->reg_id_mmfr3);
a6dc3cd7 650 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
3086d391 651 info->reg_id_pfr0, boot->reg_id_pfr0);
a6dc3cd7 652 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
3086d391 653 info->reg_id_pfr1, boot->reg_id_pfr1);
a6dc3cd7 654 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
3086d391 655 info->reg_mvfr0, boot->reg_mvfr0);
a6dc3cd7 656 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
3086d391 657 info->reg_mvfr1, boot->reg_mvfr1);
a6dc3cd7 658 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
3086d391 659 info->reg_mvfr2, boot->reg_mvfr2);
a6dc3cd7 660 }
3086d391
SP		 661
662 /*
663 * Mismatched CPU features are a recipe for disaster. Don't even
664 * pretend to support them.
665 */
8dd0ee65
WD		 666 if (taint) {
667 pr_warn_once("Unsupported CPU feature variation detected.\n");
668 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
669 }
cdcf817b
SP		 670}
671
46823dd1 672u64 read_sanitised_ftr_reg(u32 id)
b3f15378
SP		 673{
674 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
675
676 /* We shouldn't get a request for an unsupported register */
677 BUG_ON(!regp);
678 return regp->sys_val;
679}
359b7064 680
965861d6
MR		 681#define read_sysreg_case(r) \
682 case r: return read_sysreg_s(r)
683
92406f0c 684/*
46823dd1 685 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
92406f0c
SP		 686 * Read the system register on the current CPU
687 */
46823dd1 688static u64 __read_sysreg_by_encoding(u32 sys_id)
92406f0c
SP		 689{
690 switch (sys_id) {
965861d6
MR		 691 read_sysreg_case(SYS_ID_PFR0_EL1);
692 read_sysreg_case(SYS_ID_PFR1_EL1);
693 read_sysreg_case(SYS_ID_DFR0_EL1);
694 read_sysreg_case(SYS_ID_MMFR0_EL1);
695 read_sysreg_case(SYS_ID_MMFR1_EL1);
696 read_sysreg_case(SYS_ID_MMFR2_EL1);
697 read_sysreg_case(SYS_ID_MMFR3_EL1);
698 read_sysreg_case(SYS_ID_ISAR0_EL1);
699 read_sysreg_case(SYS_ID_ISAR1_EL1);
700 read_sysreg_case(SYS_ID_ISAR2_EL1);
701 read_sysreg_case(SYS_ID_ISAR3_EL1);
702 read_sysreg_case(SYS_ID_ISAR4_EL1);
703 read_sysreg_case(SYS_ID_ISAR5_EL1);
704 read_sysreg_case(SYS_MVFR0_EL1);
705 read_sysreg_case(SYS_MVFR1_EL1);
706 read_sysreg_case(SYS_MVFR2_EL1);
707
708 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
709 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
710 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
711 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
712 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
713 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
714 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
715 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
716 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
717
718 read_sysreg_case(SYS_CNTFRQ_EL0);
719 read_sysreg_case(SYS_CTR_EL0);
720 read_sysreg_case(SYS_DCZID_EL0);
721
92406f0c
SP		 722 default:
723 BUG();
724 return 0;
725 }
726}
727
963fcd40
MZ		 728#include <linux/irqchip/arm-gic-v3.h>
729
18ffa046
JM		 730static bool
731feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
732{
28c5dcb2 733 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 734
735 return val >= entry->min_field_value;
736}
737
da8d02d1 738static bool
92406f0c 739has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 740{
741 u64 val;
94a9e04a 742
92406f0c
SP		 743 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
744 if (scope == SCOPE_SYSTEM)
46823dd1 745 val = read_sanitised_ftr_reg(entry->sys_reg);
92406f0c 746 else
46823dd1 747 val = __read_sysreg_by_encoding(entry->sys_reg);
92406f0c 748
da8d02d1
SP		 749 return feature_matches(val, entry);
750}
338d4f49 751
92406f0c 752static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 753{
754 bool has_sre;
755
92406f0c 756 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 757 return false;
758
759 has_sre = gic_enable_sre();
760 if (!has_sre)
761 pr_warn_once("%s present but disabled by higher exception level\n",
762 entry->desc);
763
764 return has_sre;
765}
766
92406f0c 767static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 768{
769 u32 midr = read_cpuid_id();
d5370f75
WD		 770
771 /* Cavium ThunderX pass 1.x and 2.x */
fa5ce3d1
RR		 772 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
773 MIDR_CPU_VAR_REV(0, 0),
774 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
d5370f75
WD		 775}
776
92406f0c 777static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
d88701be
MZ		 778{
779 return is_kernel_in_hyp_mode();
780}
781
d1745910
MZ		 782static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
783 int __unused)
784{
2077be67 785 phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
d1745910
MZ		 786
787 /*
788 * Activate the lower HYP offset only if:
789 * - the idmap doesn't clash with it,
790 * - the kernel is not running at EL2.
791 */
792 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
793}
794
82e0191a
SP		 795static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
796{
46823dd1 797 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
82e0191a
SP		 798
799 return cpuid_feature_extract_signed_field(pfr0,
800 ID_AA64PFR0_FP_SHIFT) < 0;
801}
802
359b7064 803static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 804 {
805 .desc = "GIC system register CPU interface",
806 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
92406f0c 807 .def_scope = SCOPE_SYSTEM,
963fcd40 808 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 809 .sys_reg = SYS_ID_AA64PFR0_EL1,
810 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 811 .sign = FTR_UNSIGNED,
18ffa046 812 .min_field_value = 1,
94a9e04a 813 },
338d4f49
JM		 814#ifdef CONFIG_ARM64_PAN
815 {
816 .desc = "Privileged Access Never",
817 .capability = ARM64_HAS_PAN,
92406f0c 818 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP		 819 .matches = has_cpuid_feature,
820 .sys_reg = SYS_ID_AA64MMFR1_EL1,
821 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 822 .sign = FTR_UNSIGNED,
338d4f49
JM		 823 .min_field_value = 1,
824 .enable = cpu_enable_pan,
825 },
826#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 827#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
828 {
829 .desc = "LSE atomic instructions",
830 .capability = ARM64_HAS_LSE_ATOMICS,
92406f0c 831 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP		 832 .matches = has_cpuid_feature,
833 .sys_reg = SYS_ID_AA64ISAR0_EL1,
834 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 835 .sign = FTR_UNSIGNED,
2e94da13
WD		 836 .min_field_value = 2,
837 },
838#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 839 {
840 .desc = "Software prefetching using PRFM",
841 .capability = ARM64_HAS_NO_HW_PREFETCH,
92406f0c 842 .def_scope = SCOPE_SYSTEM,
d5370f75
WD		 843 .matches = has_no_hw_prefetch,
844 },
57f4959b
JM		 845#ifdef CONFIG_ARM64_UAO
846 {
847 .desc = "User Access Override",
848 .capability = ARM64_HAS_UAO,
92406f0c 849 .def_scope = SCOPE_SYSTEM,
57f4959b
JM		 850 .matches = has_cpuid_feature,
851 .sys_reg = SYS_ID_AA64MMFR2_EL1,
852 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
853 .min_field_value = 1,
c8b06e3f
JM		 854 /*
855 * We rely on stop_machine() calling uao_thread_switch() to set
856 * UAO immediately after patching.
857 */
57f4959b
JM		 858 },
859#endif /* CONFIG_ARM64_UAO */
70544196
JM		 860#ifdef CONFIG_ARM64_PAN
861 {
862 .capability = ARM64_ALT_PAN_NOT_UAO,
92406f0c 863 .def_scope = SCOPE_SYSTEM,
70544196
JM		 864 .matches = cpufeature_pan_not_uao,
865 },
866#endif /* CONFIG_ARM64_PAN */
d88701be
MZ		 867 {
868 .desc = "Virtualization Host Extensions",
869 .capability = ARM64_HAS_VIRT_HOST_EXTN,
92406f0c 870 .def_scope = SCOPE_SYSTEM,
d88701be
MZ		 871 .matches = runs_at_el2,
872 },
042446a3
SP		 873 {
874 .desc = "32-bit EL0 Support",
875 .capability = ARM64_HAS_32BIT_EL0,
92406f0c 876 .def_scope = SCOPE_SYSTEM,
042446a3
SP		 877 .matches = has_cpuid_feature,
878 .sys_reg = SYS_ID_AA64PFR0_EL1,
879 .sign = FTR_UNSIGNED,
880 .field_pos = ID_AA64PFR0_EL0_SHIFT,
881 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
882 },
d1745910
MZ		 883 {
884 .desc = "Reduced HYP mapping offset",
885 .capability = ARM64_HYP_OFFSET_LOW,
886 .def_scope = SCOPE_SYSTEM,
887 .matches = hyp_offset_low,
888 },
82e0191a
SP		 889 {
890 /* FP/SIMD is not implemented */
891 .capability = ARM64_HAS_NO_FPSIMD,
892 .def_scope = SCOPE_SYSTEM,
893 .min_field_value = 0,
894 .matches = has_no_fpsimd,
895 },
d50e071f
RM		 896#ifdef CONFIG_ARM64_PMEM
897 {
898 .desc = "Data cache clean to Point of Persistence",
899 .capability = ARM64_HAS_DCPOP,
900 .def_scope = SCOPE_SYSTEM,
901 .matches = has_cpuid_feature,
902 .sys_reg = SYS_ID_AA64ISAR1_EL1,
903 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
904 .min_field_value = 1,
905 },
906#endif
359b7064
MZ		 907 {},
908};
909
ff96f7bc 910#define HWCAP_CAP(reg, field, s, min_value, type, cap) \
37b01d53
SP		 911 { \
912 .desc = #cap, \
92406f0c 913 .def_scope = SCOPE_SYSTEM, \
37b01d53
SP		 914 .matches = has_cpuid_feature, \
915 .sys_reg = reg, \
916 .field_pos = field, \
ff96f7bc 917 .sign = s, \
37b01d53
SP		 918 .min_field_value = min_value, \
919 .hwcap_type = type, \
920 .hwcap = cap, \
921 }
922
f3efb675 923static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
ff96f7bc
SP		 924 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
925 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
926 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
927 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
f5e035f8 928 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
ff96f7bc
SP		 929 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
930 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
f92f5ce0 931 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
f5e035f8
SP		 932 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
933 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
934 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
935 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
ff96f7bc 936 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
bf500618 937 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
ff96f7bc 938 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
bf500618 939 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
7aac405e 940 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
c8c3798d 941 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
cb567e79 942 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
c651aae5 943 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
75283501
SP		 944 {},
945};
946
947static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 948#ifdef CONFIG_COMPAT
ff96f7bc
SP		 949 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
950 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
951 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
952 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
953 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 954#endif
955 {},
956};
957
f3efb675 958static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 959{
960 switch (cap->hwcap_type) {
961 case CAP_HWCAP:
962 elf_hwcap |= cap->hwcap;
963 break;
964#ifdef CONFIG_COMPAT
965 case CAP_COMPAT_HWCAP:
966 compat_elf_hwcap |= (u32)cap->hwcap;
967 break;
968 case CAP_COMPAT_HWCAP2:
969 compat_elf_hwcap2 |= (u32)cap->hwcap;
970 break;
971#endif
972 default:
973 WARN_ON(1);
974 break;
975 }
976}
977
978/* Check if we have a particular HWCAP enabled */
f3efb675 979static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 980{
981 bool rc;
982
983 switch (cap->hwcap_type) {
984 case CAP_HWCAP:
985 rc = (elf_hwcap & cap->hwcap) != 0;
986 break;
987#ifdef CONFIG_COMPAT
988 case CAP_COMPAT_HWCAP:
989 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
990 break;
991 case CAP_COMPAT_HWCAP2:
992 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
993 break;
994#endif
995 default:
996 WARN_ON(1);
997 rc = false;
998 }
999
1000 return rc;
1001}
1002
75283501 1003static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 1004{
77c97b4e
SP		 1005 /* We support emulation of accesses to CPU ID feature registers */
1006 elf_hwcap |= HWCAP_CPUID;
75283501 1007 for (; hwcaps->matches; hwcaps++)
92406f0c 1008 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
75283501 1009 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 1010}
1011
ce8b602c 1012void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
359b7064
MZ		 1013 const char *info)
1014{
75283501 1015 for (; caps->matches; caps++) {
92406f0c 1016 if (!caps->matches(caps, caps->def_scope))
359b7064
MZ		 1017 continue;
1018
75283501
SP		 1019 if (!cpus_have_cap(caps->capability) && caps->desc)
1020 pr_info("%s %s\n", info, caps->desc);
1021 cpus_set_cap(caps->capability);
359b7064 1022 }
ce8b602c
SP		 1023}
1024
1025/*
dbb4e152
SP		 1026 * Run through the enabled capabilities and enable() it on all active
1027 * CPUs
ce8b602c 1028 */
8e231852 1029void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
ce8b602c 1030{
63a1e1c9
MR		 1031 for (; caps->matches; caps++) {
1032 unsigned int num = caps->capability;
1033
1034 if (!cpus_have_cap(num))
1035 continue;
1036
1037 /* Ensure cpus_have_const_cap(num) works */
1038 static_branch_enable(&cpu_hwcap_keys[num]);
1039
1040 if (caps->enable) {
2a6dcb2b
JM		 1041 /*
1042 * Use stop_machine() as it schedules the work allowing
1043 * us to modify PSTATE, instead of on_each_cpu() which
1044 * uses an IPI, giving us a PSTATE that disappears when
1045 * we return.
1046 */
1047 stop_machine(caps->enable, NULL, cpu_online_mask);
63a1e1c9
MR		 1048 }
1049 }
dbb4e152
SP		 1050}
1051
dbb4e152
SP		 1052/*
1053 * Flag to indicate if we have computed the system wide
1054 * capabilities based on the boot time active CPUs. This
1055 * will be used to determine if a new booting CPU should
1056 * go through the verification process to make sure that it
1057 * supports the system capabilities, without using a hotplug
1058 * notifier.
1059 */
1060static bool sys_caps_initialised;
1061
1062static inline void set_sys_caps_initialised(void)
1063{
1064 sys_caps_initialised = true;
1065}
1066
1067/*
13f417f3
SP		 1068 * Check for CPU features that are used in early boot
1069 * based on the Boot CPU value.
dbb4e152 1070 */
13f417f3 1071static void check_early_cpu_features(void)
dbb4e152 1072{
ac1ad20f 1073 verify_cpu_run_el();
13f417f3 1074 verify_cpu_asid_bits();
dbb4e152 1075}
1c076303 1076
75283501
SP		 1077static void
1078verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1079{
1080
92406f0c
SP		 1081 for (; caps->matches; caps++)
1082 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 1083 pr_crit("CPU%d: missing HWCAP: %s\n",
1084 smp_processor_id(), caps->desc);
1085 cpu_die_early();
1086 }
75283501
SP		 1087}
1088
1089static void
1090verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
1091{
1092 for (; caps->matches; caps++) {
92406f0c 1093 if (!cpus_have_cap(caps->capability))
75283501
SP		 1094 continue;
1095 /*
1096 * If the new CPU misses an advertised feature, we cannot proceed
1097 * further, park the cpu.
1098 */
92406f0c 1099 if (!caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 1100 pr_crit("CPU%d: missing feature: %s\n",
1101 smp_processor_id(), caps->desc);
1102 cpu_die_early();
1103 }
1104 if (caps->enable)
1105 caps->enable(NULL);
1106 }
1107}
1108
dbb4e152
SP		 1109/*
1110 * Run through the enabled system capabilities and enable() it on this CPU.
1111 * The capabilities were decided based on the available CPUs at the boot time.
1112 * Any new CPU should match the system wide status of the capability. If the
1113 * new CPU doesn't have a capability which the system now has enabled, we
1114 * cannot do anything to fix it up and could cause unexpected failures. So
1115 * we park the CPU.
1116 */
c47a1900 1117static void verify_local_cpu_capabilities(void)
dbb4e152 1118{
c47a1900
SP		 1119 verify_local_cpu_errata_workarounds();
1120 verify_local_cpu_features(arm64_features);
1121 verify_local_elf_hwcaps(arm64_elf_hwcaps);
1122 if (system_supports_32bit_el0())
1123 verify_local_elf_hwcaps(compat_elf_hwcaps);
1124}
dbb4e152 1125
c47a1900
SP		 1126void check_local_cpu_capabilities(void)
1127{
1128 /*
1129 * All secondary CPUs should conform to the early CPU features
1130 * in use by the kernel based on boot CPU.
1131 */
13f417f3
SP		 1132 check_early_cpu_features();
1133
dbb4e152 1134 /*
c47a1900
SP		 1135 * If we haven't finalised the system capabilities, this CPU gets
1136 * a chance to update the errata work arounds.
1137 * Otherwise, this CPU should verify that it has all the system
1138 * advertised capabilities.
dbb4e152
SP		 1139 */
1140 if (!sys_caps_initialised)
c47a1900
SP		 1141 update_cpu_errata_workarounds();
1142 else
1143 verify_local_cpu_capabilities();
359b7064
MZ		 1144}
1145
a7c61a34 1146static void __init setup_feature_capabilities(void)
359b7064 1147{
ce8b602c
SP		 1148 update_cpu_capabilities(arm64_features, "detected feature:");
1149 enable_cpu_capabilities(arm64_features);
359b7064
MZ		 1150}
1151
63a1e1c9
MR		 1152DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1153EXPORT_SYMBOL(arm64_const_caps_ready);
1154
1155static void __init mark_const_caps_ready(void)
1156{
1157 static_branch_enable(&arm64_const_caps_ready);
1158}
1159
e3661b12
MZ		 1160/*
1161 * Check if the current CPU has a given feature capability.
1162 * Should be called from non-preemptible context.
1163 */
8f413758
MZ		 1164static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1165 unsigned int cap)
e3661b12
MZ		 1166{
1167 const struct arm64_cpu_capabilities *caps;
1168
1169 if (WARN_ON(preemptible()))
1170 return false;
1171
8f413758 1172 for (caps = cap_array; caps->desc; caps++)
e3661b12
MZ		 1173 if (caps->capability == cap && caps->matches)
1174 return caps->matches(caps, SCOPE_LOCAL_CPU);
1175
1176 return false;
1177}
1178
8f413758
MZ		 1179extern const struct arm64_cpu_capabilities arm64_errata[];
1180
1181bool this_cpu_has_cap(unsigned int cap)
1182{
1183 return (__this_cpu_has_cap(arm64_features, cap) ||
1184 __this_cpu_has_cap(arm64_errata, cap));
1185}
1186
9cdf8ec4 1187void __init setup_cpu_features(void)
359b7064 1188{
9cdf8ec4
SP		 1189 u32 cwg;
1190 int cls;
1191
dbb4e152
SP		 1192 /* Set the CPU feature capabilies */
1193 setup_feature_capabilities();
8e231852 1194 enable_errata_workarounds();
63a1e1c9 1195 mark_const_caps_ready();
75283501 1196 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 1197
1198 if (system_supports_32bit_el0())
1199 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152
SP		 1200
1201 /* Advertise that we have computed the system capabilities */
1202 set_sys_caps_initialised();
1203
9cdf8ec4
SP		 1204 /*
1205 * Check for sane CTR_EL0.CWG value.
1206 */
1207 cwg = cache_type_cwg();
1208 cls = cache_line_size();
1209 if (!cwg)
1210 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1211 cls);
1212 if (L1_CACHE_BYTES < cls)
1213 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1214 L1_CACHE_BYTES, cls);
359b7064 1215}
70544196
JM		 1216
1217static bool __maybe_unused
92406f0c 1218cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196 1219{
a4023f68 1220 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
70544196 1221}
77c97b4e
SP		 1222
1223/*
1224 * We emulate only the following system register space.
1225 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1226 * See Table C5-6 System instruction encodings for System register accesses,
1227 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1228 */
1229static inline bool __attribute_const__ is_emulated(u32 id)
1230{
1231 return (sys_reg_Op0(id) == 0x3 &&
1232 sys_reg_CRn(id) == 0x0 &&
1233 sys_reg_Op1(id) == 0x0 &&
1234 (sys_reg_CRm(id) == 0 ||
1235 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1236}
1237
1238/*
1239 * With CRm == 0, reg should be one of :
1240 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1241 */
1242static inline int emulate_id_reg(u32 id, u64 *valp)
1243{
1244 switch (id) {
1245 case SYS_MIDR_EL1:
1246 *valp = read_cpuid_id();
1247 break;
1248 case SYS_MPIDR_EL1:
1249 *valp = SYS_MPIDR_SAFE_VAL;
1250 break;
1251 case SYS_REVIDR_EL1:
1252 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1253 *valp = 0;
1254 break;
1255 default:
1256 return -EINVAL;
1257 }
1258
1259 return 0;
1260}
1261
1262static int emulate_sys_reg(u32 id, u64 *valp)
1263{
1264 struct arm64_ftr_reg *regp;
1265
1266 if (!is_emulated(id))
1267 return -EINVAL;
1268
1269 if (sys_reg_CRm(id) == 0)
1270 return emulate_id_reg(id, valp);
1271
1272 regp = get_arm64_ftr_reg(id);
1273 if (regp)
1274 *valp = arm64_ftr_reg_user_value(regp);
1275 else
1276 /*
1277 * The untracked registers are either IMPLEMENTATION DEFINED
1278 * (e.g, ID_AFR0_EL1) or reserved RAZ.
1279 */
1280 *valp = 0;
1281 return 0;
1282}
1283
1284static int emulate_mrs(struct pt_regs *regs, u32 insn)
1285{
1286 int rc;
1287 u32 sys_reg, dst;
1288 u64 val;
1289
1290 /*
1291 * sys_reg values are defined as used in mrs/msr instruction.
1292 * shift the imm value to get the encoding.
1293 */
1294 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1295 rc = emulate_sys_reg(sys_reg, &val);
1296 if (!rc) {
1297 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
521c6461 1298 pt_regs_write_reg(regs, dst, val);
77c97b4e
SP		 1299 regs->pc += 4;
1300 }
1301
1302 return rc;
1303}
1304
1305static struct undef_hook mrs_hook = {
1306 .instr_mask = 0xfff00000,
1307 .instr_val = 0xd5300000,
1308 .pstate_mask = COMPAT_PSR_MODE_MASK,
1309 .pstate_val = PSR_MODE_EL0t,
1310 .fn = emulate_mrs,
1311};
1312
1313static int __init enable_mrs_emulation(void)
1314{
1315 register_undef_hook(&mrs_hook);
1316 return 0;
1317}
1318
1319late_initcall(enable_mrs_emulation);
Linux 6.x block layer and io_uring tree(s)