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arm64: cpu_errata: Add Kryo to Falkor 1003 errata
[linux-2.6-block.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57 21#include <linux/bsearch.h>
2a6dcb2b 22#include <linux/cpumask.h>
3c739b57 23#include <linux/sort.h>
2a6dcb2b 24#include <linux/stop_machine.h>
359b7064 25#include <linux/types.h>
2077be67 26#include <linux/mm.h>
359b7064
MZ		 27#include <asm/cpu.h>
28#include <asm/cpufeature.h>
dbb4e152 29#include <asm/cpu_ops.h>
2e0f2478 30#include <asm/fpsimd.h>
13f417f3 31#include <asm/mmu_context.h>
338d4f49 32#include <asm/processor.h>
cdcf817b 33#include <asm/sysreg.h>
77c97b4e 34#include <asm/traps.h>
d88701be 35#include <asm/virt.h>
359b7064 36
9cdf8ec4
SP		 37unsigned long elf_hwcap __read_mostly;
38EXPORT_SYMBOL_GPL(elf_hwcap);
39
40#ifdef CONFIG_COMPAT
41#define COMPAT_ELF_HWCAP_DEFAULT \
42 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
43 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
44 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
45 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
46 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
47 COMPAT_HWCAP_LPAE)
48unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
49unsigned int compat_elf_hwcap2 __read_mostly;
50#endif
51
52DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
4b65a5db 53EXPORT_SYMBOL(cpu_hwcaps);
9cdf8ec4 54
8f1eec57
DM		 55/*
56 * Flag to indicate if we have computed the system wide
57 * capabilities based on the boot time active CPUs. This
58 * will be used to determine if a new booting CPU should
59 * go through the verification process to make sure that it
60 * supports the system capabilities, without using a hotplug
61 * notifier.
62 */
63static bool sys_caps_initialised;
64
65static inline void set_sys_caps_initialised(void)
66{
67 sys_caps_initialised = true;
68}
69
8effeaaf
MR		 70static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
71{
72 /* file-wide pr_fmt adds "CPU features: " prefix */
73 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
74 return 0;
75}
76
77static struct notifier_block cpu_hwcaps_notifier = {
78 .notifier_call = dump_cpu_hwcaps
79};
80
81static int __init register_cpu_hwcaps_dumper(void)
82{
83 atomic_notifier_chain_register(&panic_notifier_list,
84 &cpu_hwcaps_notifier);
85 return 0;
86}
87__initcall(register_cpu_hwcaps_dumper);
88
efd9e03f
CM		 89DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
90EXPORT_SYMBOL(cpu_hwcap_keys);
91
fe4fbdbc 92#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 93 { \
4f0a606b 94 .sign = SIGNED, \
fe4fbdbc 95 .visible = VISIBLE, \
3c739b57
SP		 96 .strict = STRICT, \
97 .type = TYPE, \
98 .shift = SHIFT, \
99 .width = WIDTH, \
100 .safe_val = SAFE_VAL, \
101 }
102
0710cfdb 103/* Define a feature with unsigned values */
fe4fbdbc
SP		 104#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
105 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
4f0a606b 106
0710cfdb 107/* Define a feature with a signed value */
fe4fbdbc
SP		 108#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
109 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
0710cfdb 110
3c739b57
SP		 111#define ARM64_FTR_END \
112 { \
113 .width = 0, \
114 }
115
70544196
JM		 116/* meta feature for alternatives */
117static bool __maybe_unused
92406f0c
SP		 118cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
119
70544196 120
4aa8a472
SP		 121/*
122 * NOTE: Any changes to the visibility of features should be kept in
123 * sync with the documentation of the CPU feature register ABI.
124 */
5e49d73c 125static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
3b3b6810 126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
5bdecb79
SP		 127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
fe4fbdbc
SP		 132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
134 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
136 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
3c739b57
SP		 137 ARM64_FTR_END,
138};
139
c8c3798d 140static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
5bdecb79
SP		 141 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
142 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
143 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
144 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
c8c3798d
SP		 145 ARM64_FTR_END,
146};
147
5e49d73c 148static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
179a56f6 149 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
0f15adbb 150 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
43994d82 151 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
5bdecb79 152 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
fe4fbdbc
SP		 153 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
154 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57 155 /* Linux doesn't care about the EL3 */
5bdecb79
SP		 156 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
157 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
158 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
159 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
3c739b57
SP		 160 ARM64_FTR_END,
161};
162
5e49d73c 163static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
5bdecb79
SP		 164 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
165 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
166 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
167 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
3c739b57 168 /* Linux shouldn't care about secure memory */
5bdecb79
SP		 169 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
170 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
3c739b57
SP		 172 /*
173 * Differing PARange is fine as long as all peripherals and memory are mapped
174 * within the minimum PARange of all CPUs
175 */
fe4fbdbc 176 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 177 ARM64_FTR_END,
178};
179
5e49d73c 180static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
fe4fbdbc 181 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
5bdecb79
SP		 182 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
183 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
184 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
185 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
186 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
3c739b57
SP		 187 ARM64_FTR_END,
188};
189
5e49d73c 190static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
5bdecb79
SP		 191 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 196 ARM64_FTR_END,
197};
198
5e49d73c 199static const struct arm64_ftr_bits ftr_ctr[] = {
fe4fbdbc
SP		 200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
3c739b57
SP		 204 /*
205 * Linux can handle differing I-cache policies. Userspace JITs will
ee7bc638 206 * make use of *minLine.
155433cb 207 * If we have differing I-cache policies, report it as the weakest - VIPT.
3c739b57 208 */
155433cb 209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
fe4fbdbc 210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
3c739b57
SP		 211 ARM64_FTR_END,
212};
213
675b0563
AB		 214struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
215 .name = "SYS_CTR_EL0",
216 .ftr_bits = ftr_ctr
217};
218
5e49d73c 219static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
5bdecb79
SP		 220 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
fe4fbdbc 222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
5bdecb79
SP		 223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
225 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
3c739b57
SP		 228 ARM64_FTR_END,
229};
230
5e49d73c 231static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
fe4fbdbc
SP		 232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
b20d1ba3
WD		 237 /*
238 * We can instantiate multiple PMU instances with different levels
239 * of support.
fe4fbdbc
SP		 240 */
241 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 244 ARM64_FTR_END,
245};
246
5e49d73c 247static const struct arm64_ftr_bits ftr_mvfr2[] = {
5bdecb79
SP		 248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
3c739b57
SP		 250 ARM64_FTR_END,
251};
252
5e49d73c 253static const struct arm64_ftr_bits ftr_dczid[] = {
fe4fbdbc
SP		 254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
3c739b57
SP		 256 ARM64_FTR_END,
257};
258
259
5e49d73c 260static const struct arm64_ftr_bits ftr_id_isar5[] = {
5bdecb79
SP		 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
263 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
264 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
265 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
266 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
3c739b57
SP		 267 ARM64_FTR_END,
268};
269
5e49d73c 270static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
5bdecb79 271 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
3c739b57
SP		 272 ARM64_FTR_END,
273};
274
5e49d73c 275static const struct arm64_ftr_bits ftr_id_pfr0[] = {
5bdecb79
SP		 276 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
3c739b57
SP		 280 ARM64_FTR_END,
281};
282
5e49d73c 283static const struct arm64_ftr_bits ftr_id_dfr0[] = {
fe4fbdbc
SP		 284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
285 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
e5343503
SP		 292 ARM64_FTR_END,
293};
294
2e0f2478
DM		 295static const struct arm64_ftr_bits ftr_zcr[] = {
296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
297 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
298 ARM64_FTR_END,
299};
300
3c739b57
SP		 301/*
302 * Common ftr bits for a 32bit register with all hidden, strict
303 * attributes, with 4bit feature fields and a default safe value of
304 * 0. Covers the following 32bit registers:
305 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
306 */
5e49d73c 307static const struct arm64_ftr_bits ftr_generic_32bits[] = {
fe4fbdbc
SP		 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
3c739b57
SP		 316 ARM64_FTR_END,
317};
318
eab43e88
SP		 319/* Table for a single 32bit feature value */
320static const struct arm64_ftr_bits ftr_single32[] = {
fe4fbdbc 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
3c739b57
SP		 322 ARM64_FTR_END,
323};
324
eab43e88 325static const struct arm64_ftr_bits ftr_raz[] = {
3c739b57
SP		 326 ARM64_FTR_END,
327};
328
6f2b7eef
AB		 329#define ARM64_FTR_REG(id, table) { \
330 .sys_id = id, \
331 .reg = &(struct arm64_ftr_reg){ \
3c739b57
SP		 332 .name = #id, \
333 .ftr_bits = &((table)[0]), \
6f2b7eef 334 }}
3c739b57 335
6f2b7eef
AB		 336static const struct __ftr_reg_entry {
337 u32 sys_id;
338 struct arm64_ftr_reg *reg;
339} arm64_ftr_regs[] = {
3c739b57
SP		 340
341 /* Op1 = 0, CRn = 0, CRm = 1 */
342 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
343 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 344 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 345 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
346 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
347 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
348 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
349
350 /* Op1 = 0, CRn = 0, CRm = 2 */
351 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
352 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
353 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
354 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
355 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
356 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
357 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
358
359 /* Op1 = 0, CRn = 0, CRm = 3 */
360 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
361 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
362 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
363
364 /* Op1 = 0, CRn = 0, CRm = 4 */
365 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
eab43e88 366 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz),
2e0f2478 367 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
3c739b57
SP		 368
369 /* Op1 = 0, CRn = 0, CRm = 5 */
370 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
eab43e88 371 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
3c739b57
SP		 372
373 /* Op1 = 0, CRn = 0, CRm = 6 */
374 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
c8c3798d 375 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
3c739b57
SP		 376
377 /* Op1 = 0, CRn = 0, CRm = 7 */
378 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
379 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 380 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57 381
2e0f2478
DM		 382 /* Op1 = 0, CRn = 1, CRm = 2 */
383 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
384
3c739b57 385 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 386 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP		 387 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
388
389 /* Op1 = 3, CRn = 14, CRm = 0 */
eab43e88 390 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
3c739b57
SP		 391};
392
393static int search_cmp_ftr_reg(const void *id, const void *regp)
394{
6f2b7eef 395 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP		 396}
397
398/*
399 * get_arm64_ftr_reg - Lookup a feature register entry using its
400 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
401 * ascending order of sys_id , we use binary search to find a matching
402 * entry.
403 *
404 * returns - Upon success, matching ftr_reg entry for id.
405 * - NULL on failure. It is upto the caller to decide
406 * the impact of a failure.
407 */
408static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
409{
6f2b7eef
AB		 410 const struct __ftr_reg_entry *ret;
411
412 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP		 413 arm64_ftr_regs,
414 ARRAY_SIZE(arm64_ftr_regs),
415 sizeof(arm64_ftr_regs[0]),
416 search_cmp_ftr_reg);
6f2b7eef
AB		 417 if (ret)
418 return ret->reg;
419 return NULL;
3c739b57
SP		 420}
421
5e49d73c
AB		 422static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
423 s64 ftr_val)
3c739b57
SP		 424{
425 u64 mask = arm64_ftr_mask(ftrp);
426
427 reg &= ~mask;
428 reg |= (ftr_val << ftrp->shift) & mask;
429 return reg;
430}
431
5e49d73c
AB		 432static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
433 s64 cur)
3c739b57
SP		 434{
435 s64 ret = 0;
436
437 switch (ftrp->type) {
438 case FTR_EXACT:
439 ret = ftrp->safe_val;
440 break;
441 case FTR_LOWER_SAFE:
442 ret = new < cur ? new : cur;
443 break;
444 case FTR_HIGHER_SAFE:
445 ret = new > cur ? new : cur;
446 break;
447 default:
448 BUG();
449 }
450
451 return ret;
452}
453
3c739b57
SP		 454static void __init sort_ftr_regs(void)
455{
6f2b7eef
AB		 456 int i;
457
458 /* Check that the array is sorted so that we can do the binary search */
459 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
460 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP		 461}
462
463/*
464 * Initialise the CPU feature register from Boot CPU values.
465 * Also initiliases the strict_mask for the register.
b389d799
MR		 466 * Any bits that are not covered by an arm64_ftr_bits entry are considered
467 * RES0 for the system-wide value, and must strictly match.
3c739b57
SP		 468 */
469static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
470{
471 u64 val = 0;
472 u64 strict_mask = ~0x0ULL;
fe4fbdbc 473 u64 user_mask = 0;
b389d799
MR		 474 u64 valid_mask = 0;
475
5e49d73c 476 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 477 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
478
479 BUG_ON(!reg);
480
481 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
b389d799 482 u64 ftr_mask = arm64_ftr_mask(ftrp);
3c739b57
SP		 483 s64 ftr_new = arm64_ftr_value(ftrp, new);
484
485 val = arm64_ftr_set_value(ftrp, val, ftr_new);
b389d799
MR		 486
487 valid_mask |= ftr_mask;
3c739b57 488 if (!ftrp->strict)
b389d799 489 strict_mask &= ~ftr_mask;
fe4fbdbc
SP		 490 if (ftrp->visible)
491 user_mask |= ftr_mask;
492 else
493 reg->user_val = arm64_ftr_set_value(ftrp,
494 reg->user_val,
495 ftrp->safe_val);
3c739b57 496 }
b389d799
MR		 497
498 val &= valid_mask;
499
3c739b57
SP		 500 reg->sys_val = val;
501 reg->strict_mask = strict_mask;
fe4fbdbc 502 reg->user_mask = user_mask;
3c739b57
SP		 503}
504
505void __init init_cpu_features(struct cpuinfo_arm64 *info)
506{
507 /* Before we start using the tables, make sure it is sorted */
508 sort_ftr_regs();
509
510 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
511 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
512 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
513 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
514 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
515 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
516 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
517 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
518 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 519 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 520 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
521 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
2e0f2478 522 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
a6dc3cd7
SP		 523
524 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
525 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
526 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
527 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
528 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
529 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
530 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
531 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
532 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
533 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
534 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
535 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
536 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
537 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
538 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
539 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
540 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
541 }
542
2e0f2478
DM		 543 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
544 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
545 sve_init_vq_map();
546 }
3c739b57
SP		 547}
548
3086d391 549static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 550{
5e49d73c 551 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 552
553 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
554 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
555 s64 ftr_new = arm64_ftr_value(ftrp, new);
556
557 if (ftr_cur == ftr_new)
558 continue;
559 /* Find a safe value */
560 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
561 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
562 }
563
564}
565
3086d391 566static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 567{
3086d391
SP		 568 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
569
570 BUG_ON(!regp);
571 update_cpu_ftr_reg(regp, val);
572 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
573 return 0;
574 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
575 regp->name, boot, cpu, val);
576 return 1;
577}
578
579/*
580 * Update system wide CPU feature registers with the values from a
581 * non-boot CPU. Also performs SANITY checks to make sure that there
582 * aren't any insane variations from that of the boot CPU.
583 */
584void update_cpu_features(int cpu,
585 struct cpuinfo_arm64 *info,
586 struct cpuinfo_arm64 *boot)
587{
588 int taint = 0;
589
590 /*
591 * The kernel can handle differing I-cache policies, but otherwise
592 * caches should look identical. Userspace JITs will make use of
593 * *minLine.
594 */
595 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
596 info->reg_ctr, boot->reg_ctr);
597
598 /*
599 * Userspace may perform DC ZVA instructions. Mismatched block sizes
600 * could result in too much or too little memory being zeroed if a
601 * process is preempted and migrated between CPUs.
602 */
603 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
604 info->reg_dczid, boot->reg_dczid);
605
606 /* If different, timekeeping will be broken (especially with KVM) */
607 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
608 info->reg_cntfrq, boot->reg_cntfrq);
609
610 /*
611 * The kernel uses self-hosted debug features and expects CPUs to
612 * support identical debug features. We presently need CTX_CMPs, WRPs,
613 * and BRPs to be identical.
614 * ID_AA64DFR1 is currently RES0.
615 */
616 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
617 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
618 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
619 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
620 /*
621 * Even in big.LITTLE, processors should be identical instruction-set
622 * wise.
623 */
624 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
625 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
626 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
627 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
628
629 /*
630 * Differing PARange support is fine as long as all peripherals and
631 * memory are mapped within the minimum PARange of all CPUs.
632 * Linux should not care about secure memory.
633 */
634 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
635 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
636 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
637 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 638 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
639 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 640
641 /*
642 * EL3 is not our concern.
643 * ID_AA64PFR1 is currently RES0.
644 */
645 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
646 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
647 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
648 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
649
2e0f2478
DM		 650 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
651 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
652
3086d391 653 /*
a6dc3cd7
SP		 654 * If we have AArch32, we care about 32-bit features for compat.
655 * If the system doesn't support AArch32, don't update them.
3086d391 656 */
46823dd1 657 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
a6dc3cd7
SP		 658 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
659
660 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
3086d391 661 info->reg_id_dfr0, boot->reg_id_dfr0);
a6dc3cd7 662 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
3086d391 663 info->reg_id_isar0, boot->reg_id_isar0);
a6dc3cd7 664 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
3086d391 665 info->reg_id_isar1, boot->reg_id_isar1);
a6dc3cd7 666 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
3086d391 667 info->reg_id_isar2, boot->reg_id_isar2);
a6dc3cd7 668 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
3086d391 669 info->reg_id_isar3, boot->reg_id_isar3);
a6dc3cd7 670 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
3086d391 671 info->reg_id_isar4, boot->reg_id_isar4);
a6dc3cd7 672 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
3086d391
SP		 673 info->reg_id_isar5, boot->reg_id_isar5);
674
a6dc3cd7
SP		 675 /*
676 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
677 * ACTLR formats could differ across CPUs and therefore would have to
678 * be trapped for virtualization anyway.
679 */
680 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
3086d391 681 info->reg_id_mmfr0, boot->reg_id_mmfr0);
a6dc3cd7 682 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
3086d391 683 info->reg_id_mmfr1, boot->reg_id_mmfr1);
a6dc3cd7 684 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
3086d391 685 info->reg_id_mmfr2, boot->reg_id_mmfr2);
a6dc3cd7 686 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
3086d391 687 info->reg_id_mmfr3, boot->reg_id_mmfr3);
a6dc3cd7 688 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
3086d391 689 info->reg_id_pfr0, boot->reg_id_pfr0);
a6dc3cd7 690 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
3086d391 691 info->reg_id_pfr1, boot->reg_id_pfr1);
a6dc3cd7 692 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
3086d391 693 info->reg_mvfr0, boot->reg_mvfr0);
a6dc3cd7 694 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
3086d391 695 info->reg_mvfr1, boot->reg_mvfr1);
a6dc3cd7 696 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
3086d391 697 info->reg_mvfr2, boot->reg_mvfr2);
a6dc3cd7 698 }
3086d391 699
2e0f2478
DM		 700 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
701 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
702 info->reg_zcr, boot->reg_zcr);
703
704 /* Probe vector lengths, unless we already gave up on SVE */
705 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
706 !sys_caps_initialised)
707 sve_update_vq_map();
708 }
709
3086d391
SP		 710 /*
711 * Mismatched CPU features are a recipe for disaster. Don't even
712 * pretend to support them.
713 */
8dd0ee65
WD		 714 if (taint) {
715 pr_warn_once("Unsupported CPU feature variation detected.\n");
716 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
717 }
cdcf817b
SP		 718}
719
46823dd1 720u64 read_sanitised_ftr_reg(u32 id)
b3f15378
SP		 721{
722 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
723
724 /* We shouldn't get a request for an unsupported register */
725 BUG_ON(!regp);
726 return regp->sys_val;
727}
359b7064 728
965861d6
MR		 729#define read_sysreg_case(r) \
730 case r: return read_sysreg_s(r)
731
92406f0c 732/*
46823dd1 733 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
92406f0c
SP		 734 * Read the system register on the current CPU
735 */
46823dd1 736static u64 __read_sysreg_by_encoding(u32 sys_id)
92406f0c
SP		 737{
738 switch (sys_id) {
965861d6
MR		 739 read_sysreg_case(SYS_ID_PFR0_EL1);
740 read_sysreg_case(SYS_ID_PFR1_EL1);
741 read_sysreg_case(SYS_ID_DFR0_EL1);
742 read_sysreg_case(SYS_ID_MMFR0_EL1);
743 read_sysreg_case(SYS_ID_MMFR1_EL1);
744 read_sysreg_case(SYS_ID_MMFR2_EL1);
745 read_sysreg_case(SYS_ID_MMFR3_EL1);
746 read_sysreg_case(SYS_ID_ISAR0_EL1);
747 read_sysreg_case(SYS_ID_ISAR1_EL1);
748 read_sysreg_case(SYS_ID_ISAR2_EL1);
749 read_sysreg_case(SYS_ID_ISAR3_EL1);
750 read_sysreg_case(SYS_ID_ISAR4_EL1);
751 read_sysreg_case(SYS_ID_ISAR5_EL1);
752 read_sysreg_case(SYS_MVFR0_EL1);
753 read_sysreg_case(SYS_MVFR1_EL1);
754 read_sysreg_case(SYS_MVFR2_EL1);
755
756 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
757 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
758 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
759 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
760 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
761 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
762 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
763 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
764 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
765
766 read_sysreg_case(SYS_CNTFRQ_EL0);
767 read_sysreg_case(SYS_CTR_EL0);
768 read_sysreg_case(SYS_DCZID_EL0);
769
92406f0c
SP		 770 default:
771 BUG();
772 return 0;
773 }
774}
775
963fcd40
MZ		 776#include <linux/irqchip/arm-gic-v3.h>
777
18ffa046
JM		 778static bool
779feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
780{
28c5dcb2 781 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 782
783 return val >= entry->min_field_value;
784}
785
da8d02d1 786static bool
92406f0c 787has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 788{
789 u64 val;
94a9e04a 790
92406f0c
SP		 791 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
792 if (scope == SCOPE_SYSTEM)
46823dd1 793 val = read_sanitised_ftr_reg(entry->sys_reg);
92406f0c 794 else
46823dd1 795 val = __read_sysreg_by_encoding(entry->sys_reg);
92406f0c 796
da8d02d1
SP		 797 return feature_matches(val, entry);
798}
338d4f49 799
92406f0c 800static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 801{
802 bool has_sre;
803
92406f0c 804 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 805 return false;
806
807 has_sre = gic_enable_sre();
808 if (!has_sre)
809 pr_warn_once("%s present but disabled by higher exception level\n",
810 entry->desc);
811
812 return has_sre;
813}
814
92406f0c 815static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 816{
817 u32 midr = read_cpuid_id();
d5370f75
WD		 818
819 /* Cavium ThunderX pass 1.x and 2.x */
fa5ce3d1
RR		 820 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
821 MIDR_CPU_VAR_REV(0, 0),
822 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
d5370f75
WD		 823}
824
92406f0c 825static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
d88701be
MZ		 826{
827 return is_kernel_in_hyp_mode();
828}
829
d1745910
MZ		 830static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
831 int __unused)
832{
2077be67 833 phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
d1745910
MZ		 834
835 /*
836 * Activate the lower HYP offset only if:
837 * - the idmap doesn't clash with it,
838 * - the kernel is not running at EL2.
839 */
840 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
841}
842
82e0191a
SP		 843static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
844{
46823dd1 845 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
82e0191a
SP		 846
847 return cpuid_feature_extract_signed_field(pfr0,
848 ID_AA64PFR0_FP_SHIFT) < 0;
849}
850
ea1e3de8
WD		 851#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
852static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
853
854static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
855 int __unused)
856{
179a56f6
WD		 857 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
858
ea1e3de8
WD		 859 /* Forced on command line? */
860 if (__kpti_forced) {
861 pr_info_once("kernel page table isolation forced %s by command line option\n",
862 __kpti_forced > 0 ? "ON" : "OFF");
863 return __kpti_forced > 0;
864 }
865
866 /* Useful for KASLR robustness */
867 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
868 return true;
869
179a56f6
WD		 870 /* Defer to CPU feature registers */
871 return !cpuid_feature_extract_unsigned_field(pfr0,
872 ID_AA64PFR0_CSV3_SHIFT);
ea1e3de8
WD		 873}
874
875static int __init parse_kpti(char *str)
876{
877 bool enabled;
878 int ret = strtobool(str, &enabled);
879
880 if (ret)
881 return ret;
882
883 __kpti_forced = enabled ? 1 : -1;
884 return 0;
885}
886__setup("kpti=", parse_kpti);
887#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
888
6d99b689
JM		 889static int cpu_copy_el2regs(void *__unused)
890{
891 /*
892 * Copy register values that aren't redirected by hardware.
893 *
894 * Before code patching, we only set tpidr_el1, all CPUs need to copy
895 * this value to tpidr_el2 before we patch the code. Once we've done
896 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
897 * do anything here.
898 */
899 if (!alternatives_applied)
900 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
901
902 return 0;
903}
904
359b7064 905static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 906 {
907 .desc = "GIC system register CPU interface",
908 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
92406f0c 909 .def_scope = SCOPE_SYSTEM,
963fcd40 910 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 911 .sys_reg = SYS_ID_AA64PFR0_EL1,
912 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 913 .sign = FTR_UNSIGNED,
18ffa046 914 .min_field_value = 1,
94a9e04a 915 },
338d4f49
JM		 916#ifdef CONFIG_ARM64_PAN
917 {
918 .desc = "Privileged Access Never",
919 .capability = ARM64_HAS_PAN,
92406f0c 920 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP		 921 .matches = has_cpuid_feature,
922 .sys_reg = SYS_ID_AA64MMFR1_EL1,
923 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 924 .sign = FTR_UNSIGNED,
338d4f49
JM		 925 .min_field_value = 1,
926 .enable = cpu_enable_pan,
927 },
928#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 929#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
930 {
931 .desc = "LSE atomic instructions",
932 .capability = ARM64_HAS_LSE_ATOMICS,
92406f0c 933 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP		 934 .matches = has_cpuid_feature,
935 .sys_reg = SYS_ID_AA64ISAR0_EL1,
936 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 937 .sign = FTR_UNSIGNED,
2e94da13
WD		 938 .min_field_value = 2,
939 },
940#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 941 {
942 .desc = "Software prefetching using PRFM",
943 .capability = ARM64_HAS_NO_HW_PREFETCH,
92406f0c 944 .def_scope = SCOPE_SYSTEM,
d5370f75
WD		 945 .matches = has_no_hw_prefetch,
946 },
57f4959b
JM		 947#ifdef CONFIG_ARM64_UAO
948 {
949 .desc = "User Access Override",
950 .capability = ARM64_HAS_UAO,
92406f0c 951 .def_scope = SCOPE_SYSTEM,
57f4959b
JM		 952 .matches = has_cpuid_feature,
953 .sys_reg = SYS_ID_AA64MMFR2_EL1,
954 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
955 .min_field_value = 1,
c8b06e3f
JM		 956 /*
957 * We rely on stop_machine() calling uao_thread_switch() to set
958 * UAO immediately after patching.
959 */
57f4959b
JM		 960 },
961#endif /* CONFIG_ARM64_UAO */
70544196
JM		 962#ifdef CONFIG_ARM64_PAN
963 {
964 .capability = ARM64_ALT_PAN_NOT_UAO,
92406f0c 965 .def_scope = SCOPE_SYSTEM,
70544196
JM		 966 .matches = cpufeature_pan_not_uao,
967 },
968#endif /* CONFIG_ARM64_PAN */
d88701be
MZ		 969 {
970 .desc = "Virtualization Host Extensions",
971 .capability = ARM64_HAS_VIRT_HOST_EXTN,
92406f0c 972 .def_scope = SCOPE_SYSTEM,
d88701be 973 .matches = runs_at_el2,
6d99b689 974 .enable = cpu_copy_el2regs,
d88701be 975 },
042446a3
SP		 976 {
977 .desc = "32-bit EL0 Support",
978 .capability = ARM64_HAS_32BIT_EL0,
92406f0c 979 .def_scope = SCOPE_SYSTEM,
042446a3
SP		 980 .matches = has_cpuid_feature,
981 .sys_reg = SYS_ID_AA64PFR0_EL1,
982 .sign = FTR_UNSIGNED,
983 .field_pos = ID_AA64PFR0_EL0_SHIFT,
984 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
985 },
d1745910
MZ		 986 {
987 .desc = "Reduced HYP mapping offset",
988 .capability = ARM64_HYP_OFFSET_LOW,
989 .def_scope = SCOPE_SYSTEM,
990 .matches = hyp_offset_low,
991 },
ea1e3de8
WD		 992#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
993 {
179a56f6 994 .desc = "Kernel page table isolation (KPTI)",
ea1e3de8
WD		 995 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
996 .def_scope = SCOPE_SYSTEM,
997 .matches = unmap_kernel_at_el0,
998 },
999#endif
82e0191a
SP		 1000 {
1001 /* FP/SIMD is not implemented */
1002 .capability = ARM64_HAS_NO_FPSIMD,
1003 .def_scope = SCOPE_SYSTEM,
1004 .min_field_value = 0,
1005 .matches = has_no_fpsimd,
1006 },
d50e071f
RM		 1007#ifdef CONFIG_ARM64_PMEM
1008 {
1009 .desc = "Data cache clean to Point of Persistence",
1010 .capability = ARM64_HAS_DCPOP,
1011 .def_scope = SCOPE_SYSTEM,
1012 .matches = has_cpuid_feature,
1013 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1014 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1015 .min_field_value = 1,
1016 },
1017#endif
43994d82
DM		 1018#ifdef CONFIG_ARM64_SVE
1019 {
1020 .desc = "Scalable Vector Extension",
1021 .capability = ARM64_SVE,
1022 .def_scope = SCOPE_SYSTEM,
1023 .sys_reg = SYS_ID_AA64PFR0_EL1,
1024 .sign = FTR_UNSIGNED,
1025 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1026 .min_field_value = ID_AA64PFR0_SVE,
1027 .matches = has_cpuid_feature,
1028 .enable = sve_kernel_enable,
1029 },
1030#endif /* CONFIG_ARM64_SVE */
359b7064
MZ		 1031 {},
1032};
1033
ff96f7bc 1034#define HWCAP_CAP(reg, field, s, min_value, type, cap) \
37b01d53
SP		 1035 { \
1036 .desc = #cap, \
92406f0c 1037 .def_scope = SCOPE_SYSTEM, \
37b01d53
SP		 1038 .matches = has_cpuid_feature, \
1039 .sys_reg = reg, \
1040 .field_pos = field, \
ff96f7bc 1041 .sign = s, \
37b01d53
SP		 1042 .min_field_value = min_value, \
1043 .hwcap_type = type, \
1044 .hwcap = cap, \
1045 }
1046
f3efb675 1047static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
ff96f7bc
SP		 1048 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1049 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1050 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1051 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
f5e035f8 1052 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
ff96f7bc
SP		 1053 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1054 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
f92f5ce0 1055 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
f5e035f8
SP		 1056 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1057 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1058 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1059 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
3b3b6810 1060 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
ff96f7bc 1061 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
bf500618 1062 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
ff96f7bc 1063 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
bf500618 1064 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
7aac405e 1065 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
c8c3798d 1066 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
cb567e79 1067 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
c651aae5 1068 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
43994d82
DM		 1069#ifdef CONFIG_ARM64_SVE
1070 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
1071#endif
75283501
SP		 1072 {},
1073};
1074
1075static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 1076#ifdef CONFIG_COMPAT
ff96f7bc
SP		 1077 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1078 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1079 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1080 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1081 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 1082#endif
1083 {},
1084};
1085
f3efb675 1086static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 1087{
1088 switch (cap->hwcap_type) {
1089 case CAP_HWCAP:
1090 elf_hwcap |= cap->hwcap;
1091 break;
1092#ifdef CONFIG_COMPAT
1093 case CAP_COMPAT_HWCAP:
1094 compat_elf_hwcap |= (u32)cap->hwcap;
1095 break;
1096 case CAP_COMPAT_HWCAP2:
1097 compat_elf_hwcap2 |= (u32)cap->hwcap;
1098 break;
1099#endif
1100 default:
1101 WARN_ON(1);
1102 break;
1103 }
1104}
1105
1106/* Check if we have a particular HWCAP enabled */
f3efb675 1107static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 1108{
1109 bool rc;
1110
1111 switch (cap->hwcap_type) {
1112 case CAP_HWCAP:
1113 rc = (elf_hwcap & cap->hwcap) != 0;
1114 break;
1115#ifdef CONFIG_COMPAT
1116 case CAP_COMPAT_HWCAP:
1117 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1118 break;
1119 case CAP_COMPAT_HWCAP2:
1120 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1121 break;
1122#endif
1123 default:
1124 WARN_ON(1);
1125 rc = false;
1126 }
1127
1128 return rc;
1129}
1130
75283501 1131static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 1132{
77c97b4e
SP		 1133 /* We support emulation of accesses to CPU ID feature registers */
1134 elf_hwcap |= HWCAP_CPUID;
75283501 1135 for (; hwcaps->matches; hwcaps++)
92406f0c 1136 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
75283501 1137 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 1138}
1139
ce8b602c 1140void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
359b7064
MZ		 1141 const char *info)
1142{
75283501 1143 for (; caps->matches; caps++) {
92406f0c 1144 if (!caps->matches(caps, caps->def_scope))
359b7064
MZ		 1145 continue;
1146
75283501
SP		 1147 if (!cpus_have_cap(caps->capability) && caps->desc)
1148 pr_info("%s %s\n", info, caps->desc);
1149 cpus_set_cap(caps->capability);
359b7064 1150 }
ce8b602c
SP		 1151}
1152
1153/*
dbb4e152
SP		 1154 * Run through the enabled capabilities and enable() it on all active
1155 * CPUs
ce8b602c 1156 */
8e231852 1157void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
ce8b602c 1158{
63a1e1c9
MR		 1159 for (; caps->matches; caps++) {
1160 unsigned int num = caps->capability;
1161
1162 if (!cpus_have_cap(num))
1163 continue;
1164
1165 /* Ensure cpus_have_const_cap(num) works */
1166 static_branch_enable(&cpu_hwcap_keys[num]);
1167
1168 if (caps->enable) {
2a6dcb2b
JM		 1169 /*
1170 * Use stop_machine() as it schedules the work allowing
1171 * us to modify PSTATE, instead of on_each_cpu() which
1172 * uses an IPI, giving us a PSTATE that disappears when
1173 * we return.
1174 */
0a0d111d 1175 stop_machine(caps->enable, (void *)caps, cpu_online_mask);
63a1e1c9
MR		 1176 }
1177 }
dbb4e152
SP		 1178}
1179
dbb4e152 1180/*
13f417f3
SP		 1181 * Check for CPU features that are used in early boot
1182 * based on the Boot CPU value.
dbb4e152 1183 */
13f417f3 1184static void check_early_cpu_features(void)
dbb4e152 1185{
ac1ad20f 1186 verify_cpu_run_el();
13f417f3 1187 verify_cpu_asid_bits();
dbb4e152 1188}
1c076303 1189
75283501
SP		 1190static void
1191verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1192{
1193
92406f0c
SP		 1194 for (; caps->matches; caps++)
1195 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 1196 pr_crit("CPU%d: missing HWCAP: %s\n",
1197 smp_processor_id(), caps->desc);
1198 cpu_die_early();
1199 }
75283501
SP		 1200}
1201
1202static void
1203verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
1204{
1205 for (; caps->matches; caps++) {
92406f0c 1206 if (!cpus_have_cap(caps->capability))
75283501
SP		 1207 continue;
1208 /*
1209 * If the new CPU misses an advertised feature, we cannot proceed
1210 * further, park the cpu.
1211 */
92406f0c 1212 if (!caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 1213 pr_crit("CPU%d: missing feature: %s\n",
1214 smp_processor_id(), caps->desc);
1215 cpu_die_early();
1216 }
1217 if (caps->enable)
0a0d111d 1218 caps->enable((void *)caps);
75283501
SP		 1219 }
1220}
1221
2e0f2478
DM		 1222static void verify_sve_features(void)
1223{
1224 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1225 u64 zcr = read_zcr_features();
1226
1227 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1228 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1229
1230 if (len < safe_len || sve_verify_vq_map()) {
1231 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1232 smp_processor_id());
1233 cpu_die_early();
1234 }
1235
1236 /* Add checks on other ZCR bits here if necessary */
1237}
1238
dbb4e152
SP		 1239/*
1240 * Run through the enabled system capabilities and enable() it on this CPU.
1241 * The capabilities were decided based on the available CPUs at the boot time.
1242 * Any new CPU should match the system wide status of the capability. If the
1243 * new CPU doesn't have a capability which the system now has enabled, we
1244 * cannot do anything to fix it up and could cause unexpected failures. So
1245 * we park the CPU.
1246 */
c47a1900 1247static void verify_local_cpu_capabilities(void)
dbb4e152 1248{
c47a1900
SP		 1249 verify_local_cpu_errata_workarounds();
1250 verify_local_cpu_features(arm64_features);
1251 verify_local_elf_hwcaps(arm64_elf_hwcaps);
2e0f2478 1252
c47a1900
SP		 1253 if (system_supports_32bit_el0())
1254 verify_local_elf_hwcaps(compat_elf_hwcaps);
2e0f2478
DM		 1255
1256 if (system_supports_sve())
1257 verify_sve_features();
c47a1900 1258}
dbb4e152 1259
c47a1900
SP		 1260void check_local_cpu_capabilities(void)
1261{
1262 /*
1263 * All secondary CPUs should conform to the early CPU features
1264 * in use by the kernel based on boot CPU.
1265 */
13f417f3
SP		 1266 check_early_cpu_features();
1267
dbb4e152 1268 /*
c47a1900
SP		 1269 * If we haven't finalised the system capabilities, this CPU gets
1270 * a chance to update the errata work arounds.
1271 * Otherwise, this CPU should verify that it has all the system
1272 * advertised capabilities.
dbb4e152
SP		 1273 */
1274 if (!sys_caps_initialised)
c47a1900
SP		 1275 update_cpu_errata_workarounds();
1276 else
1277 verify_local_cpu_capabilities();
359b7064
MZ		 1278}
1279
a7c61a34 1280static void __init setup_feature_capabilities(void)
359b7064 1281{
ce8b602c
SP		 1282 update_cpu_capabilities(arm64_features, "detected feature:");
1283 enable_cpu_capabilities(arm64_features);
359b7064
MZ		 1284}
1285
63a1e1c9
MR		 1286DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1287EXPORT_SYMBOL(arm64_const_caps_ready);
1288
1289static void __init mark_const_caps_ready(void)
1290{
1291 static_branch_enable(&arm64_const_caps_ready);
1292}
1293
e3661b12
MZ		 1294/*
1295 * Check if the current CPU has a given feature capability.
1296 * Should be called from non-preemptible context.
1297 */
8f413758
MZ		 1298static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1299 unsigned int cap)
e3661b12
MZ		 1300{
1301 const struct arm64_cpu_capabilities *caps;
1302
1303 if (WARN_ON(preemptible()))
1304 return false;
1305
8f413758 1306 for (caps = cap_array; caps->desc; caps++)
e3661b12
MZ		 1307 if (caps->capability == cap && caps->matches)
1308 return caps->matches(caps, SCOPE_LOCAL_CPU);
1309
1310 return false;
1311}
1312
8f413758
MZ		 1313extern const struct arm64_cpu_capabilities arm64_errata[];
1314
1315bool this_cpu_has_cap(unsigned int cap)
1316{
1317 return (__this_cpu_has_cap(arm64_features, cap) ||
1318 __this_cpu_has_cap(arm64_errata, cap));
1319}
1320
9cdf8ec4 1321void __init setup_cpu_features(void)
359b7064 1322{
9cdf8ec4
SP		 1323 u32 cwg;
1324 int cls;
1325
dbb4e152
SP		 1326 /* Set the CPU feature capabilies */
1327 setup_feature_capabilities();
8e231852 1328 enable_errata_workarounds();
63a1e1c9 1329 mark_const_caps_ready();
75283501 1330 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 1331
1332 if (system_supports_32bit_el0())
1333 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152 1334
2e0f2478
DM		 1335 sve_setup();
1336
dbb4e152
SP		 1337 /* Advertise that we have computed the system capabilities */
1338 set_sys_caps_initialised();
1339
9cdf8ec4
SP		 1340 /*
1341 * Check for sane CTR_EL0.CWG value.
1342 */
1343 cwg = cache_type_cwg();
1344 cls = cache_line_size();
1345 if (!cwg)
1346 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1347 cls);
1348 if (L1_CACHE_BYTES < cls)
1349 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1350 L1_CACHE_BYTES, cls);
359b7064 1351}
70544196
JM		 1352
1353static bool __maybe_unused
92406f0c 1354cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196 1355{
a4023f68 1356 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
70544196 1357}
77c97b4e
SP		 1358
1359/*
1360 * We emulate only the following system register space.
1361 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1362 * See Table C5-6 System instruction encodings for System register accesses,
1363 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1364 */
1365static inline bool __attribute_const__ is_emulated(u32 id)
1366{
1367 return (sys_reg_Op0(id) == 0x3 &&
1368 sys_reg_CRn(id) == 0x0 &&
1369 sys_reg_Op1(id) == 0x0 &&
1370 (sys_reg_CRm(id) == 0 ||
1371 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1372}
1373
1374/*
1375 * With CRm == 0, reg should be one of :
1376 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1377 */
1378static inline int emulate_id_reg(u32 id, u64 *valp)
1379{
1380 switch (id) {
1381 case SYS_MIDR_EL1:
1382 *valp = read_cpuid_id();
1383 break;
1384 case SYS_MPIDR_EL1:
1385 *valp = SYS_MPIDR_SAFE_VAL;
1386 break;
1387 case SYS_REVIDR_EL1:
1388 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1389 *valp = 0;
1390 break;
1391 default:
1392 return -EINVAL;
1393 }
1394
1395 return 0;
1396}
1397
1398static int emulate_sys_reg(u32 id, u64 *valp)
1399{
1400 struct arm64_ftr_reg *regp;
1401
1402 if (!is_emulated(id))
1403 return -EINVAL;
1404
1405 if (sys_reg_CRm(id) == 0)
1406 return emulate_id_reg(id, valp);
1407
1408 regp = get_arm64_ftr_reg(id);
1409 if (regp)
1410 *valp = arm64_ftr_reg_user_value(regp);
1411 else
1412 /*
1413 * The untracked registers are either IMPLEMENTATION DEFINED
1414 * (e.g, ID_AFR0_EL1) or reserved RAZ.
1415 */
1416 *valp = 0;
1417 return 0;
1418}
1419
1420static int emulate_mrs(struct pt_regs *regs, u32 insn)
1421{
1422 int rc;
1423 u32 sys_reg, dst;
1424 u64 val;
1425
1426 /*
1427 * sys_reg values are defined as used in mrs/msr instruction.
1428 * shift the imm value to get the encoding.
1429 */
1430 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1431 rc = emulate_sys_reg(sys_reg, &val);
1432 if (!rc) {
1433 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
521c6461 1434 pt_regs_write_reg(regs, dst, val);
6436beee 1435 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
77c97b4e
SP		 1436 }
1437
1438 return rc;
1439}
1440
1441static struct undef_hook mrs_hook = {
1442 .instr_mask = 0xfff00000,
1443 .instr_val = 0xd5300000,
1444 .pstate_mask = COMPAT_PSR_MODE_MASK,
1445 .pstate_val = PSR_MODE_EL0t,
1446 .fn = emulate_mrs,
1447};
1448
1449static int __init enable_mrs_emulation(void)
1450{
1451 register_undef_hook(&mrs_hook);
1452 return 0;
1453}
1454
c0d8832e 1455core_initcall(enable_mrs_emulation);
Linux 6.x block layer and io_uring tree(s)