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arm64: cpufeature: Relax checks for AArch32 support at EL[0-2]
[linux-2.6-block.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
caab277b 1// SPDX-License-Identifier: GPL-2.0-only
359b7064
MZ		 2/*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
359b7064
MZ		 6 */
7
9cdf8ec4 8#define pr_fmt(fmt) "CPU features: " fmt
359b7064 9
3c739b57 10#include <linux/bsearch.h>
2a6dcb2b 11#include <linux/cpumask.h>
5ffdfaed 12#include <linux/crash_dump.h>
3c739b57 13#include <linux/sort.h>
2a6dcb2b 14#include <linux/stop_machine.h>
359b7064 15#include <linux/types.h>
2077be67 16#include <linux/mm.h>
a111b7c0 17#include <linux/cpu.h>
359b7064
MZ		 18#include <asm/cpu.h>
19#include <asm/cpufeature.h>
dbb4e152 20#include <asm/cpu_ops.h>
2e0f2478 21#include <asm/fpsimd.h>
13f417f3 22#include <asm/mmu_context.h>
338d4f49 23#include <asm/processor.h>
cdcf817b 24#include <asm/sysreg.h>
77c97b4e 25#include <asm/traps.h>
d88701be 26#include <asm/virt.h>
359b7064 27
aec0bff7
AM		 28/* Kernel representation of AT_HWCAP and AT_HWCAP2 */
29static unsigned long elf_hwcap __read_mostly;
9cdf8ec4
SP		 30
31#ifdef CONFIG_COMPAT
32#define COMPAT_ELF_HWCAP_DEFAULT \
33 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
34 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
7559950a 35 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
9cdf8ec4
SP		 36 COMPAT_HWCAP_LPAE)
37unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
38unsigned int compat_elf_hwcap2 __read_mostly;
39#endif
40
41DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
4b65a5db 42EXPORT_SYMBOL(cpu_hwcaps);
82a3a21b 43static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
9cdf8ec4 44
0ceb0d56
DT		 45/* Need also bit for ARM64_CB_PATCH */
46DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
47
09e3c22a
MB		 48bool arm64_use_ng_mappings = false;
49EXPORT_SYMBOL(arm64_use_ng_mappings);
50
8f1eec57
DM		 51/*
52 * Flag to indicate if we have computed the system wide
53 * capabilities based on the boot time active CPUs. This
54 * will be used to determine if a new booting CPU should
55 * go through the verification process to make sure that it
56 * supports the system capabilities, without using a hotplug
b51c6ac2
SP		 57 * notifier. This is also used to decide if we could use
58 * the fast path for checking constant CPU caps.
8f1eec57 59 */
b51c6ac2
SP		 60DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
61EXPORT_SYMBOL(arm64_const_caps_ready);
62static inline void finalize_system_capabilities(void)
8f1eec57 63{
b51c6ac2 64 static_branch_enable(&arm64_const_caps_ready);
8f1eec57
DM		 65}
66
8effeaaf
MR		 67static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
68{
69 /* file-wide pr_fmt adds "CPU features: " prefix */
70 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
71 return 0;
72}
73
74static struct notifier_block cpu_hwcaps_notifier = {
75 .notifier_call = dump_cpu_hwcaps
76};
77
78static int __init register_cpu_hwcaps_dumper(void)
79{
80 atomic_notifier_chain_register(&panic_notifier_list,
81 &cpu_hwcaps_notifier);
82 return 0;
83}
84__initcall(register_cpu_hwcaps_dumper);
85
efd9e03f
CM		 86DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
87EXPORT_SYMBOL(cpu_hwcap_keys);
88
fe4fbdbc 89#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 90 { \
4f0a606b 91 .sign = SIGNED, \
fe4fbdbc 92 .visible = VISIBLE, \
3c739b57
SP		 93 .strict = STRICT, \
94 .type = TYPE, \
95 .shift = SHIFT, \
96 .width = WIDTH, \
97 .safe_val = SAFE_VAL, \
98 }
99
0710cfdb 100/* Define a feature with unsigned values */
fe4fbdbc
SP		 101#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
102 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
4f0a606b 103
0710cfdb 104/* Define a feature with a signed value */
fe4fbdbc
SP		 105#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
106 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
0710cfdb 107
3c739b57
SP		 108#define ARM64_FTR_END \
109 { \
110 .width = 0, \
111 }
112
70544196
JM		 113/* meta feature for alternatives */
114static bool __maybe_unused
92406f0c
SP		 115cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
116
5ffdfaed 117static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
70544196 118
3ff047f6
ADK		 119static bool __system_matches_cap(unsigned int n);
120
4aa8a472
SP		 121/*
122 * NOTE: Any changes to the visibility of features should be kept in
123 * sync with the documentation of the CPU feature register ABI.
124 */
5e49d73c 125static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
1a50ec0b 126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
7206dc93 127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
3b3b6810 128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
5bdecb79
SP		 129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
fe4fbdbc
SP		 134 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
136 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
137 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
138 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
3c739b57
SP		 139 ARM64_FTR_END,
140};
141
c8c3798d 142static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
d4209d8b
SP		 143 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
144 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
145 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
146 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
bd4fb6d2 147 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
7230f7e9 148 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
6984eb47
MR		 149 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
150 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
151 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
152 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
5bdecb79
SP		 153 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
154 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
155 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
6984eb47
MR		 156 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
157 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
158 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
159 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
5bdecb79 160 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
c8c3798d
SP		 161 ARM64_FTR_END,
162};
163
5e49d73c 164static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
179a56f6 165 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
0f15adbb 166 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
7206dc93 167 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
2c9d45b4 168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
3fab3999
DM		 169 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
170 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
64c02720 171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
5bdecb79 172 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
fe4fbdbc
SP		 173 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
174 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
5bdecb79 175 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
98448cdf
WD		 176 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
177 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
178 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
3c739b57
SP		 179 ARM64_FTR_END,
180};
181
d71be2b6
WD		 182static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
184 ARM64_FTR_END,
185};
186
06a916fe 187static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
d4209d8b
SP		 188 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
189 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
191 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
193 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
ec52c713
JG		 194 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
195 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
197 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
d4209d8b
SP		 198 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
199 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
ec52c713
JG		 200 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
201 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
203 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
204 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
205 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
06a916fe
DM		 206 ARM64_FTR_END,
207};
208
5e49d73c 209static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
5717fe5a
WD		 210 /*
211 * We already refuse to boot CPUs that don't support our configured
212 * page size, so we can only detect mismatches for a page size other
213 * than the one we're currently using. Unfortunately, SoCs like this
214 * exist in the wild so, even though we don't like it, we'll have to go
215 * along with it and treat them as non-strict.
216 */
217 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
218 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
219 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
220
5bdecb79 221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
3c739b57 222 /* Linux shouldn't care about secure memory */
5bdecb79
SP		 223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
3c739b57
SP		 226 /*
227 * Differing PARange is fine as long as all peripherals and memory are mapped
228 * within the minimum PARange of all CPUs
229 */
fe4fbdbc 230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 231 ARM64_FTR_END,
232};
233
5e49d73c 234static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
fe4fbdbc 235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
5bdecb79
SP		 236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
3c739b57
SP		 241 ARM64_FTR_END,
242};
243
5e49d73c 244static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
3e6c69a0 245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
e48d53a9 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
7206dc93 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
5bdecb79 248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
9d3f8881 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
5bdecb79
SP		 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 253 ARM64_FTR_END,
254};
255
5e49d73c 256static const struct arm64_ftr_bits ftr_ctr[] = {
6ae4b6e0
SD		 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
258 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
147b9635
WD		 260 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
261 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
6ae4b6e0 262 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
3c739b57
SP		 263 /*
264 * Linux can handle differing I-cache policies. Userspace JITs will
ee7bc638 265 * make use of *minLine.
155433cb 266 * If we have differing I-cache policies, report it as the weakest - VIPT.
3c739b57 267 */
155433cb 268 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
4c4a39dd 269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
3c739b57
SP		 270 ARM64_FTR_END,
271};
272
675b0563
AB		 273struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
274 .name = "SYS_CTR_EL0",
275 .ftr_bits = ftr_ctr
276};
277
5e49d73c 278static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
5bdecb79
SP		 279 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
fe4fbdbc 281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
5bdecb79
SP		 282 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
284 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
285 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
3c739b57
SP		 287 ARM64_FTR_END,
288};
289
5e49d73c 290static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
fe4fbdbc
SP		 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
b20d1ba3
WD		 296 /*
297 * We can instantiate multiple PMU instances with different levels
298 * of support.
fe4fbdbc
SP		 299 */
300 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 303 ARM64_FTR_END,
304};
305
5e49d73c 306static const struct arm64_ftr_bits ftr_mvfr2[] = {
5bdecb79
SP		 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
3c739b57
SP		 309 ARM64_FTR_END,
310};
311
5e49d73c 312static const struct arm64_ftr_bits ftr_dczid[] = {
fe4fbdbc
SP		 313 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
314 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
3c739b57
SP		 315 ARM64_FTR_END,
316};
317
318
5e49d73c 319static const struct arm64_ftr_bits ftr_id_isar5[] = {
5bdecb79
SP		 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
3c739b57
SP		 326 ARM64_FTR_END,
327};
328
5e49d73c 329static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
5bdecb79 330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
3c739b57
SP		 331 ARM64_FTR_END,
332};
333
0113340e
WD		 334static const struct arm64_ftr_bits ftr_id_isar4[] = {
335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
339 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
343 ARM64_FTR_END,
344};
345
8e3747be
AK		 346static const struct arm64_ftr_bits ftr_id_isar6[] = {
347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
354 ARM64_FTR_END,
355};
356
5e49d73c 357static const struct arm64_ftr_bits ftr_id_pfr0[] = {
5bdecb79
SP		 358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
359 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
360 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
361 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
3c739b57
SP		 362 ARM64_FTR_END,
363};
364
0113340e
WD		 365static const struct arm64_ftr_bits ftr_id_pfr1[] = {
366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
374 ARM64_FTR_END,
375};
376
5e49d73c 377static const struct arm64_ftr_bits ftr_id_dfr0[] = {
fe4fbdbc
SP		 378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
379 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
382 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
383 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
384 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
385 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
e5343503
SP		 386 ARM64_FTR_END,
387};
388
2e0f2478
DM		 389static const struct arm64_ftr_bits ftr_zcr[] = {
390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
391 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
392 ARM64_FTR_END,
393};
394
3c739b57
SP		 395/*
396 * Common ftr bits for a 32bit register with all hidden, strict
397 * attributes, with 4bit feature fields and a default safe value of
398 * 0. Covers the following 32bit registers:
399 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
400 */
5e49d73c 401static const struct arm64_ftr_bits ftr_generic_32bits[] = {
fe4fbdbc
SP		 402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
403 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
3c739b57
SP		 410 ARM64_FTR_END,
411};
412
eab43e88
SP		 413/* Table for a single 32bit feature value */
414static const struct arm64_ftr_bits ftr_single32[] = {
fe4fbdbc 415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
3c739b57
SP		 416 ARM64_FTR_END,
417};
418
eab43e88 419static const struct arm64_ftr_bits ftr_raz[] = {
3c739b57
SP		 420 ARM64_FTR_END,
421};
422
6f2b7eef
AB		 423#define ARM64_FTR_REG(id, table) { \
424 .sys_id = id, \
425 .reg = &(struct arm64_ftr_reg){ \
3c739b57
SP		 426 .name = #id, \
427 .ftr_bits = &((table)[0]), \
6f2b7eef 428 }}
3c739b57 429
6f2b7eef
AB		 430static const struct __ftr_reg_entry {
431 u32 sys_id;
432 struct arm64_ftr_reg *reg;
433} arm64_ftr_regs[] = {
3c739b57
SP		 434
435 /* Op1 = 0, CRn = 0, CRm = 1 */
436 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
0113340e 437 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
e5343503 438 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 439 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
440 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
441 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
442 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
443
444 /* Op1 = 0, CRn = 0, CRm = 2 */
445 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
446 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
447 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
448 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
0113340e 449 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
3c739b57
SP		 450 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
451 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
8e3747be 452 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
3c739b57
SP		 453
454 /* Op1 = 0, CRn = 0, CRm = 3 */
455 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
456 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
457 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
458
459 /* Op1 = 0, CRn = 0, CRm = 4 */
460 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
d71be2b6 461 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
06a916fe 462 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
3c739b57
SP		 463
464 /* Op1 = 0, CRn = 0, CRm = 5 */
465 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
eab43e88 466 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
3c739b57
SP		 467
468 /* Op1 = 0, CRn = 0, CRm = 6 */
469 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
c8c3798d 470 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
3c739b57
SP		 471
472 /* Op1 = 0, CRn = 0, CRm = 7 */
473 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
474 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 475 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57 476
2e0f2478
DM		 477 /* Op1 = 0, CRn = 1, CRm = 2 */
478 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
479
3c739b57 480 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 481 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP		 482 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
483
484 /* Op1 = 3, CRn = 14, CRm = 0 */
eab43e88 485 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
3c739b57
SP		 486};
487
488static int search_cmp_ftr_reg(const void *id, const void *regp)
489{
6f2b7eef 490 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP		 491}
492
493/*
494 * get_arm64_ftr_reg - Lookup a feature register entry using its
495 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
496 * ascending order of sys_id , we use binary search to find a matching
497 * entry.
498 *
499 * returns - Upon success, matching ftr_reg entry for id.
500 * - NULL on failure. It is upto the caller to decide
501 * the impact of a failure.
502 */
503static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
504{
6f2b7eef
AB		 505 const struct __ftr_reg_entry *ret;
506
507 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP		 508 arm64_ftr_regs,
509 ARRAY_SIZE(arm64_ftr_regs),
510 sizeof(arm64_ftr_regs[0]),
511 search_cmp_ftr_reg);
6f2b7eef
AB		 512 if (ret)
513 return ret->reg;
514 return NULL;
3c739b57
SP		 515}
516
5e49d73c
AB		 517static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
518 s64 ftr_val)
3c739b57
SP		 519{
520 u64 mask = arm64_ftr_mask(ftrp);
521
522 reg &= ~mask;
523 reg |= (ftr_val << ftrp->shift) & mask;
524 return reg;
525}
526
5e49d73c
AB		 527static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
528 s64 cur)
3c739b57
SP		 529{
530 s64 ret = 0;
531
532 switch (ftrp->type) {
533 case FTR_EXACT:
534 ret = ftrp->safe_val;
535 break;
536 case FTR_LOWER_SAFE:
537 ret = new < cur ? new : cur;
538 break;
147b9635
WD		 539 case FTR_HIGHER_OR_ZERO_SAFE:
540 if (!cur || !new)
541 break;
542 /* Fallthrough */
3c739b57
SP		 543 case FTR_HIGHER_SAFE:
544 ret = new > cur ? new : cur;
545 break;
546 default:
547 BUG();
548 }
549
550 return ret;
551}
552
3c739b57
SP		 553static void __init sort_ftr_regs(void)
554{
6f2b7eef
AB		 555 int i;
556
557 /* Check that the array is sorted so that we can do the binary search */
558 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
559 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP		 560}
561
562/*
563 * Initialise the CPU feature register from Boot CPU values.
564 * Also initiliases the strict_mask for the register.
b389d799
MR		 565 * Any bits that are not covered by an arm64_ftr_bits entry are considered
566 * RES0 for the system-wide value, and must strictly match.
3c739b57
SP		 567 */
568static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
569{
570 u64 val = 0;
571 u64 strict_mask = ~0x0ULL;
fe4fbdbc 572 u64 user_mask = 0;
b389d799
MR		 573 u64 valid_mask = 0;
574
5e49d73c 575 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 576 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
577
578 BUG_ON(!reg);
579
24b2cce9 580 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
b389d799 581 u64 ftr_mask = arm64_ftr_mask(ftrp);
3c739b57
SP		 582 s64 ftr_new = arm64_ftr_value(ftrp, new);
583
584 val = arm64_ftr_set_value(ftrp, val, ftr_new);
b389d799
MR		 585
586 valid_mask |= ftr_mask;
3c739b57 587 if (!ftrp->strict)
b389d799 588 strict_mask &= ~ftr_mask;
fe4fbdbc
SP		 589 if (ftrp->visible)
590 user_mask |= ftr_mask;
591 else
592 reg->user_val = arm64_ftr_set_value(ftrp,
593 reg->user_val,
594 ftrp->safe_val);
3c739b57 595 }
b389d799
MR		 596
597 val &= valid_mask;
598
3c739b57
SP		 599 reg->sys_val = val;
600 reg->strict_mask = strict_mask;
fe4fbdbc 601 reg->user_mask = user_mask;
3c739b57
SP		 602}
603
1e89baed 604extern const struct arm64_cpu_capabilities arm64_errata[];
82a3a21b
SP		 605static const struct arm64_cpu_capabilities arm64_features[];
606
607static void __init
608init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
609{
610 for (; caps->matches; caps++) {
611 if (WARN(caps->capability >= ARM64_NCAPS,
612 "Invalid capability %d\n", caps->capability))
613 continue;
614 if (WARN(cpu_hwcaps_ptrs[caps->capability],
615 "Duplicate entry for capability %d\n",
616 caps->capability))
617 continue;
618 cpu_hwcaps_ptrs[caps->capability] = caps;
619 }
620}
621
622static void __init init_cpu_hwcaps_indirect_list(void)
623{
624 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
625 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
626}
627
fd9d63da 628static void __init setup_boot_cpu_capabilities(void);
1e89baed 629
3c739b57
SP		 630void __init init_cpu_features(struct cpuinfo_arm64 *info)
631{
632 /* Before we start using the tables, make sure it is sorted */
633 sort_ftr_regs();
634
635 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
636 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
637 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
638 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
639 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
640 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
641 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
642 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
643 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 644 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 645 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
646 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
2e0f2478 647 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
a6dc3cd7
SP		 648
649 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
650 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
651 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
652 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
653 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
654 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
655 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
656 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
8e3747be 657 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
a6dc3cd7
SP		 658 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
659 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
660 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
661 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
662 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
663 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
664 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
665 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
666 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
667 }
668
2e0f2478
DM		 669 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
670 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
671 sve_init_vq_map();
672 }
5e91107b 673
82a3a21b
SP		 674 /*
675 * Initialize the indirect array of CPU hwcaps capabilities pointers
676 * before we handle the boot CPU below.
677 */
678 init_cpu_hwcaps_indirect_list();
679
5e91107b 680 /*
fd9d63da
SP		 681 * Detect and enable early CPU capabilities based on the boot CPU,
682 * after we have initialised the CPU feature infrastructure.
5e91107b 683 */
fd9d63da 684 setup_boot_cpu_capabilities();
3c739b57
SP		 685}
686
3086d391 687static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 688{
5e49d73c 689 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 690
691 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
692 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
693 s64 ftr_new = arm64_ftr_value(ftrp, new);
694
695 if (ftr_cur == ftr_new)
696 continue;
697 /* Find a safe value */
698 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
699 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
700 }
701
702}
703
3086d391 704static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 705{
3086d391
SP		 706 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
707
708 BUG_ON(!regp);
709 update_cpu_ftr_reg(regp, val);
710 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
711 return 0;
712 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
713 regp->name, boot, cpu, val);
714 return 1;
715}
716
eab2f926
WD		 717static void relax_cpu_ftr_reg(u32 sys_id, int field)
718{
719 const struct arm64_ftr_bits *ftrp;
720 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
721
722 if (WARN_ON(!regp))
723 return;
724
725 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
726 if (ftrp->shift == field) {
727 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
728 break;
729 }
730 }
731
732 /* Bogus field? */
733 WARN_ON(!ftrp->width);
734}
735
1efcfe79
WD		 736static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info,
737 struct cpuinfo_arm64 *boot)
738{
739 int taint = 0;
740 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
741
742 /*
743 * If we don't have AArch32 at all then skip the checks entirely
744 * as the register values may be UNKNOWN and we're not going to be
745 * using them for anything.
746 */
747 if (!id_aa64pfr0_32bit_el0(pfr0))
748 return taint;
749
eab2f926
WD		 750 /*
751 * If we don't have AArch32 at EL1, then relax the strictness of
752 * EL1-dependent register fields to avoid spurious sanity check fails.
753 */
754 if (!id_aa64pfr0_32bit_el1(pfr0)) {
755 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
756 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
757 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
758 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
759 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
760 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
761 }
762
1efcfe79
WD		 763 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
764 info->reg_id_dfr0, boot->reg_id_dfr0);
765 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
766 info->reg_id_isar0, boot->reg_id_isar0);
767 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
768 info->reg_id_isar1, boot->reg_id_isar1);
769 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
770 info->reg_id_isar2, boot->reg_id_isar2);
771 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
772 info->reg_id_isar3, boot->reg_id_isar3);
773 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
774 info->reg_id_isar4, boot->reg_id_isar4);
775 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
776 info->reg_id_isar5, boot->reg_id_isar5);
777 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
778 info->reg_id_isar6, boot->reg_id_isar6);
779
780 /*
781 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
782 * ACTLR formats could differ across CPUs and therefore would have to
783 * be trapped for virtualization anyway.
784 */
785 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
786 info->reg_id_mmfr0, boot->reg_id_mmfr0);
787 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
788 info->reg_id_mmfr1, boot->reg_id_mmfr1);
789 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
790 info->reg_id_mmfr2, boot->reg_id_mmfr2);
791 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
792 info->reg_id_mmfr3, boot->reg_id_mmfr3);
793 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
794 info->reg_id_pfr0, boot->reg_id_pfr0);
795 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
796 info->reg_id_pfr1, boot->reg_id_pfr1);
797 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
798 info->reg_mvfr0, boot->reg_mvfr0);
799 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
800 info->reg_mvfr1, boot->reg_mvfr1);
801 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
802 info->reg_mvfr2, boot->reg_mvfr2);
803
804 return taint;
805}
806
3086d391
SP		 807/*
808 * Update system wide CPU feature registers with the values from a
809 * non-boot CPU. Also performs SANITY checks to make sure that there
810 * aren't any insane variations from that of the boot CPU.
811 */
812void update_cpu_features(int cpu,
813 struct cpuinfo_arm64 *info,
814 struct cpuinfo_arm64 *boot)
815{
816 int taint = 0;
817
818 /*
819 * The kernel can handle differing I-cache policies, but otherwise
820 * caches should look identical. Userspace JITs will make use of
821 * *minLine.
822 */
823 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
824 info->reg_ctr, boot->reg_ctr);
825
826 /*
827 * Userspace may perform DC ZVA instructions. Mismatched block sizes
828 * could result in too much or too little memory being zeroed if a
829 * process is preempted and migrated between CPUs.
830 */
831 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
832 info->reg_dczid, boot->reg_dczid);
833
834 /* If different, timekeeping will be broken (especially with KVM) */
835 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
836 info->reg_cntfrq, boot->reg_cntfrq);
837
838 /*
839 * The kernel uses self-hosted debug features and expects CPUs to
840 * support identical debug features. We presently need CTX_CMPs, WRPs,
841 * and BRPs to be identical.
842 * ID_AA64DFR1 is currently RES0.
843 */
844 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
845 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
846 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
847 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
848 /*
849 * Even in big.LITTLE, processors should be identical instruction-set
850 * wise.
851 */
852 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
853 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
854 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
855 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
856
857 /*
858 * Differing PARange support is fine as long as all peripherals and
859 * memory are mapped within the minimum PARange of all CPUs.
860 * Linux should not care about secure memory.
861 */
862 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
863 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
864 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
865 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 866 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
867 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391 868
3086d391
SP		 869 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
870 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
871 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
872 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
873
2e0f2478
DM		 874 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
875 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
876
2e0f2478
DM		 877 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
878 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
879 info->reg_zcr, boot->reg_zcr);
880
881 /* Probe vector lengths, unless we already gave up on SVE */
882 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
b51c6ac2 883 !system_capabilities_finalized())
2e0f2478
DM		 884 sve_update_vq_map();
885 }
886
1efcfe79
WD		 887 /*
888 * This relies on a sanitised view of the AArch64 ID registers
889 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
890 */
891 taint |= update_32bit_cpu_features(cpu, info, boot);
892
3086d391
SP		 893 /*
894 * Mismatched CPU features are a recipe for disaster. Don't even
895 * pretend to support them.
896 */
8dd0ee65
WD		 897 if (taint) {
898 pr_warn_once("Unsupported CPU feature variation detected.\n");
899 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
900 }
cdcf817b
SP		 901}
902
46823dd1 903u64 read_sanitised_ftr_reg(u32 id)
b3f15378
SP		 904{
905 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
906
907 /* We shouldn't get a request for an unsupported register */
908 BUG_ON(!regp);
909 return regp->sys_val;
910}
359b7064 911
965861d6
MR		 912#define read_sysreg_case(r) \
913 case r: return read_sysreg_s(r)
914
92406f0c 915/*
46823dd1 916 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
92406f0c
SP		 917 * Read the system register on the current CPU
918 */
46823dd1 919static u64 __read_sysreg_by_encoding(u32 sys_id)
92406f0c
SP		 920{
921 switch (sys_id) {
965861d6
MR		 922 read_sysreg_case(SYS_ID_PFR0_EL1);
923 read_sysreg_case(SYS_ID_PFR1_EL1);
924 read_sysreg_case(SYS_ID_DFR0_EL1);
925 read_sysreg_case(SYS_ID_MMFR0_EL1);
926 read_sysreg_case(SYS_ID_MMFR1_EL1);
927 read_sysreg_case(SYS_ID_MMFR2_EL1);
928 read_sysreg_case(SYS_ID_MMFR3_EL1);
929 read_sysreg_case(SYS_ID_ISAR0_EL1);
930 read_sysreg_case(SYS_ID_ISAR1_EL1);
931 read_sysreg_case(SYS_ID_ISAR2_EL1);
932 read_sysreg_case(SYS_ID_ISAR3_EL1);
933 read_sysreg_case(SYS_ID_ISAR4_EL1);
934 read_sysreg_case(SYS_ID_ISAR5_EL1);
8e3747be 935 read_sysreg_case(SYS_ID_ISAR6_EL1);
965861d6
MR		 936 read_sysreg_case(SYS_MVFR0_EL1);
937 read_sysreg_case(SYS_MVFR1_EL1);
938 read_sysreg_case(SYS_MVFR2_EL1);
939
940 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
941 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
78ed70bf 942 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
965861d6
MR		 943 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
944 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
945 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
946 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
947 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
948 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
949 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
950
951 read_sysreg_case(SYS_CNTFRQ_EL0);
952 read_sysreg_case(SYS_CTR_EL0);
953 read_sysreg_case(SYS_DCZID_EL0);
954
92406f0c
SP		 955 default:
956 BUG();
957 return 0;
958 }
959}
960
963fcd40
MZ		 961#include <linux/irqchip/arm-gic-v3.h>
962
18ffa046
JM		 963static bool
964feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
965{
28c5dcb2 966 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 967
968 return val >= entry->min_field_value;
969}
970
da8d02d1 971static bool
92406f0c 972has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 973{
974 u64 val;
94a9e04a 975
92406f0c
SP		 976 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
977 if (scope == SCOPE_SYSTEM)
46823dd1 978 val = read_sanitised_ftr_reg(entry->sys_reg);
92406f0c 979 else
46823dd1 980 val = __read_sysreg_by_encoding(entry->sys_reg);
92406f0c 981
da8d02d1
SP		 982 return feature_matches(val, entry);
983}
338d4f49 984
92406f0c 985static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 986{
987 bool has_sre;
988
92406f0c 989 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 990 return false;
991
992 has_sre = gic_enable_sre();
993 if (!has_sre)
994 pr_warn_once("%s present but disabled by higher exception level\n",
995 entry->desc);
996
997 return has_sre;
998}
999
92406f0c 1000static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 1001{
1002 u32 midr = read_cpuid_id();
d5370f75
WD		 1003
1004 /* Cavium ThunderX pass 1.x and 2.x */
b99286b0 1005 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
fa5ce3d1
RR		 1006 MIDR_CPU_VAR_REV(0, 0),
1007 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
d5370f75
WD		 1008}
1009
82e0191a
SP		 1010static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1011{
46823dd1 1012 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
82e0191a
SP		 1013
1014 return cpuid_feature_extract_signed_field(pfr0,
1015 ID_AA64PFR0_FP_SHIFT) < 0;
1016}
1017
6ae4b6e0 1018static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
8ab66cbe 1019 int scope)
6ae4b6e0 1020{
8ab66cbe
SP		 1021 u64 ctr;
1022
1023 if (scope == SCOPE_SYSTEM)
1024 ctr = arm64_ftr_reg_ctrel0.sys_val;
1025 else
1602df02 1026 ctr = read_cpuid_effective_cachetype();
8ab66cbe
SP		 1027
1028 return ctr & BIT(CTR_IDC_SHIFT);
6ae4b6e0
SD		 1029}
1030
1602df02
SP		 1031static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1032{
1033 /*
1034 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1035 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1036 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1037 * value.
1038 */
1039 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1040 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1041}
1042
6ae4b6e0 1043static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
8ab66cbe 1044 int scope)
6ae4b6e0 1045{
8ab66cbe
SP		 1046 u64 ctr;
1047
1048 if (scope == SCOPE_SYSTEM)
1049 ctr = arm64_ftr_reg_ctrel0.sys_val;
1050 else
1051 ctr = read_cpuid_cachetype();
1052
1053 return ctr & BIT(CTR_DIC_SHIFT);
6ae4b6e0
SD		 1054}
1055
5ffdfaed
VM		 1056static bool __maybe_unused
1057has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1058{
1059 /*
1060 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1061 * may share TLB entries with a CPU stuck in the crashed
1062 * kernel.
1063 */
1064 if (is_kdump_kernel())
1065 return false;
1066
1067 return has_cpuid_feature(entry, scope);
1068}
1069
09e3c22a
MB		 1070/*
1071 * This check is triggered during the early boot before the cpufeature
1072 * is initialised. Checking the status on the local CPU allows the boot
1073 * CPU to detect the need for non-global mappings and thus avoiding a
1074 * pagetable re-write after all the CPUs are booted. This check will be
1075 * anyway run on individual CPUs, allowing us to get the consistent
1076 * state once the SMP CPUs are up and thus make the switch to non-global
1077 * mappings if required.
1078 */
1079bool kaslr_requires_kpti(void)
1080{
09e3c22a
MB		 1081 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1082 return false;
1083
1084 /*
1085 * E0PD does a similar job to KPTI so can be used instead
1086 * where available.
1087 */
1088 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
a569f5f3
WD		 1089 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1090 if (cpuid_feature_extract_unsigned_field(mmfr2,
1091 ID_AA64MMFR2_E0PD_SHIFT))
09e3c22a
MB		 1092 return false;
1093 }
1094
1095 /*
1096 * Systems affected by Cavium erratum 24756 are incompatible
1097 * with KPTI.
1098 */
ebac96ed 1099 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
09e3c22a
MB		 1100 extern const struct midr_range cavium_erratum_27456_cpus[];
1101
ebac96ed
WD		 1102 if (is_midr_in_range_list(read_cpuid_id(),
1103 cavium_erratum_27456_cpus))
1104 return false;
09e3c22a 1105 }
09e3c22a
MB		 1106
1107 return kaslr_offset() > 0;
1108}
1109
1b3ccf4b 1110static bool __meltdown_safe = true;
ea1e3de8
WD		 1111static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1112
1113static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
d3aec8a2 1114 int scope)
ea1e3de8 1115{
be5b2998
SP		 1116 /* List of CPUs that are not vulnerable and don't need KPTI */
1117 static const struct midr_range kpti_safe_list[] = {
1118 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1119 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
31d868c4 1120 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
2a355ec2
WD		 1121 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1122 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1123 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1124 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1125 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1126 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
0ecc471a 1127 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
918e1946 1128 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
71c751f2 1129 { /* sentinel */ }
be5b2998 1130 };
a111b7c0 1131 char const *str = "kpti command line option";
1b3ccf4b
JL		 1132 bool meltdown_safe;
1133
1134 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1135
1136 /* Defer to CPU feature registers */
1137 if (has_cpuid_feature(entry, scope))
1138 meltdown_safe = true;
1139
1140 if (!meltdown_safe)
1141 __meltdown_safe = false;
179a56f6 1142
6dc52b15
MZ		 1143 /*
1144 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1145 * ThunderX leads to apparent I-cache corruption of kernel text, which
1146 * ends as well as you might imagine. Don't even try.
1147 */
1148 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1149 str = "ARM64_WORKAROUND_CAVIUM_27456";
1150 __kpti_forced = -1;
1151 }
1152
1b3ccf4b 1153 /* Useful for KASLR robustness */
c2d92353 1154 if (kaslr_requires_kpti()) {
1b3ccf4b
JL		 1155 if (!__kpti_forced) {
1156 str = "KASLR";
1157 __kpti_forced = 1;
1158 }
1159 }
1160
a111b7c0
JP		 1161 if (cpu_mitigations_off() && !__kpti_forced) {
1162 str = "mitigations=off";
1163 __kpti_forced = -1;
1164 }
1165
1b3ccf4b
JL		 1166 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1167 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1168 return false;
1169 }
1170
6dc52b15 1171 /* Forced? */
ea1e3de8 1172 if (__kpti_forced) {
6dc52b15
MZ		 1173 pr_info_once("kernel page table isolation forced %s by %s\n",
1174 __kpti_forced > 0 ? "ON" : "OFF", str);
ea1e3de8
WD		 1175 return __kpti_forced > 0;
1176 }
1177
1b3ccf4b 1178 return !meltdown_safe;
ea1e3de8
WD		 1179}
1180
1b3ccf4b 1181#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
c0cda3b8
DM		 1182static void
1183kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
f992b4df
WD		 1184{
1185 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1186 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1187 kpti_remap_fn *remap_fn;
1188
f992b4df
WD		 1189 int cpu = smp_processor_id();
1190
b89d82ef
WD		 1191 /*
1192 * We don't need to rewrite the page-tables if either we've done
1193 * it already or we have KASLR enabled and therefore have not
1194 * created any global mappings at all.
1195 */
09e3c22a 1196 if (arm64_use_ng_mappings)
c0cda3b8 1197 return;
f992b4df
WD		 1198
1199 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1200
1201 cpu_install_idmap();
1202 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1203 cpu_uninstall_idmap();
1204
1205 if (!cpu)
09e3c22a 1206 arm64_use_ng_mappings = true;
f992b4df 1207
c0cda3b8 1208 return;
f992b4df 1209}
1b3ccf4b
JL		 1210#else
1211static void
1212kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1213{
1214}
1215#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
f992b4df 1216
ea1e3de8
WD		 1217static int __init parse_kpti(char *str)
1218{
1219 bool enabled;
1220 int ret = strtobool(str, &enabled);
1221
1222 if (ret)
1223 return ret;
1224
1225 __kpti_forced = enabled ? 1 : -1;
1226 return 0;
1227}
b5b7dd64 1228early_param("kpti", parse_kpti);
ea1e3de8 1229
05abb595
SP		 1230#ifdef CONFIG_ARM64_HW_AFDBM
1231static inline void __cpu_enable_hw_dbm(void)
1232{
1233 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1234
1235 write_sysreg(tcr, tcr_el1);
1236 isb();
1237}
1238
ece1397c
SP		 1239static bool cpu_has_broken_dbm(void)
1240{
1241 /* List of CPUs which have broken DBM support. */
1242 static const struct midr_range cpus[] = {
1243#ifdef CONFIG_ARM64_ERRATUM_1024718
1244 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
1245#endif
1246 {},
1247 };
1248
1249 return is_midr_in_range_list(read_cpuid_id(), cpus);
1250}
1251
05abb595
SP		 1252static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1253{
ece1397c
SP		 1254 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1255 !cpu_has_broken_dbm();
05abb595
SP		 1256}
1257
1258static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1259{
1260 if (cpu_can_use_dbm(cap))
1261 __cpu_enable_hw_dbm();
1262}
1263
1264static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1265 int __unused)
1266{
1267 static bool detected = false;
1268 /*
1269 * DBM is a non-conflicting feature. i.e, the kernel can safely
1270 * run a mix of CPUs with and without the feature. So, we
1271 * unconditionally enable the capability to allow any late CPU
1272 * to use the feature. We only enable the control bits on the
1273 * CPU, if it actually supports.
1274 *
1275 * We have to make sure we print the "feature" detection only
1276 * when at least one CPU actually uses it. So check if this CPU
1277 * can actually use it and print the message exactly once.
1278 *
1279 * This is safe as all CPUs (including secondary CPUs - due to the
1280 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1281 * goes through the "matches" check exactly once. Also if a CPU
1282 * matches the criteria, it is guaranteed that the CPU will turn
1283 * the DBM on, as the capability is unconditionally enabled.
1284 */
1285 if (!detected && cpu_can_use_dbm(cap)) {
1286 detected = true;
1287 pr_info("detected: Hardware dirty bit management\n");
1288 }
1289
1290 return true;
1291}
1292
1293#endif
1294
2c9d45b4
IV		 1295#ifdef CONFIG_ARM64_AMU_EXTN
1296
1297/*
1298 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1299 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1300 * information regarding all the events that it supports. When a CPU bit is
1301 * set in the cpumask, the user of this feature can only rely on the presence
1302 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1303 * counters are enabled or access to these counters is enabled by code
1304 * executed at higher exception levels (firmware).
1305 */
1306static struct cpumask amu_cpus __read_mostly;
1307
1308bool cpu_has_amu_feat(int cpu)
1309{
1310 return cpumask_test_cpu(cpu, &amu_cpus);
1311}
1312
cd0ed03a
IV		 1313/* Initialize the use of AMU counters for frequency invariance */
1314extern void init_cpu_freq_invariance_counters(void);
1315
2c9d45b4
IV		 1316static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1317{
1318 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1319 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1320 smp_processor_id());
1321 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
cd0ed03a 1322 init_cpu_freq_invariance_counters();
2c9d45b4
IV		 1323 }
1324}
1325
1326static bool has_amu(const struct arm64_cpu_capabilities *cap,
1327 int __unused)
1328{
1329 /*
1330 * The AMU extension is a non-conflicting feature: the kernel can
1331 * safely run a mix of CPUs with and without support for the
1332 * activity monitors extension. Therefore, unconditionally enable
1333 * the capability to allow any late CPU to use the feature.
1334 *
1335 * With this feature unconditionally enabled, the cpu_enable
1336 * function will be called for all CPUs that match the criteria,
1337 * including secondary and hotplugged, marking this feature as
1338 * present on that respective CPU. The enable function will also
1339 * print a detection message.
1340 */
1341
1342 return true;
1343}
1344#endif
1345
12eb3691
WD		 1346#ifdef CONFIG_ARM64_VHE
1347static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1348{
1349 return is_kernel_in_hyp_mode();
1350}
1351
c0cda3b8 1352static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
6d99b689
JM		 1353{
1354 /*
1355 * Copy register values that aren't redirected by hardware.
1356 *
1357 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1358 * this value to tpidr_el2 before we patch the code. Once we've done
1359 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1360 * do anything here.
1361 */
e9ab7a2e 1362 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
6d99b689 1363 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
6d99b689 1364}
12eb3691 1365#endif
6d99b689 1366
e48d53a9
MZ		 1367static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1368{
1369 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1370
1371 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1372 WARN_ON(val & (7 << 27 | 7 << 21));
1373}
1374
8f04e8e6
WD		 1375#ifdef CONFIG_ARM64_SSBD
1376static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1377{
1378 if (user_mode(regs))
1379 return 1;
1380
74e24828 1381 if (instr & BIT(PSTATE_Imm_shift))
8f04e8e6
WD		 1382 regs->pstate |= PSR_SSBS_BIT;
1383 else
1384 regs->pstate &= ~PSR_SSBS_BIT;
1385
1386 arm64_skip_faulting_instruction(regs, 4);
1387 return 0;
1388}
1389
1390static struct undef_hook ssbs_emulation_hook = {
74e24828
SP		 1391 .instr_mask = ~(1U << PSTATE_Imm_shift),
1392 .instr_val = 0xd500401f | PSTATE_SSBS,
8f04e8e6
WD		 1393 .fn = ssbs_emulation_handler,
1394};
1395
1396static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1397{
1398 static bool undef_hook_registered = false;
27e6e7d6 1399 static DEFINE_RAW_SPINLOCK(hook_lock);
8f04e8e6 1400
27e6e7d6 1401 raw_spin_lock(&hook_lock);
8f04e8e6
WD		 1402 if (!undef_hook_registered) {
1403 register_undef_hook(&ssbs_emulation_hook);
1404 undef_hook_registered = true;
1405 }
27e6e7d6 1406 raw_spin_unlock(&hook_lock);
8f04e8e6
WD		 1407
1408 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1409 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1410 arm64_set_ssbd_mitigation(false);
1411 } else {
1412 arm64_set_ssbd_mitigation(true);
1413 }
1414}
1415#endif /* CONFIG_ARM64_SSBD */
1416
b8925ee2
WD		 1417#ifdef CONFIG_ARM64_PAN
1418static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1419{
1420 /*
1421 * We modify PSTATE. This won't work from irq context as the PSTATE
1422 * is discarded once we return from the exception.
1423 */
1424 WARN_ON_ONCE(in_interrupt());
1425
1426 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1427 asm(SET_PSTATE_PAN(1));
1428}
1429#endif /* CONFIG_ARM64_PAN */
1430
1431#ifdef CONFIG_ARM64_RAS_EXTN
1432static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1433{
1434 /* Firmware may have left a deferred SError in this register. */
1435 write_sysreg_s(0, SYS_DISR_EL1);
1436}
1437#endif /* CONFIG_ARM64_RAS_EXTN */
1438
6984eb47 1439#ifdef CONFIG_ARM64_PTR_AUTH
cfef06bd
KM		 1440static bool has_address_auth(const struct arm64_cpu_capabilities *entry,
1441 int __unused)
1442{
1443 return __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_ARCH) ||
1444 __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_IMP_DEF);
1445}
1446
1447static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1448 int __unused)
75031975 1449{
cfef06bd
KM		 1450 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1451 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
75031975 1452}
6984eb47
MR		 1453#endif /* CONFIG_ARM64_PTR_AUTH */
1454
3e6c69a0
MB		 1455#ifdef CONFIG_ARM64_E0PD
1456static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1457{
1458 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1459 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1460}
1461#endif /* CONFIG_ARM64_E0PD */
1462
b90d2b22 1463#ifdef CONFIG_ARM64_PSEUDO_NMI
bc3c03cc
JT		 1464static bool enable_pseudo_nmi;
1465
1466static int __init early_enable_pseudo_nmi(char *p)
1467{
1468 return strtobool(p, &enable_pseudo_nmi);
1469}
1470early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1471
b90d2b22
JT		 1472static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1473 int scope)
1474{
bc3c03cc 1475 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
b90d2b22
JT		 1476}
1477#endif
1478
8c176e16
ADK		 1479/* Internal helper functions to match cpu capability type */
1480static bool
1481cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1482{
1483 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1484}
1485
1486static bool
1487cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1488{
1489 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1490}
1491
deeaac51
KM		 1492static bool
1493cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1494{
1495 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1496}
1497
359b7064 1498static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 1499 {
1500 .desc = "GIC system register CPU interface",
1501 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
c9bfdf73 1502 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
963fcd40 1503 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 1504 .sys_reg = SYS_ID_AA64PFR0_EL1,
1505 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 1506 .sign = FTR_UNSIGNED,
18ffa046 1507 .min_field_value = 1,
94a9e04a 1508 },
338d4f49
JM		 1509#ifdef CONFIG_ARM64_PAN
1510 {
1511 .desc = "Privileged Access Never",
1512 .capability = ARM64_HAS_PAN,
5b4747c5 1513 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1514 .matches = has_cpuid_feature,
1515 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1516 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 1517 .sign = FTR_UNSIGNED,
338d4f49 1518 .min_field_value = 1,
c0cda3b8 1519 .cpu_enable = cpu_enable_pan,
338d4f49
JM		 1520 },
1521#endif /* CONFIG_ARM64_PAN */
395af861 1522#ifdef CONFIG_ARM64_LSE_ATOMICS
2e94da13
WD		 1523 {
1524 .desc = "LSE atomic instructions",
1525 .capability = ARM64_HAS_LSE_ATOMICS,
5b4747c5 1526 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1527 .matches = has_cpuid_feature,
1528 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1529 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 1530 .sign = FTR_UNSIGNED,
2e94da13
WD		 1531 .min_field_value = 2,
1532 },
395af861 1533#endif /* CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 1534 {
1535 .desc = "Software prefetching using PRFM",
1536 .capability = ARM64_HAS_NO_HW_PREFETCH,
5c137714 1537 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
d5370f75
WD		 1538 .matches = has_no_hw_prefetch,
1539 },
57f4959b
JM		 1540#ifdef CONFIG_ARM64_UAO
1541 {
1542 .desc = "User Access Override",
1543 .capability = ARM64_HAS_UAO,
5b4747c5 1544 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
57f4959b
JM		 1545 .matches = has_cpuid_feature,
1546 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1547 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1548 .min_field_value = 1,
c8b06e3f
JM		 1549 /*
1550 * We rely on stop_machine() calling uao_thread_switch() to set
1551 * UAO immediately after patching.
1552 */
57f4959b
JM		 1553 },
1554#endif /* CONFIG_ARM64_UAO */
70544196
JM		 1555#ifdef CONFIG_ARM64_PAN
1556 {
1557 .capability = ARM64_ALT_PAN_NOT_UAO,
5b4747c5 1558 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
70544196
JM		 1559 .matches = cpufeature_pan_not_uao,
1560 },
1561#endif /* CONFIG_ARM64_PAN */
830dcc9f 1562#ifdef CONFIG_ARM64_VHE
d88701be
MZ		 1563 {
1564 .desc = "Virtualization Host Extensions",
1565 .capability = ARM64_HAS_VIRT_HOST_EXTN,
830dcc9f 1566 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
d88701be 1567 .matches = runs_at_el2,
c0cda3b8 1568 .cpu_enable = cpu_copy_el2regs,
d88701be 1569 },
830dcc9f 1570#endif /* CONFIG_ARM64_VHE */
042446a3
SP		 1571 {
1572 .desc = "32-bit EL0 Support",
1573 .capability = ARM64_HAS_32BIT_EL0,
5b4747c5 1574 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
042446a3
SP		 1575 .matches = has_cpuid_feature,
1576 .sys_reg = SYS_ID_AA64PFR0_EL1,
1577 .sign = FTR_UNSIGNED,
1578 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1579 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1580 },
540f76d1
WD		 1581#ifdef CONFIG_KVM
1582 {
1583 .desc = "32-bit EL1 Support",
1584 .capability = ARM64_HAS_32BIT_EL1,
1585 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1586 .matches = has_cpuid_feature,
1587 .sys_reg = SYS_ID_AA64PFR0_EL1,
1588 .sign = FTR_UNSIGNED,
1589 .field_pos = ID_AA64PFR0_EL1_SHIFT,
1590 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
1591 },
1592#endif
ea1e3de8 1593 {
179a56f6 1594 .desc = "Kernel page table isolation (KPTI)",
ea1e3de8 1595 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
d3aec8a2
SP		 1596 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1597 /*
1598 * The ID feature fields below are used to indicate that
1599 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1600 * more details.
1601 */
1602 .sys_reg = SYS_ID_AA64PFR0_EL1,
1603 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1604 .min_field_value = 1,
ea1e3de8 1605 .matches = unmap_kernel_at_el0,
c0cda3b8 1606 .cpu_enable = kpti_install_ng_mappings,
ea1e3de8 1607 },
82e0191a
SP		 1608 {
1609 /* FP/SIMD is not implemented */
1610 .capability = ARM64_HAS_NO_FPSIMD,
449443c0 1611 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
82e0191a
SP		 1612 .min_field_value = 0,
1613 .matches = has_no_fpsimd,
1614 },
d50e071f
RM		 1615#ifdef CONFIG_ARM64_PMEM
1616 {
1617 .desc = "Data cache clean to Point of Persistence",
1618 .capability = ARM64_HAS_DCPOP,
5b4747c5 1619 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
d50e071f
RM		 1620 .matches = has_cpuid_feature,
1621 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1622 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1623 .min_field_value = 1,
1624 },
b9585f53
AM		 1625 {
1626 .desc = "Data cache clean to Point of Deep Persistence",
1627 .capability = ARM64_HAS_DCPODP,
1628 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1629 .matches = has_cpuid_feature,
1630 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1631 .sign = FTR_UNSIGNED,
1632 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1633 .min_field_value = 2,
1634 },
d50e071f 1635#endif
43994d82
DM		 1636#ifdef CONFIG_ARM64_SVE
1637 {
1638 .desc = "Scalable Vector Extension",
5b4747c5 1639 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
43994d82 1640 .capability = ARM64_SVE,
43994d82
DM		 1641 .sys_reg = SYS_ID_AA64PFR0_EL1,
1642 .sign = FTR_UNSIGNED,
1643 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1644 .min_field_value = ID_AA64PFR0_SVE,
1645 .matches = has_cpuid_feature,
c0cda3b8 1646 .cpu_enable = sve_kernel_enable,
43994d82
DM		 1647 },
1648#endif /* CONFIG_ARM64_SVE */
64c02720
XX		 1649#ifdef CONFIG_ARM64_RAS_EXTN
1650 {
1651 .desc = "RAS Extension Support",
1652 .capability = ARM64_HAS_RAS_EXTN,
5b4747c5 1653 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
64c02720
XX		 1654 .matches = has_cpuid_feature,
1655 .sys_reg = SYS_ID_AA64PFR0_EL1,
1656 .sign = FTR_UNSIGNED,
1657 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1658 .min_field_value = ID_AA64PFR0_RAS_V1,
c0cda3b8 1659 .cpu_enable = cpu_clear_disr,
64c02720
XX		 1660 },
1661#endif /* CONFIG_ARM64_RAS_EXTN */
2c9d45b4
IV		 1662#ifdef CONFIG_ARM64_AMU_EXTN
1663 {
1664 /*
1665 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
1666 * Therefore, don't provide .desc as we don't want the detection
1667 * message to be shown until at least one CPU is detected to
1668 * support the feature.
1669 */
1670 .capability = ARM64_HAS_AMU_EXTN,
1671 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1672 .matches = has_amu,
1673 .sys_reg = SYS_ID_AA64PFR0_EL1,
1674 .sign = FTR_UNSIGNED,
1675 .field_pos = ID_AA64PFR0_AMU_SHIFT,
1676 .min_field_value = ID_AA64PFR0_AMU,
1677 .cpu_enable = cpu_amu_enable,
1678 },
1679#endif /* CONFIG_ARM64_AMU_EXTN */
6ae4b6e0
SD		 1680 {
1681 .desc = "Data cache clean to the PoU not required for I/D coherence",
1682 .capability = ARM64_HAS_CACHE_IDC,
5b4747c5 1683 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0 1684 .matches = has_cache_idc,
1602df02 1685 .cpu_enable = cpu_emulate_effective_ctr,
6ae4b6e0
SD		 1686 },
1687 {
1688 .desc = "Instruction cache invalidation not required for I/D coherence",
1689 .capability = ARM64_HAS_CACHE_DIC,
5b4747c5 1690 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0
SD		 1691 .matches = has_cache_dic,
1692 },
e48d53a9
MZ		 1693 {
1694 .desc = "Stage-2 Force Write-Back",
1695 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1696 .capability = ARM64_HAS_STAGE2_FWB,
1697 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1698 .sign = FTR_UNSIGNED,
1699 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1700 .min_field_value = 1,
1701 .matches = has_cpuid_feature,
1702 .cpu_enable = cpu_has_fwb,
1703 },
05abb595
SP		 1704#ifdef CONFIG_ARM64_HW_AFDBM
1705 {
1706 /*
1707 * Since we turn this on always, we don't want the user to
1708 * think that the feature is available when it may not be.
1709 * So hide the description.
1710 *
1711 * .desc = "Hardware pagetable Dirty Bit Management",
1712 *
1713 */
1714 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1715 .capability = ARM64_HW_DBM,
1716 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1717 .sign = FTR_UNSIGNED,
1718 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1719 .min_field_value = 2,
1720 .matches = has_hw_dbm,
1721 .cpu_enable = cpu_enable_hw_dbm,
1722 },
1723#endif
86d0dd34
AB		 1724 {
1725 .desc = "CRC32 instructions",
1726 .capability = ARM64_HAS_CRC32,
1727 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1728 .matches = has_cpuid_feature,
1729 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1730 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1731 .min_field_value = 1,
1732 },
4f9f4964 1733#ifdef CONFIG_ARM64_SSBD
d71be2b6
WD		 1734 {
1735 .desc = "Speculative Store Bypassing Safe (SSBS)",
1736 .capability = ARM64_SSBS,
1737 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1738 .matches = has_cpuid_feature,
1739 .sys_reg = SYS_ID_AA64PFR1_EL1,
1740 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1741 .sign = FTR_UNSIGNED,
1742 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
8f04e8e6 1743 .cpu_enable = cpu_enable_ssbs,
d71be2b6 1744 },
5ffdfaed
VM		 1745#endif
1746#ifdef CONFIG_ARM64_CNP
1747 {
1748 .desc = "Common not Private translations",
1749 .capability = ARM64_HAS_CNP,
1750 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1751 .matches = has_useable_cnp,
1752 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1753 .sign = FTR_UNSIGNED,
1754 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1755 .min_field_value = 1,
1756 .cpu_enable = cpu_enable_cnp,
1757 },
8f04e8e6 1758#endif
bd4fb6d2
WD		 1759 {
1760 .desc = "Speculation barrier (SB)",
1761 .capability = ARM64_HAS_SB,
1762 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1763 .matches = has_cpuid_feature,
1764 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1765 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1766 .sign = FTR_UNSIGNED,
1767 .min_field_value = 1,
1768 },
6984eb47
MR		 1769#ifdef CONFIG_ARM64_PTR_AUTH
1770 {
1771 .desc = "Address authentication (architected algorithm)",
1772 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
6982934e 1773 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
6984eb47
MR		 1774 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1775 .sign = FTR_UNSIGNED,
1776 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1777 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1778 .matches = has_cpuid_feature,
1779 },
1780 {
1781 .desc = "Address authentication (IMP DEF algorithm)",
1782 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
6982934e 1783 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
6984eb47
MR		 1784 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1785 .sign = FTR_UNSIGNED,
1786 .field_pos = ID_AA64ISAR1_API_SHIFT,
1787 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1788 .matches = has_cpuid_feature,
cfef06bd
KM		 1789 },
1790 {
1791 .capability = ARM64_HAS_ADDRESS_AUTH,
6982934e 1792 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
cfef06bd 1793 .matches = has_address_auth,
6984eb47
MR		 1794 },
1795 {
1796 .desc = "Generic authentication (architected algorithm)",
1797 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1798 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1799 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1800 .sign = FTR_UNSIGNED,
1801 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1802 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1803 .matches = has_cpuid_feature,
1804 },
1805 {
1806 .desc = "Generic authentication (IMP DEF algorithm)",
1807 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1808 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1809 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1810 .sign = FTR_UNSIGNED,
1811 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1812 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1813 .matches = has_cpuid_feature,
1814 },
cfef06bd
KM		 1815 {
1816 .capability = ARM64_HAS_GENERIC_AUTH,
1817 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1818 .matches = has_generic_auth,
1819 },
6984eb47 1820#endif /* CONFIG_ARM64_PTR_AUTH */
b90d2b22
JT		 1821#ifdef CONFIG_ARM64_PSEUDO_NMI
1822 {
1823 /*
1824 * Depends on having GICv3
1825 */
1826 .desc = "IRQ priority masking",
1827 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1828 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1829 .matches = can_use_gic_priorities,
1830 .sys_reg = SYS_ID_AA64PFR0_EL1,
1831 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1832 .sign = FTR_UNSIGNED,
1833 .min_field_value = 1,
1834 },
3e6c69a0
MB		 1835#endif
1836#ifdef CONFIG_ARM64_E0PD
1837 {
1838 .desc = "E0PD",
1839 .capability = ARM64_HAS_E0PD,
1840 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1841 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1842 .sign = FTR_UNSIGNED,
1843 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
1844 .matches = has_cpuid_feature,
1845 .min_field_value = 1,
1846 .cpu_enable = cpu_enable_e0pd,
1847 },
bc206065 1848#endif
1a50ec0b
RH		 1849#ifdef CONFIG_ARCH_RANDOM
1850 {
1851 .desc = "Random Number Generator",
1852 .capability = ARM64_HAS_RNG,
1853 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1854 .matches = has_cpuid_feature,
1855 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1856 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
1857 .sign = FTR_UNSIGNED,
1858 .min_field_value = 1,
1859 },
b90d2b22 1860#endif
359b7064
MZ		 1861 {},
1862};
1863
1e013d06
WD		 1864#define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1865 .matches = has_cpuid_feature, \
1866 .sys_reg = reg, \
1867 .field_pos = field, \
1868 .sign = s, \
1869 .min_field_value = min_value,
1870
1871#define __HWCAP_CAP(name, cap_type, cap) \
1872 .desc = name, \
1873 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
1874 .hwcap_type = cap_type, \
1875 .hwcap = cap, \
1876
1877#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
1878 { \
1879 __HWCAP_CAP(#cap, cap_type, cap) \
1880 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
37b01d53
SP		 1881 }
1882
1e013d06
WD		 1883#define HWCAP_MULTI_CAP(list, cap_type, cap) \
1884 { \
1885 __HWCAP_CAP(#cap, cap_type, cap) \
1886 .matches = cpucap_multi_entry_cap_matches, \
1887 .match_list = list, \
1888 }
1889
7559950a
SP		 1890#define HWCAP_CAP_MATCH(match, cap_type, cap) \
1891 { \
1892 __HWCAP_CAP(#cap, cap_type, cap) \
1893 .matches = match, \
1894 }
1895
1e013d06
WD		 1896#ifdef CONFIG_ARM64_PTR_AUTH
1897static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1898 {
1899 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1900 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1901 },
1902 {
1903 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1904 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1905 },
1906 {},
1907};
1908
1909static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1910 {
1911 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1912 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1913 },
1914 {
1915 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1916 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1917 },
1918 {},
1919};
1920#endif
1921
f3efb675 1922static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
aaba098f
AM		 1923 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1924 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1925 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1926 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1927 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1928 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1929 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1930 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1931 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1932 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1933 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1934 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1935 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1936 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
12019374 1937 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1a50ec0b 1938 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
aaba098f
AM		 1939 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1940 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1941 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1942 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1943 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1944 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
671db581 1945 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
aaba098f
AM		 1946 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1947 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1948 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1949 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
ca9503fc 1950 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
aaba098f 1951 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
d4209d8b
SP		 1952 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
1953 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
1954 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
aaba098f 1955 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
43994d82 1956#ifdef CONFIG_ARM64_SVE
aaba098f 1957 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
06a916fe
DM		 1958 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1959 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1960 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1961 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
d4209d8b 1962 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
06a916fe
DM		 1963 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1964 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
d4209d8b
SP		 1965 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
1966 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
1967 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
43994d82 1968#endif
aaba098f 1969 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
75031975 1970#ifdef CONFIG_ARM64_PTR_AUTH
aaba098f
AM		 1971 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1972 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
75031975 1973#endif
75283501
SP		 1974 {},
1975};
1976
7559950a
SP		 1977#ifdef CONFIG_COMPAT
1978static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
1979{
1980 /*
1981 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
1982 * in line with that of arm32 as in vfp_init(). We make sure that the
1983 * check is future proof, by making sure value is non-zero.
1984 */
1985 u32 mvfr1;
1986
1987 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1988 if (scope == SCOPE_SYSTEM)
1989 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
1990 else
1991 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
1992
1993 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
1994 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
1995 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
1996}
1997#endif
1998
75283501 1999static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 2000#ifdef CONFIG_COMPAT
7559950a
SP		 2001 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2002 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2003 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2004 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2005 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
ff96f7bc
SP		 2006 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2007 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2008 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2009 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2010 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 2011#endif
2012 {},
2013};
2014
f3efb675 2015static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 2016{
2017 switch (cap->hwcap_type) {
2018 case CAP_HWCAP:
aaba098f 2019 cpu_set_feature(cap->hwcap);
37b01d53
SP		 2020 break;
2021#ifdef CONFIG_COMPAT
2022 case CAP_COMPAT_HWCAP:
2023 compat_elf_hwcap |= (u32)cap->hwcap;
2024 break;
2025 case CAP_COMPAT_HWCAP2:
2026 compat_elf_hwcap2 |= (u32)cap->hwcap;
2027 break;
2028#endif
2029 default:
2030 WARN_ON(1);
2031 break;
2032 }
2033}
2034
2035/* Check if we have a particular HWCAP enabled */
f3efb675 2036static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 2037{
2038 bool rc;
2039
2040 switch (cap->hwcap_type) {
2041 case CAP_HWCAP:
aaba098f 2042 rc = cpu_have_feature(cap->hwcap);
37b01d53
SP		 2043 break;
2044#ifdef CONFIG_COMPAT
2045 case CAP_COMPAT_HWCAP:
2046 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2047 break;
2048 case CAP_COMPAT_HWCAP2:
2049 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2050 break;
2051#endif
2052 default:
2053 WARN_ON(1);
2054 rc = false;
2055 }
2056
2057 return rc;
2058}
2059
75283501 2060static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 2061{
77c97b4e 2062 /* We support emulation of accesses to CPU ID feature registers */
aaba098f 2063 cpu_set_named_feature(CPUID);
75283501 2064 for (; hwcaps->matches; hwcaps++)
143ba05d 2065 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
75283501 2066 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 2067}
2068
606f8e7b 2069static void update_cpu_capabilities(u16 scope_mask)
67948af4 2070{
606f8e7b 2071 int i;
67948af4
SP		 2072 const struct arm64_cpu_capabilities *caps;
2073
cce360b5 2074 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
606f8e7b
SP		 2075 for (i = 0; i < ARM64_NCAPS; i++) {
2076 caps = cpu_hwcaps_ptrs[i];
2077 if (!caps || !(caps->type & scope_mask) ||
2078 cpus_have_cap(caps->capability) ||
cce360b5 2079 !caps->matches(caps, cpucap_default_scope(caps)))
359b7064
MZ		 2080 continue;
2081
606f8e7b
SP		 2082 if (caps->desc)
2083 pr_info("detected: %s\n", caps->desc);
75283501 2084 cpus_set_cap(caps->capability);
0ceb0d56
DT		 2085
2086 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2087 set_bit(caps->capability, boot_capabilities);
359b7064 2088 }
ce8b602c
SP		 2089}
2090
0b587c84
SP		 2091/*
2092 * Enable all the available capabilities on this CPU. The capabilities
2093 * with BOOT_CPU scope are handled separately and hence skipped here.
2094 */
2095static int cpu_enable_non_boot_scope_capabilities(void *__unused)
ed478b3f 2096{
0b587c84
SP		 2097 int i;
2098 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
ed478b3f 2099
0b587c84
SP		 2100 for_each_available_cap(i) {
2101 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2102
2103 if (WARN_ON(!cap))
2104 continue;
c0cda3b8 2105
0b587c84
SP		 2106 if (!(cap->type & non_boot_scope))
2107 continue;
2108
2109 if (cap->cpu_enable)
2110 cap->cpu_enable(cap);
2111 }
c0cda3b8
DM		 2112 return 0;
2113}
2114
ce8b602c 2115/*
dbb4e152
SP		 2116 * Run through the enabled capabilities and enable() it on all active
2117 * CPUs
ce8b602c 2118 */
0b587c84 2119static void __init enable_cpu_capabilities(u16 scope_mask)
ce8b602c 2120{
0b587c84
SP		 2121 int i;
2122 const struct arm64_cpu_capabilities *caps;
2123 bool boot_scope;
2124
cce360b5 2125 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
0b587c84 2126 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
63a1e1c9 2127
0b587c84
SP		 2128 for (i = 0; i < ARM64_NCAPS; i++) {
2129 unsigned int num;
2130
2131 caps = cpu_hwcaps_ptrs[i];
2132 if (!caps || !(caps->type & scope_mask))
2133 continue;
2134 num = caps->capability;
2135 if (!cpus_have_cap(num))
63a1e1c9
MR		 2136 continue;
2137
2138 /* Ensure cpus_have_const_cap(num) works */
2139 static_branch_enable(&cpu_hwcap_keys[num]);
2140
0b587c84 2141 if (boot_scope && caps->cpu_enable)
2a6dcb2b 2142 /*
fd9d63da
SP		 2143 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2144 * before any secondary CPU boots. Thus, each secondary
2145 * will enable the capability as appropriate via
2146 * check_local_cpu_capabilities(). The only exception is
2147 * the boot CPU, for which the capability must be
2148 * enabled here. This approach avoids costly
2149 * stop_machine() calls for this case.
2a6dcb2b 2150 */
0b587c84 2151 caps->cpu_enable(caps);
63a1e1c9 2152 }
dbb4e152 2153
0b587c84
SP		 2154 /*
2155 * For all non-boot scope capabilities, use stop_machine()
2156 * as it schedules the work allowing us to modify PSTATE,
2157 * instead of on_each_cpu() which uses an IPI, giving us a
2158 * PSTATE that disappears when we return.
2159 */
2160 if (!boot_scope)
2161 stop_machine(cpu_enable_non_boot_scope_capabilities,
2162 NULL, cpu_online_mask);
ed478b3f
SP		 2163}
2164
eaac4d83
SP		 2165/*
2166 * Run through the list of capabilities to check for conflicts.
2167 * If the system has already detected a capability, take necessary
2168 * action on this CPU.
eaac4d83 2169 */
deeaac51 2170static void verify_local_cpu_caps(u16 scope_mask)
eaac4d83 2171{
606f8e7b 2172 int i;
eaac4d83 2173 bool cpu_has_cap, system_has_cap;
606f8e7b 2174 const struct arm64_cpu_capabilities *caps;
eaac4d83 2175
cce360b5
SP		 2176 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2177
606f8e7b
SP		 2178 for (i = 0; i < ARM64_NCAPS; i++) {
2179 caps = cpu_hwcaps_ptrs[i];
2180 if (!caps || !(caps->type & scope_mask))
cce360b5
SP		 2181 continue;
2182
ba7d9233 2183 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
eaac4d83
SP		 2184 system_has_cap = cpus_have_cap(caps->capability);
2185
2186 if (system_has_cap) {
2187 /*
2188 * Check if the new CPU misses an advertised feature,
2189 * which is not safe to miss.
2190 */
2191 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2192 break;
2193 /*
2194 * We have to issue cpu_enable() irrespective of
2195 * whether the CPU has it or not, as it is enabeld
2196 * system wide. It is upto the call back to take
2197 * appropriate action on this CPU.
2198 */
2199 if (caps->cpu_enable)
2200 caps->cpu_enable(caps);
2201 } else {
2202 /*
2203 * Check if the CPU has this capability if it isn't
2204 * safe to have when the system doesn't.
2205 */
2206 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2207 break;
2208 }
2209 }
2210
606f8e7b 2211 if (i < ARM64_NCAPS) {
eaac4d83
SP		 2212 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2213 smp_processor_id(), caps->capability,
2214 caps->desc, system_has_cap, cpu_has_cap);
eaac4d83 2215
deeaac51
KM		 2216 if (cpucap_panic_on_conflict(caps))
2217 cpu_panic_kernel();
2218 else
2219 cpu_die_early();
2220 }
eaac4d83
SP		 2221}
2222
dbb4e152 2223/*
13f417f3
SP		 2224 * Check for CPU features that are used in early boot
2225 * based on the Boot CPU value.
dbb4e152 2226 */
13f417f3 2227static void check_early_cpu_features(void)
dbb4e152 2228{
13f417f3 2229 verify_cpu_asid_bits();
deeaac51
KM		 2230
2231 verify_local_cpu_caps(SCOPE_BOOT_CPU);
dbb4e152 2232}
1c076303 2233
75283501
SP		 2234static void
2235verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2236{
2237
92406f0c
SP		 2238 for (; caps->matches; caps++)
2239 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 2240 pr_crit("CPU%d: missing HWCAP: %s\n",
2241 smp_processor_id(), caps->desc);
2242 cpu_die_early();
2243 }
75283501
SP		 2244}
2245
2e0f2478
DM		 2246static void verify_sve_features(void)
2247{
2248 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2249 u64 zcr = read_zcr_features();
2250
2251 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2252 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2253
2254 if (len < safe_len || sve_verify_vq_map()) {
d06b76be 2255 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2e0f2478
DM		 2256 smp_processor_id());
2257 cpu_die_early();
2258 }
2259
2260 /* Add checks on other ZCR bits here if necessary */
2261}
2262
1e89baed 2263
dbb4e152
SP		 2264/*
2265 * Run through the enabled system capabilities and enable() it on this CPU.
2266 * The capabilities were decided based on the available CPUs at the boot time.
2267 * Any new CPU should match the system wide status of the capability. If the
2268 * new CPU doesn't have a capability which the system now has enabled, we
2269 * cannot do anything to fix it up and could cause unexpected failures. So
2270 * we park the CPU.
2271 */
c47a1900 2272static void verify_local_cpu_capabilities(void)
dbb4e152 2273{
fd9d63da
SP		 2274 /*
2275 * The capabilities with SCOPE_BOOT_CPU are checked from
2276 * check_early_cpu_features(), as they need to be verified
2277 * on all secondary CPUs.
2278 */
deeaac51 2279 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
ed478b3f 2280
c47a1900 2281 verify_local_elf_hwcaps(arm64_elf_hwcaps);
2e0f2478 2282
c47a1900
SP		 2283 if (system_supports_32bit_el0())
2284 verify_local_elf_hwcaps(compat_elf_hwcaps);
2e0f2478
DM		 2285
2286 if (system_supports_sve())
2287 verify_sve_features();
c47a1900 2288}
dbb4e152 2289
c47a1900
SP		 2290void check_local_cpu_capabilities(void)
2291{
2292 /*
2293 * All secondary CPUs should conform to the early CPU features
2294 * in use by the kernel based on boot CPU.
2295 */
13f417f3
SP		 2296 check_early_cpu_features();
2297
dbb4e152 2298 /*
c47a1900 2299 * If we haven't finalised the system capabilities, this CPU gets
fbd890b9 2300 * a chance to update the errata work arounds and local features.
c47a1900
SP		 2301 * Otherwise, this CPU should verify that it has all the system
2302 * advertised capabilities.
dbb4e152 2303 */
b51c6ac2 2304 if (!system_capabilities_finalized())
ed478b3f
SP		 2305 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2306 else
c47a1900 2307 verify_local_cpu_capabilities();
359b7064
MZ		 2308}
2309
fd9d63da
SP		 2310static void __init setup_boot_cpu_capabilities(void)
2311{
2312 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2313 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2314 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2315 enable_cpu_capabilities(SCOPE_BOOT_CPU);
2316}
2317
f7bfc14a 2318bool this_cpu_has_cap(unsigned int n)
8f413758 2319{
f7bfc14a
SP		 2320 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2321 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2322
2323 if (cap)
2324 return cap->matches(cap, SCOPE_LOCAL_CPU);
2325 }
2326
2327 return false;
8f413758
MZ		 2328}
2329
3ff047f6
ADK		 2330/*
2331 * This helper function is used in a narrow window when,
2332 * - The system wide safe registers are set with all the SMP CPUs and,
2333 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2334 * In all other cases cpus_have_{const_}cap() should be used.
2335 */
2336static bool __system_matches_cap(unsigned int n)
2337{
2338 if (n < ARM64_NCAPS) {
2339 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2340
2341 if (cap)
2342 return cap->matches(cap, SCOPE_SYSTEM);
2343 }
2344 return false;
2345}
2346
aec0bff7
AM		 2347void cpu_set_feature(unsigned int num)
2348{
2349 WARN_ON(num >= MAX_CPU_FEATURES);
2350 elf_hwcap |= BIT(num);
2351}
2352EXPORT_SYMBOL_GPL(cpu_set_feature);
2353
2354bool cpu_have_feature(unsigned int num)
2355{
2356 WARN_ON(num >= MAX_CPU_FEATURES);
2357 return elf_hwcap & BIT(num);
2358}
2359EXPORT_SYMBOL_GPL(cpu_have_feature);
2360
2361unsigned long cpu_get_elf_hwcap(void)
2362{
2363 /*
2364 * We currently only populate the first 32 bits of AT_HWCAP. Please
2365 * note that for userspace compatibility we guarantee that bits 62
2366 * and 63 will always be returned as 0.
2367 */
2368 return lower_32_bits(elf_hwcap);
2369}
2370
2371unsigned long cpu_get_elf_hwcap2(void)
2372{
2373 return upper_32_bits(elf_hwcap);
2374}
2375
ed478b3f
SP		 2376static void __init setup_system_capabilities(void)
2377{
2378 /*
2379 * We have finalised the system-wide safe feature
2380 * registers, finalise the capabilities that depend
fd9d63da
SP		 2381 * on it. Also enable all the available capabilities,
2382 * that are not enabled already.
ed478b3f
SP		 2383 */
2384 update_cpu_capabilities(SCOPE_SYSTEM);
fd9d63da 2385 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
ed478b3f
SP		 2386}
2387
9cdf8ec4 2388void __init setup_cpu_features(void)
359b7064 2389{
9cdf8ec4 2390 u32 cwg;
9cdf8ec4 2391
ed478b3f 2392 setup_system_capabilities();
75283501 2393 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 2394
2395 if (system_supports_32bit_el0())
2396 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152 2397
2e6f549f
KC		 2398 if (system_uses_ttbr0_pan())
2399 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2400
2e0f2478 2401 sve_setup();
94b07c1f 2402 minsigstksz_setup();
2e0f2478 2403
dbb4e152 2404 /* Advertise that we have computed the system capabilities */
b51c6ac2 2405 finalize_system_capabilities();
dbb4e152 2406
9cdf8ec4
SP		 2407 /*
2408 * Check for sane CTR_EL0.CWG value.
2409 */
2410 cwg = cache_type_cwg();
9cdf8ec4 2411 if (!cwg)
ebc7e21e
CM		 2412 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2413 ARCH_DMA_MINALIGN);
359b7064 2414}
70544196
JM		 2415
2416static bool __maybe_unused
92406f0c 2417cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196 2418{
3ff047f6 2419 return (__system_matches_cap(ARM64_HAS_PAN) && !__system_matches_cap(ARM64_HAS_UAO));
70544196 2420}
77c97b4e 2421
5ffdfaed
VM		 2422static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2423{
2424 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2425}
2426
77c97b4e
SP		 2427/*
2428 * We emulate only the following system register space.
2429 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2430 * See Table C5-6 System instruction encodings for System register accesses,
2431 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2432 */
2433static inline bool __attribute_const__ is_emulated(u32 id)
2434{
2435 return (sys_reg_Op0(id) == 0x3 &&
2436 sys_reg_CRn(id) == 0x0 &&
2437 sys_reg_Op1(id) == 0x0 &&
2438 (sys_reg_CRm(id) == 0 ||
2439 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2440}
2441
2442/*
2443 * With CRm == 0, reg should be one of :
2444 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2445 */
2446static inline int emulate_id_reg(u32 id, u64 *valp)
2447{
2448 switch (id) {
2449 case SYS_MIDR_EL1:
2450 *valp = read_cpuid_id();
2451 break;
2452 case SYS_MPIDR_EL1:
2453 *valp = SYS_MPIDR_SAFE_VAL;
2454 break;
2455 case SYS_REVIDR_EL1:
2456 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2457 *valp = 0;
2458 break;
2459 default:
2460 return -EINVAL;
2461 }
2462
2463 return 0;
2464}
2465
2466static int emulate_sys_reg(u32 id, u64 *valp)
2467{
2468 struct arm64_ftr_reg *regp;
2469
2470 if (!is_emulated(id))
2471 return -EINVAL;
2472
2473 if (sys_reg_CRm(id) == 0)
2474 return emulate_id_reg(id, valp);
2475
2476 regp = get_arm64_ftr_reg(id);
2477 if (regp)
2478 *valp = arm64_ftr_reg_user_value(regp);
2479 else
2480 /*
2481 * The untracked registers are either IMPLEMENTATION DEFINED
2482 * (e.g, ID_AFR0_EL1) or reserved RAZ.
2483 */
2484 *valp = 0;
2485 return 0;
2486}
2487
520ad988 2488int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
77c97b4e
SP		 2489{
2490 int rc;
77c97b4e
SP		 2491 u64 val;
2492
77c97b4e
SP		 2493 rc = emulate_sys_reg(sys_reg, &val);
2494 if (!rc) {
520ad988 2495 pt_regs_write_reg(regs, rt, val);
6436beee 2496 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
77c97b4e 2497 }
77c97b4e
SP		 2498 return rc;
2499}
2500
520ad988
AK		 2501static int emulate_mrs(struct pt_regs *regs, u32 insn)
2502{
2503 u32 sys_reg, rt;
2504
2505 /*
2506 * sys_reg values are defined as used in mrs/msr instruction.
2507 * shift the imm value to get the encoding.
2508 */
2509 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2510 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2511 return do_emulate_mrs(regs, sys_reg, rt);
2512}
2513
77c97b4e
SP		 2514static struct undef_hook mrs_hook = {
2515 .instr_mask = 0xfff00000,
2516 .instr_val = 0xd5300000,
d64567f6 2517 .pstate_mask = PSR_AA32_MODE_MASK,
77c97b4e
SP		 2518 .pstate_val = PSR_MODE_EL0t,
2519 .fn = emulate_mrs,
2520};
2521
2522static int __init enable_mrs_emulation(void)
2523{
2524 register_undef_hook(&mrs_hook);
2525 return 0;
2526}
2527
c0d8832e 2528core_initcall(enable_mrs_emulation);
1b3ccf4b
JL		 2529
2530ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2531 char *buf)
2532{
2533 if (__meltdown_safe)
2534 return sprintf(buf, "Not affected\n");
2535
2536 if (arm64_kernel_unmapped_at_el0())
2537 return sprintf(buf, "Mitigation: PTI\n");
2538
2539 return sprintf(buf, "Vulnerable\n");
2540}
Linux 6.x block layer and io_uring tree(s)