projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
arm64: daifflags: Include PMR in daifflags restore operations
[linux-2.6-block.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57 21#include <linux/bsearch.h>
2a6dcb2b 22#include <linux/cpumask.h>
5ffdfaed 23#include <linux/crash_dump.h>
3c739b57 24#include <linux/sort.h>
2a6dcb2b 25#include <linux/stop_machine.h>
359b7064 26#include <linux/types.h>
2077be67 27#include <linux/mm.h>
359b7064
MZ		 28#include <asm/cpu.h>
29#include <asm/cpufeature.h>
dbb4e152 30#include <asm/cpu_ops.h>
2e0f2478 31#include <asm/fpsimd.h>
13f417f3 32#include <asm/mmu_context.h>
338d4f49 33#include <asm/processor.h>
cdcf817b 34#include <asm/sysreg.h>
77c97b4e 35#include <asm/traps.h>
d88701be 36#include <asm/virt.h>
359b7064 37
9cdf8ec4
SP		 38unsigned long elf_hwcap __read_mostly;
39EXPORT_SYMBOL_GPL(elf_hwcap);
40
41#ifdef CONFIG_COMPAT
42#define COMPAT_ELF_HWCAP_DEFAULT \
43 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
44 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
45 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
46 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
47 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
48 COMPAT_HWCAP_LPAE)
49unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
50unsigned int compat_elf_hwcap2 __read_mostly;
51#endif
52
53DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
4b65a5db 54EXPORT_SYMBOL(cpu_hwcaps);
82a3a21b 55static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
9cdf8ec4 56
8f1eec57
DM		 57/*
58 * Flag to indicate if we have computed the system wide
59 * capabilities based on the boot time active CPUs. This
60 * will be used to determine if a new booting CPU should
61 * go through the verification process to make sure that it
62 * supports the system capabilities, without using a hotplug
63 * notifier.
64 */
65static bool sys_caps_initialised;
66
67static inline void set_sys_caps_initialised(void)
68{
69 sys_caps_initialised = true;
70}
71
8effeaaf
MR		 72static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
73{
74 /* file-wide pr_fmt adds "CPU features: " prefix */
75 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
76 return 0;
77}
78
79static struct notifier_block cpu_hwcaps_notifier = {
80 .notifier_call = dump_cpu_hwcaps
81};
82
83static int __init register_cpu_hwcaps_dumper(void)
84{
85 atomic_notifier_chain_register(&panic_notifier_list,
86 &cpu_hwcaps_notifier);
87 return 0;
88}
89__initcall(register_cpu_hwcaps_dumper);
90
efd9e03f
CM		 91DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
92EXPORT_SYMBOL(cpu_hwcap_keys);
93
fe4fbdbc 94#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 95 { \
4f0a606b 96 .sign = SIGNED, \
fe4fbdbc 97 .visible = VISIBLE, \
3c739b57
SP		 98 .strict = STRICT, \
99 .type = TYPE, \
100 .shift = SHIFT, \
101 .width = WIDTH, \
102 .safe_val = SAFE_VAL, \
103 }
104
0710cfdb 105/* Define a feature with unsigned values */
fe4fbdbc
SP		 106#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
107 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
4f0a606b 108
0710cfdb 109/* Define a feature with a signed value */
fe4fbdbc
SP		 110#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
111 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
0710cfdb 112
3c739b57
SP		 113#define ARM64_FTR_END \
114 { \
115 .width = 0, \
116 }
117
70544196
JM		 118/* meta feature for alternatives */
119static bool __maybe_unused
92406f0c
SP		 120cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
121
5ffdfaed 122static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
70544196 123
4aa8a472
SP		 124/*
125 * NOTE: Any changes to the visibility of features should be kept in
126 * sync with the documentation of the CPU feature register ABI.
127 */
5e49d73c 128static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
7206dc93 129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
3b3b6810 130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
5bdecb79
SP		 131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
134 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
fe4fbdbc
SP		 136 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
137 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
138 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
139 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
140 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
3c739b57
SP		 141 ARM64_FTR_END,
142};
143
c8c3798d 144static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
bd4fb6d2 145 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
6984eb47
MR		 146 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
147 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
148 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
149 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
5bdecb79
SP		 150 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
151 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
152 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
6984eb47
MR		 153 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
154 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
155 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
156 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
5bdecb79 157 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
c8c3798d
SP		 158 ARM64_FTR_END,
159};
160
5e49d73c 161static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
179a56f6 162 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
0f15adbb 163 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
7206dc93 164 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
3fab3999
DM		 165 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
166 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
64c02720 167 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
5bdecb79 168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
fe4fbdbc
SP		 169 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
170 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57 171 /* Linux doesn't care about the EL3 */
5bdecb79
SP		 172 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
173 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
174 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
175 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
3c739b57
SP		 176 ARM64_FTR_END,
177};
178
d71be2b6
WD		 179static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
181 ARM64_FTR_END,
182};
183
5e49d73c 184static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
5bdecb79
SP		 185 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
186 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
187 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
3c739b57 189 /* Linux shouldn't care about secure memory */
5bdecb79
SP		 190 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
3c739b57
SP		 193 /*
194 * Differing PARange is fine as long as all peripherals and memory are mapped
195 * within the minimum PARange of all CPUs
196 */
fe4fbdbc 197 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 198 ARM64_FTR_END,
199};
200
5e49d73c 201static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
fe4fbdbc 202 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
5bdecb79
SP		 203 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
205 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
206 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
3c739b57
SP		 208 ARM64_FTR_END,
209};
210
5e49d73c 211static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
e48d53a9 212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
7206dc93 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
5bdecb79
SP		 214 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 219 ARM64_FTR_END,
220};
221
5e49d73c 222static const struct arm64_ftr_bits ftr_ctr[] = {
6ae4b6e0
SD		 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0),
227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0),
228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
3c739b57
SP		 229 /*
230 * Linux can handle differing I-cache policies. Userspace JITs will
ee7bc638 231 * make use of *minLine.
155433cb 232 * If we have differing I-cache policies, report it as the weakest - VIPT.
3c739b57 233 */
155433cb 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
4c4a39dd 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
3c739b57
SP		 236 ARM64_FTR_END,
237};
238
675b0563
AB		 239struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
240 .name = "SYS_CTR_EL0",
241 .ftr_bits = ftr_ctr
242};
243
5e49d73c 244static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
5bdecb79
SP		 245 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
fe4fbdbc 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
5bdecb79
SP		 248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
250 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
3c739b57
SP		 253 ARM64_FTR_END,
254};
255
5e49d73c 256static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
fe4fbdbc
SP		 257 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
b20d1ba3
WD		 262 /*
263 * We can instantiate multiple PMU instances with different levels
264 * of support.
fe4fbdbc
SP		 265 */
266 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 269 ARM64_FTR_END,
270};
271
5e49d73c 272static const struct arm64_ftr_bits ftr_mvfr2[] = {
5bdecb79
SP		 273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
274 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
3c739b57
SP		 275 ARM64_FTR_END,
276};
277
5e49d73c 278static const struct arm64_ftr_bits ftr_dczid[] = {
fe4fbdbc
SP		 279 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
3c739b57
SP		 281 ARM64_FTR_END,
282};
283
284
5e49d73c 285static const struct arm64_ftr_bits ftr_id_isar5[] = {
5bdecb79
SP		 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
3c739b57
SP		 292 ARM64_FTR_END,
293};
294
5e49d73c 295static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
5bdecb79 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
3c739b57
SP		 297 ARM64_FTR_END,
298};
299
5e49d73c 300static const struct arm64_ftr_bits ftr_id_pfr0[] = {
5bdecb79
SP		 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
3c739b57
SP		 305 ARM64_FTR_END,
306};
307
5e49d73c 308static const struct arm64_ftr_bits ftr_id_dfr0[] = {
fe4fbdbc
SP		 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
310 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
e5343503
SP		 317 ARM64_FTR_END,
318};
319
2e0f2478
DM		 320static const struct arm64_ftr_bits ftr_zcr[] = {
321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
322 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
323 ARM64_FTR_END,
324};
325
3c739b57
SP		 326/*
327 * Common ftr bits for a 32bit register with all hidden, strict
328 * attributes, with 4bit feature fields and a default safe value of
329 * 0. Covers the following 32bit registers:
330 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
331 */
5e49d73c 332static const struct arm64_ftr_bits ftr_generic_32bits[] = {
fe4fbdbc
SP		 333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
339 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
3c739b57
SP		 341 ARM64_FTR_END,
342};
343
eab43e88
SP		 344/* Table for a single 32bit feature value */
345static const struct arm64_ftr_bits ftr_single32[] = {
fe4fbdbc 346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
3c739b57
SP		 347 ARM64_FTR_END,
348};
349
eab43e88 350static const struct arm64_ftr_bits ftr_raz[] = {
3c739b57
SP		 351 ARM64_FTR_END,
352};
353
6f2b7eef
AB		 354#define ARM64_FTR_REG(id, table) { \
355 .sys_id = id, \
356 .reg = &(struct arm64_ftr_reg){ \
3c739b57
SP		 357 .name = #id, \
358 .ftr_bits = &((table)[0]), \
6f2b7eef 359 }}
3c739b57 360
6f2b7eef
AB		 361static const struct __ftr_reg_entry {
362 u32 sys_id;
363 struct arm64_ftr_reg *reg;
364} arm64_ftr_regs[] = {
3c739b57
SP		 365
366 /* Op1 = 0, CRn = 0, CRm = 1 */
367 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
368 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 369 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 370 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
371 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
372 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
373 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
374
375 /* Op1 = 0, CRn = 0, CRm = 2 */
376 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
377 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
378 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
379 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
380 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
381 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
382 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
383
384 /* Op1 = 0, CRn = 0, CRm = 3 */
385 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
386 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
387 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
388
389 /* Op1 = 0, CRn = 0, CRm = 4 */
390 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
d71be2b6 391 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
2e0f2478 392 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
3c739b57
SP		 393
394 /* Op1 = 0, CRn = 0, CRm = 5 */
395 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
eab43e88 396 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
3c739b57
SP		 397
398 /* Op1 = 0, CRn = 0, CRm = 6 */
399 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
c8c3798d 400 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
3c739b57
SP		 401
402 /* Op1 = 0, CRn = 0, CRm = 7 */
403 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
404 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 405 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57 406
2e0f2478
DM		 407 /* Op1 = 0, CRn = 1, CRm = 2 */
408 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
409
3c739b57 410 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 411 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP		 412 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
413
414 /* Op1 = 3, CRn = 14, CRm = 0 */
eab43e88 415 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
3c739b57
SP		 416};
417
418static int search_cmp_ftr_reg(const void *id, const void *regp)
419{
6f2b7eef 420 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP		 421}
422
423/*
424 * get_arm64_ftr_reg - Lookup a feature register entry using its
425 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
426 * ascending order of sys_id , we use binary search to find a matching
427 * entry.
428 *
429 * returns - Upon success, matching ftr_reg entry for id.
430 * - NULL on failure. It is upto the caller to decide
431 * the impact of a failure.
432 */
433static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
434{
6f2b7eef
AB		 435 const struct __ftr_reg_entry *ret;
436
437 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP		 438 arm64_ftr_regs,
439 ARRAY_SIZE(arm64_ftr_regs),
440 sizeof(arm64_ftr_regs[0]),
441 search_cmp_ftr_reg);
6f2b7eef
AB		 442 if (ret)
443 return ret->reg;
444 return NULL;
3c739b57
SP		 445}
446
5e49d73c
AB		 447static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
448 s64 ftr_val)
3c739b57
SP		 449{
450 u64 mask = arm64_ftr_mask(ftrp);
451
452 reg &= ~mask;
453 reg |= (ftr_val << ftrp->shift) & mask;
454 return reg;
455}
456
5e49d73c
AB		 457static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
458 s64 cur)
3c739b57
SP		 459{
460 s64 ret = 0;
461
462 switch (ftrp->type) {
463 case FTR_EXACT:
464 ret = ftrp->safe_val;
465 break;
466 case FTR_LOWER_SAFE:
467 ret = new < cur ? new : cur;
468 break;
469 case FTR_HIGHER_SAFE:
470 ret = new > cur ? new : cur;
471 break;
472 default:
473 BUG();
474 }
475
476 return ret;
477}
478
3c739b57
SP		 479static void __init sort_ftr_regs(void)
480{
6f2b7eef
AB		 481 int i;
482
483 /* Check that the array is sorted so that we can do the binary search */
484 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
485 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP		 486}
487
488/*
489 * Initialise the CPU feature register from Boot CPU values.
490 * Also initiliases the strict_mask for the register.
b389d799
MR		 491 * Any bits that are not covered by an arm64_ftr_bits entry are considered
492 * RES0 for the system-wide value, and must strictly match.
3c739b57
SP		 493 */
494static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
495{
496 u64 val = 0;
497 u64 strict_mask = ~0x0ULL;
fe4fbdbc 498 u64 user_mask = 0;
b389d799
MR		 499 u64 valid_mask = 0;
500
5e49d73c 501 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 502 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
503
504 BUG_ON(!reg);
505
506 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
b389d799 507 u64 ftr_mask = arm64_ftr_mask(ftrp);
3c739b57
SP		 508 s64 ftr_new = arm64_ftr_value(ftrp, new);
509
510 val = arm64_ftr_set_value(ftrp, val, ftr_new);
b389d799
MR		 511
512 valid_mask |= ftr_mask;
3c739b57 513 if (!ftrp->strict)
b389d799 514 strict_mask &= ~ftr_mask;
fe4fbdbc
SP		 515 if (ftrp->visible)
516 user_mask |= ftr_mask;
517 else
518 reg->user_val = arm64_ftr_set_value(ftrp,
519 reg->user_val,
520 ftrp->safe_val);
3c739b57 521 }
b389d799
MR		 522
523 val &= valid_mask;
524
3c739b57
SP		 525 reg->sys_val = val;
526 reg->strict_mask = strict_mask;
fe4fbdbc 527 reg->user_mask = user_mask;
3c739b57
SP		 528}
529
1e89baed 530extern const struct arm64_cpu_capabilities arm64_errata[];
82a3a21b
SP		 531static const struct arm64_cpu_capabilities arm64_features[];
532
533static void __init
534init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
535{
536 for (; caps->matches; caps++) {
537 if (WARN(caps->capability >= ARM64_NCAPS,
538 "Invalid capability %d\n", caps->capability))
539 continue;
540 if (WARN(cpu_hwcaps_ptrs[caps->capability],
541 "Duplicate entry for capability %d\n",
542 caps->capability))
543 continue;
544 cpu_hwcaps_ptrs[caps->capability] = caps;
545 }
546}
547
548static void __init init_cpu_hwcaps_indirect_list(void)
549{
550 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
551 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
552}
553
fd9d63da 554static void __init setup_boot_cpu_capabilities(void);
1e89baed 555
3c739b57
SP		 556void __init init_cpu_features(struct cpuinfo_arm64 *info)
557{
558 /* Before we start using the tables, make sure it is sorted */
559 sort_ftr_regs();
560
561 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
562 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
563 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
564 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
565 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
566 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
567 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
568 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
569 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 570 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 571 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
572 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
2e0f2478 573 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
a6dc3cd7
SP		 574
575 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
576 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
577 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
578 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
579 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
580 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
581 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
582 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
583 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
584 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
585 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
586 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
587 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
588 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
589 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
590 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
591 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
592 }
593
2e0f2478
DM		 594 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
595 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
596 sve_init_vq_map();
597 }
5e91107b 598
82a3a21b
SP		 599 /*
600 * Initialize the indirect array of CPU hwcaps capabilities pointers
601 * before we handle the boot CPU below.
602 */
603 init_cpu_hwcaps_indirect_list();
604
5e91107b 605 /*
fd9d63da
SP		 606 * Detect and enable early CPU capabilities based on the boot CPU,
607 * after we have initialised the CPU feature infrastructure.
5e91107b 608 */
fd9d63da 609 setup_boot_cpu_capabilities();
3c739b57
SP		 610}
611
3086d391 612static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 613{
5e49d73c 614 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 615
616 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
617 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
618 s64 ftr_new = arm64_ftr_value(ftrp, new);
619
620 if (ftr_cur == ftr_new)
621 continue;
622 /* Find a safe value */
623 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
624 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
625 }
626
627}
628
3086d391 629static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 630{
3086d391
SP		 631 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
632
633 BUG_ON(!regp);
634 update_cpu_ftr_reg(regp, val);
635 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
636 return 0;
637 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
638 regp->name, boot, cpu, val);
639 return 1;
640}
641
642/*
643 * Update system wide CPU feature registers with the values from a
644 * non-boot CPU. Also performs SANITY checks to make sure that there
645 * aren't any insane variations from that of the boot CPU.
646 */
647void update_cpu_features(int cpu,
648 struct cpuinfo_arm64 *info,
649 struct cpuinfo_arm64 *boot)
650{
651 int taint = 0;
652
653 /*
654 * The kernel can handle differing I-cache policies, but otherwise
655 * caches should look identical. Userspace JITs will make use of
656 * *minLine.
657 */
658 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
659 info->reg_ctr, boot->reg_ctr);
660
661 /*
662 * Userspace may perform DC ZVA instructions. Mismatched block sizes
663 * could result in too much or too little memory being zeroed if a
664 * process is preempted and migrated between CPUs.
665 */
666 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
667 info->reg_dczid, boot->reg_dczid);
668
669 /* If different, timekeeping will be broken (especially with KVM) */
670 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
671 info->reg_cntfrq, boot->reg_cntfrq);
672
673 /*
674 * The kernel uses self-hosted debug features and expects CPUs to
675 * support identical debug features. We presently need CTX_CMPs, WRPs,
676 * and BRPs to be identical.
677 * ID_AA64DFR1 is currently RES0.
678 */
679 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
680 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
681 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
682 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
683 /*
684 * Even in big.LITTLE, processors should be identical instruction-set
685 * wise.
686 */
687 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
688 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
689 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
690 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
691
692 /*
693 * Differing PARange support is fine as long as all peripherals and
694 * memory are mapped within the minimum PARange of all CPUs.
695 * Linux should not care about secure memory.
696 */
697 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
698 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
699 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
700 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 701 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
702 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 703
704 /*
705 * EL3 is not our concern.
3086d391
SP		 706 */
707 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
708 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
709 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
710 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
711
2e0f2478
DM		 712 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
713 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
714
3086d391 715 /*
a6dc3cd7
SP		 716 * If we have AArch32, we care about 32-bit features for compat.
717 * If the system doesn't support AArch32, don't update them.
3086d391 718 */
46823dd1 719 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
a6dc3cd7
SP		 720 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
721
722 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
3086d391 723 info->reg_id_dfr0, boot->reg_id_dfr0);
a6dc3cd7 724 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
3086d391 725 info->reg_id_isar0, boot->reg_id_isar0);
a6dc3cd7 726 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
3086d391 727 info->reg_id_isar1, boot->reg_id_isar1);
a6dc3cd7 728 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
3086d391 729 info->reg_id_isar2, boot->reg_id_isar2);
a6dc3cd7 730 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
3086d391 731 info->reg_id_isar3, boot->reg_id_isar3);
a6dc3cd7 732 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
3086d391 733 info->reg_id_isar4, boot->reg_id_isar4);
a6dc3cd7 734 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
3086d391
SP		 735 info->reg_id_isar5, boot->reg_id_isar5);
736
a6dc3cd7
SP		 737 /*
738 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
739 * ACTLR formats could differ across CPUs and therefore would have to
740 * be trapped for virtualization anyway.
741 */
742 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
3086d391 743 info->reg_id_mmfr0, boot->reg_id_mmfr0);
a6dc3cd7 744 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
3086d391 745 info->reg_id_mmfr1, boot->reg_id_mmfr1);
a6dc3cd7 746 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
3086d391 747 info->reg_id_mmfr2, boot->reg_id_mmfr2);
a6dc3cd7 748 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
3086d391 749 info->reg_id_mmfr3, boot->reg_id_mmfr3);
a6dc3cd7 750 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
3086d391 751 info->reg_id_pfr0, boot->reg_id_pfr0);
a6dc3cd7 752 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
3086d391 753 info->reg_id_pfr1, boot->reg_id_pfr1);
a6dc3cd7 754 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
3086d391 755 info->reg_mvfr0, boot->reg_mvfr0);
a6dc3cd7 756 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
3086d391 757 info->reg_mvfr1, boot->reg_mvfr1);
a6dc3cd7 758 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
3086d391 759 info->reg_mvfr2, boot->reg_mvfr2);
a6dc3cd7 760 }
3086d391 761
2e0f2478
DM		 762 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
763 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
764 info->reg_zcr, boot->reg_zcr);
765
766 /* Probe vector lengths, unless we already gave up on SVE */
767 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
768 !sys_caps_initialised)
769 sve_update_vq_map();
770 }
771
3086d391
SP		 772 /*
773 * Mismatched CPU features are a recipe for disaster. Don't even
774 * pretend to support them.
775 */
8dd0ee65
WD		 776 if (taint) {
777 pr_warn_once("Unsupported CPU feature variation detected.\n");
778 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
779 }
cdcf817b
SP		 780}
781
46823dd1 782u64 read_sanitised_ftr_reg(u32 id)
b3f15378
SP		 783{
784 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
785
786 /* We shouldn't get a request for an unsupported register */
787 BUG_ON(!regp);
788 return regp->sys_val;
789}
359b7064 790
965861d6
MR		 791#define read_sysreg_case(r) \
792 case r: return read_sysreg_s(r)
793
92406f0c 794/*
46823dd1 795 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
92406f0c
SP		 796 * Read the system register on the current CPU
797 */
46823dd1 798static u64 __read_sysreg_by_encoding(u32 sys_id)
92406f0c
SP		 799{
800 switch (sys_id) {
965861d6
MR		 801 read_sysreg_case(SYS_ID_PFR0_EL1);
802 read_sysreg_case(SYS_ID_PFR1_EL1);
803 read_sysreg_case(SYS_ID_DFR0_EL1);
804 read_sysreg_case(SYS_ID_MMFR0_EL1);
805 read_sysreg_case(SYS_ID_MMFR1_EL1);
806 read_sysreg_case(SYS_ID_MMFR2_EL1);
807 read_sysreg_case(SYS_ID_MMFR3_EL1);
808 read_sysreg_case(SYS_ID_ISAR0_EL1);
809 read_sysreg_case(SYS_ID_ISAR1_EL1);
810 read_sysreg_case(SYS_ID_ISAR2_EL1);
811 read_sysreg_case(SYS_ID_ISAR3_EL1);
812 read_sysreg_case(SYS_ID_ISAR4_EL1);
813 read_sysreg_case(SYS_ID_ISAR5_EL1);
814 read_sysreg_case(SYS_MVFR0_EL1);
815 read_sysreg_case(SYS_MVFR1_EL1);
816 read_sysreg_case(SYS_MVFR2_EL1);
817
818 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
819 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
820 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
821 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
822 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
823 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
824 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
825 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
826 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
827
828 read_sysreg_case(SYS_CNTFRQ_EL0);
829 read_sysreg_case(SYS_CTR_EL0);
830 read_sysreg_case(SYS_DCZID_EL0);
831
92406f0c
SP		 832 default:
833 BUG();
834 return 0;
835 }
836}
837
963fcd40
MZ		 838#include <linux/irqchip/arm-gic-v3.h>
839
18ffa046
JM		 840static bool
841feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
842{
28c5dcb2 843 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 844
845 return val >= entry->min_field_value;
846}
847
da8d02d1 848static bool
92406f0c 849has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 850{
851 u64 val;
94a9e04a 852
92406f0c
SP		 853 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
854 if (scope == SCOPE_SYSTEM)
46823dd1 855 val = read_sanitised_ftr_reg(entry->sys_reg);
92406f0c 856 else
46823dd1 857 val = __read_sysreg_by_encoding(entry->sys_reg);
92406f0c 858
da8d02d1
SP		 859 return feature_matches(val, entry);
860}
338d4f49 861
92406f0c 862static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 863{
864 bool has_sre;
865
92406f0c 866 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 867 return false;
868
869 has_sre = gic_enable_sre();
870 if (!has_sre)
871 pr_warn_once("%s present but disabled by higher exception level\n",
872 entry->desc);
873
874 return has_sre;
875}
876
92406f0c 877static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 878{
879 u32 midr = read_cpuid_id();
d5370f75
WD		 880
881 /* Cavium ThunderX pass 1.x and 2.x */
fa5ce3d1
RR		 882 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
883 MIDR_CPU_VAR_REV(0, 0),
884 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
d5370f75
WD		 885}
886
82e0191a
SP		 887static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
888{
46823dd1 889 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
82e0191a
SP		 890
891 return cpuid_feature_extract_signed_field(pfr0,
892 ID_AA64PFR0_FP_SHIFT) < 0;
893}
894
6ae4b6e0 895static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
8ab66cbe 896 int scope)
6ae4b6e0 897{
8ab66cbe
SP		 898 u64 ctr;
899
900 if (scope == SCOPE_SYSTEM)
901 ctr = arm64_ftr_reg_ctrel0.sys_val;
902 else
1602df02 903 ctr = read_cpuid_effective_cachetype();
8ab66cbe
SP		 904
905 return ctr & BIT(CTR_IDC_SHIFT);
6ae4b6e0
SD		 906}
907
1602df02
SP		 908static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
909{
910 /*
911 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
912 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
913 * to the CTR_EL0 on this CPU and emulate it with the real/safe
914 * value.
915 */
916 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
917 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
918}
919
6ae4b6e0 920static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
8ab66cbe 921 int scope)
6ae4b6e0 922{
8ab66cbe
SP		 923 u64 ctr;
924
925 if (scope == SCOPE_SYSTEM)
926 ctr = arm64_ftr_reg_ctrel0.sys_val;
927 else
928 ctr = read_cpuid_cachetype();
929
930 return ctr & BIT(CTR_DIC_SHIFT);
6ae4b6e0
SD		 931}
932
5ffdfaed
VM		 933static bool __maybe_unused
934has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
935{
936 /*
937 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
938 * may share TLB entries with a CPU stuck in the crashed
939 * kernel.
940 */
941 if (is_kdump_kernel())
942 return false;
943
944 return has_cpuid_feature(entry, scope);
945}
946
ea1e3de8
WD		 947#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
948static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
949
950static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
d3aec8a2 951 int scope)
ea1e3de8 952{
be5b2998
SP		 953 /* List of CPUs that are not vulnerable and don't need KPTI */
954 static const struct midr_range kpti_safe_list[] = {
955 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
956 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
2a355ec2
WD		 957 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
958 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
959 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
960 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
961 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
962 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
71c751f2 963 { /* sentinel */ }
be5b2998 964 };
6dc52b15 965 char const *str = "command line option";
179a56f6 966
6dc52b15
MZ		 967 /*
968 * For reasons that aren't entirely clear, enabling KPTI on Cavium
969 * ThunderX leads to apparent I-cache corruption of kernel text, which
970 * ends as well as you might imagine. Don't even try.
971 */
972 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
973 str = "ARM64_WORKAROUND_CAVIUM_27456";
974 __kpti_forced = -1;
975 }
976
977 /* Forced? */
ea1e3de8 978 if (__kpti_forced) {
6dc52b15
MZ		 979 pr_info_once("kernel page table isolation forced %s by %s\n",
980 __kpti_forced > 0 ? "ON" : "OFF", str);
ea1e3de8
WD		 981 return __kpti_forced > 0;
982 }
983
984 /* Useful for KASLR robustness */
985 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
b89d82ef 986 return kaslr_offset() > 0;
ea1e3de8 987
0ba2e29c 988 /* Don't force KPTI for CPUs that are not vulnerable */
be5b2998 989 if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list))
0ba2e29c 990 return false;
0ba2e29c 991
179a56f6 992 /* Defer to CPU feature registers */
d3aec8a2 993 return !has_cpuid_feature(entry, scope);
ea1e3de8
WD		 994}
995
c0cda3b8
DM		 996static void
997kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
f992b4df
WD		 998{
999 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1000 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1001 kpti_remap_fn *remap_fn;
1002
1003 static bool kpti_applied = false;
1004 int cpu = smp_processor_id();
1005
b89d82ef
WD		 1006 /*
1007 * We don't need to rewrite the page-tables if either we've done
1008 * it already or we have KASLR enabled and therefore have not
1009 * created any global mappings at all.
1010 */
1011 if (kpti_applied || kaslr_offset() > 0)
c0cda3b8 1012 return;
f992b4df
WD		 1013
1014 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1015
1016 cpu_install_idmap();
1017 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1018 cpu_uninstall_idmap();
1019
1020 if (!cpu)
1021 kpti_applied = true;
1022
c0cda3b8 1023 return;
f992b4df
WD		 1024}
1025
ea1e3de8
WD		 1026static int __init parse_kpti(char *str)
1027{
1028 bool enabled;
1029 int ret = strtobool(str, &enabled);
1030
1031 if (ret)
1032 return ret;
1033
1034 __kpti_forced = enabled ? 1 : -1;
1035 return 0;
1036}
b5b7dd64 1037early_param("kpti", parse_kpti);
ea1e3de8
WD		 1038#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1039
05abb595
SP		 1040#ifdef CONFIG_ARM64_HW_AFDBM
1041static inline void __cpu_enable_hw_dbm(void)
1042{
1043 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1044
1045 write_sysreg(tcr, tcr_el1);
1046 isb();
1047}
1048
ece1397c
SP		 1049static bool cpu_has_broken_dbm(void)
1050{
1051 /* List of CPUs which have broken DBM support. */
1052 static const struct midr_range cpus[] = {
1053#ifdef CONFIG_ARM64_ERRATUM_1024718
1054 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
1055#endif
1056 {},
1057 };
1058
1059 return is_midr_in_range_list(read_cpuid_id(), cpus);
1060}
1061
05abb595
SP		 1062static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1063{
ece1397c
SP		 1064 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1065 !cpu_has_broken_dbm();
05abb595
SP		 1066}
1067
1068static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1069{
1070 if (cpu_can_use_dbm(cap))
1071 __cpu_enable_hw_dbm();
1072}
1073
1074static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1075 int __unused)
1076{
1077 static bool detected = false;
1078 /*
1079 * DBM is a non-conflicting feature. i.e, the kernel can safely
1080 * run a mix of CPUs with and without the feature. So, we
1081 * unconditionally enable the capability to allow any late CPU
1082 * to use the feature. We only enable the control bits on the
1083 * CPU, if it actually supports.
1084 *
1085 * We have to make sure we print the "feature" detection only
1086 * when at least one CPU actually uses it. So check if this CPU
1087 * can actually use it and print the message exactly once.
1088 *
1089 * This is safe as all CPUs (including secondary CPUs - due to the
1090 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1091 * goes through the "matches" check exactly once. Also if a CPU
1092 * matches the criteria, it is guaranteed that the CPU will turn
1093 * the DBM on, as the capability is unconditionally enabled.
1094 */
1095 if (!detected && cpu_can_use_dbm(cap)) {
1096 detected = true;
1097 pr_info("detected: Hardware dirty bit management\n");
1098 }
1099
1100 return true;
1101}
1102
1103#endif
1104
12eb3691
WD		 1105#ifdef CONFIG_ARM64_VHE
1106static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1107{
1108 return is_kernel_in_hyp_mode();
1109}
1110
c0cda3b8 1111static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
6d99b689
JM		 1112{
1113 /*
1114 * Copy register values that aren't redirected by hardware.
1115 *
1116 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1117 * this value to tpidr_el2 before we patch the code. Once we've done
1118 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1119 * do anything here.
1120 */
1121 if (!alternatives_applied)
1122 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
6d99b689 1123}
12eb3691 1124#endif
6d99b689 1125
e48d53a9
MZ		 1126static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1127{
1128 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1129
1130 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1131 WARN_ON(val & (7 << 27 | 7 << 21));
1132}
1133
8f04e8e6
WD		 1134#ifdef CONFIG_ARM64_SSBD
1135static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1136{
1137 if (user_mode(regs))
1138 return 1;
1139
74e24828 1140 if (instr & BIT(PSTATE_Imm_shift))
8f04e8e6
WD		 1141 regs->pstate |= PSR_SSBS_BIT;
1142 else
1143 regs->pstate &= ~PSR_SSBS_BIT;
1144
1145 arm64_skip_faulting_instruction(regs, 4);
1146 return 0;
1147}
1148
1149static struct undef_hook ssbs_emulation_hook = {
74e24828
SP		 1150 .instr_mask = ~(1U << PSTATE_Imm_shift),
1151 .instr_val = 0xd500401f | PSTATE_SSBS,
8f04e8e6
WD		 1152 .fn = ssbs_emulation_handler,
1153};
1154
1155static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1156{
1157 static bool undef_hook_registered = false;
1158 static DEFINE_SPINLOCK(hook_lock);
1159
1160 spin_lock(&hook_lock);
1161 if (!undef_hook_registered) {
1162 register_undef_hook(&ssbs_emulation_hook);
1163 undef_hook_registered = true;
1164 }
1165 spin_unlock(&hook_lock);
1166
1167 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1168 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1169 arm64_set_ssbd_mitigation(false);
1170 } else {
1171 arm64_set_ssbd_mitigation(true);
1172 }
1173}
1174#endif /* CONFIG_ARM64_SSBD */
1175
b8925ee2
WD		 1176#ifdef CONFIG_ARM64_PAN
1177static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1178{
1179 /*
1180 * We modify PSTATE. This won't work from irq context as the PSTATE
1181 * is discarded once we return from the exception.
1182 */
1183 WARN_ON_ONCE(in_interrupt());
1184
1185 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1186 asm(SET_PSTATE_PAN(1));
1187}
1188#endif /* CONFIG_ARM64_PAN */
1189
1190#ifdef CONFIG_ARM64_RAS_EXTN
1191static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1192{
1193 /* Firmware may have left a deferred SError in this register. */
1194 write_sysreg_s(0, SYS_DISR_EL1);
1195}
1196#endif /* CONFIG_ARM64_RAS_EXTN */
1197
6984eb47 1198#ifdef CONFIG_ARM64_PTR_AUTH
75031975
MR		 1199static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1200{
1201 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1202 SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1203}
6984eb47
MR		 1204#endif /* CONFIG_ARM64_PTR_AUTH */
1205
b90d2b22
JT		 1206#ifdef CONFIG_ARM64_PSEUDO_NMI
1207static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1208 int scope)
1209{
1210 return false;
1211}
1212#endif
1213
359b7064 1214static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 1215 {
1216 .desc = "GIC system register CPU interface",
1217 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
c9bfdf73 1218 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
963fcd40 1219 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 1220 .sys_reg = SYS_ID_AA64PFR0_EL1,
1221 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 1222 .sign = FTR_UNSIGNED,
18ffa046 1223 .min_field_value = 1,
94a9e04a 1224 },
338d4f49
JM		 1225#ifdef CONFIG_ARM64_PAN
1226 {
1227 .desc = "Privileged Access Never",
1228 .capability = ARM64_HAS_PAN,
5b4747c5 1229 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1230 .matches = has_cpuid_feature,
1231 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1232 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 1233 .sign = FTR_UNSIGNED,
338d4f49 1234 .min_field_value = 1,
c0cda3b8 1235 .cpu_enable = cpu_enable_pan,
338d4f49
JM		 1236 },
1237#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 1238#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1239 {
1240 .desc = "LSE atomic instructions",
1241 .capability = ARM64_HAS_LSE_ATOMICS,
5b4747c5 1242 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
da8d02d1
SP		 1243 .matches = has_cpuid_feature,
1244 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1245 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 1246 .sign = FTR_UNSIGNED,
2e94da13
WD		 1247 .min_field_value = 2,
1248 },
1249#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 1250 {
1251 .desc = "Software prefetching using PRFM",
1252 .capability = ARM64_HAS_NO_HW_PREFETCH,
5c137714 1253 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
d5370f75
WD		 1254 .matches = has_no_hw_prefetch,
1255 },
57f4959b
JM		 1256#ifdef CONFIG_ARM64_UAO
1257 {
1258 .desc = "User Access Override",
1259 .capability = ARM64_HAS_UAO,
5b4747c5 1260 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
57f4959b
JM		 1261 .matches = has_cpuid_feature,
1262 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1263 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1264 .min_field_value = 1,
c8b06e3f
JM		 1265 /*
1266 * We rely on stop_machine() calling uao_thread_switch() to set
1267 * UAO immediately after patching.
1268 */
57f4959b
JM		 1269 },
1270#endif /* CONFIG_ARM64_UAO */
70544196
JM		 1271#ifdef CONFIG_ARM64_PAN
1272 {
1273 .capability = ARM64_ALT_PAN_NOT_UAO,
5b4747c5 1274 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
70544196
JM		 1275 .matches = cpufeature_pan_not_uao,
1276 },
1277#endif /* CONFIG_ARM64_PAN */
830dcc9f 1278#ifdef CONFIG_ARM64_VHE
d88701be
MZ		 1279 {
1280 .desc = "Virtualization Host Extensions",
1281 .capability = ARM64_HAS_VIRT_HOST_EXTN,
830dcc9f 1282 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
d88701be 1283 .matches = runs_at_el2,
c0cda3b8 1284 .cpu_enable = cpu_copy_el2regs,
d88701be 1285 },
830dcc9f 1286#endif /* CONFIG_ARM64_VHE */
042446a3
SP		 1287 {
1288 .desc = "32-bit EL0 Support",
1289 .capability = ARM64_HAS_32BIT_EL0,
5b4747c5 1290 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
042446a3
SP		 1291 .matches = has_cpuid_feature,
1292 .sys_reg = SYS_ID_AA64PFR0_EL1,
1293 .sign = FTR_UNSIGNED,
1294 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1295 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1296 },
ea1e3de8
WD		 1297#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1298 {
179a56f6 1299 .desc = "Kernel page table isolation (KPTI)",
ea1e3de8 1300 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
d3aec8a2
SP		 1301 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1302 /*
1303 * The ID feature fields below are used to indicate that
1304 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1305 * more details.
1306 */
1307 .sys_reg = SYS_ID_AA64PFR0_EL1,
1308 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1309 .min_field_value = 1,
ea1e3de8 1310 .matches = unmap_kernel_at_el0,
c0cda3b8 1311 .cpu_enable = kpti_install_ng_mappings,
ea1e3de8
WD		 1312 },
1313#endif
82e0191a
SP		 1314 {
1315 /* FP/SIMD is not implemented */
1316 .capability = ARM64_HAS_NO_FPSIMD,
5b4747c5 1317 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
82e0191a
SP		 1318 .min_field_value = 0,
1319 .matches = has_no_fpsimd,
1320 },
d50e071f
RM		 1321#ifdef CONFIG_ARM64_PMEM
1322 {
1323 .desc = "Data cache clean to Point of Persistence",
1324 .capability = ARM64_HAS_DCPOP,
5b4747c5 1325 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
d50e071f
RM		 1326 .matches = has_cpuid_feature,
1327 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1328 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1329 .min_field_value = 1,
1330 },
1331#endif
43994d82
DM		 1332#ifdef CONFIG_ARM64_SVE
1333 {
1334 .desc = "Scalable Vector Extension",
5b4747c5 1335 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
43994d82 1336 .capability = ARM64_SVE,
43994d82
DM		 1337 .sys_reg = SYS_ID_AA64PFR0_EL1,
1338 .sign = FTR_UNSIGNED,
1339 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1340 .min_field_value = ID_AA64PFR0_SVE,
1341 .matches = has_cpuid_feature,
c0cda3b8 1342 .cpu_enable = sve_kernel_enable,
43994d82
DM		 1343 },
1344#endif /* CONFIG_ARM64_SVE */
64c02720
XX		 1345#ifdef CONFIG_ARM64_RAS_EXTN
1346 {
1347 .desc = "RAS Extension Support",
1348 .capability = ARM64_HAS_RAS_EXTN,
5b4747c5 1349 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
64c02720
XX		 1350 .matches = has_cpuid_feature,
1351 .sys_reg = SYS_ID_AA64PFR0_EL1,
1352 .sign = FTR_UNSIGNED,
1353 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1354 .min_field_value = ID_AA64PFR0_RAS_V1,
c0cda3b8 1355 .cpu_enable = cpu_clear_disr,
64c02720
XX		 1356 },
1357#endif /* CONFIG_ARM64_RAS_EXTN */
6ae4b6e0
SD		 1358 {
1359 .desc = "Data cache clean to the PoU not required for I/D coherence",
1360 .capability = ARM64_HAS_CACHE_IDC,
5b4747c5 1361 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0 1362 .matches = has_cache_idc,
1602df02 1363 .cpu_enable = cpu_emulate_effective_ctr,
6ae4b6e0
SD		 1364 },
1365 {
1366 .desc = "Instruction cache invalidation not required for I/D coherence",
1367 .capability = ARM64_HAS_CACHE_DIC,
5b4747c5 1368 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
6ae4b6e0
SD		 1369 .matches = has_cache_dic,
1370 },
e48d53a9
MZ		 1371 {
1372 .desc = "Stage-2 Force Write-Back",
1373 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1374 .capability = ARM64_HAS_STAGE2_FWB,
1375 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1376 .sign = FTR_UNSIGNED,
1377 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1378 .min_field_value = 1,
1379 .matches = has_cpuid_feature,
1380 .cpu_enable = cpu_has_fwb,
1381 },
05abb595
SP		 1382#ifdef CONFIG_ARM64_HW_AFDBM
1383 {
1384 /*
1385 * Since we turn this on always, we don't want the user to
1386 * think that the feature is available when it may not be.
1387 * So hide the description.
1388 *
1389 * .desc = "Hardware pagetable Dirty Bit Management",
1390 *
1391 */
1392 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1393 .capability = ARM64_HW_DBM,
1394 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1395 .sign = FTR_UNSIGNED,
1396 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1397 .min_field_value = 2,
1398 .matches = has_hw_dbm,
1399 .cpu_enable = cpu_enable_hw_dbm,
1400 },
1401#endif
86d0dd34
AB		 1402 {
1403 .desc = "CRC32 instructions",
1404 .capability = ARM64_HAS_CRC32,
1405 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1406 .matches = has_cpuid_feature,
1407 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1408 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1409 .min_field_value = 1,
1410 },
4f9f4964 1411#ifdef CONFIG_ARM64_SSBD
d71be2b6
WD		 1412 {
1413 .desc = "Speculative Store Bypassing Safe (SSBS)",
1414 .capability = ARM64_SSBS,
1415 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1416 .matches = has_cpuid_feature,
1417 .sys_reg = SYS_ID_AA64PFR1_EL1,
1418 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1419 .sign = FTR_UNSIGNED,
1420 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
8f04e8e6 1421 .cpu_enable = cpu_enable_ssbs,
d71be2b6 1422 },
5ffdfaed
VM		 1423#endif
1424#ifdef CONFIG_ARM64_CNP
1425 {
1426 .desc = "Common not Private translations",
1427 .capability = ARM64_HAS_CNP,
1428 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1429 .matches = has_useable_cnp,
1430 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1431 .sign = FTR_UNSIGNED,
1432 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1433 .min_field_value = 1,
1434 .cpu_enable = cpu_enable_cnp,
1435 },
8f04e8e6 1436#endif
bd4fb6d2
WD		 1437 {
1438 .desc = "Speculation barrier (SB)",
1439 .capability = ARM64_HAS_SB,
1440 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1441 .matches = has_cpuid_feature,
1442 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1443 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1444 .sign = FTR_UNSIGNED,
1445 .min_field_value = 1,
1446 },
6984eb47
MR		 1447#ifdef CONFIG_ARM64_PTR_AUTH
1448 {
1449 .desc = "Address authentication (architected algorithm)",
1450 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1451 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1452 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1453 .sign = FTR_UNSIGNED,
1454 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1455 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1456 .matches = has_cpuid_feature,
a56005d3 1457 .cpu_enable = cpu_enable_address_auth,
6984eb47
MR		 1458 },
1459 {
1460 .desc = "Address authentication (IMP DEF algorithm)",
1461 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1462 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1463 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1464 .sign = FTR_UNSIGNED,
1465 .field_pos = ID_AA64ISAR1_API_SHIFT,
1466 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1467 .matches = has_cpuid_feature,
75031975 1468 .cpu_enable = cpu_enable_address_auth,
6984eb47
MR		 1469 },
1470 {
1471 .desc = "Generic authentication (architected algorithm)",
1472 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1473 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1474 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1475 .sign = FTR_UNSIGNED,
1476 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1477 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1478 .matches = has_cpuid_feature,
1479 },
1480 {
1481 .desc = "Generic authentication (IMP DEF algorithm)",
1482 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1483 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1484 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1485 .sign = FTR_UNSIGNED,
1486 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1487 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1488 .matches = has_cpuid_feature,
1489 },
6984eb47 1490#endif /* CONFIG_ARM64_PTR_AUTH */
b90d2b22
JT		 1491#ifdef CONFIG_ARM64_PSEUDO_NMI
1492 {
1493 /*
1494 * Depends on having GICv3
1495 */
1496 .desc = "IRQ priority masking",
1497 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1498 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1499 .matches = can_use_gic_priorities,
1500 .sys_reg = SYS_ID_AA64PFR0_EL1,
1501 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1502 .sign = FTR_UNSIGNED,
1503 .min_field_value = 1,
1504 },
1505#endif
359b7064
MZ		 1506 {},
1507};
1508
1e013d06
WD		 1509#define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1510 .matches = has_cpuid_feature, \
1511 .sys_reg = reg, \
1512 .field_pos = field, \
1513 .sign = s, \
1514 .min_field_value = min_value,
1515
1516#define __HWCAP_CAP(name, cap_type, cap) \
1517 .desc = name, \
1518 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
1519 .hwcap_type = cap_type, \
1520 .hwcap = cap, \
1521
1522#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
1523 { \
1524 __HWCAP_CAP(#cap, cap_type, cap) \
1525 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
37b01d53
SP		 1526 }
1527
1e013d06
WD		 1528#define HWCAP_MULTI_CAP(list, cap_type, cap) \
1529 { \
1530 __HWCAP_CAP(#cap, cap_type, cap) \
1531 .matches = cpucap_multi_entry_cap_matches, \
1532 .match_list = list, \
1533 }
1534
1535#ifdef CONFIG_ARM64_PTR_AUTH
1536static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1537 {
1538 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1539 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1540 },
1541 {
1542 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1543 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1544 },
1545 {},
1546};
1547
1548static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1549 {
1550 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1551 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1552 },
1553 {
1554 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1555 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1556 },
1557 {},
1558};
1559#endif
1560
f3efb675 1561static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
ff96f7bc
SP		 1562 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1563 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1564 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1565 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
f5e035f8 1566 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
ff96f7bc
SP		 1567 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1568 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
f92f5ce0 1569 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
f5e035f8
SP		 1570 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1571 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1572 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1573 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
3b3b6810 1574 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
7206dc93 1575 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
ff96f7bc 1576 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
bf500618 1577 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
ff96f7bc 1578 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
bf500618 1579 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
7206dc93 1580 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
7aac405e 1581 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
c8c3798d 1582 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
cb567e79 1583 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
c651aae5 1584 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
7206dc93 1585 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
bd4fb6d2 1586 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SB),
7206dc93 1587 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
43994d82
DM		 1588#ifdef CONFIG_ARM64_SVE
1589 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
1590#endif
d71be2b6 1591 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
75031975 1592#ifdef CONFIG_ARM64_PTR_AUTH
1e013d06
WD		 1593 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, HWCAP_PACA),
1594 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, HWCAP_PACG),
75031975 1595#endif
75283501
SP		 1596 {},
1597};
1598
1599static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 1600#ifdef CONFIG_COMPAT
ff96f7bc
SP		 1601 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1602 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1603 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1604 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1605 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 1606#endif
1607 {},
1608};
1609
f3efb675 1610static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 1611{
1612 switch (cap->hwcap_type) {
1613 case CAP_HWCAP:
1614 elf_hwcap |= cap->hwcap;
1615 break;
1616#ifdef CONFIG_COMPAT
1617 case CAP_COMPAT_HWCAP:
1618 compat_elf_hwcap |= (u32)cap->hwcap;
1619 break;
1620 case CAP_COMPAT_HWCAP2:
1621 compat_elf_hwcap2 |= (u32)cap->hwcap;
1622 break;
1623#endif
1624 default:
1625 WARN_ON(1);
1626 break;
1627 }
1628}
1629
1630/* Check if we have a particular HWCAP enabled */
f3efb675 1631static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 1632{
1633 bool rc;
1634
1635 switch (cap->hwcap_type) {
1636 case CAP_HWCAP:
1637 rc = (elf_hwcap & cap->hwcap) != 0;
1638 break;
1639#ifdef CONFIG_COMPAT
1640 case CAP_COMPAT_HWCAP:
1641 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1642 break;
1643 case CAP_COMPAT_HWCAP2:
1644 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1645 break;
1646#endif
1647 default:
1648 WARN_ON(1);
1649 rc = false;
1650 }
1651
1652 return rc;
1653}
1654
75283501 1655static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 1656{
77c97b4e
SP		 1657 /* We support emulation of accesses to CPU ID feature registers */
1658 elf_hwcap |= HWCAP_CPUID;
75283501 1659 for (; hwcaps->matches; hwcaps++)
143ba05d 1660 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
75283501 1661 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 1662}
1663
606f8e7b 1664static void update_cpu_capabilities(u16 scope_mask)
67948af4 1665{
606f8e7b 1666 int i;
67948af4
SP		 1667 const struct arm64_cpu_capabilities *caps;
1668
cce360b5 1669 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
606f8e7b
SP		 1670 for (i = 0; i < ARM64_NCAPS; i++) {
1671 caps = cpu_hwcaps_ptrs[i];
1672 if (!caps || !(caps->type & scope_mask) ||
1673 cpus_have_cap(caps->capability) ||
cce360b5 1674 !caps->matches(caps, cpucap_default_scope(caps)))
359b7064
MZ		 1675 continue;
1676
606f8e7b
SP		 1677 if (caps->desc)
1678 pr_info("detected: %s\n", caps->desc);
75283501 1679 cpus_set_cap(caps->capability);
359b7064 1680 }
ce8b602c
SP		 1681}
1682
0b587c84
SP		 1683/*
1684 * Enable all the available capabilities on this CPU. The capabilities
1685 * with BOOT_CPU scope are handled separately and hence skipped here.
1686 */
1687static int cpu_enable_non_boot_scope_capabilities(void *__unused)
ed478b3f 1688{
0b587c84
SP		 1689 int i;
1690 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
ed478b3f 1691
0b587c84
SP		 1692 for_each_available_cap(i) {
1693 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1694
1695 if (WARN_ON(!cap))
1696 continue;
c0cda3b8 1697
0b587c84
SP		 1698 if (!(cap->type & non_boot_scope))
1699 continue;
1700
1701 if (cap->cpu_enable)
1702 cap->cpu_enable(cap);
1703 }
c0cda3b8
DM		 1704 return 0;
1705}
1706
ce8b602c 1707/*
dbb4e152
SP		 1708 * Run through the enabled capabilities and enable() it on all active
1709 * CPUs
ce8b602c 1710 */
0b587c84 1711static void __init enable_cpu_capabilities(u16 scope_mask)
ce8b602c 1712{
0b587c84
SP		 1713 int i;
1714 const struct arm64_cpu_capabilities *caps;
1715 bool boot_scope;
1716
cce360b5 1717 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
0b587c84 1718 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
63a1e1c9 1719
0b587c84
SP		 1720 for (i = 0; i < ARM64_NCAPS; i++) {
1721 unsigned int num;
1722
1723 caps = cpu_hwcaps_ptrs[i];
1724 if (!caps || !(caps->type & scope_mask))
1725 continue;
1726 num = caps->capability;
1727 if (!cpus_have_cap(num))
63a1e1c9
MR		 1728 continue;
1729
1730 /* Ensure cpus_have_const_cap(num) works */
1731 static_branch_enable(&cpu_hwcap_keys[num]);
1732
0b587c84 1733 if (boot_scope && caps->cpu_enable)
2a6dcb2b 1734 /*
fd9d63da
SP		 1735 * Capabilities with SCOPE_BOOT_CPU scope are finalised
1736 * before any secondary CPU boots. Thus, each secondary
1737 * will enable the capability as appropriate via
1738 * check_local_cpu_capabilities(). The only exception is
1739 * the boot CPU, for which the capability must be
1740 * enabled here. This approach avoids costly
1741 * stop_machine() calls for this case.
2a6dcb2b 1742 */
0b587c84 1743 caps->cpu_enable(caps);
63a1e1c9 1744 }
dbb4e152 1745
0b587c84
SP		 1746 /*
1747 * For all non-boot scope capabilities, use stop_machine()
1748 * as it schedules the work allowing us to modify PSTATE,
1749 * instead of on_each_cpu() which uses an IPI, giving us a
1750 * PSTATE that disappears when we return.
1751 */
1752 if (!boot_scope)
1753 stop_machine(cpu_enable_non_boot_scope_capabilities,
1754 NULL, cpu_online_mask);
ed478b3f
SP		 1755}
1756
eaac4d83
SP		 1757/*
1758 * Run through the list of capabilities to check for conflicts.
1759 * If the system has already detected a capability, take necessary
1760 * action on this CPU.
1761 *
1762 * Returns "false" on conflicts.
1763 */
606f8e7b 1764static bool verify_local_cpu_caps(u16 scope_mask)
eaac4d83 1765{
606f8e7b 1766 int i;
eaac4d83 1767 bool cpu_has_cap, system_has_cap;
606f8e7b 1768 const struct arm64_cpu_capabilities *caps;
eaac4d83 1769
cce360b5
SP		 1770 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1771
606f8e7b
SP		 1772 for (i = 0; i < ARM64_NCAPS; i++) {
1773 caps = cpu_hwcaps_ptrs[i];
1774 if (!caps || !(caps->type & scope_mask))
cce360b5
SP		 1775 continue;
1776
ba7d9233 1777 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
eaac4d83
SP		 1778 system_has_cap = cpus_have_cap(caps->capability);
1779
1780 if (system_has_cap) {
1781 /*
1782 * Check if the new CPU misses an advertised feature,
1783 * which is not safe to miss.
1784 */
1785 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1786 break;
1787 /*
1788 * We have to issue cpu_enable() irrespective of
1789 * whether the CPU has it or not, as it is enabeld
1790 * system wide. It is upto the call back to take
1791 * appropriate action on this CPU.
1792 */
1793 if (caps->cpu_enable)
1794 caps->cpu_enable(caps);
1795 } else {
1796 /*
1797 * Check if the CPU has this capability if it isn't
1798 * safe to have when the system doesn't.
1799 */
1800 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1801 break;
1802 }
1803 }
1804
606f8e7b 1805 if (i < ARM64_NCAPS) {
eaac4d83
SP		 1806 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1807 smp_processor_id(), caps->capability,
1808 caps->desc, system_has_cap, cpu_has_cap);
1809 return false;
1810 }
1811
1812 return true;
1813}
1814
dbb4e152 1815/*
13f417f3
SP		 1816 * Check for CPU features that are used in early boot
1817 * based on the Boot CPU value.
dbb4e152 1818 */
13f417f3 1819static void check_early_cpu_features(void)
dbb4e152 1820{
13f417f3 1821 verify_cpu_asid_bits();
fd9d63da
SP		 1822 /*
1823 * Early features are used by the kernel already. If there
1824 * is a conflict, we cannot proceed further.
1825 */
1826 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1827 cpu_panic_kernel();
dbb4e152 1828}
1c076303 1829
75283501
SP		 1830static void
1831verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1832{
1833
92406f0c
SP		 1834 for (; caps->matches; caps++)
1835 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 1836 pr_crit("CPU%d: missing HWCAP: %s\n",
1837 smp_processor_id(), caps->desc);
1838 cpu_die_early();
1839 }
75283501
SP		 1840}
1841
2e0f2478
DM		 1842static void verify_sve_features(void)
1843{
1844 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1845 u64 zcr = read_zcr_features();
1846
1847 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1848 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1849
1850 if (len < safe_len || sve_verify_vq_map()) {
1851 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1852 smp_processor_id());
1853 cpu_die_early();
1854 }
1855
1856 /* Add checks on other ZCR bits here if necessary */
1857}
1858
1e89baed 1859
dbb4e152
SP		 1860/*
1861 * Run through the enabled system capabilities and enable() it on this CPU.
1862 * The capabilities were decided based on the available CPUs at the boot time.
1863 * Any new CPU should match the system wide status of the capability. If the
1864 * new CPU doesn't have a capability which the system now has enabled, we
1865 * cannot do anything to fix it up and could cause unexpected failures. So
1866 * we park the CPU.
1867 */
c47a1900 1868static void verify_local_cpu_capabilities(void)
dbb4e152 1869{
fd9d63da
SP		 1870 /*
1871 * The capabilities with SCOPE_BOOT_CPU are checked from
1872 * check_early_cpu_features(), as they need to be verified
1873 * on all secondary CPUs.
1874 */
1875 if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
600b9c91 1876 cpu_die_early();
ed478b3f 1877
c47a1900 1878 verify_local_elf_hwcaps(arm64_elf_hwcaps);
2e0f2478 1879
c47a1900
SP		 1880 if (system_supports_32bit_el0())
1881 verify_local_elf_hwcaps(compat_elf_hwcaps);
2e0f2478
DM		 1882
1883 if (system_supports_sve())
1884 verify_sve_features();
c47a1900 1885}
dbb4e152 1886
c47a1900
SP		 1887void check_local_cpu_capabilities(void)
1888{
1889 /*
1890 * All secondary CPUs should conform to the early CPU features
1891 * in use by the kernel based on boot CPU.
1892 */
13f417f3
SP		 1893 check_early_cpu_features();
1894
dbb4e152 1895 /*
c47a1900 1896 * If we haven't finalised the system capabilities, this CPU gets
fbd890b9 1897 * a chance to update the errata work arounds and local features.
c47a1900
SP		 1898 * Otherwise, this CPU should verify that it has all the system
1899 * advertised capabilities.
dbb4e152 1900 */
ed478b3f
SP		 1901 if (!sys_caps_initialised)
1902 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1903 else
c47a1900 1904 verify_local_cpu_capabilities();
359b7064
MZ		 1905}
1906
fd9d63da
SP		 1907static void __init setup_boot_cpu_capabilities(void)
1908{
1909 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1910 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1911 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1912 enable_cpu_capabilities(SCOPE_BOOT_CPU);
1913}
1914
63a1e1c9
MR		 1915DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1916EXPORT_SYMBOL(arm64_const_caps_ready);
1917
1918static void __init mark_const_caps_ready(void)
1919{
1920 static_branch_enable(&arm64_const_caps_ready);
1921}
1922
f7bfc14a 1923bool this_cpu_has_cap(unsigned int n)
8f413758 1924{
f7bfc14a
SP		 1925 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
1926 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
1927
1928 if (cap)
1929 return cap->matches(cap, SCOPE_LOCAL_CPU);
1930 }
1931
1932 return false;
8f413758
MZ		 1933}
1934
ed478b3f
SP		 1935static void __init setup_system_capabilities(void)
1936{
1937 /*
1938 * We have finalised the system-wide safe feature
1939 * registers, finalise the capabilities that depend
fd9d63da
SP		 1940 * on it. Also enable all the available capabilities,
1941 * that are not enabled already.
ed478b3f
SP		 1942 */
1943 update_cpu_capabilities(SCOPE_SYSTEM);
fd9d63da 1944 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
ed478b3f
SP		 1945}
1946
9cdf8ec4 1947void __init setup_cpu_features(void)
359b7064 1948{
9cdf8ec4 1949 u32 cwg;
9cdf8ec4 1950
ed478b3f 1951 setup_system_capabilities();
63a1e1c9 1952 mark_const_caps_ready();
75283501 1953 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 1954
1955 if (system_supports_32bit_el0())
1956 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152 1957
2e6f549f
KC		 1958 if (system_uses_ttbr0_pan())
1959 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
1960
2e0f2478 1961 sve_setup();
94b07c1f 1962 minsigstksz_setup();
2e0f2478 1963
dbb4e152
SP		 1964 /* Advertise that we have computed the system capabilities */
1965 set_sys_caps_initialised();
1966
9cdf8ec4
SP		 1967 /*
1968 * Check for sane CTR_EL0.CWG value.
1969 */
1970 cwg = cache_type_cwg();
9cdf8ec4 1971 if (!cwg)
ebc7e21e
CM		 1972 pr_warn("No Cache Writeback Granule information, assuming %d\n",
1973 ARCH_DMA_MINALIGN);
359b7064 1974}
70544196
JM		 1975
1976static bool __maybe_unused
92406f0c 1977cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196 1978{
a4023f68 1979 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
70544196 1980}
77c97b4e 1981
5ffdfaed
VM		 1982static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
1983{
1984 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
1985}
1986
77c97b4e
SP		 1987/*
1988 * We emulate only the following system register space.
1989 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1990 * See Table C5-6 System instruction encodings for System register accesses,
1991 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1992 */
1993static inline bool __attribute_const__ is_emulated(u32 id)
1994{
1995 return (sys_reg_Op0(id) == 0x3 &&
1996 sys_reg_CRn(id) == 0x0 &&
1997 sys_reg_Op1(id) == 0x0 &&
1998 (sys_reg_CRm(id) == 0 ||
1999 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2000}
2001
2002/*
2003 * With CRm == 0, reg should be one of :
2004 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2005 */
2006static inline int emulate_id_reg(u32 id, u64 *valp)
2007{
2008 switch (id) {
2009 case SYS_MIDR_EL1:
2010 *valp = read_cpuid_id();
2011 break;
2012 case SYS_MPIDR_EL1:
2013 *valp = SYS_MPIDR_SAFE_VAL;
2014 break;
2015 case SYS_REVIDR_EL1:
2016 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2017 *valp = 0;
2018 break;
2019 default:
2020 return -EINVAL;
2021 }
2022
2023 return 0;
2024}
2025
2026static int emulate_sys_reg(u32 id, u64 *valp)
2027{
2028 struct arm64_ftr_reg *regp;
2029
2030 if (!is_emulated(id))
2031 return -EINVAL;
2032
2033 if (sys_reg_CRm(id) == 0)
2034 return emulate_id_reg(id, valp);
2035
2036 regp = get_arm64_ftr_reg(id);
2037 if (regp)
2038 *valp = arm64_ftr_reg_user_value(regp);
2039 else
2040 /*
2041 * The untracked registers are either IMPLEMENTATION DEFINED
2042 * (e.g, ID_AFR0_EL1) or reserved RAZ.
2043 */
2044 *valp = 0;
2045 return 0;
2046}
2047
520ad988 2048int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
77c97b4e
SP		 2049{
2050 int rc;
77c97b4e
SP		 2051 u64 val;
2052
77c97b4e
SP		 2053 rc = emulate_sys_reg(sys_reg, &val);
2054 if (!rc) {
520ad988 2055 pt_regs_write_reg(regs, rt, val);
6436beee 2056 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
77c97b4e 2057 }
77c97b4e
SP		 2058 return rc;
2059}
2060
520ad988
AK		 2061static int emulate_mrs(struct pt_regs *regs, u32 insn)
2062{
2063 u32 sys_reg, rt;
2064
2065 /*
2066 * sys_reg values are defined as used in mrs/msr instruction.
2067 * shift the imm value to get the encoding.
2068 */
2069 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2070 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2071 return do_emulate_mrs(regs, sys_reg, rt);
2072}
2073
77c97b4e
SP		 2074static struct undef_hook mrs_hook = {
2075 .instr_mask = 0xfff00000,
2076 .instr_val = 0xd5300000,
d64567f6 2077 .pstate_mask = PSR_AA32_MODE_MASK,
77c97b4e
SP		 2078 .pstate_val = PSR_MODE_EL0t,
2079 .fn = emulate_mrs,
2080};
2081
2082static int __init enable_mrs_emulation(void)
2083{
2084 register_undef_hook(&mrs_hook);
2085 return 0;
2086}
2087
c0d8832e 2088core_initcall(enable_mrs_emulation);
Linux 6.x block layer and io_uring tree(s)